141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 541fd4caeSFaiz Abbas * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 999909b55SFaiz Abbas #include <linux/of.h> 1041fd4caeSFaiz Abbas #include <linux/module.h> 1141fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1241fd4caeSFaiz Abbas #include <linux/property.h> 1341fd4caeSFaiz Abbas #include <linux/regmap.h> 1441fd4caeSFaiz Abbas 15f545702bSFaiz Abbas #include "cqhci.h" 1641fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1741fd4caeSFaiz Abbas 1841fd4caeSFaiz Abbas /* CTL_CFG Registers */ 1941fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 2041fd4caeSFaiz Abbas 2141fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2241fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 2341fd4caeSFaiz Abbas 2441fd4caeSFaiz Abbas /* PHY Registers */ 2541fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 2641fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 2741fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 2841fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 2941fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3041fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3141fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3241fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3341fd4caeSFaiz Abbas 3441fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3541fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 3641fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 3741fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 3841fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 3941fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4041fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4199909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4299909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4341fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4441fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4541fd4caeSFaiz Abbas #define SEL100_SHIFT 9 4641fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 4799909b55SFaiz Abbas #define FREQSEL_SHIFT 8 4899909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 4941fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5041fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5141fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5241fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 5341fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 5441fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 5541fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 5641fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 5741fd4caeSFaiz Abbas #define PDB_SHIFT 0 5841fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 5941fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6041fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6141fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6241fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 6341fd4caeSFaiz Abbas 6441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 6541fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 6641fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 6741fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 6841fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 6941fd4caeSFaiz Abbas 7041fd4caeSFaiz Abbas #define CLOCK_TOO_SLOW_HZ 400000 7141fd4caeSFaiz Abbas 72f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 73f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 74f545702bSFaiz Abbas 7541fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 7641fd4caeSFaiz Abbas .reg_bits = 32, 7741fd4caeSFaiz Abbas .val_bits = 32, 7841fd4caeSFaiz Abbas .reg_stride = 4, 7941fd4caeSFaiz Abbas .fast_io = true, 8041fd4caeSFaiz Abbas }; 8141fd4caeSFaiz Abbas 8241fd4caeSFaiz Abbas struct sdhci_am654_data { 8341fd4caeSFaiz Abbas struct regmap *base; 8441fd4caeSFaiz Abbas int otap_del_sel; 8541fd4caeSFaiz Abbas int trm_icp; 8641fd4caeSFaiz Abbas int drv_strength; 8741fd4caeSFaiz Abbas bool dll_on; 8899909b55SFaiz Abbas int strb_sel; 8999909b55SFaiz Abbas u32 flags; 9099909b55SFaiz Abbas }; 9199909b55SFaiz Abbas 9299909b55SFaiz Abbas struct sdhci_am654_driver_data { 9399909b55SFaiz Abbas const struct sdhci_pltfm_data *pdata; 9499909b55SFaiz Abbas u32 flags; 9599909b55SFaiz Abbas #define IOMUX_PRESENT (1 << 0) 9699909b55SFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 9799909b55SFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 981accbcedSFaiz Abbas #define DLL_PRESENT (1 << 3) 9941fd4caeSFaiz Abbas }; 10041fd4caeSFaiz Abbas 10141fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 10241fd4caeSFaiz Abbas { 10341fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10441fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 10599909b55SFaiz Abbas int sel50, sel100, freqsel; 10641fd4caeSFaiz Abbas u32 mask, val; 10741fd4caeSFaiz Abbas int ret; 10841fd4caeSFaiz Abbas 10941fd4caeSFaiz Abbas if (sdhci_am654->dll_on) { 1108023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 11141fd4caeSFaiz Abbas 11241fd4caeSFaiz Abbas sdhci_am654->dll_on = false; 11341fd4caeSFaiz Abbas } 11441fd4caeSFaiz Abbas 11541fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 11641fd4caeSFaiz Abbas 11741fd4caeSFaiz Abbas if (clock > CLOCK_TOO_SLOW_HZ) { 11841fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 11941fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 12041fd4caeSFaiz Abbas val = (1 << OTAPDLYENA_SHIFT) | 12141fd4caeSFaiz Abbas (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 1228023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 12399909b55SFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 12499909b55SFaiz Abbas if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 12599909b55SFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 12699909b55SFaiz Abbas mask = STRBSEL_4BIT_MASK; 12799909b55SFaiz Abbas else 12899909b55SFaiz Abbas mask = STRBSEL_8BIT_MASK; 12999909b55SFaiz Abbas 13099909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 13199909b55SFaiz Abbas sdhci_am654->strb_sel << 13299909b55SFaiz Abbas STRBSEL_SHIFT); 13399909b55SFaiz Abbas } 13499909b55SFaiz Abbas 13599909b55SFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 13641fd4caeSFaiz Abbas switch (clock) { 13741fd4caeSFaiz Abbas case 200000000: 13841fd4caeSFaiz Abbas sel50 = 0; 13941fd4caeSFaiz Abbas sel100 = 0; 14041fd4caeSFaiz Abbas break; 14141fd4caeSFaiz Abbas case 100000000: 14241fd4caeSFaiz Abbas sel50 = 0; 14341fd4caeSFaiz Abbas sel100 = 1; 14441fd4caeSFaiz Abbas break; 14541fd4caeSFaiz Abbas default: 14641fd4caeSFaiz Abbas sel50 = 1; 14741fd4caeSFaiz Abbas sel100 = 0; 14841fd4caeSFaiz Abbas } 14941fd4caeSFaiz Abbas 15041fd4caeSFaiz Abbas /* Configure PHY DLL frequency */ 15141fd4caeSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 15241fd4caeSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 15399909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, 15499909b55SFaiz Abbas val); 15599909b55SFaiz Abbas } else { 15699909b55SFaiz Abbas switch (clock) { 15799909b55SFaiz Abbas case 200000000: 15899909b55SFaiz Abbas freqsel = 0x0; 15999909b55SFaiz Abbas break; 16099909b55SFaiz Abbas default: 16199909b55SFaiz Abbas freqsel = 0x4; 16299909b55SFaiz Abbas } 16399909b55SFaiz Abbas 16499909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 16599909b55SFaiz Abbas FREQSEL_MASK, 16699909b55SFaiz Abbas freqsel << FREQSEL_SHIFT); 16799909b55SFaiz Abbas } 16899909b55SFaiz Abbas 16941fd4caeSFaiz Abbas /* Configure DLL TRIM */ 17041fd4caeSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 17141fd4caeSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 17241fd4caeSFaiz Abbas 17341fd4caeSFaiz Abbas /* Configure DLL driver strength */ 17441fd4caeSFaiz Abbas mask |= DR_TY_MASK; 17541fd4caeSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 1768023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 17741fd4caeSFaiz Abbas /* Enable DLL */ 1788023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 1798023cf26SFaiz Abbas 0x1 << ENDLL_SHIFT); 18041fd4caeSFaiz Abbas /* 18141fd4caeSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 18241fd4caeSFaiz Abbas * Works in all experiments done so far 18341fd4caeSFaiz Abbas */ 1848023cf26SFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 1858023cf26SFaiz Abbas val, val & DLLRDY_MASK, 1000, 1868023cf26SFaiz Abbas 1000000); 1877e24e28bSFaiz Abbas if (ret) { 1887e24e28bSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 1897e24e28bSFaiz Abbas return; 1907e24e28bSFaiz Abbas } 1917e24e28bSFaiz Abbas 19241fd4caeSFaiz Abbas sdhci_am654->dll_on = true; 19341fd4caeSFaiz Abbas } 19441fd4caeSFaiz Abbas } 19541fd4caeSFaiz Abbas 1968751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 1978751c8bdSYueHaibing unsigned int clock) 1981accbcedSFaiz Abbas { 1991accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2001accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2011accbcedSFaiz Abbas int val, mask; 2021accbcedSFaiz Abbas 2031accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2041accbcedSFaiz Abbas val = (1 << OTAPDLYENA_SHIFT) | 2051accbcedSFaiz Abbas (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 2061accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2071accbcedSFaiz Abbas 2081accbcedSFaiz Abbas sdhci_set_clock(host, clock); 2091accbcedSFaiz Abbas } 2101accbcedSFaiz Abbas 21141fd4caeSFaiz Abbas static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 21241fd4caeSFaiz Abbas unsigned short vdd) 21341fd4caeSFaiz Abbas { 21441fd4caeSFaiz Abbas if (!IS_ERR(host->mmc->supply.vmmc)) { 21541fd4caeSFaiz Abbas struct mmc_host *mmc = host->mmc; 21641fd4caeSFaiz Abbas 21741fd4caeSFaiz Abbas mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 21841fd4caeSFaiz Abbas } 21941fd4caeSFaiz Abbas sdhci_set_power_noreg(host, mode, vdd); 22041fd4caeSFaiz Abbas } 22141fd4caeSFaiz Abbas 222e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 223e374e875SFaiz Abbas { 224e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 225e374e875SFaiz Abbas 226e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 227e374e875SFaiz Abbas switch (timing) { 228e374e875SFaiz Abbas /* 229e374e875SFaiz Abbas * According to the data manual, HISPD bit 230e374e875SFaiz Abbas * should not be set in these speed modes. 231e374e875SFaiz Abbas */ 232e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 233e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 234e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 235e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 236e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 237e374e875SFaiz Abbas } 238e374e875SFaiz Abbas } 239e374e875SFaiz Abbas 240e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 241e374e875SFaiz Abbas } 242e374e875SFaiz Abbas 2434e47345aSWei Yongjun static struct sdhci_ops sdhci_am654_ops = { 24441fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 24541fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 24641fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 24741fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 24841fd4caeSFaiz Abbas .set_power = sdhci_am654_set_power, 24941fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 250e374e875SFaiz Abbas .write_b = sdhci_am654_write_b, 25141fd4caeSFaiz Abbas .reset = sdhci_reset, 25241fd4caeSFaiz Abbas }; 25341fd4caeSFaiz Abbas 25441fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 25541fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 2564d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 25741fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 25841fd4caeSFaiz Abbas }; 25941fd4caeSFaiz Abbas 26099909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 26199909b55SFaiz Abbas .pdata = &sdhci_am654_pdata, 2621accbcedSFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 26399909b55SFaiz Abbas }; 26499909b55SFaiz Abbas 265f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 266f545702bSFaiz Abbas { 267f545702bSFaiz Abbas int cmd_error = 0; 268f545702bSFaiz Abbas int data_error = 0; 269f545702bSFaiz Abbas 270f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 271f545702bSFaiz Abbas return intmask; 272f545702bSFaiz Abbas 273f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 274f545702bSFaiz Abbas 275f545702bSFaiz Abbas return 0; 276f545702bSFaiz Abbas } 277f545702bSFaiz Abbas 2788751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 27999909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 28099909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 28199909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 28299909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 28399909b55SFaiz Abbas .set_power = sdhci_am654_set_power, 28499909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 28599909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 286f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 28799909b55SFaiz Abbas .reset = sdhci_reset, 28899909b55SFaiz Abbas }; 28999909b55SFaiz Abbas 29099909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 29199909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 2924d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 29399909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 29499909b55SFaiz Abbas }; 29599909b55SFaiz Abbas 29699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 29799909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 2981accbcedSFaiz Abbas .flags = DLL_PRESENT, 29999909b55SFaiz Abbas }; 30099909b55SFaiz Abbas 3018751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 3021accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 3031accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 3041accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 3051accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 3061accbcedSFaiz Abbas .set_power = sdhci_am654_set_power, 3071accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 3081accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 309f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 3101accbcedSFaiz Abbas .reset = sdhci_reset, 3111accbcedSFaiz Abbas }; 3121accbcedSFaiz Abbas 3131accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 3141accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 3154d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 3161accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 3171accbcedSFaiz Abbas }; 3181accbcedSFaiz Abbas 3191accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 3201accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 3211accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 3221accbcedSFaiz Abbas }; 323f545702bSFaiz Abbas 324f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 325f545702bSFaiz Abbas { 326f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 327f545702bSFaiz Abbas } 328f545702bSFaiz Abbas 329f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 330f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 331f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 332f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 333f545702bSFaiz Abbas }; 334f545702bSFaiz Abbas 335f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 336f545702bSFaiz Abbas { 337f545702bSFaiz Abbas struct cqhci_host *cq_host; 338f545702bSFaiz Abbas int ret; 339f545702bSFaiz Abbas 340f545702bSFaiz Abbas cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 341f545702bSFaiz Abbas GFP_KERNEL); 342f545702bSFaiz Abbas if (!cq_host) 343f545702bSFaiz Abbas return -ENOMEM; 344f545702bSFaiz Abbas 345f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 346f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 347f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 348f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 349f545702bSFaiz Abbas 350f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 351f545702bSFaiz Abbas 352f545702bSFaiz Abbas ret = cqhci_init(cq_host, host->mmc, 1); 353f545702bSFaiz Abbas 354f545702bSFaiz Abbas return ret; 355f545702bSFaiz Abbas } 356f545702bSFaiz Abbas 35741fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 35841fd4caeSFaiz Abbas { 35941fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 36041fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 36141fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 36241fd4caeSFaiz Abbas u32 mask; 36341fd4caeSFaiz Abbas u32 val; 36441fd4caeSFaiz Abbas int ret; 36541fd4caeSFaiz Abbas 36641fd4caeSFaiz Abbas /* Reset OTAP to default value */ 36741fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3688023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 36941fd4caeSFaiz Abbas 3701accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 37141fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 37241fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 37341fd4caeSFaiz Abbas /* Calibrate IO lines */ 37441fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 37541fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 3761accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 3771accbcedSFaiz Abbas PHY_STAT1, val, 3781accbcedSFaiz Abbas val & CALDONE_MASK, 3791accbcedSFaiz Abbas 1, 20); 38041fd4caeSFaiz Abbas if (ret) 38141fd4caeSFaiz Abbas return ret; 38241fd4caeSFaiz Abbas } 3831accbcedSFaiz Abbas } 38441fd4caeSFaiz Abbas 38541fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 38699909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 38799909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 38899909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 38941fd4caeSFaiz Abbas 39041fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 39141fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 39241fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 39341fd4caeSFaiz Abbas 3948023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 3958023cf26SFaiz Abbas ctl_cfg_2); 39641fd4caeSFaiz Abbas 397f545702bSFaiz Abbas ret = sdhci_setup_host(host); 398f545702bSFaiz Abbas if (ret) 399f545702bSFaiz Abbas return ret; 400f545702bSFaiz Abbas 401f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 402f545702bSFaiz Abbas if (ret) 403f545702bSFaiz Abbas goto err_cleanup_host; 404f545702bSFaiz Abbas 405f545702bSFaiz Abbas ret = __sdhci_add_host(host); 406f545702bSFaiz Abbas if (ret) 407f545702bSFaiz Abbas goto err_cleanup_host; 408f545702bSFaiz Abbas 409f545702bSFaiz Abbas return 0; 410f545702bSFaiz Abbas 411f545702bSFaiz Abbas err_cleanup_host: 412f545702bSFaiz Abbas sdhci_cleanup_host(host); 413f545702bSFaiz Abbas return ret; 41441fd4caeSFaiz Abbas } 41541fd4caeSFaiz Abbas 41641fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 41741fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 41841fd4caeSFaiz Abbas { 41941fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 42041fd4caeSFaiz Abbas int drv_strength; 42141fd4caeSFaiz Abbas int ret; 42241fd4caeSFaiz Abbas 4231accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 4241accbcedSFaiz Abbas &sdhci_am654->otap_del_sel); 42541fd4caeSFaiz Abbas if (ret) 42641fd4caeSFaiz Abbas return ret; 42741fd4caeSFaiz Abbas 4281accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 4291accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 4301accbcedSFaiz Abbas &sdhci_am654->trm_icp); 43141fd4caeSFaiz Abbas if (ret) 43241fd4caeSFaiz Abbas return ret; 43341fd4caeSFaiz Abbas 43441fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 43541fd4caeSFaiz Abbas &drv_strength); 43641fd4caeSFaiz Abbas if (ret) 43741fd4caeSFaiz Abbas return ret; 43841fd4caeSFaiz Abbas 43941fd4caeSFaiz Abbas switch (drv_strength) { 44041fd4caeSFaiz Abbas case 50: 44141fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 44241fd4caeSFaiz Abbas break; 44341fd4caeSFaiz Abbas case 33: 44441fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 44541fd4caeSFaiz Abbas break; 44641fd4caeSFaiz Abbas case 66: 44741fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 44841fd4caeSFaiz Abbas break; 44941fd4caeSFaiz Abbas case 100: 45041fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 45141fd4caeSFaiz Abbas break; 45241fd4caeSFaiz Abbas case 40: 45341fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 45441fd4caeSFaiz Abbas break; 45541fd4caeSFaiz Abbas default: 45641fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 45741fd4caeSFaiz Abbas return -EINVAL; 45841fd4caeSFaiz Abbas } 4591accbcedSFaiz Abbas } 46041fd4caeSFaiz Abbas 46199909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 46299909b55SFaiz Abbas 46341fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 46441fd4caeSFaiz Abbas 46541fd4caeSFaiz Abbas return 0; 46641fd4caeSFaiz Abbas } 46741fd4caeSFaiz Abbas 46899909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 46999909b55SFaiz Abbas { 47099909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 47199909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 47299909b55SFaiz Abbas }, 47399909b55SFaiz Abbas { 47499909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 47599909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 47699909b55SFaiz Abbas }, 4771accbcedSFaiz Abbas { 4781accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 4791accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 4801accbcedSFaiz Abbas }, 48199909b55SFaiz Abbas { /* sentinel */ } 48299909b55SFaiz Abbas }; 48399909b55SFaiz Abbas 48441fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 48541fd4caeSFaiz Abbas { 48699909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 48741fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 48841fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 48999909b55SFaiz Abbas const struct of_device_id *match; 49041fd4caeSFaiz Abbas struct sdhci_host *host; 49141fd4caeSFaiz Abbas struct resource *res; 49241fd4caeSFaiz Abbas struct clk *clk_xin; 49341fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 49441fd4caeSFaiz Abbas void __iomem *base; 49541fd4caeSFaiz Abbas int ret; 49641fd4caeSFaiz Abbas 49799909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 49899909b55SFaiz Abbas drvdata = match->data; 49999909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 50041fd4caeSFaiz Abbas if (IS_ERR(host)) 50141fd4caeSFaiz Abbas return PTR_ERR(host); 50241fd4caeSFaiz Abbas 50341fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 50441fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 50599909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 50641fd4caeSFaiz Abbas 50741fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 50841fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 50941fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 51041fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 51141fd4caeSFaiz Abbas goto err_pltfm_free; 51241fd4caeSFaiz Abbas } 51341fd4caeSFaiz Abbas 51441fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 51541fd4caeSFaiz Abbas 51641fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 51741fd4caeSFaiz Abbas pm_runtime_enable(dev); 51841fd4caeSFaiz Abbas ret = pm_runtime_get_sync(dev); 51941fd4caeSFaiz Abbas if (ret < 0) { 52041fd4caeSFaiz Abbas pm_runtime_put_noidle(dev); 52141fd4caeSFaiz Abbas goto pm_runtime_disable; 52241fd4caeSFaiz Abbas } 52341fd4caeSFaiz Abbas 52441fd4caeSFaiz Abbas res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 52541fd4caeSFaiz Abbas base = devm_ioremap_resource(dev, res); 52641fd4caeSFaiz Abbas if (IS_ERR(base)) { 52741fd4caeSFaiz Abbas ret = PTR_ERR(base); 52841fd4caeSFaiz Abbas goto pm_runtime_put; 52941fd4caeSFaiz Abbas } 53041fd4caeSFaiz Abbas 53141fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 53241fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 53341fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 53441fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 53541fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 53641fd4caeSFaiz Abbas goto pm_runtime_put; 53741fd4caeSFaiz Abbas } 53841fd4caeSFaiz Abbas 53941fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 54041fd4caeSFaiz Abbas if (ret) 54141fd4caeSFaiz Abbas goto pm_runtime_put; 54241fd4caeSFaiz Abbas 54341fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 54441fd4caeSFaiz Abbas if (ret) { 54541fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 54641fd4caeSFaiz Abbas goto pm_runtime_put; 54741fd4caeSFaiz Abbas } 54841fd4caeSFaiz Abbas 54941fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 55041fd4caeSFaiz Abbas if (ret) 55141fd4caeSFaiz Abbas goto pm_runtime_put; 55241fd4caeSFaiz Abbas 55341fd4caeSFaiz Abbas return 0; 55441fd4caeSFaiz Abbas 55541fd4caeSFaiz Abbas pm_runtime_put: 55641fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 55741fd4caeSFaiz Abbas pm_runtime_disable: 55841fd4caeSFaiz Abbas pm_runtime_disable(dev); 55941fd4caeSFaiz Abbas err_pltfm_free: 56041fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 56141fd4caeSFaiz Abbas return ret; 56241fd4caeSFaiz Abbas } 56341fd4caeSFaiz Abbas 56441fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 56541fd4caeSFaiz Abbas { 56641fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 56741fd4caeSFaiz Abbas int ret; 56841fd4caeSFaiz Abbas 56941fd4caeSFaiz Abbas sdhci_remove_host(host, true); 57041fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 57141fd4caeSFaiz Abbas if (ret < 0) 57241fd4caeSFaiz Abbas return ret; 57341fd4caeSFaiz Abbas 57441fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 57541fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 57641fd4caeSFaiz Abbas 57741fd4caeSFaiz Abbas return 0; 57841fd4caeSFaiz Abbas } 57941fd4caeSFaiz Abbas 58041fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 58141fd4caeSFaiz Abbas .driver = { 58241fd4caeSFaiz Abbas .name = "sdhci-am654", 58341fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 58441fd4caeSFaiz Abbas }, 58541fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 58641fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 58741fd4caeSFaiz Abbas }; 58841fd4caeSFaiz Abbas 58941fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 59041fd4caeSFaiz Abbas 59141fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 59241fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 59341fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 594