141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 59481b45cSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 97ca0f166SFaiz Abbas #include <linux/iopoll.h> 1099909b55SFaiz Abbas #include <linux/of.h> 1141fd4caeSFaiz Abbas #include <linux/module.h> 1241fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1341fd4caeSFaiz Abbas #include <linux/property.h> 1441fd4caeSFaiz Abbas #include <linux/regmap.h> 1509db9943SFaiz Abbas #include <linux/sys_soc.h> 1641fd4caeSFaiz Abbas 17f545702bSFaiz Abbas #include "cqhci.h" 18162503fdSBrian Norris #include "sdhci-cqhci.h" 1941fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 2041fd4caeSFaiz Abbas 2141fd4caeSFaiz Abbas /* CTL_CFG Registers */ 2241fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 23764384d0SFaiz Abbas #define CTL_CFG_3 0x18 2441fd4caeSFaiz Abbas 2541fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2641fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 27764384d0SFaiz Abbas #define TUNINGFORSDR50_MASK BIT(13) 2841fd4caeSFaiz Abbas 2941fd4caeSFaiz Abbas /* PHY Registers */ 3041fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 3141fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 3241fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 3341fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 3441fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3541fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3641fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3741fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3841fd4caeSFaiz Abbas 3941fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 4041fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 4141fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 4241fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 4341fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 4441fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4541fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4699909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4799909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4841fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4941fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 5041fd4caeSFaiz Abbas #define SEL100_SHIFT 9 5141fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 5299909b55SFaiz Abbas #define FREQSEL_SHIFT 8 5399909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 5461d9c4aaSFaiz Abbas #define CLKBUFSEL_SHIFT 0 5561d9c4aaSFaiz Abbas #define CLKBUFSEL_MASK GENMASK(2, 0) 5641fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5741fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5841fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5941fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 6041fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 6141fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 6241fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 6341fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 6441fd4caeSFaiz Abbas #define PDB_SHIFT 0 6541fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 6641fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6741fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6841fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6941fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 700003417dSFaiz Abbas #define SELDLYTXCLK_SHIFT 17 710003417dSFaiz Abbas #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72a0a62497SFaiz Abbas #define SELDLYRXCLK_SHIFT 16 73a0a62497SFaiz Abbas #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74a0a62497SFaiz Abbas #define ITAPDLYSEL_SHIFT 0 75a0a62497SFaiz Abbas #define ITAPDLYSEL_MASK GENMASK(4, 0) 76a0a62497SFaiz Abbas #define ITAPDLYENA_SHIFT 8 77a0a62497SFaiz Abbas #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78a0a62497SFaiz Abbas #define ITAPCHGWIN_SHIFT 9 79a0a62497SFaiz Abbas #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 8041fd4caeSFaiz Abbas 8141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 8241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 8341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 8441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 8541fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 8641fd4caeSFaiz Abbas 87a0a62497SFaiz Abbas #define CLOCK_TOO_SLOW_HZ 50000000 889d2e77ffSAswath Govindraju #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 8941fd4caeSFaiz Abbas 90f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 91f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92f545702bSFaiz Abbas 9341fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 9441fd4caeSFaiz Abbas .reg_bits = 32, 9541fd4caeSFaiz Abbas .val_bits = 32, 9641fd4caeSFaiz Abbas .reg_stride = 4, 9741fd4caeSFaiz Abbas .fast_io = true, 9841fd4caeSFaiz Abbas }; 9941fd4caeSFaiz Abbas 1008ee5fc0eSFaiz Abbas struct timing_data { 101a0a62497SFaiz Abbas const char *otap_binding; 102a0a62497SFaiz Abbas const char *itap_binding; 1038ee5fc0eSFaiz Abbas u32 capability; 1048ee5fc0eSFaiz Abbas }; 1058ee5fc0eSFaiz Abbas 1068ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 107a0a62497SFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108a0a62497SFaiz Abbas "ti,itap-del-sel-legacy", 109a0a62497SFaiz Abbas 0}, 110a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111a0a62497SFaiz Abbas "ti,itap-del-sel-mmc-hs", 112a0a62497SFaiz Abbas MMC_CAP_MMC_HIGHSPEED}, 113a0a62497SFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114a0a62497SFaiz Abbas "ti,itap-del-sel-sd-hs", 115a0a62497SFaiz Abbas MMC_CAP_SD_HIGHSPEED}, 116a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117a0a62497SFaiz Abbas "ti,itap-del-sel-sdr12", 118a0a62497SFaiz Abbas MMC_CAP_UHS_SDR12}, 119a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120a0a62497SFaiz Abbas "ti,itap-del-sel-sdr25", 121a0a62497SFaiz Abbas MMC_CAP_UHS_SDR25}, 122a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123a0a62497SFaiz Abbas NULL, 124a0a62497SFaiz Abbas MMC_CAP_UHS_SDR50}, 1258ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126a0a62497SFaiz Abbas NULL, 1278ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 128a0a62497SFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129a0a62497SFaiz Abbas NULL, 130a0a62497SFaiz Abbas MMC_CAP_UHS_DDR50}, 131a0a62497SFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132a0a62497SFaiz Abbas "ti,itap-del-sel-ddr52", 133a0a62497SFaiz Abbas MMC_CAP_DDR}, 134a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135a0a62497SFaiz Abbas NULL, 136a0a62497SFaiz Abbas MMC_CAP2_HS200}, 137a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138a0a62497SFaiz Abbas NULL, 139a0a62497SFaiz Abbas MMC_CAP2_HS400}, 1408ee5fc0eSFaiz Abbas }; 1418ee5fc0eSFaiz Abbas 1421e753dbbSFaiz Abbas struct sdhci_am654_data { 1431e753dbbSFaiz Abbas struct regmap *base; 1441e753dbbSFaiz Abbas int otap_del_sel[ARRAY_SIZE(td)]; 145a0a62497SFaiz Abbas int itap_del_sel[ARRAY_SIZE(td)]; 1463433a340SJudith Mendez u32 itap_del_ena[ARRAY_SIZE(td)]; 1471e753dbbSFaiz Abbas int clkbuf_sel; 1481e753dbbSFaiz Abbas int trm_icp; 1491e753dbbSFaiz Abbas int drv_strength; 1501e753dbbSFaiz Abbas int strb_sel; 1511e753dbbSFaiz Abbas u32 flags; 152c7666240SVignesh Raghavendra u32 quirks; 15357205cf9SJudith Mendez bool dll_enable; 154c7666240SVignesh Raghavendra 155c7666240SVignesh Raghavendra #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 1561e753dbbSFaiz Abbas }; 1571e753dbbSFaiz Abbas 15857205cf9SJudith Mendez struct window { 15957205cf9SJudith Mendez u8 start; 16057205cf9SJudith Mendez u8 end; 16157205cf9SJudith Mendez u8 length; 16257205cf9SJudith Mendez }; 16357205cf9SJudith Mendez 1641e753dbbSFaiz Abbas struct sdhci_am654_driver_data { 1651e753dbbSFaiz Abbas const struct sdhci_pltfm_data *pdata; 1661e753dbbSFaiz Abbas u32 flags; 1671e753dbbSFaiz Abbas #define IOMUX_PRESENT (1 << 0) 1681e753dbbSFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 1691e753dbbSFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 1701e753dbbSFaiz Abbas #define DLL_PRESENT (1 << 3) 1711e753dbbSFaiz Abbas #define DLL_CALIB (1 << 4) 1721e753dbbSFaiz Abbas }; 1731e753dbbSFaiz Abbas 174a161c45fSFaiz Abbas static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 175a161c45fSFaiz Abbas { 176a161c45fSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177a161c45fSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 178a161c45fSFaiz Abbas int sel50, sel100, freqsel; 179a161c45fSFaiz Abbas u32 mask, val; 180a161c45fSFaiz Abbas int ret; 181a161c45fSFaiz Abbas 182a0a62497SFaiz Abbas /* Disable delay chain mode */ 183a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 184a0a62497SFaiz Abbas SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 185a0a62497SFaiz Abbas 186a161c45fSFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 187a161c45fSFaiz Abbas switch (clock) { 188a161c45fSFaiz Abbas case 200000000: 189a161c45fSFaiz Abbas sel50 = 0; 190a161c45fSFaiz Abbas sel100 = 0; 191a161c45fSFaiz Abbas break; 192a161c45fSFaiz Abbas case 100000000: 193a161c45fSFaiz Abbas sel50 = 0; 194a161c45fSFaiz Abbas sel100 = 1; 195a161c45fSFaiz Abbas break; 196a161c45fSFaiz Abbas default: 197a161c45fSFaiz Abbas sel50 = 1; 198a161c45fSFaiz Abbas sel100 = 0; 199a161c45fSFaiz Abbas } 200a161c45fSFaiz Abbas 201a161c45fSFaiz Abbas /* Configure PHY DLL frequency */ 202a161c45fSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 203a161c45fSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 204a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 205a161c45fSFaiz Abbas 206a161c45fSFaiz Abbas } else { 207a161c45fSFaiz Abbas switch (clock) { 208a161c45fSFaiz Abbas case 200000000: 209a161c45fSFaiz Abbas freqsel = 0x0; 210a161c45fSFaiz Abbas break; 211a161c45fSFaiz Abbas default: 212a161c45fSFaiz Abbas freqsel = 0x4; 213a161c45fSFaiz Abbas } 214a161c45fSFaiz Abbas 215a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 216a161c45fSFaiz Abbas freqsel << FREQSEL_SHIFT); 217a161c45fSFaiz Abbas } 218a161c45fSFaiz Abbas /* Configure DLL TRIM */ 219a161c45fSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 220a161c45fSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 221a161c45fSFaiz Abbas 222a161c45fSFaiz Abbas /* Configure DLL driver strength */ 223a161c45fSFaiz Abbas mask |= DR_TY_MASK; 224a161c45fSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 225a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 226a161c45fSFaiz Abbas 227a161c45fSFaiz Abbas /* Enable DLL */ 228a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 229a161c45fSFaiz Abbas 0x1 << ENDLL_SHIFT); 230a161c45fSFaiz Abbas /* 231a161c45fSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 232a161c45fSFaiz Abbas * Works in all experiments done so far 233a161c45fSFaiz Abbas */ 234a161c45fSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 235a161c45fSFaiz Abbas val & DLLRDY_MASK, 1000, 1000000); 236a161c45fSFaiz Abbas if (ret) { 237a161c45fSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 238a161c45fSFaiz Abbas return; 239a161c45fSFaiz Abbas } 240a0a62497SFaiz Abbas } 241a161c45fSFaiz Abbas 242a0a62497SFaiz Abbas static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 2433433a340SJudith Mendez u32 itapdly, u32 enable) 244a0a62497SFaiz Abbas { 245a0a62497SFaiz Abbas /* Set ITAPCHGWIN before writing to ITAPDLY */ 246a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247a0a62497SFaiz Abbas 1 << ITAPCHGWIN_SHIFT); 2483433a340SJudith Mendez regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 2493433a340SJudith Mendez enable << ITAPDLYENA_SHIFT); 250a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 251a0a62497SFaiz Abbas itapdly << ITAPDLYSEL_SHIFT); 252a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 253a0a62497SFaiz Abbas } 254a0a62497SFaiz Abbas 255a0a62497SFaiz Abbas static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 256a0a62497SFaiz Abbas unsigned char timing) 257a0a62497SFaiz Abbas { 258a0a62497SFaiz Abbas u32 mask, val; 259a0a62497SFaiz Abbas 260a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 261a0a62497SFaiz Abbas 262a0a62497SFaiz Abbas val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 263a0a62497SFaiz Abbas mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 264a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 265a0a62497SFaiz Abbas 2663433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 2673433a340SJudith Mendez sdhci_am654->itap_del_ena[timing]); 268a161c45fSFaiz Abbas } 269a161c45fSFaiz Abbas 27041fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 27141fd4caeSFaiz Abbas { 27241fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 27341fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2748ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2758ee5fc0eSFaiz Abbas u32 otap_del_sel; 27641fd4caeSFaiz Abbas u32 mask, val; 27741fd4caeSFaiz Abbas 2788023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 27941fd4caeSFaiz Abbas 28041fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 28141fd4caeSFaiz Abbas 28241fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 2838ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 2848ee5fc0eSFaiz Abbas 2858ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2863433a340SJudith Mendez val = (0x1 << OTAPDLYENA_SHIFT) | 2878ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2888ee5fc0eSFaiz Abbas 2898ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 2908ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 2918ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 2928ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 2938ee5fc0eSFaiz Abbas else 2948ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 2958ee5fc0eSFaiz Abbas 2968ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 29799909b55SFaiz Abbas } 29899909b55SFaiz Abbas 2998ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3008ee5fc0eSFaiz Abbas 30157205cf9SJudith Mendez if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 302a161c45fSFaiz Abbas sdhci_am654_setup_dll(host, clock); 30357205cf9SJudith Mendez sdhci_am654->dll_enable = true; 3043433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 3053433a340SJudith Mendez sdhci_am654->itap_del_ena[timing]); 30657205cf9SJudith Mendez } else { 307a0a62497SFaiz Abbas sdhci_am654_setup_delay_chain(sdhci_am654, timing); 30857205cf9SJudith Mendez sdhci_am654->dll_enable = false; 30957205cf9SJudith Mendez } 31061d9c4aaSFaiz Abbas 31161d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 31261d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 31341fd4caeSFaiz Abbas } 31441fd4caeSFaiz Abbas 3158751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 3168751c8bdSYueHaibing unsigned int clock) 3171accbcedSFaiz Abbas { 3181accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3191accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 3208ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3218ee5fc0eSFaiz Abbas u32 otap_del_sel; 3223433a340SJudith Mendez u32 itap_del_ena; 3238ee5fc0eSFaiz Abbas u32 mask, val; 3248ee5fc0eSFaiz Abbas 3258ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 3268ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 3271accbcedSFaiz Abbas 3281accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3298ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 3308ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 3313433a340SJudith Mendez 3323433a340SJudith Mendez itap_del_ena = sdhci_am654->itap_del_ena[timing]; 3333433a340SJudith Mendez 3343433a340SJudith Mendez mask |= ITAPDLYENA_MASK; 3353433a340SJudith Mendez val |= (itap_del_ena << ITAPDLYENA_SHIFT); 3363433a340SJudith Mendez 3371accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3381accbcedSFaiz Abbas 33961d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 34061d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 34161d9c4aaSFaiz Abbas 3421accbcedSFaiz Abbas sdhci_set_clock(host, clock); 3431accbcedSFaiz Abbas } 3441accbcedSFaiz Abbas 3457ca0f166SFaiz Abbas static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 3467ca0f166SFaiz Abbas { 3477ca0f166SFaiz Abbas writeb(val, host->ioaddr + reg); 3487ca0f166SFaiz Abbas usleep_range(1000, 10000); 3497ca0f166SFaiz Abbas return readb(host->ioaddr + reg); 3507ca0f166SFaiz Abbas } 3517ca0f166SFaiz Abbas 3527ca0f166SFaiz Abbas #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 353e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 354e374e875SFaiz Abbas { 355e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3567ca0f166SFaiz Abbas u8 pwr; 3577ca0f166SFaiz Abbas int ret; 358e374e875SFaiz Abbas 359e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 360e374e875SFaiz Abbas switch (timing) { 361e374e875SFaiz Abbas /* 362e374e875SFaiz Abbas * According to the data manual, HISPD bit 363e374e875SFaiz Abbas * should not be set in these speed modes. 364e374e875SFaiz Abbas */ 365e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 366e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 367e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 368e374e875SFaiz Abbas } 369e374e875SFaiz Abbas } 370e374e875SFaiz Abbas 371e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 3727ca0f166SFaiz Abbas if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 3737ca0f166SFaiz Abbas /* 3747ca0f166SFaiz Abbas * Power on will not happen until the card detect debounce 3757ca0f166SFaiz Abbas * timer expires. Wait at least 1.5 seconds for the power on 3767ca0f166SFaiz Abbas * bit to be set 3777ca0f166SFaiz Abbas */ 3787ca0f166SFaiz Abbas ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 3797ca0f166SFaiz Abbas pwr & SDHCI_POWER_ON, 0, 3807ca0f166SFaiz Abbas MAX_POWER_ON_TIMEOUT, false, host, val, 3817ca0f166SFaiz Abbas reg); 3827ca0f166SFaiz Abbas if (ret) 38311440da7SFrancesco Dolcini dev_info(mmc_dev(host->mmc), "Power on failed\n"); 3847ca0f166SFaiz Abbas } 385e374e875SFaiz Abbas } 386e374e875SFaiz Abbas 387c7666240SVignesh Raghavendra static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 388c7666240SVignesh Raghavendra { 389c7666240SVignesh Raghavendra u8 ctrl; 390c7666240SVignesh Raghavendra struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 391c7666240SVignesh Raghavendra struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 392c7666240SVignesh Raghavendra 393162503fdSBrian Norris sdhci_and_cqhci_reset(host, mask); 394c7666240SVignesh Raghavendra 395c7666240SVignesh Raghavendra if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 396c7666240SVignesh Raghavendra ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 397c7666240SVignesh Raghavendra ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 398c7666240SVignesh Raghavendra sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 399c7666240SVignesh Raghavendra } 400c7666240SVignesh Raghavendra } 401c7666240SVignesh Raghavendra 402de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 403de31f6abSFaiz Abbas { 404de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 405de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 40641fd4caeSFaiz Abbas 407de31f6abSFaiz Abbas if (err) 408de31f6abSFaiz Abbas return err; 409de31f6abSFaiz Abbas /* 410de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 411de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 412de31f6abSFaiz Abbas */ 413de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 41441fd4caeSFaiz Abbas 415de31f6abSFaiz Abbas return 0; 416de31f6abSFaiz Abbas } 41799909b55SFaiz Abbas 418f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 419f545702bSFaiz Abbas { 420f545702bSFaiz Abbas int cmd_error = 0; 421f545702bSFaiz Abbas int data_error = 0; 422f545702bSFaiz Abbas 423f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 424f545702bSFaiz Abbas return intmask; 425f545702bSFaiz Abbas 426f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 427f545702bSFaiz Abbas 428f545702bSFaiz Abbas return 0; 429f545702bSFaiz Abbas } 430f545702bSFaiz Abbas 43157205cf9SJudith Mendez #define ITAPDLY_LENGTH 32 43257205cf9SJudith Mendez #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 43357205cf9SJudith Mendez 43457205cf9SJudith Mendez static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 43557205cf9SJudith Mendez *fail_window, u8 num_fails, bool circular_buffer) 43657205cf9SJudith Mendez { 43757205cf9SJudith Mendez u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 43857205cf9SJudith Mendez u8 first_fail_start = 0, last_fail_end = 0; 43957205cf9SJudith Mendez struct device *dev = mmc_dev(host->mmc); 44057205cf9SJudith Mendez struct window pass_window = {0, 0, 0}; 44157205cf9SJudith Mendez int prev_fail_end = -1; 44257205cf9SJudith Mendez u8 i; 44357205cf9SJudith Mendez 44457205cf9SJudith Mendez if (!num_fails) 44557205cf9SJudith Mendez return ITAPDLY_LAST_INDEX >> 1; 44657205cf9SJudith Mendez 44757205cf9SJudith Mendez if (fail_window->length == ITAPDLY_LENGTH) { 44857205cf9SJudith Mendez dev_err(dev, "No passing ITAPDLY, return 0\n"); 44957205cf9SJudith Mendez return 0; 45057205cf9SJudith Mendez } 45157205cf9SJudith Mendez 45257205cf9SJudith Mendez first_fail_start = fail_window->start; 45357205cf9SJudith Mendez last_fail_end = fail_window[num_fails - 1].end; 45457205cf9SJudith Mendez 45557205cf9SJudith Mendez for (i = 0; i < num_fails; i++) { 45657205cf9SJudith Mendez start_fail = fail_window[i].start; 45757205cf9SJudith Mendez end_fail = fail_window[i].end; 45857205cf9SJudith Mendez pass_length = start_fail - (prev_fail_end + 1); 45957205cf9SJudith Mendez 46057205cf9SJudith Mendez if (pass_length > pass_window.length) { 46157205cf9SJudith Mendez pass_window.start = prev_fail_end + 1; 46257205cf9SJudith Mendez pass_window.length = pass_length; 46357205cf9SJudith Mendez } 46457205cf9SJudith Mendez prev_fail_end = end_fail; 46557205cf9SJudith Mendez } 46657205cf9SJudith Mendez 46757205cf9SJudith Mendez if (!circular_buffer) 46857205cf9SJudith Mendez pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 46957205cf9SJudith Mendez else 47057205cf9SJudith Mendez pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 47157205cf9SJudith Mendez 47257205cf9SJudith Mendez if (pass_length > pass_window.length) { 47357205cf9SJudith Mendez pass_window.start = last_fail_end + 1; 47457205cf9SJudith Mendez pass_window.length = pass_length; 47557205cf9SJudith Mendez } 47657205cf9SJudith Mendez 47757205cf9SJudith Mendez if (!circular_buffer) 47857205cf9SJudith Mendez itap = pass_window.start + (pass_window.length >> 1); 47957205cf9SJudith Mendez else 48057205cf9SJudith Mendez itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 48157205cf9SJudith Mendez 48257205cf9SJudith Mendez return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 48357205cf9SJudith Mendez } 48457205cf9SJudith Mendez 48513ebeae6SFaiz Abbas static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 48613ebeae6SFaiz Abbas u32 opcode) 48713ebeae6SFaiz Abbas { 48813ebeae6SFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 48913ebeae6SFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 4903433a340SJudith Mendez unsigned char timing = host->mmc->ios.timing; 49157205cf9SJudith Mendez struct window fail_window[ITAPDLY_LENGTH]; 49257205cf9SJudith Mendez u8 curr_pass, itap; 49357205cf9SJudith Mendez u8 fail_index = 0; 49457205cf9SJudith Mendez u8 prev_pass = 1; 49557205cf9SJudith Mendez 49657205cf9SJudith Mendez memset(fail_window, 0, sizeof(fail_window)); 49713ebeae6SFaiz Abbas 49813ebeae6SFaiz Abbas /* Enable ITAPDLY */ 4993433a340SJudith Mendez sdhci_am654->itap_del_ena[timing] = 0x1; 50013ebeae6SFaiz Abbas 50157205cf9SJudith Mendez for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 5023433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 50313ebeae6SFaiz Abbas 50457205cf9SJudith Mendez curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 50513ebeae6SFaiz Abbas 50657205cf9SJudith Mendez if (!curr_pass && prev_pass) 50757205cf9SJudith Mendez fail_window[fail_index].start = itap; 50813ebeae6SFaiz Abbas 50957205cf9SJudith Mendez if (!curr_pass) { 51057205cf9SJudith Mendez fail_window[fail_index].end = itap; 51157205cf9SJudith Mendez fail_window[fail_index].length++; 51213ebeae6SFaiz Abbas } 51357205cf9SJudith Mendez 51457205cf9SJudith Mendez if (curr_pass && !prev_pass) 51557205cf9SJudith Mendez fail_index++; 51657205cf9SJudith Mendez 51757205cf9SJudith Mendez prev_pass = curr_pass; 51857205cf9SJudith Mendez } 51957205cf9SJudith Mendez 52057205cf9SJudith Mendez if (fail_window[fail_index].length != 0) 52157205cf9SJudith Mendez fail_index++; 52257205cf9SJudith Mendez 52357205cf9SJudith Mendez itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 52457205cf9SJudith Mendez sdhci_am654->dll_enable); 52557205cf9SJudith Mendez 5263433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 52713ebeae6SFaiz Abbas 52813ebeae6SFaiz Abbas return 0; 52913ebeae6SFaiz Abbas } 53013ebeae6SFaiz Abbas 53141fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 53213ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 53341fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 53441fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 53541fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 53641fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5379d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 53841fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 53941fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 54027f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 541162503fdSBrian Norris .reset = sdhci_and_cqhci_reset, 54241fd4caeSFaiz Abbas }; 54341fd4caeSFaiz Abbas 54441fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 54541fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 5464d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 54741fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 54841fd4caeSFaiz Abbas }; 54941fd4caeSFaiz Abbas 55009db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 55141fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 55223514731SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 55323514731SFaiz Abbas DLL_CALIB, 55441fd4caeSFaiz Abbas }; 55541fd4caeSFaiz Abbas 55609db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 55709db9943SFaiz Abbas .pdata = &sdhci_am654_pdata, 55809db9943SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 55909db9943SFaiz Abbas }; 56009db9943SFaiz Abbas 5618751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 56213ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 56399909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 56499909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 56599909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 56699909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5679d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 56899909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 56999909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 570f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 571162503fdSBrian Norris .reset = sdhci_and_cqhci_reset, 57299909b55SFaiz Abbas }; 57399909b55SFaiz Abbas 57499909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 57599909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 5764d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 57799909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 57899909b55SFaiz Abbas }; 57999909b55SFaiz Abbas 58099909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 58199909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 58223514731SFaiz Abbas .flags = DLL_PRESENT | DLL_CALIB, 58399909b55SFaiz Abbas }; 58499909b55SFaiz Abbas 5858751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 58613ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 5871accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 5881accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 5891accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 5901accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5919d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 5921accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 5931accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 594f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 595c7666240SVignesh Raghavendra .reset = sdhci_am654_reset, 5961accbcedSFaiz Abbas }; 5971accbcedSFaiz Abbas 5981accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 5991accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 6004d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 6011accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 6021accbcedSFaiz Abbas }; 6031accbcedSFaiz Abbas 6041accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 6051accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 6061accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 6071accbcedSFaiz Abbas }; 608f545702bSFaiz Abbas 60909db9943SFaiz Abbas static const struct soc_device_attribute sdhci_am654_devices[] = { 61009db9943SFaiz Abbas { .family = "AM65X", 61109db9943SFaiz Abbas .revision = "SR1.0", 61209db9943SFaiz Abbas .data = &sdhci_am654_sr1_drvdata 61309db9943SFaiz Abbas }, 61409db9943SFaiz Abbas {/* sentinel */} 61509db9943SFaiz Abbas }; 61609db9943SFaiz Abbas 617f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 618f545702bSFaiz Abbas { 619f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 620f545702bSFaiz Abbas } 621f545702bSFaiz Abbas 622f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 623f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 624f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 625f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 626f545702bSFaiz Abbas }; 627f545702bSFaiz Abbas 628f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 629f545702bSFaiz Abbas { 630f545702bSFaiz Abbas struct cqhci_host *cq_host; 631f545702bSFaiz Abbas 632bac53336SJisheng Zhang cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 633f545702bSFaiz Abbas GFP_KERNEL); 634f545702bSFaiz Abbas if (!cq_host) 635f545702bSFaiz Abbas return -ENOMEM; 636f545702bSFaiz Abbas 637f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 638f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 639f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 640f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 641f545702bSFaiz Abbas 642f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 643f545702bSFaiz Abbas 644c0470f43Sye xingchen return cqhci_init(cq_host, host->mmc, 1); 645f545702bSFaiz Abbas } 646f545702bSFaiz Abbas 6478ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 6488ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 6498ee5fc0eSFaiz Abbas { 6508ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 6518ee5fc0eSFaiz Abbas int i; 6528ee5fc0eSFaiz Abbas int ret; 6538ee5fc0eSFaiz Abbas 65458220885SNitin Yadav for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 6558ee5fc0eSFaiz Abbas 656a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[i].otap_binding, 6578ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 6588ee5fc0eSFaiz Abbas if (ret) { 6593525baf3SVignesh Raghavendra if (i == MMC_TIMING_LEGACY) { 6603525baf3SVignesh Raghavendra dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); 6613525baf3SVignesh Raghavendra return ret; 6623525baf3SVignesh Raghavendra } 6638ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 664a0a62497SFaiz Abbas td[i].otap_binding); 6658ee5fc0eSFaiz Abbas /* 6668ee5fc0eSFaiz Abbas * Remove the corresponding capability 6678ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 6688ee5fc0eSFaiz Abbas */ 6698ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 6708ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 6718ee5fc0eSFaiz Abbas else 6728ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 6738ee5fc0eSFaiz Abbas } 674a0a62497SFaiz Abbas 6753433a340SJudith Mendez if (td[i].itap_binding) { 6763433a340SJudith Mendez ret = device_property_read_u32(dev, td[i].itap_binding, 677a0a62497SFaiz Abbas &sdhci_am654->itap_del_sel[i]); 6783433a340SJudith Mendez if (!ret) 6793433a340SJudith Mendez sdhci_am654->itap_del_ena[i] = 0x1; 6803433a340SJudith Mendez } 6818ee5fc0eSFaiz Abbas } 6828ee5fc0eSFaiz Abbas 6838ee5fc0eSFaiz Abbas return 0; 6848ee5fc0eSFaiz Abbas } 6858ee5fc0eSFaiz Abbas 68641fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 68741fd4caeSFaiz Abbas { 68841fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 68941fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 69041fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 69141fd4caeSFaiz Abbas u32 mask; 69241fd4caeSFaiz Abbas u32 val; 69341fd4caeSFaiz Abbas int ret; 69441fd4caeSFaiz Abbas 69541fd4caeSFaiz Abbas /* Reset OTAP to default value */ 69641fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 6978023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 69841fd4caeSFaiz Abbas 69923514731SFaiz Abbas if (sdhci_am654->flags & DLL_CALIB) { 70041fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 70141fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 70241fd4caeSFaiz Abbas /* Calibrate IO lines */ 70341fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 70441fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 7051accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 7061accbcedSFaiz Abbas PHY_STAT1, val, 7071accbcedSFaiz Abbas val & CALDONE_MASK, 7081accbcedSFaiz Abbas 1, 20); 70941fd4caeSFaiz Abbas if (ret) 71041fd4caeSFaiz Abbas return ret; 71141fd4caeSFaiz Abbas } 7121accbcedSFaiz Abbas } 71341fd4caeSFaiz Abbas 71441fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 71599909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 71699909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 71799909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 71841fd4caeSFaiz Abbas 71941fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 72041fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 72141fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 72241fd4caeSFaiz Abbas 7238023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 7248023cf26SFaiz Abbas ctl_cfg_2); 72541fd4caeSFaiz Abbas 726764384d0SFaiz Abbas /* Enable tuning for SDR50 */ 727764384d0SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 728764384d0SFaiz Abbas TUNINGFORSDR50_MASK); 729764384d0SFaiz Abbas 730f545702bSFaiz Abbas ret = sdhci_setup_host(host); 731f545702bSFaiz Abbas if (ret) 732f545702bSFaiz Abbas return ret; 733f545702bSFaiz Abbas 734f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 735f545702bSFaiz Abbas if (ret) 736f545702bSFaiz Abbas goto err_cleanup_host; 737f545702bSFaiz Abbas 7388ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 7398ee5fc0eSFaiz Abbas if (ret) 7408ee5fc0eSFaiz Abbas goto err_cleanup_host; 7418ee5fc0eSFaiz Abbas 742f545702bSFaiz Abbas ret = __sdhci_add_host(host); 743f545702bSFaiz Abbas if (ret) 744f545702bSFaiz Abbas goto err_cleanup_host; 745f545702bSFaiz Abbas 746f545702bSFaiz Abbas return 0; 747f545702bSFaiz Abbas 748f545702bSFaiz Abbas err_cleanup_host: 749f545702bSFaiz Abbas sdhci_cleanup_host(host); 750f545702bSFaiz Abbas return ret; 75141fd4caeSFaiz Abbas } 75241fd4caeSFaiz Abbas 75341fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 75441fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 75541fd4caeSFaiz Abbas { 75641fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 75741fd4caeSFaiz Abbas int drv_strength; 75841fd4caeSFaiz Abbas int ret; 75941fd4caeSFaiz Abbas 7601accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 7611accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 7621accbcedSFaiz Abbas &sdhci_am654->trm_icp); 76341fd4caeSFaiz Abbas if (ret) 76441fd4caeSFaiz Abbas return ret; 76541fd4caeSFaiz Abbas 76641fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 76741fd4caeSFaiz Abbas &drv_strength); 76841fd4caeSFaiz Abbas if (ret) 76941fd4caeSFaiz Abbas return ret; 77041fd4caeSFaiz Abbas 77141fd4caeSFaiz Abbas switch (drv_strength) { 77241fd4caeSFaiz Abbas case 50: 77341fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 77441fd4caeSFaiz Abbas break; 77541fd4caeSFaiz Abbas case 33: 77641fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 77741fd4caeSFaiz Abbas break; 77841fd4caeSFaiz Abbas case 66: 77941fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 78041fd4caeSFaiz Abbas break; 78141fd4caeSFaiz Abbas case 100: 78241fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 78341fd4caeSFaiz Abbas break; 78441fd4caeSFaiz Abbas case 40: 78541fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 78641fd4caeSFaiz Abbas break; 78741fd4caeSFaiz Abbas default: 78841fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 78941fd4caeSFaiz Abbas return -EINVAL; 79041fd4caeSFaiz Abbas } 7911accbcedSFaiz Abbas } 79241fd4caeSFaiz Abbas 79399909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 79461d9c4aaSFaiz Abbas device_property_read_u32(dev, "ti,clkbuf-sel", 79561d9c4aaSFaiz Abbas &sdhci_am654->clkbuf_sel); 79699909b55SFaiz Abbas 797c7666240SVignesh Raghavendra if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 798c7666240SVignesh Raghavendra sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 799c7666240SVignesh Raghavendra 80041fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 80141fd4caeSFaiz Abbas 80241fd4caeSFaiz Abbas return 0; 80341fd4caeSFaiz Abbas } 80441fd4caeSFaiz Abbas 80599909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 80699909b55SFaiz Abbas { 80799909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 80899909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 80999909b55SFaiz Abbas }, 81099909b55SFaiz Abbas { 81199909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 81299909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 81399909b55SFaiz Abbas }, 8141accbcedSFaiz Abbas { 8151accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 8161accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 8171accbcedSFaiz Abbas }, 818754b7f2fSFaiz Abbas { 819754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-8bit", 8203b7340f1SAswath Govindraju .data = &sdhci_j721e_8bit_drvdata, 821754b7f2fSFaiz Abbas }, 822754b7f2fSFaiz Abbas { 823754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-4bit", 8243b7340f1SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 825754b7f2fSFaiz Abbas }, 82602538e45SAswath Govindraju { 82702538e45SAswath Govindraju .compatible = "ti,am62-sdhci", 82802538e45SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 82902538e45SAswath Govindraju }, 83099909b55SFaiz Abbas { /* sentinel */ } 83199909b55SFaiz Abbas }; 8321e23400fSFaiz Abbas MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 83399909b55SFaiz Abbas 83441fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 83541fd4caeSFaiz Abbas { 83699909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 83709db9943SFaiz Abbas const struct soc_device_attribute *soc; 83841fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 83941fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 84099909b55SFaiz Abbas const struct of_device_id *match; 84141fd4caeSFaiz Abbas struct sdhci_host *host; 84241fd4caeSFaiz Abbas struct clk *clk_xin; 84341fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 84441fd4caeSFaiz Abbas void __iomem *base; 84541fd4caeSFaiz Abbas int ret; 84641fd4caeSFaiz Abbas 84799909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 84899909b55SFaiz Abbas drvdata = match->data; 84909db9943SFaiz Abbas 85009db9943SFaiz Abbas /* Update drvdata based on SoC revision */ 85109db9943SFaiz Abbas soc = soc_device_match(sdhci_am654_devices); 85209db9943SFaiz Abbas if (soc && soc->data) 85309db9943SFaiz Abbas drvdata = soc->data; 85409db9943SFaiz Abbas 85599909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 85641fd4caeSFaiz Abbas if (IS_ERR(host)) 85741fd4caeSFaiz Abbas return PTR_ERR(host); 85841fd4caeSFaiz Abbas 85941fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 86041fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 86199909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 86241fd4caeSFaiz Abbas 86341fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 86441fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 86541fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 86641fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 86741fd4caeSFaiz Abbas goto err_pltfm_free; 86841fd4caeSFaiz Abbas } 86941fd4caeSFaiz Abbas 87041fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 87141fd4caeSFaiz Abbas 8724942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 87341fd4caeSFaiz Abbas if (IS_ERR(base)) { 87441fd4caeSFaiz Abbas ret = PTR_ERR(base); 8759d2e77ffSAswath Govindraju goto err_pltfm_free; 87641fd4caeSFaiz Abbas } 87741fd4caeSFaiz Abbas 87841fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 87941fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 88041fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 88141fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 88241fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 8839d2e77ffSAswath Govindraju goto err_pltfm_free; 88441fd4caeSFaiz Abbas } 88541fd4caeSFaiz Abbas 88641fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 88741fd4caeSFaiz Abbas if (ret) 8889d2e77ffSAswath Govindraju goto err_pltfm_free; 88941fd4caeSFaiz Abbas 89041fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 89141fd4caeSFaiz Abbas if (ret) { 892654993b3SMatthias Schiffer dev_err_probe(dev, ret, "parsing dt failed\n"); 8939d2e77ffSAswath Govindraju goto err_pltfm_free; 89441fd4caeSFaiz Abbas } 89541fd4caeSFaiz Abbas 896de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 897de31f6abSFaiz Abbas 8989d2e77ffSAswath Govindraju pm_runtime_get_noresume(dev); 8999d2e77ffSAswath Govindraju ret = pm_runtime_set_active(dev); 9009d2e77ffSAswath Govindraju if (ret) 9019d2e77ffSAswath Govindraju goto pm_put; 9029d2e77ffSAswath Govindraju pm_runtime_enable(dev); 9039d2e77ffSAswath Govindraju ret = clk_prepare_enable(pltfm_host->clk); 9049d2e77ffSAswath Govindraju if (ret) 9059d2e77ffSAswath Govindraju goto pm_disable; 9069d2e77ffSAswath Govindraju 90741fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 90841fd4caeSFaiz Abbas if (ret) 9099d2e77ffSAswath Govindraju goto clk_disable; 91041fd4caeSFaiz Abbas 9119d2e77ffSAswath Govindraju /* Setting up autosuspend */ 9129d2e77ffSAswath Govindraju pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 9139d2e77ffSAswath Govindraju pm_runtime_use_autosuspend(dev); 9149d2e77ffSAswath Govindraju pm_runtime_mark_last_busy(dev); 9159d2e77ffSAswath Govindraju pm_runtime_put_autosuspend(dev); 91641fd4caeSFaiz Abbas return 0; 91741fd4caeSFaiz Abbas 9189d2e77ffSAswath Govindraju clk_disable: 9199d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 9209d2e77ffSAswath Govindraju pm_disable: 92141fd4caeSFaiz Abbas pm_runtime_disable(dev); 9229d2e77ffSAswath Govindraju pm_put: 9239d2e77ffSAswath Govindraju pm_runtime_put_noidle(dev); 92441fd4caeSFaiz Abbas err_pltfm_free: 92541fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 92641fd4caeSFaiz Abbas return ret; 92741fd4caeSFaiz Abbas } 92841fd4caeSFaiz Abbas 929de29ade4SYangtao Li static void sdhci_am654_remove(struct platform_device *pdev) 93041fd4caeSFaiz Abbas { 93141fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 9329d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 933854034e2SYangtao Li struct device *dev = &pdev->dev; 93441fd4caeSFaiz Abbas int ret; 93541fd4caeSFaiz Abbas 936854034e2SYangtao Li ret = pm_runtime_get_sync(dev); 93741fd4caeSFaiz Abbas if (ret < 0) 938854034e2SYangtao Li dev_err(dev, "pm_runtime_get_sync() Failed\n"); 93941fd4caeSFaiz Abbas 9409d2e77ffSAswath Govindraju sdhci_remove_host(host, true); 9419d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 942854034e2SYangtao Li pm_runtime_disable(dev); 943854034e2SYangtao Li pm_runtime_put_noidle(dev); 94441fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 9459d2e77ffSAswath Govindraju } 9469d2e77ffSAswath Govindraju 9479d2e77ffSAswath Govindraju #ifdef CONFIG_PM 9489d2e77ffSAswath Govindraju static int sdhci_am654_restore(struct sdhci_host *host) 9499d2e77ffSAswath Govindraju { 9509d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 9519d2e77ffSAswath Govindraju struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 9529d2e77ffSAswath Govindraju u32 ctl_cfg_2 = 0; 9539d2e77ffSAswath Govindraju u32 val; 9549d2e77ffSAswath Govindraju int ret; 9559d2e77ffSAswath Govindraju 9569d2e77ffSAswath Govindraju if (sdhci_am654->flags & DLL_CALIB) { 9579d2e77ffSAswath Govindraju regmap_read(sdhci_am654->base, PHY_STAT1, &val); 9589d2e77ffSAswath Govindraju if (~val & CALDONE_MASK) { 9599d2e77ffSAswath Govindraju /* Calibrate IO lines */ 9609d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 9619d2e77ffSAswath Govindraju PDB_MASK, PDB_MASK); 9629d2e77ffSAswath Govindraju ret = regmap_read_poll_timeout(sdhci_am654->base, 9639d2e77ffSAswath Govindraju PHY_STAT1, val, 9649d2e77ffSAswath Govindraju val & CALDONE_MASK, 9659d2e77ffSAswath Govindraju 1, 20); 9669d2e77ffSAswath Govindraju if (ret) 9679d2e77ffSAswath Govindraju return ret; 9689d2e77ffSAswath Govindraju } 9699d2e77ffSAswath Govindraju } 9709d2e77ffSAswath Govindraju 9719d2e77ffSAswath Govindraju /* Enable pins by setting IO mux to 0 */ 9729d2e77ffSAswath Govindraju if (sdhci_am654->flags & IOMUX_PRESENT) 9739d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 9749d2e77ffSAswath Govindraju IOMUX_ENABLE_MASK, 0); 9759d2e77ffSAswath Govindraju 9769d2e77ffSAswath Govindraju /* Set slot type based on SD or eMMC */ 9779d2e77ffSAswath Govindraju if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 9789d2e77ffSAswath Govindraju ctl_cfg_2 = SLOTTYPE_EMBEDDED; 9799d2e77ffSAswath Govindraju 9809d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 9819d2e77ffSAswath Govindraju ctl_cfg_2); 9829d2e77ffSAswath Govindraju 9839d2e77ffSAswath Govindraju regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 9849d2e77ffSAswath Govindraju if (~val & TUNINGFORSDR50_MASK) 9859d2e77ffSAswath Govindraju /* Enable tuning for SDR50 */ 9869d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 9879d2e77ffSAswath Govindraju TUNINGFORSDR50_MASK); 98841fd4caeSFaiz Abbas 98941fd4caeSFaiz Abbas return 0; 99041fd4caeSFaiz Abbas } 99141fd4caeSFaiz Abbas 9929d2e77ffSAswath Govindraju static int sdhci_am654_runtime_suspend(struct device *dev) 9939d2e77ffSAswath Govindraju { 9949d2e77ffSAswath Govindraju struct sdhci_host *host = dev_get_drvdata(dev); 9959d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 9969d2e77ffSAswath Govindraju int ret; 9979d2e77ffSAswath Govindraju 9989d2e77ffSAswath Govindraju if (host->tuning_mode != SDHCI_TUNING_MODE_3) 9999d2e77ffSAswath Govindraju mmc_retune_needed(host->mmc); 10009d2e77ffSAswath Govindraju 10019d2e77ffSAswath Govindraju ret = cqhci_suspend(host->mmc); 10029d2e77ffSAswath Govindraju if (ret) 10039d2e77ffSAswath Govindraju return ret; 10049d2e77ffSAswath Govindraju 10059d2e77ffSAswath Govindraju ret = sdhci_runtime_suspend_host(host); 10069d2e77ffSAswath Govindraju if (ret) 10079d2e77ffSAswath Govindraju return ret; 10089d2e77ffSAswath Govindraju 10099d2e77ffSAswath Govindraju /* disable the clock */ 10109d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 10119d2e77ffSAswath Govindraju return 0; 10129d2e77ffSAswath Govindraju } 10139d2e77ffSAswath Govindraju 10149d2e77ffSAswath Govindraju static int sdhci_am654_runtime_resume(struct device *dev) 10159d2e77ffSAswath Govindraju { 10169d2e77ffSAswath Govindraju struct sdhci_host *host = dev_get_drvdata(dev); 10179d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10189d2e77ffSAswath Govindraju int ret; 10199d2e77ffSAswath Govindraju 10209d2e77ffSAswath Govindraju /* Enable the clock */ 10219d2e77ffSAswath Govindraju ret = clk_prepare_enable(pltfm_host->clk); 10229d2e77ffSAswath Govindraju if (ret) 10239d2e77ffSAswath Govindraju return ret; 10249d2e77ffSAswath Govindraju 10259d2e77ffSAswath Govindraju ret = sdhci_am654_restore(host); 10269d2e77ffSAswath Govindraju if (ret) 10279d2e77ffSAswath Govindraju return ret; 10289d2e77ffSAswath Govindraju 10299d2e77ffSAswath Govindraju ret = sdhci_runtime_resume_host(host, 0); 10309d2e77ffSAswath Govindraju if (ret) 10319d2e77ffSAswath Govindraju return ret; 10329d2e77ffSAswath Govindraju 10339d2e77ffSAswath Govindraju ret = cqhci_resume(host->mmc); 10349d2e77ffSAswath Govindraju if (ret) 10359d2e77ffSAswath Govindraju return ret; 10369d2e77ffSAswath Govindraju 10379d2e77ffSAswath Govindraju return 0; 10389d2e77ffSAswath Govindraju } 10399d2e77ffSAswath Govindraju #endif 10409d2e77ffSAswath Govindraju 10419d2e77ffSAswath Govindraju static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 10429d2e77ffSAswath Govindraju SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 10439d2e77ffSAswath Govindraju sdhci_am654_runtime_resume, NULL) 10449d2e77ffSAswath Govindraju SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 10459d2e77ffSAswath Govindraju pm_runtime_force_resume) 10469d2e77ffSAswath Govindraju }; 10479d2e77ffSAswath Govindraju 104841fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 104941fd4caeSFaiz Abbas .driver = { 105041fd4caeSFaiz Abbas .name = "sdhci-am654", 1051d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 10529d2e77ffSAswath Govindraju .pm = &sdhci_am654_dev_pm_ops, 105341fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 105441fd4caeSFaiz Abbas }, 105541fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 1056de29ade4SYangtao Li .remove_new = sdhci_am654_remove, 105741fd4caeSFaiz Abbas }; 105841fd4caeSFaiz Abbas 105941fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 106041fd4caeSFaiz Abbas 106141fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 106241fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 106341fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 1064