141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 59481b45cSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 97ca0f166SFaiz Abbas #include <linux/iopoll.h> 1099909b55SFaiz Abbas #include <linux/of.h> 1141fd4caeSFaiz Abbas #include <linux/module.h> 1241fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1341fd4caeSFaiz Abbas #include <linux/property.h> 1441fd4caeSFaiz Abbas #include <linux/regmap.h> 1509db9943SFaiz Abbas #include <linux/sys_soc.h> 1641fd4caeSFaiz Abbas 17f545702bSFaiz Abbas #include "cqhci.h" 18162503fdSBrian Norris #include "sdhci-cqhci.h" 1941fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 2041fd4caeSFaiz Abbas 2141fd4caeSFaiz Abbas /* CTL_CFG Registers */ 2241fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 23764384d0SFaiz Abbas #define CTL_CFG_3 0x18 2441fd4caeSFaiz Abbas 2541fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2641fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 27764384d0SFaiz Abbas #define TUNINGFORSDR50_MASK BIT(13) 2841fd4caeSFaiz Abbas 2941fd4caeSFaiz Abbas /* PHY Registers */ 3041fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 3141fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 3241fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 3341fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 3441fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3541fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3641fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3741fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3841fd4caeSFaiz Abbas 3941fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 4041fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 4141fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 4241fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 4341fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 4441fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4541fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4699909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4799909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4841fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4941fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 5041fd4caeSFaiz Abbas #define SEL100_SHIFT 9 5141fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 5299909b55SFaiz Abbas #define FREQSEL_SHIFT 8 5399909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 5461d9c4aaSFaiz Abbas #define CLKBUFSEL_SHIFT 0 5561d9c4aaSFaiz Abbas #define CLKBUFSEL_MASK GENMASK(2, 0) 5641fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5741fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5841fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5941fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 6041fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 6141fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 6241fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 6341fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 6441fd4caeSFaiz Abbas #define PDB_SHIFT 0 6541fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 6641fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6741fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6841fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6941fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 700003417dSFaiz Abbas #define SELDLYTXCLK_SHIFT 17 710003417dSFaiz Abbas #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72a0a62497SFaiz Abbas #define SELDLYRXCLK_SHIFT 16 73a0a62497SFaiz Abbas #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74a0a62497SFaiz Abbas #define ITAPDLYSEL_SHIFT 0 75a0a62497SFaiz Abbas #define ITAPDLYSEL_MASK GENMASK(4, 0) 76a0a62497SFaiz Abbas #define ITAPDLYENA_SHIFT 8 77a0a62497SFaiz Abbas #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78a0a62497SFaiz Abbas #define ITAPCHGWIN_SHIFT 9 79a0a62497SFaiz Abbas #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 8041fd4caeSFaiz Abbas 8141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 8241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 8341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 8441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 8541fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 8641fd4caeSFaiz Abbas 87a0a62497SFaiz Abbas #define CLOCK_TOO_SLOW_HZ 50000000 889d2e77ffSAswath Govindraju #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 8941fd4caeSFaiz Abbas 90f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 91f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92f545702bSFaiz Abbas 9341fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 9441fd4caeSFaiz Abbas .reg_bits = 32, 9541fd4caeSFaiz Abbas .val_bits = 32, 9641fd4caeSFaiz Abbas .reg_stride = 4, 9741fd4caeSFaiz Abbas .fast_io = true, 9841fd4caeSFaiz Abbas }; 9941fd4caeSFaiz Abbas 1008ee5fc0eSFaiz Abbas struct timing_data { 101a0a62497SFaiz Abbas const char *otap_binding; 102a0a62497SFaiz Abbas const char *itap_binding; 1038ee5fc0eSFaiz Abbas u32 capability; 1048ee5fc0eSFaiz Abbas }; 1058ee5fc0eSFaiz Abbas 1068ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 107a0a62497SFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108a0a62497SFaiz Abbas "ti,itap-del-sel-legacy", 109a0a62497SFaiz Abbas 0}, 110a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111a0a62497SFaiz Abbas "ti,itap-del-sel-mmc-hs", 112a0a62497SFaiz Abbas MMC_CAP_MMC_HIGHSPEED}, 113a0a62497SFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114a0a62497SFaiz Abbas "ti,itap-del-sel-sd-hs", 115a0a62497SFaiz Abbas MMC_CAP_SD_HIGHSPEED}, 116a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117a0a62497SFaiz Abbas "ti,itap-del-sel-sdr12", 118a0a62497SFaiz Abbas MMC_CAP_UHS_SDR12}, 119a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120a0a62497SFaiz Abbas "ti,itap-del-sel-sdr25", 121a0a62497SFaiz Abbas MMC_CAP_UHS_SDR25}, 122a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123a0a62497SFaiz Abbas NULL, 124a0a62497SFaiz Abbas MMC_CAP_UHS_SDR50}, 1258ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126a0a62497SFaiz Abbas NULL, 1278ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 128a0a62497SFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129a0a62497SFaiz Abbas NULL, 130a0a62497SFaiz Abbas MMC_CAP_UHS_DDR50}, 131a0a62497SFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132a0a62497SFaiz Abbas "ti,itap-del-sel-ddr52", 133a0a62497SFaiz Abbas MMC_CAP_DDR}, 134a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135a0a62497SFaiz Abbas NULL, 136a0a62497SFaiz Abbas MMC_CAP2_HS200}, 137a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138a0a62497SFaiz Abbas NULL, 139a0a62497SFaiz Abbas MMC_CAP2_HS400}, 1408ee5fc0eSFaiz Abbas }; 1418ee5fc0eSFaiz Abbas 1421e753dbbSFaiz Abbas struct sdhci_am654_data { 1431e753dbbSFaiz Abbas struct regmap *base; 1441e753dbbSFaiz Abbas int otap_del_sel[ARRAY_SIZE(td)]; 145a0a62497SFaiz Abbas int itap_del_sel[ARRAY_SIZE(td)]; 1463433a340SJudith Mendez u32 itap_del_ena[ARRAY_SIZE(td)]; 1471e753dbbSFaiz Abbas int clkbuf_sel; 1481e753dbbSFaiz Abbas int trm_icp; 1491e753dbbSFaiz Abbas int drv_strength; 1501e753dbbSFaiz Abbas int strb_sel; 1511e753dbbSFaiz Abbas u32 flags; 152c7666240SVignesh Raghavendra u32 quirks; 15357205cf9SJudith Mendez bool dll_enable; 154c7666240SVignesh Raghavendra 155c7666240SVignesh Raghavendra #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 1561e753dbbSFaiz Abbas }; 1571e753dbbSFaiz Abbas 15857205cf9SJudith Mendez struct window { 15957205cf9SJudith Mendez u8 start; 16057205cf9SJudith Mendez u8 end; 16157205cf9SJudith Mendez u8 length; 16257205cf9SJudith Mendez }; 16357205cf9SJudith Mendez 1641e753dbbSFaiz Abbas struct sdhci_am654_driver_data { 1651e753dbbSFaiz Abbas const struct sdhci_pltfm_data *pdata; 1661e753dbbSFaiz Abbas u32 flags; 1671e753dbbSFaiz Abbas #define IOMUX_PRESENT (1 << 0) 1681e753dbbSFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 1691e753dbbSFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 1701e753dbbSFaiz Abbas #define DLL_PRESENT (1 << 3) 1711e753dbbSFaiz Abbas #define DLL_CALIB (1 << 4) 1721e753dbbSFaiz Abbas }; 1731e753dbbSFaiz Abbas 174a161c45fSFaiz Abbas static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 175a161c45fSFaiz Abbas { 176a161c45fSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177a161c45fSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 178a161c45fSFaiz Abbas int sel50, sel100, freqsel; 179a161c45fSFaiz Abbas u32 mask, val; 180a161c45fSFaiz Abbas int ret; 181a161c45fSFaiz Abbas 182a0a62497SFaiz Abbas /* Disable delay chain mode */ 183a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 184a0a62497SFaiz Abbas SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 185a0a62497SFaiz Abbas 186a161c45fSFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 187a161c45fSFaiz Abbas switch (clock) { 188a161c45fSFaiz Abbas case 200000000: 189a161c45fSFaiz Abbas sel50 = 0; 190a161c45fSFaiz Abbas sel100 = 0; 191a161c45fSFaiz Abbas break; 192a161c45fSFaiz Abbas case 100000000: 193a161c45fSFaiz Abbas sel50 = 0; 194a161c45fSFaiz Abbas sel100 = 1; 195a161c45fSFaiz Abbas break; 196a161c45fSFaiz Abbas default: 197a161c45fSFaiz Abbas sel50 = 1; 198a161c45fSFaiz Abbas sel100 = 0; 199a161c45fSFaiz Abbas } 200a161c45fSFaiz Abbas 201a161c45fSFaiz Abbas /* Configure PHY DLL frequency */ 202a161c45fSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 203a161c45fSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 204a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 205a161c45fSFaiz Abbas 206a161c45fSFaiz Abbas } else { 207a161c45fSFaiz Abbas switch (clock) { 208a161c45fSFaiz Abbas case 200000000: 209a161c45fSFaiz Abbas freqsel = 0x0; 210a161c45fSFaiz Abbas break; 211a161c45fSFaiz Abbas default: 212a161c45fSFaiz Abbas freqsel = 0x4; 213a161c45fSFaiz Abbas } 214a161c45fSFaiz Abbas 215a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 216a161c45fSFaiz Abbas freqsel << FREQSEL_SHIFT); 217a161c45fSFaiz Abbas } 218a161c45fSFaiz Abbas /* Configure DLL TRIM */ 219a161c45fSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 220a161c45fSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 221a161c45fSFaiz Abbas 222a161c45fSFaiz Abbas /* Configure DLL driver strength */ 223a161c45fSFaiz Abbas mask |= DR_TY_MASK; 224a161c45fSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 225a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 226a161c45fSFaiz Abbas 227a161c45fSFaiz Abbas /* Enable DLL */ 228a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 229a161c45fSFaiz Abbas 0x1 << ENDLL_SHIFT); 230a161c45fSFaiz Abbas /* 231a161c45fSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 232a161c45fSFaiz Abbas * Works in all experiments done so far 233a161c45fSFaiz Abbas */ 234a161c45fSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 235a161c45fSFaiz Abbas val & DLLRDY_MASK, 1000, 1000000); 236a161c45fSFaiz Abbas if (ret) { 237a161c45fSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 238a161c45fSFaiz Abbas return; 239a161c45fSFaiz Abbas } 240a0a62497SFaiz Abbas } 241a161c45fSFaiz Abbas 242a0a62497SFaiz Abbas static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 2433433a340SJudith Mendez u32 itapdly, u32 enable) 244a0a62497SFaiz Abbas { 245a0a62497SFaiz Abbas /* Set ITAPCHGWIN before writing to ITAPDLY */ 246a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247a0a62497SFaiz Abbas 1 << ITAPCHGWIN_SHIFT); 2483433a340SJudith Mendez regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 2493433a340SJudith Mendez enable << ITAPDLYENA_SHIFT); 250a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 251a0a62497SFaiz Abbas itapdly << ITAPDLYSEL_SHIFT); 252a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 253a0a62497SFaiz Abbas } 254a0a62497SFaiz Abbas 255a0a62497SFaiz Abbas static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 256a0a62497SFaiz Abbas unsigned char timing) 257a0a62497SFaiz Abbas { 258a0a62497SFaiz Abbas u32 mask, val; 259a0a62497SFaiz Abbas 260a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 261a0a62497SFaiz Abbas 262a0a62497SFaiz Abbas val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 263a0a62497SFaiz Abbas mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 264a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 265a0a62497SFaiz Abbas 2663433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 2673433a340SJudith Mendez sdhci_am654->itap_del_ena[timing]); 268a161c45fSFaiz Abbas } 269a161c45fSFaiz Abbas 27041fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 27141fd4caeSFaiz Abbas { 27241fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 27341fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2748ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2758ee5fc0eSFaiz Abbas u32 otap_del_sel; 27641fd4caeSFaiz Abbas u32 mask, val; 27741fd4caeSFaiz Abbas 2788023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 27941fd4caeSFaiz Abbas 28041fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 28141fd4caeSFaiz Abbas 28241fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 2838ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 2848ee5fc0eSFaiz Abbas 2858ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2863433a340SJudith Mendez val = (0x1 << OTAPDLYENA_SHIFT) | 2878ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2888ee5fc0eSFaiz Abbas 2898ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 2908ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 2918ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 2928ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 2938ee5fc0eSFaiz Abbas else 2948ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 2958ee5fc0eSFaiz Abbas 2968ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 29799909b55SFaiz Abbas } 29899909b55SFaiz Abbas 2998ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3008ee5fc0eSFaiz Abbas 30157205cf9SJudith Mendez if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 302a161c45fSFaiz Abbas sdhci_am654_setup_dll(host, clock); 30357205cf9SJudith Mendez sdhci_am654->dll_enable = true; 3043433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 3053433a340SJudith Mendez sdhci_am654->itap_del_ena[timing]); 30657205cf9SJudith Mendez } else { 307a0a62497SFaiz Abbas sdhci_am654_setup_delay_chain(sdhci_am654, timing); 30857205cf9SJudith Mendez sdhci_am654->dll_enable = false; 30957205cf9SJudith Mendez } 31061d9c4aaSFaiz Abbas 31161d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 31261d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 31341fd4caeSFaiz Abbas } 31441fd4caeSFaiz Abbas 3158751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 3168751c8bdSYueHaibing unsigned int clock) 3171accbcedSFaiz Abbas { 3181accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3191accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 3208ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3218ee5fc0eSFaiz Abbas u32 otap_del_sel; 3223433a340SJudith Mendez u32 itap_del_ena; 3232b8d2a6eSJudith Mendez u32 itap_del_sel; 3248ee5fc0eSFaiz Abbas u32 mask, val; 3258ee5fc0eSFaiz Abbas 3268ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 3278ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 3281accbcedSFaiz Abbas 3291accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3308ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 3318ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 3323433a340SJudith Mendez 3332b8d2a6eSJudith Mendez /* Setup Input TAP delay */ 3343433a340SJudith Mendez itap_del_ena = sdhci_am654->itap_del_ena[timing]; 3352b8d2a6eSJudith Mendez itap_del_sel = sdhci_am654->itap_del_sel[timing]; 3363433a340SJudith Mendez 3372b8d2a6eSJudith Mendez mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK; 3382b8d2a6eSJudith Mendez val |= (itap_del_ena << ITAPDLYENA_SHIFT) | 3392b8d2a6eSJudith Mendez (itap_del_sel << ITAPDLYSEL_SHIFT); 3403433a340SJudith Mendez 3412b8d2a6eSJudith Mendez regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 3422b8d2a6eSJudith Mendez 1 << ITAPCHGWIN_SHIFT); 3431accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3442b8d2a6eSJudith Mendez regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 34561d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 34661d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 34761d9c4aaSFaiz Abbas 3481accbcedSFaiz Abbas sdhci_set_clock(host, clock); 3491accbcedSFaiz Abbas } 3501accbcedSFaiz Abbas 3517ca0f166SFaiz Abbas static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 3527ca0f166SFaiz Abbas { 3537ca0f166SFaiz Abbas writeb(val, host->ioaddr + reg); 3547ca0f166SFaiz Abbas usleep_range(1000, 10000); 3557ca0f166SFaiz Abbas return readb(host->ioaddr + reg); 3567ca0f166SFaiz Abbas } 3577ca0f166SFaiz Abbas 3587ca0f166SFaiz Abbas #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 359e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 360e374e875SFaiz Abbas { 361e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3627ca0f166SFaiz Abbas u8 pwr; 3637ca0f166SFaiz Abbas int ret; 364e374e875SFaiz Abbas 365e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 366e374e875SFaiz Abbas switch (timing) { 367e374e875SFaiz Abbas /* 368e374e875SFaiz Abbas * According to the data manual, HISPD bit 369e374e875SFaiz Abbas * should not be set in these speed modes. 370e374e875SFaiz Abbas */ 371e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 372e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 373e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 374e374e875SFaiz Abbas } 375e374e875SFaiz Abbas } 376e374e875SFaiz Abbas 377e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 3787ca0f166SFaiz Abbas if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 3797ca0f166SFaiz Abbas /* 3807ca0f166SFaiz Abbas * Power on will not happen until the card detect debounce 3817ca0f166SFaiz Abbas * timer expires. Wait at least 1.5 seconds for the power on 3827ca0f166SFaiz Abbas * bit to be set 3837ca0f166SFaiz Abbas */ 3847ca0f166SFaiz Abbas ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 3857ca0f166SFaiz Abbas pwr & SDHCI_POWER_ON, 0, 3867ca0f166SFaiz Abbas MAX_POWER_ON_TIMEOUT, false, host, val, 3877ca0f166SFaiz Abbas reg); 3887ca0f166SFaiz Abbas if (ret) 38911440da7SFrancesco Dolcini dev_info(mmc_dev(host->mmc), "Power on failed\n"); 3907ca0f166SFaiz Abbas } 391e374e875SFaiz Abbas } 392e374e875SFaiz Abbas 393c7666240SVignesh Raghavendra static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 394c7666240SVignesh Raghavendra { 395c7666240SVignesh Raghavendra u8 ctrl; 396c7666240SVignesh Raghavendra struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 397c7666240SVignesh Raghavendra struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 398c7666240SVignesh Raghavendra 399162503fdSBrian Norris sdhci_and_cqhci_reset(host, mask); 400c7666240SVignesh Raghavendra 401c7666240SVignesh Raghavendra if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 402c7666240SVignesh Raghavendra ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 403c7666240SVignesh Raghavendra ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 404c7666240SVignesh Raghavendra sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 405c7666240SVignesh Raghavendra } 406c7666240SVignesh Raghavendra } 407c7666240SVignesh Raghavendra 408de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 409de31f6abSFaiz Abbas { 410de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 411de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 41241fd4caeSFaiz Abbas 413de31f6abSFaiz Abbas if (err) 414de31f6abSFaiz Abbas return err; 415de31f6abSFaiz Abbas /* 416de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 417de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 418de31f6abSFaiz Abbas */ 419de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 42041fd4caeSFaiz Abbas 421de31f6abSFaiz Abbas return 0; 422de31f6abSFaiz Abbas } 42399909b55SFaiz Abbas 424f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 425f545702bSFaiz Abbas { 426f545702bSFaiz Abbas int cmd_error = 0; 427f545702bSFaiz Abbas int data_error = 0; 428f545702bSFaiz Abbas 429f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 430f545702bSFaiz Abbas return intmask; 431f545702bSFaiz Abbas 432f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 433f545702bSFaiz Abbas 434f545702bSFaiz Abbas return 0; 435f545702bSFaiz Abbas } 436f545702bSFaiz Abbas 43757205cf9SJudith Mendez #define ITAPDLY_LENGTH 32 43857205cf9SJudith Mendez #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 43957205cf9SJudith Mendez 44057205cf9SJudith Mendez static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 44157205cf9SJudith Mendez *fail_window, u8 num_fails, bool circular_buffer) 44257205cf9SJudith Mendez { 44357205cf9SJudith Mendez u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 44457205cf9SJudith Mendez u8 first_fail_start = 0, last_fail_end = 0; 44557205cf9SJudith Mendez struct device *dev = mmc_dev(host->mmc); 44657205cf9SJudith Mendez struct window pass_window = {0, 0, 0}; 44757205cf9SJudith Mendez int prev_fail_end = -1; 44857205cf9SJudith Mendez u8 i; 44957205cf9SJudith Mendez 45057205cf9SJudith Mendez if (!num_fails) 45157205cf9SJudith Mendez return ITAPDLY_LAST_INDEX >> 1; 45257205cf9SJudith Mendez 45357205cf9SJudith Mendez if (fail_window->length == ITAPDLY_LENGTH) { 45457205cf9SJudith Mendez dev_err(dev, "No passing ITAPDLY, return 0\n"); 45557205cf9SJudith Mendez return 0; 45657205cf9SJudith Mendez } 45757205cf9SJudith Mendez 45857205cf9SJudith Mendez first_fail_start = fail_window->start; 45957205cf9SJudith Mendez last_fail_end = fail_window[num_fails - 1].end; 46057205cf9SJudith Mendez 46157205cf9SJudith Mendez for (i = 0; i < num_fails; i++) { 46257205cf9SJudith Mendez start_fail = fail_window[i].start; 46357205cf9SJudith Mendez end_fail = fail_window[i].end; 46457205cf9SJudith Mendez pass_length = start_fail - (prev_fail_end + 1); 46557205cf9SJudith Mendez 46657205cf9SJudith Mendez if (pass_length > pass_window.length) { 46757205cf9SJudith Mendez pass_window.start = prev_fail_end + 1; 46857205cf9SJudith Mendez pass_window.length = pass_length; 46957205cf9SJudith Mendez } 47057205cf9SJudith Mendez prev_fail_end = end_fail; 47157205cf9SJudith Mendez } 47257205cf9SJudith Mendez 47357205cf9SJudith Mendez if (!circular_buffer) 47457205cf9SJudith Mendez pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 47557205cf9SJudith Mendez else 47657205cf9SJudith Mendez pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 47757205cf9SJudith Mendez 47857205cf9SJudith Mendez if (pass_length > pass_window.length) { 47957205cf9SJudith Mendez pass_window.start = last_fail_end + 1; 48057205cf9SJudith Mendez pass_window.length = pass_length; 48157205cf9SJudith Mendez } 48257205cf9SJudith Mendez 48357205cf9SJudith Mendez if (!circular_buffer) 48457205cf9SJudith Mendez itap = pass_window.start + (pass_window.length >> 1); 48557205cf9SJudith Mendez else 48657205cf9SJudith Mendez itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 48757205cf9SJudith Mendez 48857205cf9SJudith Mendez return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 48957205cf9SJudith Mendez } 49057205cf9SJudith Mendez 49113ebeae6SFaiz Abbas static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 49213ebeae6SFaiz Abbas u32 opcode) 49313ebeae6SFaiz Abbas { 49413ebeae6SFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 49513ebeae6SFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 4963433a340SJudith Mendez unsigned char timing = host->mmc->ios.timing; 49757205cf9SJudith Mendez struct window fail_window[ITAPDLY_LENGTH]; 49857205cf9SJudith Mendez u8 curr_pass, itap; 49957205cf9SJudith Mendez u8 fail_index = 0; 50057205cf9SJudith Mendez u8 prev_pass = 1; 50157205cf9SJudith Mendez 50257205cf9SJudith Mendez memset(fail_window, 0, sizeof(fail_window)); 50313ebeae6SFaiz Abbas 50413ebeae6SFaiz Abbas /* Enable ITAPDLY */ 5053433a340SJudith Mendez sdhci_am654->itap_del_ena[timing] = 0x1; 50613ebeae6SFaiz Abbas 50757205cf9SJudith Mendez for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 5083433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 50913ebeae6SFaiz Abbas 51057205cf9SJudith Mendez curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 51113ebeae6SFaiz Abbas 51257205cf9SJudith Mendez if (!curr_pass && prev_pass) 51357205cf9SJudith Mendez fail_window[fail_index].start = itap; 51413ebeae6SFaiz Abbas 51557205cf9SJudith Mendez if (!curr_pass) { 51657205cf9SJudith Mendez fail_window[fail_index].end = itap; 51757205cf9SJudith Mendez fail_window[fail_index].length++; 51813ebeae6SFaiz Abbas } 51957205cf9SJudith Mendez 52057205cf9SJudith Mendez if (curr_pass && !prev_pass) 52157205cf9SJudith Mendez fail_index++; 52257205cf9SJudith Mendez 52357205cf9SJudith Mendez prev_pass = curr_pass; 52457205cf9SJudith Mendez } 52557205cf9SJudith Mendez 52657205cf9SJudith Mendez if (fail_window[fail_index].length != 0) 52757205cf9SJudith Mendez fail_index++; 52857205cf9SJudith Mendez 52957205cf9SJudith Mendez itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 53057205cf9SJudith Mendez sdhci_am654->dll_enable); 53157205cf9SJudith Mendez 5323433a340SJudith Mendez sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 53313ebeae6SFaiz Abbas 53413ebeae6SFaiz Abbas return 0; 53513ebeae6SFaiz Abbas } 53613ebeae6SFaiz Abbas 53741fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 53813ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 53941fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 54041fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 54141fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 54241fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5439d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 54441fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 54541fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 54627f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 547162503fdSBrian Norris .reset = sdhci_and_cqhci_reset, 54841fd4caeSFaiz Abbas }; 54941fd4caeSFaiz Abbas 55041fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 55141fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 5524d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 55341fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 55441fd4caeSFaiz Abbas }; 55541fd4caeSFaiz Abbas 55609db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 55741fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 55823514731SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 55923514731SFaiz Abbas DLL_CALIB, 56041fd4caeSFaiz Abbas }; 56141fd4caeSFaiz Abbas 56209db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 56309db9943SFaiz Abbas .pdata = &sdhci_am654_pdata, 56409db9943SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 56509db9943SFaiz Abbas }; 56609db9943SFaiz Abbas 5678751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 56813ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 56999909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 57099909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 57199909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 57299909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5739d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 57499909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 57599909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 576f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 577162503fdSBrian Norris .reset = sdhci_and_cqhci_reset, 57899909b55SFaiz Abbas }; 57999909b55SFaiz Abbas 58099909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 58199909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 5824d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 58399909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 58499909b55SFaiz Abbas }; 58599909b55SFaiz Abbas 58699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 58799909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 58823514731SFaiz Abbas .flags = DLL_PRESENT | DLL_CALIB, 58999909b55SFaiz Abbas }; 59099909b55SFaiz Abbas 5918751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 59213ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 5931accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 5941accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 5951accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 5961accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5979d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 5981accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 5991accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 600f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 601c7666240SVignesh Raghavendra .reset = sdhci_am654_reset, 6021accbcedSFaiz Abbas }; 6031accbcedSFaiz Abbas 6041accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 6051accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 6064d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 6071accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 6081accbcedSFaiz Abbas }; 6091accbcedSFaiz Abbas 6101accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 6111accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 6121accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 6131accbcedSFaiz Abbas }; 614f545702bSFaiz Abbas 61509db9943SFaiz Abbas static const struct soc_device_attribute sdhci_am654_devices[] = { 61609db9943SFaiz Abbas { .family = "AM65X", 61709db9943SFaiz Abbas .revision = "SR1.0", 61809db9943SFaiz Abbas .data = &sdhci_am654_sr1_drvdata 61909db9943SFaiz Abbas }, 62009db9943SFaiz Abbas {/* sentinel */} 62109db9943SFaiz Abbas }; 62209db9943SFaiz Abbas 623f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 624f545702bSFaiz Abbas { 625f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 626f545702bSFaiz Abbas } 627f545702bSFaiz Abbas 628f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 629f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 630f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 631f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 632f545702bSFaiz Abbas }; 633f545702bSFaiz Abbas 634f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 635f545702bSFaiz Abbas { 636f545702bSFaiz Abbas struct cqhci_host *cq_host; 637f545702bSFaiz Abbas 638bac53336SJisheng Zhang cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 639f545702bSFaiz Abbas GFP_KERNEL); 640f545702bSFaiz Abbas if (!cq_host) 641f545702bSFaiz Abbas return -ENOMEM; 642f545702bSFaiz Abbas 643f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 644f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 645f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 646f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 647f545702bSFaiz Abbas 648f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 649f545702bSFaiz Abbas 650c0470f43Sye xingchen return cqhci_init(cq_host, host->mmc, 1); 651f545702bSFaiz Abbas } 652f545702bSFaiz Abbas 6538ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 6548ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 6558ee5fc0eSFaiz Abbas { 6568ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 6578ee5fc0eSFaiz Abbas int i; 6588ee5fc0eSFaiz Abbas int ret; 6598ee5fc0eSFaiz Abbas 66058220885SNitin Yadav for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 6618ee5fc0eSFaiz Abbas 662a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[i].otap_binding, 6638ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 6648ee5fc0eSFaiz Abbas if (ret) { 6653525baf3SVignesh Raghavendra if (i == MMC_TIMING_LEGACY) { 6663525baf3SVignesh Raghavendra dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); 6673525baf3SVignesh Raghavendra return ret; 6683525baf3SVignesh Raghavendra } 6698ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 670a0a62497SFaiz Abbas td[i].otap_binding); 6718ee5fc0eSFaiz Abbas /* 6728ee5fc0eSFaiz Abbas * Remove the corresponding capability 6738ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 6748ee5fc0eSFaiz Abbas */ 6758ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 6768ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 6778ee5fc0eSFaiz Abbas else 6788ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 6798ee5fc0eSFaiz Abbas } 680a0a62497SFaiz Abbas 6813433a340SJudith Mendez if (td[i].itap_binding) { 6823433a340SJudith Mendez ret = device_property_read_u32(dev, td[i].itap_binding, 683a0a62497SFaiz Abbas &sdhci_am654->itap_del_sel[i]); 6843433a340SJudith Mendez if (!ret) 6853433a340SJudith Mendez sdhci_am654->itap_del_ena[i] = 0x1; 6863433a340SJudith Mendez } 6878ee5fc0eSFaiz Abbas } 6888ee5fc0eSFaiz Abbas 6898ee5fc0eSFaiz Abbas return 0; 6908ee5fc0eSFaiz Abbas } 6918ee5fc0eSFaiz Abbas 69241fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 69341fd4caeSFaiz Abbas { 69441fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 69541fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 69641fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 69741fd4caeSFaiz Abbas u32 mask; 69841fd4caeSFaiz Abbas u32 val; 69941fd4caeSFaiz Abbas int ret; 70041fd4caeSFaiz Abbas 70141fd4caeSFaiz Abbas /* Reset OTAP to default value */ 70241fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 7038023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 70441fd4caeSFaiz Abbas 70523514731SFaiz Abbas if (sdhci_am654->flags & DLL_CALIB) { 70641fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 70741fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 70841fd4caeSFaiz Abbas /* Calibrate IO lines */ 70941fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 71041fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 7111accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 7121accbcedSFaiz Abbas PHY_STAT1, val, 7131accbcedSFaiz Abbas val & CALDONE_MASK, 7141accbcedSFaiz Abbas 1, 20); 71541fd4caeSFaiz Abbas if (ret) 71641fd4caeSFaiz Abbas return ret; 71741fd4caeSFaiz Abbas } 7181accbcedSFaiz Abbas } 71941fd4caeSFaiz Abbas 72041fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 72199909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 72299909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 72399909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 72441fd4caeSFaiz Abbas 72541fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 72641fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 72741fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 72841fd4caeSFaiz Abbas 7298023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 7308023cf26SFaiz Abbas ctl_cfg_2); 73141fd4caeSFaiz Abbas 732764384d0SFaiz Abbas /* Enable tuning for SDR50 */ 733764384d0SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 734764384d0SFaiz Abbas TUNINGFORSDR50_MASK); 735764384d0SFaiz Abbas 736f545702bSFaiz Abbas ret = sdhci_setup_host(host); 737f545702bSFaiz Abbas if (ret) 738f545702bSFaiz Abbas return ret; 739f545702bSFaiz Abbas 740f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 741f545702bSFaiz Abbas if (ret) 742f545702bSFaiz Abbas goto err_cleanup_host; 743f545702bSFaiz Abbas 7448ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 7458ee5fc0eSFaiz Abbas if (ret) 7468ee5fc0eSFaiz Abbas goto err_cleanup_host; 7478ee5fc0eSFaiz Abbas 748f545702bSFaiz Abbas ret = __sdhci_add_host(host); 749f545702bSFaiz Abbas if (ret) 750f545702bSFaiz Abbas goto err_cleanup_host; 751f545702bSFaiz Abbas 752f545702bSFaiz Abbas return 0; 753f545702bSFaiz Abbas 754f545702bSFaiz Abbas err_cleanup_host: 755f545702bSFaiz Abbas sdhci_cleanup_host(host); 756f545702bSFaiz Abbas return ret; 75741fd4caeSFaiz Abbas } 75841fd4caeSFaiz Abbas 75941fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 76041fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 76141fd4caeSFaiz Abbas { 76241fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 76341fd4caeSFaiz Abbas int drv_strength; 76441fd4caeSFaiz Abbas int ret; 76541fd4caeSFaiz Abbas 7661accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 7671accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 7681accbcedSFaiz Abbas &sdhci_am654->trm_icp); 76941fd4caeSFaiz Abbas if (ret) 77041fd4caeSFaiz Abbas return ret; 77141fd4caeSFaiz Abbas 77241fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 77341fd4caeSFaiz Abbas &drv_strength); 77441fd4caeSFaiz Abbas if (ret) 77541fd4caeSFaiz Abbas return ret; 77641fd4caeSFaiz Abbas 77741fd4caeSFaiz Abbas switch (drv_strength) { 77841fd4caeSFaiz Abbas case 50: 77941fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 78041fd4caeSFaiz Abbas break; 78141fd4caeSFaiz Abbas case 33: 78241fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 78341fd4caeSFaiz Abbas break; 78441fd4caeSFaiz Abbas case 66: 78541fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 78641fd4caeSFaiz Abbas break; 78741fd4caeSFaiz Abbas case 100: 78841fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 78941fd4caeSFaiz Abbas break; 79041fd4caeSFaiz Abbas case 40: 79141fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 79241fd4caeSFaiz Abbas break; 79341fd4caeSFaiz Abbas default: 79441fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 79541fd4caeSFaiz Abbas return -EINVAL; 79641fd4caeSFaiz Abbas } 7971accbcedSFaiz Abbas } 79841fd4caeSFaiz Abbas 79999909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 80061d9c4aaSFaiz Abbas device_property_read_u32(dev, "ti,clkbuf-sel", 80161d9c4aaSFaiz Abbas &sdhci_am654->clkbuf_sel); 80299909b55SFaiz Abbas 803c7666240SVignesh Raghavendra if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 804c7666240SVignesh Raghavendra sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 805c7666240SVignesh Raghavendra 80641fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 80741fd4caeSFaiz Abbas 80841fd4caeSFaiz Abbas return 0; 80941fd4caeSFaiz Abbas } 81041fd4caeSFaiz Abbas 81199909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 81299909b55SFaiz Abbas { 81399909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 81499909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 81599909b55SFaiz Abbas }, 81699909b55SFaiz Abbas { 81799909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 81899909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 81999909b55SFaiz Abbas }, 8201accbcedSFaiz Abbas { 8211accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 8221accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 8231accbcedSFaiz Abbas }, 824754b7f2fSFaiz Abbas { 825754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-8bit", 8263b7340f1SAswath Govindraju .data = &sdhci_j721e_8bit_drvdata, 827754b7f2fSFaiz Abbas }, 828754b7f2fSFaiz Abbas { 829754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-4bit", 8303b7340f1SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 831754b7f2fSFaiz Abbas }, 83202538e45SAswath Govindraju { 83302538e45SAswath Govindraju .compatible = "ti,am62-sdhci", 83402538e45SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 83502538e45SAswath Govindraju }, 83699909b55SFaiz Abbas { /* sentinel */ } 83799909b55SFaiz Abbas }; 8381e23400fSFaiz Abbas MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 83999909b55SFaiz Abbas 84041fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 84141fd4caeSFaiz Abbas { 84299909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 84309db9943SFaiz Abbas const struct soc_device_attribute *soc; 84441fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 84541fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 84699909b55SFaiz Abbas const struct of_device_id *match; 84741fd4caeSFaiz Abbas struct sdhci_host *host; 84841fd4caeSFaiz Abbas struct clk *clk_xin; 84941fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 85041fd4caeSFaiz Abbas void __iomem *base; 85141fd4caeSFaiz Abbas int ret; 85241fd4caeSFaiz Abbas 85399909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 85499909b55SFaiz Abbas drvdata = match->data; 85509db9943SFaiz Abbas 85609db9943SFaiz Abbas /* Update drvdata based on SoC revision */ 85709db9943SFaiz Abbas soc = soc_device_match(sdhci_am654_devices); 85809db9943SFaiz Abbas if (soc && soc->data) 85909db9943SFaiz Abbas drvdata = soc->data; 86009db9943SFaiz Abbas 86199909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 86241fd4caeSFaiz Abbas if (IS_ERR(host)) 86341fd4caeSFaiz Abbas return PTR_ERR(host); 86441fd4caeSFaiz Abbas 86541fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 86641fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 86799909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 86841fd4caeSFaiz Abbas 86941fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 87041fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 87141fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 87241fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 87341fd4caeSFaiz Abbas goto err_pltfm_free; 87441fd4caeSFaiz Abbas } 87541fd4caeSFaiz Abbas 87641fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 87741fd4caeSFaiz Abbas 8784942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 87941fd4caeSFaiz Abbas if (IS_ERR(base)) { 88041fd4caeSFaiz Abbas ret = PTR_ERR(base); 8819d2e77ffSAswath Govindraju goto err_pltfm_free; 88241fd4caeSFaiz Abbas } 88341fd4caeSFaiz Abbas 88441fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 88541fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 88641fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 88741fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 88841fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 8899d2e77ffSAswath Govindraju goto err_pltfm_free; 89041fd4caeSFaiz Abbas } 89141fd4caeSFaiz Abbas 89241fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 89341fd4caeSFaiz Abbas if (ret) 8949d2e77ffSAswath Govindraju goto err_pltfm_free; 89541fd4caeSFaiz Abbas 89641fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 89741fd4caeSFaiz Abbas if (ret) { 898654993b3SMatthias Schiffer dev_err_probe(dev, ret, "parsing dt failed\n"); 8999d2e77ffSAswath Govindraju goto err_pltfm_free; 90041fd4caeSFaiz Abbas } 90141fd4caeSFaiz Abbas 902de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 903de31f6abSFaiz Abbas 9049d2e77ffSAswath Govindraju pm_runtime_get_noresume(dev); 9059d2e77ffSAswath Govindraju ret = pm_runtime_set_active(dev); 9069d2e77ffSAswath Govindraju if (ret) 9079d2e77ffSAswath Govindraju goto pm_put; 9089d2e77ffSAswath Govindraju pm_runtime_enable(dev); 9099d2e77ffSAswath Govindraju ret = clk_prepare_enable(pltfm_host->clk); 9109d2e77ffSAswath Govindraju if (ret) 9119d2e77ffSAswath Govindraju goto pm_disable; 9129d2e77ffSAswath Govindraju 91341fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 91441fd4caeSFaiz Abbas if (ret) 9159d2e77ffSAswath Govindraju goto clk_disable; 91641fd4caeSFaiz Abbas 9179d2e77ffSAswath Govindraju /* Setting up autosuspend */ 9189d2e77ffSAswath Govindraju pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 9199d2e77ffSAswath Govindraju pm_runtime_use_autosuspend(dev); 9209d2e77ffSAswath Govindraju pm_runtime_mark_last_busy(dev); 9219d2e77ffSAswath Govindraju pm_runtime_put_autosuspend(dev); 92241fd4caeSFaiz Abbas return 0; 92341fd4caeSFaiz Abbas 9249d2e77ffSAswath Govindraju clk_disable: 9259d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 9269d2e77ffSAswath Govindraju pm_disable: 92741fd4caeSFaiz Abbas pm_runtime_disable(dev); 9289d2e77ffSAswath Govindraju pm_put: 9299d2e77ffSAswath Govindraju pm_runtime_put_noidle(dev); 93041fd4caeSFaiz Abbas err_pltfm_free: 93141fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 93241fd4caeSFaiz Abbas return ret; 93341fd4caeSFaiz Abbas } 93441fd4caeSFaiz Abbas 935de29ade4SYangtao Li static void sdhci_am654_remove(struct platform_device *pdev) 93641fd4caeSFaiz Abbas { 93741fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 9389d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 939854034e2SYangtao Li struct device *dev = &pdev->dev; 94041fd4caeSFaiz Abbas int ret; 94141fd4caeSFaiz Abbas 942854034e2SYangtao Li ret = pm_runtime_get_sync(dev); 94341fd4caeSFaiz Abbas if (ret < 0) 944854034e2SYangtao Li dev_err(dev, "pm_runtime_get_sync() Failed\n"); 94541fd4caeSFaiz Abbas 9469d2e77ffSAswath Govindraju sdhci_remove_host(host, true); 9479d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 948854034e2SYangtao Li pm_runtime_disable(dev); 949854034e2SYangtao Li pm_runtime_put_noidle(dev); 95041fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 9519d2e77ffSAswath Govindraju } 9529d2e77ffSAswath Govindraju 9539d2e77ffSAswath Govindraju #ifdef CONFIG_PM 9549d2e77ffSAswath Govindraju static int sdhci_am654_restore(struct sdhci_host *host) 9559d2e77ffSAswath Govindraju { 9569d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 9579d2e77ffSAswath Govindraju struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 9589d2e77ffSAswath Govindraju u32 ctl_cfg_2 = 0; 9599d2e77ffSAswath Govindraju u32 val; 9609d2e77ffSAswath Govindraju int ret; 9619d2e77ffSAswath Govindraju 9629d2e77ffSAswath Govindraju if (sdhci_am654->flags & DLL_CALIB) { 9639d2e77ffSAswath Govindraju regmap_read(sdhci_am654->base, PHY_STAT1, &val); 9649d2e77ffSAswath Govindraju if (~val & CALDONE_MASK) { 9659d2e77ffSAswath Govindraju /* Calibrate IO lines */ 9669d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 9679d2e77ffSAswath Govindraju PDB_MASK, PDB_MASK); 9689d2e77ffSAswath Govindraju ret = regmap_read_poll_timeout(sdhci_am654->base, 9699d2e77ffSAswath Govindraju PHY_STAT1, val, 9709d2e77ffSAswath Govindraju val & CALDONE_MASK, 9719d2e77ffSAswath Govindraju 1, 20); 9729d2e77ffSAswath Govindraju if (ret) 9739d2e77ffSAswath Govindraju return ret; 9749d2e77ffSAswath Govindraju } 9759d2e77ffSAswath Govindraju } 9769d2e77ffSAswath Govindraju 9779d2e77ffSAswath Govindraju /* Enable pins by setting IO mux to 0 */ 9789d2e77ffSAswath Govindraju if (sdhci_am654->flags & IOMUX_PRESENT) 9799d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 9809d2e77ffSAswath Govindraju IOMUX_ENABLE_MASK, 0); 9819d2e77ffSAswath Govindraju 9829d2e77ffSAswath Govindraju /* Set slot type based on SD or eMMC */ 9839d2e77ffSAswath Govindraju if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 9849d2e77ffSAswath Govindraju ctl_cfg_2 = SLOTTYPE_EMBEDDED; 9859d2e77ffSAswath Govindraju 9869d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 9879d2e77ffSAswath Govindraju ctl_cfg_2); 9889d2e77ffSAswath Govindraju 9899d2e77ffSAswath Govindraju regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 9909d2e77ffSAswath Govindraju if (~val & TUNINGFORSDR50_MASK) 9919d2e77ffSAswath Govindraju /* Enable tuning for SDR50 */ 9929d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 9939d2e77ffSAswath Govindraju TUNINGFORSDR50_MASK); 99441fd4caeSFaiz Abbas 99541fd4caeSFaiz Abbas return 0; 99641fd4caeSFaiz Abbas } 99741fd4caeSFaiz Abbas 9989d2e77ffSAswath Govindraju static int sdhci_am654_runtime_suspend(struct device *dev) 9999d2e77ffSAswath Govindraju { 10009d2e77ffSAswath Govindraju struct sdhci_host *host = dev_get_drvdata(dev); 10019d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10029d2e77ffSAswath Govindraju int ret; 10039d2e77ffSAswath Govindraju 10049d2e77ffSAswath Govindraju if (host->tuning_mode != SDHCI_TUNING_MODE_3) 10059d2e77ffSAswath Govindraju mmc_retune_needed(host->mmc); 10069d2e77ffSAswath Govindraju 10079d2e77ffSAswath Govindraju ret = cqhci_suspend(host->mmc); 10089d2e77ffSAswath Govindraju if (ret) 10099d2e77ffSAswath Govindraju return ret; 10109d2e77ffSAswath Govindraju 10119d2e77ffSAswath Govindraju ret = sdhci_runtime_suspend_host(host); 10129d2e77ffSAswath Govindraju if (ret) 10139d2e77ffSAswath Govindraju return ret; 10149d2e77ffSAswath Govindraju 10159d2e77ffSAswath Govindraju /* disable the clock */ 10169d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 10179d2e77ffSAswath Govindraju return 0; 10189d2e77ffSAswath Govindraju } 10199d2e77ffSAswath Govindraju 10209d2e77ffSAswath Govindraju static int sdhci_am654_runtime_resume(struct device *dev) 10219d2e77ffSAswath Govindraju { 10229d2e77ffSAswath Govindraju struct sdhci_host *host = dev_get_drvdata(dev); 10239d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10249d2e77ffSAswath Govindraju int ret; 10259d2e77ffSAswath Govindraju 10269d2e77ffSAswath Govindraju /* Enable the clock */ 10279d2e77ffSAswath Govindraju ret = clk_prepare_enable(pltfm_host->clk); 10289d2e77ffSAswath Govindraju if (ret) 10299d2e77ffSAswath Govindraju return ret; 10309d2e77ffSAswath Govindraju 10319d2e77ffSAswath Govindraju ret = sdhci_am654_restore(host); 10329d2e77ffSAswath Govindraju if (ret) 10339d2e77ffSAswath Govindraju return ret; 10349d2e77ffSAswath Govindraju 10359d2e77ffSAswath Govindraju ret = sdhci_runtime_resume_host(host, 0); 10369d2e77ffSAswath Govindraju if (ret) 10379d2e77ffSAswath Govindraju return ret; 10389d2e77ffSAswath Govindraju 10399d2e77ffSAswath Govindraju ret = cqhci_resume(host->mmc); 10409d2e77ffSAswath Govindraju if (ret) 10419d2e77ffSAswath Govindraju return ret; 10429d2e77ffSAswath Govindraju 10439d2e77ffSAswath Govindraju return 0; 10449d2e77ffSAswath Govindraju } 10459d2e77ffSAswath Govindraju #endif 10469d2e77ffSAswath Govindraju 10479d2e77ffSAswath Govindraju static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 10489d2e77ffSAswath Govindraju SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 10499d2e77ffSAswath Govindraju sdhci_am654_runtime_resume, NULL) 10509d2e77ffSAswath Govindraju SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 10519d2e77ffSAswath Govindraju pm_runtime_force_resume) 10529d2e77ffSAswath Govindraju }; 10539d2e77ffSAswath Govindraju 105441fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 105541fd4caeSFaiz Abbas .driver = { 105641fd4caeSFaiz Abbas .name = "sdhci-am654", 1057d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 10589d2e77ffSAswath Govindraju .pm = &sdhci_am654_dev_pm_ops, 105941fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 106041fd4caeSFaiz Abbas }, 106141fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 1062de29ade4SYangtao Li .remove_new = sdhci_am654_remove, 106341fd4caeSFaiz Abbas }; 106441fd4caeSFaiz Abbas 106541fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 106641fd4caeSFaiz Abbas 106741fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 106841fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 106941fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 1070