141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 541fd4caeSFaiz Abbas * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 999909b55SFaiz Abbas #include <linux/of.h> 1041fd4caeSFaiz Abbas #include <linux/module.h> 1141fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1241fd4caeSFaiz Abbas #include <linux/property.h> 1341fd4caeSFaiz Abbas #include <linux/regmap.h> 1441fd4caeSFaiz Abbas 1541fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1641fd4caeSFaiz Abbas 1741fd4caeSFaiz Abbas /* CTL_CFG Registers */ 1841fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 1941fd4caeSFaiz Abbas 2041fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2141fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 2241fd4caeSFaiz Abbas 2341fd4caeSFaiz Abbas /* PHY Registers */ 2441fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 2541fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 2641fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 2741fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 2841fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 2941fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3041fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3141fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3241fd4caeSFaiz Abbas 3341fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3441fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 3541fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 3641fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 3741fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 3841fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 3941fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4099909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4199909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4241fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4341fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4441fd4caeSFaiz Abbas #define SEL100_SHIFT 9 4541fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 4699909b55SFaiz Abbas #define FREQSEL_SHIFT 8 4799909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 4841fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 4941fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5041fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5141fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 5241fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 5341fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 5441fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 5541fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 5641fd4caeSFaiz Abbas #define PDB_SHIFT 0 5741fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 5841fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 5941fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6041fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6141fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 6241fd4caeSFaiz Abbas 6341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 6441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 6541fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 6641fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 6741fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 6841fd4caeSFaiz Abbas 6941fd4caeSFaiz Abbas #define CLOCK_TOO_SLOW_HZ 400000 7041fd4caeSFaiz Abbas 7141fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 7241fd4caeSFaiz Abbas .reg_bits = 32, 7341fd4caeSFaiz Abbas .val_bits = 32, 7441fd4caeSFaiz Abbas .reg_stride = 4, 7541fd4caeSFaiz Abbas .fast_io = true, 7641fd4caeSFaiz Abbas }; 7741fd4caeSFaiz Abbas 7841fd4caeSFaiz Abbas struct sdhci_am654_data { 7941fd4caeSFaiz Abbas struct regmap *base; 8041fd4caeSFaiz Abbas int otap_del_sel; 8141fd4caeSFaiz Abbas int trm_icp; 8241fd4caeSFaiz Abbas int drv_strength; 8341fd4caeSFaiz Abbas bool dll_on; 8499909b55SFaiz Abbas int strb_sel; 8599909b55SFaiz Abbas u32 flags; 8699909b55SFaiz Abbas }; 8799909b55SFaiz Abbas 8899909b55SFaiz Abbas struct sdhci_am654_driver_data { 8999909b55SFaiz Abbas const struct sdhci_pltfm_data *pdata; 9099909b55SFaiz Abbas u32 flags; 9199909b55SFaiz Abbas #define IOMUX_PRESENT (1 << 0) 9299909b55SFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 9399909b55SFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 941accbcedSFaiz Abbas #define DLL_PRESENT (1 << 3) 9541fd4caeSFaiz Abbas }; 9641fd4caeSFaiz Abbas 9741fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 9841fd4caeSFaiz Abbas { 9941fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10041fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 10199909b55SFaiz Abbas int sel50, sel100, freqsel; 10241fd4caeSFaiz Abbas u32 mask, val; 10341fd4caeSFaiz Abbas int ret; 10441fd4caeSFaiz Abbas 10541fd4caeSFaiz Abbas if (sdhci_am654->dll_on) { 1068023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 10741fd4caeSFaiz Abbas 10841fd4caeSFaiz Abbas sdhci_am654->dll_on = false; 10941fd4caeSFaiz Abbas } 11041fd4caeSFaiz Abbas 11141fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 11241fd4caeSFaiz Abbas 11341fd4caeSFaiz Abbas if (clock > CLOCK_TOO_SLOW_HZ) { 11441fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 11541fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 11641fd4caeSFaiz Abbas val = (1 << OTAPDLYENA_SHIFT) | 11741fd4caeSFaiz Abbas (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 1188023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 11999909b55SFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 12099909b55SFaiz Abbas if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 12199909b55SFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 12299909b55SFaiz Abbas mask = STRBSEL_4BIT_MASK; 12399909b55SFaiz Abbas else 12499909b55SFaiz Abbas mask = STRBSEL_8BIT_MASK; 12599909b55SFaiz Abbas 12699909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 12799909b55SFaiz Abbas sdhci_am654->strb_sel << 12899909b55SFaiz Abbas STRBSEL_SHIFT); 12999909b55SFaiz Abbas } 13099909b55SFaiz Abbas 13199909b55SFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 13241fd4caeSFaiz Abbas switch (clock) { 13341fd4caeSFaiz Abbas case 200000000: 13441fd4caeSFaiz Abbas sel50 = 0; 13541fd4caeSFaiz Abbas sel100 = 0; 13641fd4caeSFaiz Abbas break; 13741fd4caeSFaiz Abbas case 100000000: 13841fd4caeSFaiz Abbas sel50 = 0; 13941fd4caeSFaiz Abbas sel100 = 1; 14041fd4caeSFaiz Abbas break; 14141fd4caeSFaiz Abbas default: 14241fd4caeSFaiz Abbas sel50 = 1; 14341fd4caeSFaiz Abbas sel100 = 0; 14441fd4caeSFaiz Abbas } 14541fd4caeSFaiz Abbas 14641fd4caeSFaiz Abbas /* Configure PHY DLL frequency */ 14741fd4caeSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 14841fd4caeSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 14999909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, 15099909b55SFaiz Abbas val); 15199909b55SFaiz Abbas } else { 15299909b55SFaiz Abbas switch (clock) { 15399909b55SFaiz Abbas case 200000000: 15499909b55SFaiz Abbas freqsel = 0x0; 15599909b55SFaiz Abbas break; 15699909b55SFaiz Abbas default: 15799909b55SFaiz Abbas freqsel = 0x4; 15899909b55SFaiz Abbas } 15999909b55SFaiz Abbas 16099909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 16199909b55SFaiz Abbas FREQSEL_MASK, 16299909b55SFaiz Abbas freqsel << FREQSEL_SHIFT); 16399909b55SFaiz Abbas } 16499909b55SFaiz Abbas 16541fd4caeSFaiz Abbas /* Configure DLL TRIM */ 16641fd4caeSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 16741fd4caeSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 16841fd4caeSFaiz Abbas 16941fd4caeSFaiz Abbas /* Configure DLL driver strength */ 17041fd4caeSFaiz Abbas mask |= DR_TY_MASK; 17141fd4caeSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 1728023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 17341fd4caeSFaiz Abbas /* Enable DLL */ 1748023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 1758023cf26SFaiz Abbas 0x1 << ENDLL_SHIFT); 17641fd4caeSFaiz Abbas /* 17741fd4caeSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 17841fd4caeSFaiz Abbas * Works in all experiments done so far 17941fd4caeSFaiz Abbas */ 1808023cf26SFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 1818023cf26SFaiz Abbas val, val & DLLRDY_MASK, 1000, 1828023cf26SFaiz Abbas 1000000); 1837e24e28bSFaiz Abbas if (ret) { 1847e24e28bSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 1857e24e28bSFaiz Abbas return; 1867e24e28bSFaiz Abbas } 1877e24e28bSFaiz Abbas 18841fd4caeSFaiz Abbas sdhci_am654->dll_on = true; 18941fd4caeSFaiz Abbas } 19041fd4caeSFaiz Abbas } 19141fd4caeSFaiz Abbas 1921accbcedSFaiz Abbas void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, unsigned int clock) 1931accbcedSFaiz Abbas { 1941accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1951accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 1961accbcedSFaiz Abbas int val, mask; 1971accbcedSFaiz Abbas 1981accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 1991accbcedSFaiz Abbas val = (1 << OTAPDLYENA_SHIFT) | 2001accbcedSFaiz Abbas (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 2011accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2021accbcedSFaiz Abbas 2031accbcedSFaiz Abbas sdhci_set_clock(host, clock); 2041accbcedSFaiz Abbas } 2051accbcedSFaiz Abbas 20641fd4caeSFaiz Abbas static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 20741fd4caeSFaiz Abbas unsigned short vdd) 20841fd4caeSFaiz Abbas { 20941fd4caeSFaiz Abbas if (!IS_ERR(host->mmc->supply.vmmc)) { 21041fd4caeSFaiz Abbas struct mmc_host *mmc = host->mmc; 21141fd4caeSFaiz Abbas 21241fd4caeSFaiz Abbas mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 21341fd4caeSFaiz Abbas } 21441fd4caeSFaiz Abbas sdhci_set_power_noreg(host, mode, vdd); 21541fd4caeSFaiz Abbas } 21641fd4caeSFaiz Abbas 217e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 218e374e875SFaiz Abbas { 219e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 220e374e875SFaiz Abbas 221e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 222e374e875SFaiz Abbas switch (timing) { 223e374e875SFaiz Abbas /* 224e374e875SFaiz Abbas * According to the data manual, HISPD bit 225e374e875SFaiz Abbas * should not be set in these speed modes. 226e374e875SFaiz Abbas */ 227e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 228e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 229e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 230e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 231e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 232e374e875SFaiz Abbas } 233e374e875SFaiz Abbas } 234e374e875SFaiz Abbas 235e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 236e374e875SFaiz Abbas } 237e374e875SFaiz Abbas 2384e47345aSWei Yongjun static struct sdhci_ops sdhci_am654_ops = { 23941fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 24041fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 24141fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 24241fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 24341fd4caeSFaiz Abbas .set_power = sdhci_am654_set_power, 24441fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 245e374e875SFaiz Abbas .write_b = sdhci_am654_write_b, 24641fd4caeSFaiz Abbas .reset = sdhci_reset, 24741fd4caeSFaiz Abbas }; 24841fd4caeSFaiz Abbas 24941fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 25041fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 25141fd4caeSFaiz Abbas .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 25241fd4caeSFaiz Abbas SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 25341fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 25441fd4caeSFaiz Abbas }; 25541fd4caeSFaiz Abbas 25699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 25799909b55SFaiz Abbas .pdata = &sdhci_am654_pdata, 2581accbcedSFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 25999909b55SFaiz Abbas }; 26099909b55SFaiz Abbas 26199909b55SFaiz Abbas struct sdhci_ops sdhci_j721e_8bit_ops = { 26299909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 26399909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 26499909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 26599909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 26699909b55SFaiz Abbas .set_power = sdhci_am654_set_power, 26799909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 26899909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 26999909b55SFaiz Abbas .reset = sdhci_reset, 27099909b55SFaiz Abbas }; 27199909b55SFaiz Abbas 27299909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 27399909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 27499909b55SFaiz Abbas .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 27599909b55SFaiz Abbas SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 27699909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 27799909b55SFaiz Abbas }; 27899909b55SFaiz Abbas 27999909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 28099909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 2811accbcedSFaiz Abbas .flags = DLL_PRESENT, 28299909b55SFaiz Abbas }; 28399909b55SFaiz Abbas 2841accbcedSFaiz Abbas struct sdhci_ops sdhci_j721e_4bit_ops = { 2851accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 2861accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 2871accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 2881accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 2891accbcedSFaiz Abbas .set_power = sdhci_am654_set_power, 2901accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 2911accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 2921accbcedSFaiz Abbas .reset = sdhci_reset, 2931accbcedSFaiz Abbas }; 2941accbcedSFaiz Abbas 2951accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 2961accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 2971accbcedSFaiz Abbas .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 2981accbcedSFaiz Abbas SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 2991accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 3001accbcedSFaiz Abbas }; 3011accbcedSFaiz Abbas 3021accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 3031accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 3041accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 3051accbcedSFaiz Abbas }; 30641fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 30741fd4caeSFaiz Abbas { 30841fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 30941fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 31041fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 31141fd4caeSFaiz Abbas u32 mask; 31241fd4caeSFaiz Abbas u32 val; 31341fd4caeSFaiz Abbas int ret; 31441fd4caeSFaiz Abbas 31541fd4caeSFaiz Abbas /* Reset OTAP to default value */ 31641fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3178023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 31841fd4caeSFaiz Abbas 3191accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 32041fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 32141fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 32241fd4caeSFaiz Abbas /* Calibrate IO lines */ 32341fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 32441fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 3251accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 3261accbcedSFaiz Abbas PHY_STAT1, val, 3271accbcedSFaiz Abbas val & CALDONE_MASK, 3281accbcedSFaiz Abbas 1, 20); 32941fd4caeSFaiz Abbas if (ret) 33041fd4caeSFaiz Abbas return ret; 33141fd4caeSFaiz Abbas } 3321accbcedSFaiz Abbas } 33341fd4caeSFaiz Abbas 33441fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 33599909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 33699909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 33799909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 33841fd4caeSFaiz Abbas 33941fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 34041fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 34141fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 34241fd4caeSFaiz Abbas 3438023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 3448023cf26SFaiz Abbas ctl_cfg_2); 34541fd4caeSFaiz Abbas 34641fd4caeSFaiz Abbas return sdhci_add_host(host); 34741fd4caeSFaiz Abbas } 34841fd4caeSFaiz Abbas 34941fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 35041fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 35141fd4caeSFaiz Abbas { 35241fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 35341fd4caeSFaiz Abbas int drv_strength; 35441fd4caeSFaiz Abbas int ret; 35541fd4caeSFaiz Abbas 3561accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 3571accbcedSFaiz Abbas &sdhci_am654->otap_del_sel); 35841fd4caeSFaiz Abbas if (ret) 35941fd4caeSFaiz Abbas return ret; 36041fd4caeSFaiz Abbas 3611accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 3621accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 3631accbcedSFaiz Abbas &sdhci_am654->trm_icp); 36441fd4caeSFaiz Abbas if (ret) 36541fd4caeSFaiz Abbas return ret; 36641fd4caeSFaiz Abbas 36741fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 36841fd4caeSFaiz Abbas &drv_strength); 36941fd4caeSFaiz Abbas if (ret) 37041fd4caeSFaiz Abbas return ret; 37141fd4caeSFaiz Abbas 37241fd4caeSFaiz Abbas switch (drv_strength) { 37341fd4caeSFaiz Abbas case 50: 37441fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 37541fd4caeSFaiz Abbas break; 37641fd4caeSFaiz Abbas case 33: 37741fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 37841fd4caeSFaiz Abbas break; 37941fd4caeSFaiz Abbas case 66: 38041fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 38141fd4caeSFaiz Abbas break; 38241fd4caeSFaiz Abbas case 100: 38341fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 38441fd4caeSFaiz Abbas break; 38541fd4caeSFaiz Abbas case 40: 38641fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 38741fd4caeSFaiz Abbas break; 38841fd4caeSFaiz Abbas default: 38941fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 39041fd4caeSFaiz Abbas return -EINVAL; 39141fd4caeSFaiz Abbas } 3921accbcedSFaiz Abbas } 39341fd4caeSFaiz Abbas 39499909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 39599909b55SFaiz Abbas 39641fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 39741fd4caeSFaiz Abbas 39841fd4caeSFaiz Abbas return 0; 39941fd4caeSFaiz Abbas } 40041fd4caeSFaiz Abbas 40199909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 40299909b55SFaiz Abbas { 40399909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 40499909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 40599909b55SFaiz Abbas }, 40699909b55SFaiz Abbas { 40799909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 40899909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 40999909b55SFaiz Abbas }, 4101accbcedSFaiz Abbas { 4111accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 4121accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 4131accbcedSFaiz Abbas }, 41499909b55SFaiz Abbas { /* sentinel */ } 41599909b55SFaiz Abbas }; 41699909b55SFaiz Abbas 41741fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 41841fd4caeSFaiz Abbas { 41999909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 42041fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 42141fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 42299909b55SFaiz Abbas const struct of_device_id *match; 42341fd4caeSFaiz Abbas struct sdhci_host *host; 42441fd4caeSFaiz Abbas struct resource *res; 42541fd4caeSFaiz Abbas struct clk *clk_xin; 42641fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 42741fd4caeSFaiz Abbas void __iomem *base; 42841fd4caeSFaiz Abbas int ret; 42941fd4caeSFaiz Abbas 43099909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 43199909b55SFaiz Abbas drvdata = match->data; 43299909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 43341fd4caeSFaiz Abbas if (IS_ERR(host)) 43441fd4caeSFaiz Abbas return PTR_ERR(host); 43541fd4caeSFaiz Abbas 43641fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 43741fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 43899909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 43941fd4caeSFaiz Abbas 44041fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 44141fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 44241fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 44341fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 44441fd4caeSFaiz Abbas goto err_pltfm_free; 44541fd4caeSFaiz Abbas } 44641fd4caeSFaiz Abbas 44741fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 44841fd4caeSFaiz Abbas 44941fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 45041fd4caeSFaiz Abbas pm_runtime_enable(dev); 45141fd4caeSFaiz Abbas ret = pm_runtime_get_sync(dev); 45241fd4caeSFaiz Abbas if (ret < 0) { 45341fd4caeSFaiz Abbas pm_runtime_put_noidle(dev); 45441fd4caeSFaiz Abbas goto pm_runtime_disable; 45541fd4caeSFaiz Abbas } 45641fd4caeSFaiz Abbas 45741fd4caeSFaiz Abbas res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 45841fd4caeSFaiz Abbas base = devm_ioremap_resource(dev, res); 45941fd4caeSFaiz Abbas if (IS_ERR(base)) { 46041fd4caeSFaiz Abbas ret = PTR_ERR(base); 46141fd4caeSFaiz Abbas goto pm_runtime_put; 46241fd4caeSFaiz Abbas } 46341fd4caeSFaiz Abbas 46441fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 46541fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 46641fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 46741fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 46841fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 46941fd4caeSFaiz Abbas goto pm_runtime_put; 47041fd4caeSFaiz Abbas } 47141fd4caeSFaiz Abbas 47241fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 47341fd4caeSFaiz Abbas if (ret) 47441fd4caeSFaiz Abbas goto pm_runtime_put; 47541fd4caeSFaiz Abbas 47641fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 47741fd4caeSFaiz Abbas if (ret) { 47841fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 47941fd4caeSFaiz Abbas goto pm_runtime_put; 48041fd4caeSFaiz Abbas } 48141fd4caeSFaiz Abbas 48241fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 48341fd4caeSFaiz Abbas if (ret) 48441fd4caeSFaiz Abbas goto pm_runtime_put; 48541fd4caeSFaiz Abbas 48641fd4caeSFaiz Abbas return 0; 48741fd4caeSFaiz Abbas 48841fd4caeSFaiz Abbas pm_runtime_put: 48941fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 49041fd4caeSFaiz Abbas pm_runtime_disable: 49141fd4caeSFaiz Abbas pm_runtime_disable(dev); 49241fd4caeSFaiz Abbas err_pltfm_free: 49341fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 49441fd4caeSFaiz Abbas return ret; 49541fd4caeSFaiz Abbas } 49641fd4caeSFaiz Abbas 49741fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 49841fd4caeSFaiz Abbas { 49941fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 50041fd4caeSFaiz Abbas int ret; 50141fd4caeSFaiz Abbas 50241fd4caeSFaiz Abbas sdhci_remove_host(host, true); 50341fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 50441fd4caeSFaiz Abbas if (ret < 0) 50541fd4caeSFaiz Abbas return ret; 50641fd4caeSFaiz Abbas 50741fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 50841fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 50941fd4caeSFaiz Abbas 51041fd4caeSFaiz Abbas return 0; 51141fd4caeSFaiz Abbas } 51241fd4caeSFaiz Abbas 51341fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 51441fd4caeSFaiz Abbas .driver = { 51541fd4caeSFaiz Abbas .name = "sdhci-am654", 51641fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 51741fd4caeSFaiz Abbas }, 51841fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 51941fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 52041fd4caeSFaiz Abbas }; 52141fd4caeSFaiz Abbas 52241fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 52341fd4caeSFaiz Abbas 52441fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 52541fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 52641fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 527