xref: /openbmc/linux/drivers/mmc/host/sdhci.h (revision d188b8c9)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
4  *
5  * Header file for Host Controller registers and I/O accessors.
6  *
7  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
8  */
9 #ifndef __SDHCI_HW_H
10 #define __SDHCI_HW_H
11 
12 #include <linux/scatterlist.h>
13 #include <linux/compiler.h>
14 #include <linux/types.h>
15 #include <linux/io.h>
16 #include <linux/leds.h>
17 #include <linux/interrupt.h>
18 
19 #include <linux/mmc/host.h>
20 
21 /*
22  * Controller registers
23  */
24 
25 #define SDHCI_DMA_ADDRESS	0x00
26 #define SDHCI_ARGUMENT2		SDHCI_DMA_ADDRESS
27 #define SDHCI_32BIT_BLK_CNT	SDHCI_DMA_ADDRESS
28 
29 #define SDHCI_BLOCK_SIZE	0x04
30 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
31 
32 #define SDHCI_BLOCK_COUNT	0x06
33 
34 #define SDHCI_ARGUMENT		0x08
35 
36 #define SDHCI_TRANSFER_MODE	0x0C
37 #define  SDHCI_TRNS_DMA		0x01
38 #define  SDHCI_TRNS_BLK_CNT_EN	0x02
39 #define  SDHCI_TRNS_AUTO_CMD12	0x04
40 #define  SDHCI_TRNS_AUTO_CMD23	0x08
41 #define  SDHCI_TRNS_AUTO_SEL	0x0C
42 #define  SDHCI_TRNS_READ	0x10
43 #define  SDHCI_TRNS_MULTI	0x20
44 
45 #define SDHCI_COMMAND		0x0E
46 #define  SDHCI_CMD_RESP_MASK	0x03
47 #define  SDHCI_CMD_CRC		0x08
48 #define  SDHCI_CMD_INDEX	0x10
49 #define  SDHCI_CMD_DATA		0x20
50 #define  SDHCI_CMD_ABORTCMD	0xC0
51 
52 #define  SDHCI_CMD_RESP_NONE	0x00
53 #define  SDHCI_CMD_RESP_LONG	0x01
54 #define  SDHCI_CMD_RESP_SHORT	0x02
55 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
56 
57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
59 
60 #define SDHCI_RESPONSE		0x10
61 
62 #define SDHCI_BUFFER		0x20
63 
64 #define SDHCI_PRESENT_STATE	0x24
65 #define  SDHCI_CMD_INHIBIT	0x00000001
66 #define  SDHCI_DATA_INHIBIT	0x00000002
67 #define  SDHCI_DOING_WRITE	0x00000100
68 #define  SDHCI_DOING_READ	0x00000200
69 #define  SDHCI_SPACE_AVAILABLE	0x00000400
70 #define  SDHCI_DATA_AVAILABLE	0x00000800
71 #define  SDHCI_CARD_PRESENT	0x00010000
72 #define   SDHCI_CARD_PRES_SHIFT	16
73 #define  SDHCI_CD_STABLE	0x00020000
74 #define  SDHCI_CD_LVL		0x00040000
75 #define   SDHCI_CD_LVL_SHIFT	18
76 #define  SDHCI_WRITE_PROTECT	0x00080000
77 #define  SDHCI_DATA_LVL_MASK	0x00F00000
78 #define   SDHCI_DATA_LVL_SHIFT	20
79 #define   SDHCI_DATA_0_LVL_MASK	0x00100000
80 #define  SDHCI_CMD_LVL		0x01000000
81 
82 #define SDHCI_HOST_CONTROL	0x28
83 #define  SDHCI_CTRL_LED		0x01
84 #define  SDHCI_CTRL_4BITBUS	0x02
85 #define  SDHCI_CTRL_HISPD	0x04
86 #define  SDHCI_CTRL_DMA_MASK	0x18
87 #define   SDHCI_CTRL_SDMA	0x00
88 #define   SDHCI_CTRL_ADMA1	0x08
89 #define   SDHCI_CTRL_ADMA32	0x10
90 #define   SDHCI_CTRL_ADMA64	0x18
91 #define   SDHCI_CTRL_ADMA3	0x18
92 #define  SDHCI_CTRL_8BITBUS	0x20
93 #define  SDHCI_CTRL_CDTEST_INS	0x40
94 #define  SDHCI_CTRL_CDTEST_EN	0x80
95 
96 #define SDHCI_POWER_CONTROL	0x29
97 #define  SDHCI_POWER_ON		0x01
98 #define  SDHCI_POWER_180	0x0A
99 #define  SDHCI_POWER_300	0x0C
100 #define  SDHCI_POWER_330	0x0E
101 
102 #define SDHCI_BLOCK_GAP_CONTROL	0x2A
103 
104 #define SDHCI_WAKE_UP_CONTROL	0x2B
105 #define  SDHCI_WAKE_ON_INT	0x01
106 #define  SDHCI_WAKE_ON_INSERT	0x02
107 #define  SDHCI_WAKE_ON_REMOVE	0x04
108 
109 #define SDHCI_CLOCK_CONTROL	0x2C
110 #define  SDHCI_DIVIDER_SHIFT	8
111 #define  SDHCI_DIVIDER_HI_SHIFT	6
112 #define  SDHCI_DIV_MASK	0xFF
113 #define  SDHCI_DIV_MASK_LEN	8
114 #define  SDHCI_DIV_HI_MASK	0x300
115 #define  SDHCI_PROG_CLOCK_MODE	0x0020
116 #define  SDHCI_CLOCK_CARD_EN	0x0004
117 #define  SDHCI_CLOCK_PLL_EN	0x0008
118 #define  SDHCI_CLOCK_INT_STABLE	0x0002
119 #define  SDHCI_CLOCK_INT_EN	0x0001
120 
121 #define SDHCI_TIMEOUT_CONTROL	0x2E
122 
123 #define SDHCI_SOFTWARE_RESET	0x2F
124 #define  SDHCI_RESET_ALL	0x01
125 #define  SDHCI_RESET_CMD	0x02
126 #define  SDHCI_RESET_DATA	0x04
127 
128 #define SDHCI_INT_STATUS	0x30
129 #define SDHCI_INT_ENABLE	0x34
130 #define SDHCI_SIGNAL_ENABLE	0x38
131 #define  SDHCI_INT_RESPONSE	0x00000001
132 #define  SDHCI_INT_DATA_END	0x00000002
133 #define  SDHCI_INT_BLK_GAP	0x00000004
134 #define  SDHCI_INT_DMA_END	0x00000008
135 #define  SDHCI_INT_SPACE_AVAIL	0x00000010
136 #define  SDHCI_INT_DATA_AVAIL	0x00000020
137 #define  SDHCI_INT_CARD_INSERT	0x00000040
138 #define  SDHCI_INT_CARD_REMOVE	0x00000080
139 #define  SDHCI_INT_CARD_INT	0x00000100
140 #define  SDHCI_INT_RETUNE	0x00001000
141 #define  SDHCI_INT_CQE		0x00004000
142 #define  SDHCI_INT_ERROR	0x00008000
143 #define  SDHCI_INT_TIMEOUT	0x00010000
144 #define  SDHCI_INT_CRC		0x00020000
145 #define  SDHCI_INT_END_BIT	0x00040000
146 #define  SDHCI_INT_INDEX	0x00080000
147 #define  SDHCI_INT_DATA_TIMEOUT	0x00100000
148 #define  SDHCI_INT_DATA_CRC	0x00200000
149 #define  SDHCI_INT_DATA_END_BIT	0x00400000
150 #define  SDHCI_INT_BUS_POWER	0x00800000
151 #define  SDHCI_INT_AUTO_CMD_ERR	0x01000000
152 #define  SDHCI_INT_ADMA_ERROR	0x02000000
153 
154 #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
155 #define  SDHCI_INT_ERROR_MASK	0xFFFF8000
156 
157 #define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
158 		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
159 		SDHCI_INT_AUTO_CMD_ERR)
160 #define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
161 		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
162 		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
163 		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
164 		SDHCI_INT_BLK_GAP)
165 #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
166 
167 #define SDHCI_CQE_INT_ERR_MASK ( \
168 	SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
169 	SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
170 	SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
171 
172 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
173 
174 #define SDHCI_AUTO_CMD_STATUS	0x3C
175 #define  SDHCI_AUTO_CMD_TIMEOUT	0x00000002
176 #define  SDHCI_AUTO_CMD_CRC	0x00000004
177 #define  SDHCI_AUTO_CMD_END_BIT	0x00000008
178 #define  SDHCI_AUTO_CMD_INDEX	0x00000010
179 
180 #define SDHCI_HOST_CONTROL2		0x3E
181 #define  SDHCI_CTRL_UHS_MASK		0x0007
182 #define   SDHCI_CTRL_UHS_SDR12		0x0000
183 #define   SDHCI_CTRL_UHS_SDR25		0x0001
184 #define   SDHCI_CTRL_UHS_SDR50		0x0002
185 #define   SDHCI_CTRL_UHS_SDR104		0x0003
186 #define   SDHCI_CTRL_UHS_DDR50		0x0004
187 #define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
188 #define  SDHCI_CTRL_VDD_180		0x0008
189 #define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
190 #define   SDHCI_CTRL_DRV_TYPE_B		0x0000
191 #define   SDHCI_CTRL_DRV_TYPE_A		0x0010
192 #define   SDHCI_CTRL_DRV_TYPE_C		0x0020
193 #define   SDHCI_CTRL_DRV_TYPE_D		0x0030
194 #define  SDHCI_CTRL_EXEC_TUNING		0x0040
195 #define  SDHCI_CTRL_TUNED_CLK		0x0080
196 #define  SDHCI_CMD23_ENABLE		0x0800
197 #define  SDHCI_CTRL_V4_MODE		0x1000
198 #define  SDHCI_CTRL_64BIT_ADDR		0x2000
199 #define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000
200 
201 #define SDHCI_CAPABILITIES	0x40
202 #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
203 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
204 #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
205 #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
206 #define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
207 #define  SDHCI_CLOCK_BASE_SHIFT	8
208 #define  SDHCI_MAX_BLOCK_MASK	0x00030000
209 #define  SDHCI_MAX_BLOCK_SHIFT  16
210 #define  SDHCI_CAN_DO_8BIT	0x00040000
211 #define  SDHCI_CAN_DO_ADMA2	0x00080000
212 #define  SDHCI_CAN_DO_ADMA1	0x00100000
213 #define  SDHCI_CAN_DO_HISPD	0x00200000
214 #define  SDHCI_CAN_DO_SDMA	0x00400000
215 #define  SDHCI_CAN_DO_SUSPEND	0x00800000
216 #define  SDHCI_CAN_VDD_330	0x01000000
217 #define  SDHCI_CAN_VDD_300	0x02000000
218 #define  SDHCI_CAN_VDD_180	0x04000000
219 #define  SDHCI_CAN_64BIT_V4	0x08000000
220 #define  SDHCI_CAN_64BIT	0x10000000
221 
222 #define  SDHCI_SUPPORT_SDR50	0x00000001
223 #define  SDHCI_SUPPORT_SDR104	0x00000002
224 #define  SDHCI_SUPPORT_DDR50	0x00000004
225 #define  SDHCI_DRIVER_TYPE_A	0x00000010
226 #define  SDHCI_DRIVER_TYPE_C	0x00000020
227 #define  SDHCI_DRIVER_TYPE_D	0x00000040
228 #define  SDHCI_RETUNING_TIMER_COUNT_MASK	0x00000F00
229 #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT	8
230 #define  SDHCI_USE_SDR50_TUNING			0x00002000
231 #define  SDHCI_RETUNING_MODE_MASK		0x0000C000
232 #define  SDHCI_RETUNING_MODE_SHIFT		14
233 #define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
234 #define  SDHCI_CLOCK_MUL_SHIFT	16
235 #define  SDHCI_CAN_DO_ADMA3	0x08000000
236 #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
237 
238 #define SDHCI_CAPABILITIES_1	0x44
239 
240 #define SDHCI_MAX_CURRENT		0x48
241 #define  SDHCI_MAX_CURRENT_LIMIT	0xFF
242 #define  SDHCI_MAX_CURRENT_330_MASK	0x0000FF
243 #define  SDHCI_MAX_CURRENT_330_SHIFT	0
244 #define  SDHCI_MAX_CURRENT_300_MASK	0x00FF00
245 #define  SDHCI_MAX_CURRENT_300_SHIFT	8
246 #define  SDHCI_MAX_CURRENT_180_MASK	0xFF0000
247 #define  SDHCI_MAX_CURRENT_180_SHIFT	16
248 #define   SDHCI_MAX_CURRENT_MULTIPLIER	4
249 
250 /* 4C-4F reserved for more max current */
251 
252 #define SDHCI_SET_ACMD12_ERROR	0x50
253 #define SDHCI_SET_INT_ERROR	0x52
254 
255 #define SDHCI_ADMA_ERROR	0x54
256 
257 /* 55-57 reserved */
258 
259 #define SDHCI_ADMA_ADDRESS	0x58
260 #define SDHCI_ADMA_ADDRESS_HI	0x5C
261 
262 /* 60-FB reserved */
263 
264 #define SDHCI_PRESET_FOR_SDR12 0x66
265 #define SDHCI_PRESET_FOR_SDR25 0x68
266 #define SDHCI_PRESET_FOR_SDR50 0x6A
267 #define SDHCI_PRESET_FOR_SDR104        0x6C
268 #define SDHCI_PRESET_FOR_DDR50 0x6E
269 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
270 #define SDHCI_PRESET_DRV_MASK  0xC000
271 #define SDHCI_PRESET_DRV_SHIFT  14
272 #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
273 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT	10
274 #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
275 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT	0
276 
277 #define SDHCI_SLOT_INT_STATUS	0xFC
278 
279 #define SDHCI_HOST_VERSION	0xFE
280 #define  SDHCI_VENDOR_VER_MASK	0xFF00
281 #define  SDHCI_VENDOR_VER_SHIFT	8
282 #define  SDHCI_SPEC_VER_MASK	0x00FF
283 #define  SDHCI_SPEC_VER_SHIFT	0
284 #define   SDHCI_SPEC_100	0
285 #define   SDHCI_SPEC_200	1
286 #define   SDHCI_SPEC_300	2
287 #define   SDHCI_SPEC_400	3
288 #define   SDHCI_SPEC_410	4
289 #define   SDHCI_SPEC_420	5
290 
291 /*
292  * End of controller registers.
293  */
294 
295 #define SDHCI_MAX_DIV_SPEC_200	256
296 #define SDHCI_MAX_DIV_SPEC_300	2046
297 
298 /*
299  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
300  */
301 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
302 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
303 
304 /* ADMA2 32-bit DMA descriptor size */
305 #define SDHCI_ADMA2_32_DESC_SZ	8
306 
307 /* ADMA2 32-bit descriptor */
308 struct sdhci_adma2_32_desc {
309 	__le16	cmd;
310 	__le16	len;
311 	__le32	addr;
312 }  __packed __aligned(4);
313 
314 /* ADMA2 data alignment */
315 #define SDHCI_ADMA2_ALIGN	4
316 #define SDHCI_ADMA2_MASK	(SDHCI_ADMA2_ALIGN - 1)
317 
318 /*
319  * ADMA2 descriptor alignment.  Some controllers (e.g. Intel) require 8 byte
320  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
321  * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
322  */
323 #define SDHCI_ADMA2_DESC_ALIGN	8
324 
325 /*
326  * ADMA2 64-bit DMA descriptor size
327  * According to SD Host Controller spec v4.10, there are two kinds of
328  * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
329  * Descriptor, if Host Version 4 Enable is set in the Host Control 2
330  * register, 128-bit Descriptor will be selected.
331  */
332 #define SDHCI_ADMA2_64_DESC_SZ(host)	((host)->v4_mode ? 16 : 12)
333 
334 /*
335  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
336  * aligned.
337  */
338 struct sdhci_adma2_64_desc {
339 	__le16	cmd;
340 	__le16	len;
341 	__le32	addr_lo;
342 	__le32	addr_hi;
343 }  __packed __aligned(4);
344 
345 #define ADMA2_TRAN_VALID	0x21
346 #define ADMA2_NOP_END_VALID	0x3
347 #define ADMA2_END		0x2
348 
349 /*
350  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
351  * 4KiB page size.
352  */
353 #define SDHCI_MAX_SEGS		128
354 
355 /* Allow for a a command request and a data request at the same time */
356 #define SDHCI_MAX_MRQS		2
357 
358 /*
359  * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
360  * However since the start time of the command, the time between
361  * command and response, and the time between response and start of data is
362  * not known, set the command transfer time to 10ms.
363  */
364 #define MMC_CMD_TRANSFER_TIME	(10 * NSEC_PER_MSEC) /* max 10 ms */
365 
366 enum sdhci_cookie {
367 	COOKIE_UNMAPPED,
368 	COOKIE_PRE_MAPPED,	/* mapped by sdhci_pre_req() */
369 	COOKIE_MAPPED,		/* mapped by sdhci_prepare_data() */
370 };
371 
372 struct sdhci_host {
373 	/* Data set by hardware interface driver */
374 	const char *hw_name;	/* Hardware bus name */
375 
376 	unsigned int quirks;	/* Deviations from spec. */
377 
378 /* Controller doesn't honor resets unless we touch the clock register */
379 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
380 /* Controller has bad caps bits, but really supports DMA */
381 #define SDHCI_QUIRK_FORCE_DMA				(1<<1)
382 /* Controller doesn't like to be reset when there is no card inserted. */
383 #define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
384 /* Controller doesn't like clearing the power reg before a change */
385 #define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
386 /* Controller has flaky internal state so reset it on each ios change */
387 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
388 /* Controller has an unusable DMA engine */
389 #define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
390 /* Controller has an unusable ADMA engine */
391 #define SDHCI_QUIRK_BROKEN_ADMA				(1<<6)
392 /* Controller can only DMA from 32-bit aligned addresses */
393 #define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<7)
394 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
395 #define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<8)
396 /* Controller can only ADMA chunks that are a multiple of 32 bits */
397 #define SDHCI_QUIRK_32BIT_ADMA_SIZE			(1<<9)
398 /* Controller needs to be reset after each request to stay stable */
399 #define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<10)
400 /* Controller needs voltage and power writes to happen separately */
401 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<11)
402 /* Controller provides an incorrect timeout value for transfers */
403 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1<<12)
404 /* Controller has an issue with buffer bits for small transfers */
405 #define SDHCI_QUIRK_BROKEN_SMALL_PIO			(1<<13)
406 /* Controller does not provide transfer-complete interrupt when not busy */
407 #define SDHCI_QUIRK_NO_BUSY_IRQ				(1<<14)
408 /* Controller has unreliable card detection */
409 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION		(1<<15)
410 /* Controller reports inverted write-protect state */
411 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT		(1<<16)
412 /* Controller does not like fast PIO transfers */
413 #define SDHCI_QUIRK_PIO_NEEDS_DELAY			(1<<18)
414 /* Controller does not have a LED */
415 #define SDHCI_QUIRK_NO_LED				(1<<19)
416 /* Controller has to be forced to use block size of 2048 bytes */
417 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048			(1<<20)
418 /* Controller cannot do multi-block transfers */
419 #define SDHCI_QUIRK_NO_MULTIBLOCK			(1<<21)
420 /* Controller can only handle 1-bit data transfers */
421 #define SDHCI_QUIRK_FORCE_1_BIT_DATA			(1<<22)
422 /* Controller needs 10ms delay between applying power and clock */
423 #define SDHCI_QUIRK_DELAY_AFTER_POWER			(1<<23)
424 /* Controller uses SDCLK instead of TMCLK for data timeouts */
425 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK		(1<<24)
426 /* Controller reports wrong base clock capability */
427 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
428 /* Controller cannot support End Attribute in NOP ADMA descriptor */
429 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
430 /* Controller is missing device caps. Use caps provided by host */
431 #define SDHCI_QUIRK_MISSING_CAPS			(1<<27)
432 /* Controller uses Auto CMD12 command to stop the transfer */
433 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12		(1<<28)
434 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
435 #define SDHCI_QUIRK_NO_HISPD_BIT			(1<<29)
436 /* Controller treats ADMA descriptors with length 0000h incorrectly */
437 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC		(1<<30)
438 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
439 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1<<31)
440 
441 	unsigned int quirks2;	/* More deviations from spec. */
442 
443 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON			(1<<0)
444 #define SDHCI_QUIRK2_HOST_NO_CMD23			(1<<1)
445 /* The system physically doesn't support 1.8v, even if the host does */
446 #define SDHCI_QUIRK2_NO_1_8_V				(1<<2)
447 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN		(1<<3)
448 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON		(1<<4)
449 /* Controller has a non-standard host control register */
450 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL		(1<<5)
451 /* Controller does not support HS200 */
452 #define SDHCI_QUIRK2_BROKEN_HS200			(1<<6)
453 /* Controller does not support DDR50 */
454 #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
455 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
456 #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
457 /* Controller does not support 64-bit DMA */
458 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA			(1<<9)
459 /* need clear transfer mode register before send cmd */
460 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
461 /* Capability register bit-63 indicates HS400 support */
462 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<11)
463 /* forced tuned clock */
464 #define SDHCI_QUIRK2_TUNING_WORK_AROUND			(1<<12)
465 /* disable the block count for single block transactions */
466 #define SDHCI_QUIRK2_SUPPORT_SINGLE			(1<<13)
467 /* Controller broken with using ACMD23 */
468 #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
469 /* Broken Clock divider zero in controller */
470 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
471 /* Controller has CRC in 136 bit Command Response */
472 #define SDHCI_QUIRK2_RSP_136_HAS_CRC			(1<<16)
473 /*
474  * Disable HW timeout if the requested timeout is more than the maximum
475  * obtainable timeout.
476  */
477 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT			(1<<17)
478 /*
479  * 32-bit block count may not support eMMC where upper bits of CMD23 are used
480  * for other purposes.  Consequently we support 16-bit block count by default.
481  * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
482  * block count.
483  */
484 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT			(1<<18)
485 
486 	int irq;		/* Device IRQ */
487 	void __iomem *ioaddr;	/* Mapped address */
488 	char *bounce_buffer;	/* For packing SDMA reads/writes */
489 	dma_addr_t bounce_addr;
490 	unsigned int bounce_buffer_size;
491 
492 	const struct sdhci_ops *ops;	/* Low level hw interface */
493 
494 	/* Internal data */
495 	struct mmc_host *mmc;	/* MMC structure */
496 	struct mmc_host_ops mmc_host_ops;	/* MMC host ops */
497 	u64 dma_mask;		/* custom DMA mask */
498 
499 #if IS_ENABLED(CONFIG_LEDS_CLASS)
500 	struct led_classdev led;	/* LED control */
501 	char led_name[32];
502 #endif
503 
504 	spinlock_t lock;	/* Mutex */
505 
506 	int flags;		/* Host attributes */
507 #define SDHCI_USE_SDMA		(1<<0)	/* Host is SDMA capable */
508 #define SDHCI_USE_ADMA		(1<<1)	/* Host is ADMA capable */
509 #define SDHCI_REQ_USE_DMA	(1<<2)	/* Use DMA for this req. */
510 #define SDHCI_DEVICE_DEAD	(1<<3)	/* Device unresponsive */
511 #define SDHCI_SDR50_NEEDS_TUNING (1<<4)	/* SDR50 needs tuning */
512 #define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
513 #define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
514 #define SDHCI_PV_ENABLED	(1<<8)	/* Preset value enabled */
515 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
516 #define SDHCI_HS400_TUNING	(1<<13)	/* Tuning for HS400 */
517 #define SDHCI_SIGNALING_330	(1<<14)	/* Host is capable of 3.3V signaling */
518 #define SDHCI_SIGNALING_180	(1<<15)	/* Host is capable of 1.8V signaling */
519 #define SDHCI_SIGNALING_120	(1<<16)	/* Host is capable of 1.2V signaling */
520 
521 	unsigned int version;	/* SDHCI spec. version */
522 
523 	unsigned int max_clk;	/* Max possible freq (MHz) */
524 	unsigned int timeout_clk;	/* Timeout freq (KHz) */
525 	unsigned int clk_mul;	/* Clock Muliplier value */
526 
527 	unsigned int clock;	/* Current clock (MHz) */
528 	u8 pwr;			/* Current voltage */
529 
530 	bool runtime_suspended;	/* Host is runtime suspended */
531 	bool bus_on;		/* Bus power prevents runtime suspend */
532 	bool preset_enabled;	/* Preset is enabled */
533 	bool pending_reset;	/* Cmd/data reset is pending */
534 	bool irq_wake_enabled;	/* IRQ wakeup is enabled */
535 	bool v4_mode;		/* Host Version 4 Enable */
536 
537 	struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];	/* Requests done */
538 	struct mmc_command *cmd;	/* Current command */
539 	struct mmc_command *data_cmd;	/* Current data command */
540 	struct mmc_data *data;	/* Current data request */
541 	unsigned int data_early:1;	/* Data finished before cmd */
542 
543 	struct sg_mapping_iter sg_miter;	/* SG state for PIO */
544 	unsigned int blocks;	/* remaining PIO blocks */
545 
546 	int sg_count;		/* Mapped sg entries */
547 
548 	void *adma_table;	/* ADMA descriptor table */
549 	void *align_buffer;	/* Bounce buffer */
550 
551 	size_t adma_table_sz;	/* ADMA descriptor table size */
552 	size_t align_buffer_sz;	/* Bounce buffer size */
553 
554 	dma_addr_t adma_addr;	/* Mapped ADMA descr. table */
555 	dma_addr_t align_addr;	/* Mapped bounce buffer */
556 
557 	unsigned int desc_sz;	/* ADMA descriptor size */
558 
559 	struct workqueue_struct *complete_wq;	/* Request completion wq */
560 	struct work_struct	complete_work;	/* Request completion work */
561 
562 	struct timer_list timer;	/* Timer for timeouts */
563 	struct timer_list data_timer;	/* Timer for data timeouts */
564 
565 	u32 caps;		/* CAPABILITY_0 */
566 	u32 caps1;		/* CAPABILITY_1 */
567 	bool read_caps;		/* Capability flags have been read */
568 
569 	unsigned int            ocr_avail_sdio;	/* OCR bit masks */
570 	unsigned int            ocr_avail_sd;
571 	unsigned int            ocr_avail_mmc;
572 	u32 ocr_mask;		/* available voltages */
573 
574 	unsigned		timing;		/* Current timing */
575 
576 	u32			thread_isr;
577 
578 	/* cached registers */
579 	u32			ier;
580 
581 	bool			cqe_on;		/* CQE is operating */
582 	u32			cqe_ier;	/* CQE interrupt mask */
583 	u32			cqe_err_ier;	/* CQE error interrupt mask */
584 
585 	wait_queue_head_t	buf_ready_int;	/* Waitqueue for Buffer Read Ready interrupt */
586 	unsigned int		tuning_done;	/* Condition flag set when CMD19 succeeds */
587 
588 	unsigned int		tuning_count;	/* Timer count for re-tuning */
589 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
590 	unsigned int		tuning_err;	/* Error code for re-tuning */
591 #define SDHCI_TUNING_MODE_1	0
592 #define SDHCI_TUNING_MODE_2	1
593 #define SDHCI_TUNING_MODE_3	2
594 	/* Delay (ms) between tuning commands */
595 	int			tuning_delay;
596 	int			tuning_loop_count;
597 
598 	/* Host SDMA buffer boundary. */
599 	u32			sdma_boundary;
600 
601 	/* Host ADMA table count */
602 	u32			adma_table_cnt;
603 
604 	u64			data_timeout;
605 
606 	unsigned long private[0] ____cacheline_aligned;
607 };
608 
609 struct sdhci_ops {
610 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
611 	u32		(*read_l)(struct sdhci_host *host, int reg);
612 	u16		(*read_w)(struct sdhci_host *host, int reg);
613 	u8		(*read_b)(struct sdhci_host *host, int reg);
614 	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
615 	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
616 	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
617 #endif
618 
619 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);
620 	void	(*set_power)(struct sdhci_host *host, unsigned char mode,
621 			     unsigned short vdd);
622 
623 	u32		(*irq)(struct sdhci_host *host, u32 intmask);
624 
625 	int		(*set_dma_mask)(struct sdhci_host *host);
626 	int		(*enable_dma)(struct sdhci_host *host);
627 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
628 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
629 	/* get_timeout_clock should return clk rate in unit of Hz */
630 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
631 	unsigned int	(*get_max_timeout_count)(struct sdhci_host *host);
632 	void		(*set_timeout)(struct sdhci_host *host,
633 				       struct mmc_command *cmd);
634 	void		(*set_bus_width)(struct sdhci_host *host, int width);
635 	void (*platform_send_init_74_clocks)(struct sdhci_host *host,
636 					     u8 power_mode);
637 	unsigned int    (*get_ro)(struct sdhci_host *host);
638 	void		(*reset)(struct sdhci_host *host, u8 mask);
639 	int	(*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
640 	void	(*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
641 	void	(*hw_reset)(struct sdhci_host *host);
642 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
643 	void    (*card_event)(struct sdhci_host *host);
644 	void	(*voltage_switch)(struct sdhci_host *host);
645 	void	(*adma_write_desc)(struct sdhci_host *host, void **desc,
646 				   dma_addr_t addr, int len, unsigned int cmd);
647 };
648 
649 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
650 
651 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
652 {
653 	if (unlikely(host->ops->write_l))
654 		host->ops->write_l(host, val, reg);
655 	else
656 		writel(val, host->ioaddr + reg);
657 }
658 
659 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
660 {
661 	if (unlikely(host->ops->write_w))
662 		host->ops->write_w(host, val, reg);
663 	else
664 		writew(val, host->ioaddr + reg);
665 }
666 
667 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
668 {
669 	if (unlikely(host->ops->write_b))
670 		host->ops->write_b(host, val, reg);
671 	else
672 		writeb(val, host->ioaddr + reg);
673 }
674 
675 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
676 {
677 	if (unlikely(host->ops->read_l))
678 		return host->ops->read_l(host, reg);
679 	else
680 		return readl(host->ioaddr + reg);
681 }
682 
683 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
684 {
685 	if (unlikely(host->ops->read_w))
686 		return host->ops->read_w(host, reg);
687 	else
688 		return readw(host->ioaddr + reg);
689 }
690 
691 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
692 {
693 	if (unlikely(host->ops->read_b))
694 		return host->ops->read_b(host, reg);
695 	else
696 		return readb(host->ioaddr + reg);
697 }
698 
699 #else
700 
701 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
702 {
703 	writel(val, host->ioaddr + reg);
704 }
705 
706 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
707 {
708 	writew(val, host->ioaddr + reg);
709 }
710 
711 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
712 {
713 	writeb(val, host->ioaddr + reg);
714 }
715 
716 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
717 {
718 	return readl(host->ioaddr + reg);
719 }
720 
721 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
722 {
723 	return readw(host->ioaddr + reg);
724 }
725 
726 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
727 {
728 	return readb(host->ioaddr + reg);
729 }
730 
731 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
732 
733 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
734 void sdhci_free_host(struct sdhci_host *host);
735 
736 static inline void *sdhci_priv(struct sdhci_host *host)
737 {
738 	return host->private;
739 }
740 
741 void sdhci_card_detect(struct sdhci_host *host);
742 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
743 		       const u32 *caps, const u32 *caps1);
744 int sdhci_setup_host(struct sdhci_host *host);
745 void sdhci_cleanup_host(struct sdhci_host *host);
746 int __sdhci_add_host(struct sdhci_host *host);
747 int sdhci_add_host(struct sdhci_host *host);
748 void sdhci_remove_host(struct sdhci_host *host, int dead);
749 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
750 
751 static inline void sdhci_read_caps(struct sdhci_host *host)
752 {
753 	__sdhci_read_caps(host, NULL, NULL, NULL);
754 }
755 
756 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
757 		   unsigned int *actual_clock);
758 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
759 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
760 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
761 		     unsigned short vdd);
762 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
763 			   unsigned short vdd);
764 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
765 void sdhci_set_bus_width(struct sdhci_host *host, int width);
766 void sdhci_reset(struct sdhci_host *host, u8 mask);
767 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
768 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
769 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
770 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
771 				      struct mmc_ios *ios);
772 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
773 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
774 			   dma_addr_t addr, int len, unsigned int cmd);
775 
776 #ifdef CONFIG_PM
777 int sdhci_suspend_host(struct sdhci_host *host);
778 int sdhci_resume_host(struct sdhci_host *host);
779 int sdhci_runtime_suspend_host(struct sdhci_host *host);
780 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
781 #endif
782 
783 void sdhci_cqe_enable(struct mmc_host *mmc);
784 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
785 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
786 		   int *data_error);
787 
788 void sdhci_dumpregs(struct sdhci_host *host);
789 void sdhci_enable_v4_mode(struct sdhci_host *host);
790 
791 void sdhci_start_tuning(struct sdhci_host *host);
792 void sdhci_end_tuning(struct sdhci_host *host);
793 void sdhci_reset_tuning(struct sdhci_host *host);
794 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
795 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
796 
797 #endif /* __SDHCI_HW_H */
798