1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 21 #include <linux/mmc/host.h> 22 23 /* 24 * Controller registers 25 */ 26 27 #define SDHCI_DMA_ADDRESS 0x00 28 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_READ 0x10 43 #define SDHCI_TRNS_MULTI 0x20 44 45 #define SDHCI_COMMAND 0x0E 46 #define SDHCI_CMD_RESP_MASK 0x03 47 #define SDHCI_CMD_CRC 0x08 48 #define SDHCI_CMD_INDEX 0x10 49 #define SDHCI_CMD_DATA 0x20 50 #define SDHCI_CMD_ABORTCMD 0xC0 51 52 #define SDHCI_CMD_RESP_NONE 0x00 53 #define SDHCI_CMD_RESP_LONG 0x01 54 #define SDHCI_CMD_RESP_SHORT 0x02 55 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 56 57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 59 60 #define SDHCI_RESPONSE 0x10 61 62 #define SDHCI_BUFFER 0x20 63 64 #define SDHCI_PRESENT_STATE 0x24 65 #define SDHCI_CMD_INHIBIT 0x00000001 66 #define SDHCI_DATA_INHIBIT 0x00000002 67 #define SDHCI_DOING_WRITE 0x00000100 68 #define SDHCI_DOING_READ 0x00000200 69 #define SDHCI_SPACE_AVAILABLE 0x00000400 70 #define SDHCI_DATA_AVAILABLE 0x00000800 71 #define SDHCI_CARD_PRESENT 0x00010000 72 #define SDHCI_WRITE_PROTECT 0x00080000 73 #define SDHCI_DATA_LVL_MASK 0x00F00000 74 #define SDHCI_DATA_LVL_SHIFT 20 75 #define SDHCI_DATA_0_LVL_MASK 0x00100000 76 77 #define SDHCI_HOST_CONTROL 0x28 78 #define SDHCI_CTRL_LED 0x01 79 #define SDHCI_CTRL_4BITBUS 0x02 80 #define SDHCI_CTRL_HISPD 0x04 81 #define SDHCI_CTRL_DMA_MASK 0x18 82 #define SDHCI_CTRL_SDMA 0x00 83 #define SDHCI_CTRL_ADMA1 0x08 84 #define SDHCI_CTRL_ADMA32 0x10 85 #define SDHCI_CTRL_ADMA64 0x18 86 #define SDHCI_CTRL_8BITBUS 0x20 87 88 #define SDHCI_POWER_CONTROL 0x29 89 #define SDHCI_POWER_ON 0x01 90 #define SDHCI_POWER_180 0x0A 91 #define SDHCI_POWER_300 0x0C 92 #define SDHCI_POWER_330 0x0E 93 94 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 95 96 #define SDHCI_WAKE_UP_CONTROL 0x2B 97 #define SDHCI_WAKE_ON_INT 0x01 98 #define SDHCI_WAKE_ON_INSERT 0x02 99 #define SDHCI_WAKE_ON_REMOVE 0x04 100 101 #define SDHCI_CLOCK_CONTROL 0x2C 102 #define SDHCI_DIVIDER_SHIFT 8 103 #define SDHCI_DIVIDER_HI_SHIFT 6 104 #define SDHCI_DIV_MASK 0xFF 105 #define SDHCI_DIV_MASK_LEN 8 106 #define SDHCI_DIV_HI_MASK 0x300 107 #define SDHCI_PROG_CLOCK_MODE 0x0020 108 #define SDHCI_CLOCK_CARD_EN 0x0004 109 #define SDHCI_CLOCK_INT_STABLE 0x0002 110 #define SDHCI_CLOCK_INT_EN 0x0001 111 112 #define SDHCI_TIMEOUT_CONTROL 0x2E 113 114 #define SDHCI_SOFTWARE_RESET 0x2F 115 #define SDHCI_RESET_ALL 0x01 116 #define SDHCI_RESET_CMD 0x02 117 #define SDHCI_RESET_DATA 0x04 118 119 #define SDHCI_INT_STATUS 0x30 120 #define SDHCI_INT_ENABLE 0x34 121 #define SDHCI_SIGNAL_ENABLE 0x38 122 #define SDHCI_INT_RESPONSE 0x00000001 123 #define SDHCI_INT_DATA_END 0x00000002 124 #define SDHCI_INT_BLK_GAP 0x00000004 125 #define SDHCI_INT_DMA_END 0x00000008 126 #define SDHCI_INT_SPACE_AVAIL 0x00000010 127 #define SDHCI_INT_DATA_AVAIL 0x00000020 128 #define SDHCI_INT_CARD_INSERT 0x00000040 129 #define SDHCI_INT_CARD_REMOVE 0x00000080 130 #define SDHCI_INT_CARD_INT 0x00000100 131 #define SDHCI_INT_ERROR 0x00008000 132 #define SDHCI_INT_TIMEOUT 0x00010000 133 #define SDHCI_INT_CRC 0x00020000 134 #define SDHCI_INT_END_BIT 0x00040000 135 #define SDHCI_INT_INDEX 0x00080000 136 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 137 #define SDHCI_INT_DATA_CRC 0x00200000 138 #define SDHCI_INT_DATA_END_BIT 0x00400000 139 #define SDHCI_INT_BUS_POWER 0x00800000 140 #define SDHCI_INT_ACMD12ERR 0x01000000 141 #define SDHCI_INT_ADMA_ERROR 0x02000000 142 143 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 144 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 145 146 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 147 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 148 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 149 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 150 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 151 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 152 SDHCI_INT_BLK_GAP) 153 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 154 155 #define SDHCI_ACMD12_ERR 0x3C 156 157 #define SDHCI_HOST_CONTROL2 0x3E 158 #define SDHCI_CTRL_UHS_MASK 0x0007 159 #define SDHCI_CTRL_UHS_SDR12 0x0000 160 #define SDHCI_CTRL_UHS_SDR25 0x0001 161 #define SDHCI_CTRL_UHS_SDR50 0x0002 162 #define SDHCI_CTRL_UHS_SDR104 0x0003 163 #define SDHCI_CTRL_UHS_DDR50 0x0004 164 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 165 #define SDHCI_CTRL_VDD_180 0x0008 166 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 167 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 168 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 169 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 170 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 171 #define SDHCI_CTRL_EXEC_TUNING 0x0040 172 #define SDHCI_CTRL_TUNED_CLK 0x0080 173 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 174 175 #define SDHCI_CAPABILITIES 0x40 176 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 177 #define SDHCI_TIMEOUT_CLK_SHIFT 0 178 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 179 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 180 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 181 #define SDHCI_CLOCK_BASE_SHIFT 8 182 #define SDHCI_MAX_BLOCK_MASK 0x00030000 183 #define SDHCI_MAX_BLOCK_SHIFT 16 184 #define SDHCI_CAN_DO_8BIT 0x00040000 185 #define SDHCI_CAN_DO_ADMA2 0x00080000 186 #define SDHCI_CAN_DO_ADMA1 0x00100000 187 #define SDHCI_CAN_DO_HISPD 0x00200000 188 #define SDHCI_CAN_DO_SDMA 0x00400000 189 #define SDHCI_CAN_VDD_330 0x01000000 190 #define SDHCI_CAN_VDD_300 0x02000000 191 #define SDHCI_CAN_VDD_180 0x04000000 192 #define SDHCI_CAN_64BIT 0x10000000 193 194 #define SDHCI_SUPPORT_SDR50 0x00000001 195 #define SDHCI_SUPPORT_SDR104 0x00000002 196 #define SDHCI_SUPPORT_DDR50 0x00000004 197 #define SDHCI_DRIVER_TYPE_A 0x00000010 198 #define SDHCI_DRIVER_TYPE_C 0x00000020 199 #define SDHCI_DRIVER_TYPE_D 0x00000040 200 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 201 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 202 #define SDHCI_USE_SDR50_TUNING 0x00002000 203 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 204 #define SDHCI_RETUNING_MODE_SHIFT 14 205 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 206 #define SDHCI_CLOCK_MUL_SHIFT 16 207 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 208 209 #define SDHCI_CAPABILITIES_1 0x44 210 211 #define SDHCI_MAX_CURRENT 0x48 212 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 213 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 214 #define SDHCI_MAX_CURRENT_330_SHIFT 0 215 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 216 #define SDHCI_MAX_CURRENT_300_SHIFT 8 217 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 218 #define SDHCI_MAX_CURRENT_180_SHIFT 16 219 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 220 221 /* 4C-4F reserved for more max current */ 222 223 #define SDHCI_SET_ACMD12_ERROR 0x50 224 #define SDHCI_SET_INT_ERROR 0x52 225 226 #define SDHCI_ADMA_ERROR 0x54 227 228 /* 55-57 reserved */ 229 230 #define SDHCI_ADMA_ADDRESS 0x58 231 #define SDHCI_ADMA_ADDRESS_HI 0x5C 232 233 /* 60-FB reserved */ 234 235 #define SDHCI_PRESET_FOR_SDR12 0x66 236 #define SDHCI_PRESET_FOR_SDR25 0x68 237 #define SDHCI_PRESET_FOR_SDR50 0x6A 238 #define SDHCI_PRESET_FOR_SDR104 0x6C 239 #define SDHCI_PRESET_FOR_DDR50 0x6E 240 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 241 #define SDHCI_PRESET_DRV_MASK 0xC000 242 #define SDHCI_PRESET_DRV_SHIFT 14 243 #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 244 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 245 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 246 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 247 248 #define SDHCI_SLOT_INT_STATUS 0xFC 249 250 #define SDHCI_HOST_VERSION 0xFE 251 #define SDHCI_VENDOR_VER_MASK 0xFF00 252 #define SDHCI_VENDOR_VER_SHIFT 8 253 #define SDHCI_SPEC_VER_MASK 0x00FF 254 #define SDHCI_SPEC_VER_SHIFT 0 255 #define SDHCI_SPEC_100 0 256 #define SDHCI_SPEC_200 1 257 #define SDHCI_SPEC_300 2 258 259 /* 260 * End of controller registers. 261 */ 262 263 #define SDHCI_MAX_DIV_SPEC_200 256 264 #define SDHCI_MAX_DIV_SPEC_300 2046 265 266 /* 267 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 268 */ 269 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 270 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 271 272 /* ADMA2 32-bit DMA descriptor size */ 273 #define SDHCI_ADMA2_32_DESC_SZ 8 274 275 /* ADMA2 32-bit descriptor */ 276 struct sdhci_adma2_32_desc { 277 __le16 cmd; 278 __le16 len; 279 __le32 addr; 280 } __packed __aligned(4); 281 282 /* ADMA2 data alignment */ 283 #define SDHCI_ADMA2_ALIGN 4 284 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 285 286 /* 287 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 288 * alignment for the descriptor table even in 32-bit DMA mode. Memory 289 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 290 */ 291 #define SDHCI_ADMA2_DESC_ALIGN 8 292 293 /* ADMA2 64-bit DMA descriptor size */ 294 #define SDHCI_ADMA2_64_DESC_SZ 12 295 296 /* 297 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 298 * aligned. 299 */ 300 struct sdhci_adma2_64_desc { 301 __le16 cmd; 302 __le16 len; 303 __le32 addr_lo; 304 __le32 addr_hi; 305 } __packed __aligned(4); 306 307 #define ADMA2_TRAN_VALID 0x21 308 #define ADMA2_NOP_END_VALID 0x3 309 #define ADMA2_END 0x2 310 311 /* 312 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 313 * 4KiB page size. 314 */ 315 #define SDHCI_MAX_SEGS 128 316 317 enum sdhci_cookie { 318 COOKIE_UNMAPPED, 319 COOKIE_MAPPED, 320 COOKIE_GIVEN, 321 }; 322 323 struct sdhci_host { 324 /* Data set by hardware interface driver */ 325 const char *hw_name; /* Hardware bus name */ 326 327 unsigned int quirks; /* Deviations from spec. */ 328 329 /* Controller doesn't honor resets unless we touch the clock register */ 330 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 331 /* Controller has bad caps bits, but really supports DMA */ 332 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 333 /* Controller doesn't like to be reset when there is no card inserted. */ 334 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 335 /* Controller doesn't like clearing the power reg before a change */ 336 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 337 /* Controller has flaky internal state so reset it on each ios change */ 338 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 339 /* Controller has an unusable DMA engine */ 340 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 341 /* Controller has an unusable ADMA engine */ 342 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 343 /* Controller can only DMA from 32-bit aligned addresses */ 344 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 345 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 346 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 347 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 348 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 349 /* Controller needs to be reset after each request to stay stable */ 350 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 351 /* Controller needs voltage and power writes to happen separately */ 352 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 353 /* Controller provides an incorrect timeout value for transfers */ 354 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 355 /* Controller has an issue with buffer bits for small transfers */ 356 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 357 /* Controller does not provide transfer-complete interrupt when not busy */ 358 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 359 /* Controller has unreliable card detection */ 360 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 361 /* Controller reports inverted write-protect state */ 362 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 363 /* Controller does not like fast PIO transfers */ 364 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 365 /* Controller has to be forced to use block size of 2048 bytes */ 366 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 367 /* Controller cannot do multi-block transfers */ 368 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 369 /* Controller can only handle 1-bit data transfers */ 370 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 371 /* Controller needs 10ms delay between applying power and clock */ 372 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 373 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 374 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 375 /* Controller reports wrong base clock capability */ 376 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 377 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 378 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 379 /* Controller is missing device caps. Use caps provided by host */ 380 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 381 /* Controller uses Auto CMD12 command to stop the transfer */ 382 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 383 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 384 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 385 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 386 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 387 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 388 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 389 390 unsigned int quirks2; /* More deviations from spec. */ 391 392 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 393 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 394 /* The system physically doesn't support 1.8v, even if the host does */ 395 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 396 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 397 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 398 /* Controller has a non-standard host control register */ 399 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 400 /* Controller does not support HS200 */ 401 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 402 /* Controller does not support DDR50 */ 403 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 404 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 405 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 406 /* Controller does not support 64-bit DMA */ 407 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 408 /* need clear transfer mode register before send cmd */ 409 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 410 /* Capability register bit-63 indicates HS400 support */ 411 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 412 /* forced tuned clock */ 413 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 414 /* disable the block count for single block transactions */ 415 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 416 /* Controller broken with using ACMD23 */ 417 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 418 /* Broken Clock divider zero in controller */ 419 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 420 /* 421 * When internal clock is disabled, a delay is needed before modifying the 422 * SD clock frequency or enabling back the internal clock. 423 */ 424 #define SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST (1<<16) 425 426 int irq; /* Device IRQ */ 427 void __iomem *ioaddr; /* Mapped address */ 428 429 const struct sdhci_ops *ops; /* Low level hw interface */ 430 431 /* Internal data */ 432 struct mmc_host *mmc; /* MMC structure */ 433 u64 dma_mask; /* custom DMA mask */ 434 435 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 436 struct led_classdev led; /* LED control */ 437 char led_name[32]; 438 #endif 439 440 spinlock_t lock; /* Mutex */ 441 442 int flags; /* Host attributes */ 443 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 444 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 445 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 446 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 447 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 448 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 449 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 450 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 451 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 452 #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ 453 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 454 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 455 456 unsigned int version; /* SDHCI spec. version */ 457 458 unsigned int max_clk; /* Max possible freq (MHz) */ 459 unsigned int timeout_clk; /* Timeout freq (KHz) */ 460 unsigned int clk_mul; /* Clock Muliplier value */ 461 462 unsigned int clock; /* Current clock (MHz) */ 463 u8 pwr; /* Current voltage */ 464 465 bool runtime_suspended; /* Host is runtime suspended */ 466 bool bus_on; /* Bus power prevents runtime suspend */ 467 bool preset_enabled; /* Preset is enabled */ 468 469 struct mmc_request *mrq; /* Current request */ 470 struct mmc_command *cmd; /* Current command */ 471 struct mmc_data *data; /* Current data request */ 472 unsigned int data_early:1; /* Data finished before cmd */ 473 unsigned int busy_handle:1; /* Handling the order of Busy-end */ 474 475 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 476 unsigned int blocks; /* remaining PIO blocks */ 477 478 int sg_count; /* Mapped sg entries */ 479 480 void *adma_table; /* ADMA descriptor table */ 481 void *align_buffer; /* Bounce buffer */ 482 483 size_t adma_table_sz; /* ADMA descriptor table size */ 484 size_t align_buffer_sz; /* Bounce buffer size */ 485 486 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 487 dma_addr_t align_addr; /* Mapped bounce buffer */ 488 489 unsigned int desc_sz; /* ADMA descriptor size */ 490 491 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 492 493 struct timer_list timer; /* Timer for timeouts */ 494 495 u32 caps; /* Alternative CAPABILITY_0 */ 496 u32 caps1; /* Alternative CAPABILITY_1 */ 497 498 unsigned int ocr_avail_sdio; /* OCR bit masks */ 499 unsigned int ocr_avail_sd; 500 unsigned int ocr_avail_mmc; 501 u32 ocr_mask; /* available voltages */ 502 503 unsigned timing; /* Current timing */ 504 505 u32 thread_isr; 506 507 /* cached registers */ 508 u32 ier; 509 510 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 511 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 512 513 unsigned int tuning_count; /* Timer count for re-tuning */ 514 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 515 #define SDHCI_TUNING_MODE_1 0 516 517 unsigned long private[0] ____cacheline_aligned; 518 }; 519 520 struct sdhci_ops { 521 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 522 u32 (*read_l)(struct sdhci_host *host, int reg); 523 u16 (*read_w)(struct sdhci_host *host, int reg); 524 u8 (*read_b)(struct sdhci_host *host, int reg); 525 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 526 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 527 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 528 #endif 529 530 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 531 532 int (*enable_dma)(struct sdhci_host *host); 533 unsigned int (*get_max_clock)(struct sdhci_host *host); 534 unsigned int (*get_min_clock)(struct sdhci_host *host); 535 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 536 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 537 void (*set_timeout)(struct sdhci_host *host, 538 struct mmc_command *cmd); 539 void (*set_bus_width)(struct sdhci_host *host, int width); 540 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 541 u8 power_mode); 542 unsigned int (*get_ro)(struct sdhci_host *host); 543 void (*reset)(struct sdhci_host *host, u8 mask); 544 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 545 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 546 void (*hw_reset)(struct sdhci_host *host); 547 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 548 void (*platform_init)(struct sdhci_host *host); 549 void (*card_event)(struct sdhci_host *host); 550 void (*voltage_switch)(struct sdhci_host *host); 551 int (*select_drive_strength)(struct sdhci_host *host, 552 struct mmc_card *card, 553 unsigned int max_dtr, int host_drv, 554 int card_drv, int *drv_type); 555 }; 556 557 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 558 559 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 560 { 561 if (unlikely(host->ops->write_l)) 562 host->ops->write_l(host, val, reg); 563 else 564 writel(val, host->ioaddr + reg); 565 } 566 567 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 568 { 569 if (unlikely(host->ops->write_w)) 570 host->ops->write_w(host, val, reg); 571 else 572 writew(val, host->ioaddr + reg); 573 } 574 575 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 576 { 577 if (unlikely(host->ops->write_b)) 578 host->ops->write_b(host, val, reg); 579 else 580 writeb(val, host->ioaddr + reg); 581 } 582 583 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 584 { 585 if (unlikely(host->ops->read_l)) 586 return host->ops->read_l(host, reg); 587 else 588 return readl(host->ioaddr + reg); 589 } 590 591 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 592 { 593 if (unlikely(host->ops->read_w)) 594 return host->ops->read_w(host, reg); 595 else 596 return readw(host->ioaddr + reg); 597 } 598 599 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 600 { 601 if (unlikely(host->ops->read_b)) 602 return host->ops->read_b(host, reg); 603 else 604 return readb(host->ioaddr + reg); 605 } 606 607 #else 608 609 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 610 { 611 writel(val, host->ioaddr + reg); 612 } 613 614 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 615 { 616 writew(val, host->ioaddr + reg); 617 } 618 619 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 620 { 621 writeb(val, host->ioaddr + reg); 622 } 623 624 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 625 { 626 return readl(host->ioaddr + reg); 627 } 628 629 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 630 { 631 return readw(host->ioaddr + reg); 632 } 633 634 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 635 { 636 return readb(host->ioaddr + reg); 637 } 638 639 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 640 641 extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 642 size_t priv_size); 643 extern void sdhci_free_host(struct sdhci_host *host); 644 645 static inline void *sdhci_priv(struct sdhci_host *host) 646 { 647 return (void *)host->private; 648 } 649 650 extern void sdhci_card_detect(struct sdhci_host *host); 651 extern int sdhci_add_host(struct sdhci_host *host); 652 extern void sdhci_remove_host(struct sdhci_host *host, int dead); 653 extern void sdhci_send_command(struct sdhci_host *host, 654 struct mmc_command *cmd); 655 656 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 657 { 658 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 659 } 660 661 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 662 void sdhci_set_bus_width(struct sdhci_host *host, int width); 663 void sdhci_reset(struct sdhci_host *host, u8 mask); 664 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 665 666 #ifdef CONFIG_PM 667 extern int sdhci_suspend_host(struct sdhci_host *host); 668 extern int sdhci_resume_host(struct sdhci_host *host); 669 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 670 extern int sdhci_runtime_suspend_host(struct sdhci_host *host); 671 extern int sdhci_runtime_resume_host(struct sdhci_host *host); 672 #endif 673 674 #endif /* __SDHCI_HW_H */ 675