1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/leds.h> 21 #include <linux/interrupt.h> 22 23 #include <linux/mmc/host.h> 24 25 /* 26 * Controller registers 27 */ 28 29 #define SDHCI_DMA_ADDRESS 0x00 30 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 31 32 #define SDHCI_BLOCK_SIZE 0x04 33 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 34 35 #define SDHCI_BLOCK_COUNT 0x06 36 37 #define SDHCI_ARGUMENT 0x08 38 39 #define SDHCI_TRANSFER_MODE 0x0C 40 #define SDHCI_TRNS_DMA 0x01 41 #define SDHCI_TRNS_BLK_CNT_EN 0x02 42 #define SDHCI_TRNS_AUTO_CMD12 0x04 43 #define SDHCI_TRNS_AUTO_CMD23 0x08 44 #define SDHCI_TRNS_READ 0x10 45 #define SDHCI_TRNS_MULTI 0x20 46 47 #define SDHCI_COMMAND 0x0E 48 #define SDHCI_CMD_RESP_MASK 0x03 49 #define SDHCI_CMD_CRC 0x08 50 #define SDHCI_CMD_INDEX 0x10 51 #define SDHCI_CMD_DATA 0x20 52 #define SDHCI_CMD_ABORTCMD 0xC0 53 54 #define SDHCI_CMD_RESP_NONE 0x00 55 #define SDHCI_CMD_RESP_LONG 0x01 56 #define SDHCI_CMD_RESP_SHORT 0x02 57 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 58 59 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 60 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 61 62 #define SDHCI_RESPONSE 0x10 63 64 #define SDHCI_BUFFER 0x20 65 66 #define SDHCI_PRESENT_STATE 0x24 67 #define SDHCI_CMD_INHIBIT 0x00000001 68 #define SDHCI_DATA_INHIBIT 0x00000002 69 #define SDHCI_DOING_WRITE 0x00000100 70 #define SDHCI_DOING_READ 0x00000200 71 #define SDHCI_SPACE_AVAILABLE 0x00000400 72 #define SDHCI_DATA_AVAILABLE 0x00000800 73 #define SDHCI_CARD_PRESENT 0x00010000 74 #define SDHCI_WRITE_PROTECT 0x00080000 75 #define SDHCI_DATA_LVL_MASK 0x00F00000 76 #define SDHCI_DATA_LVL_SHIFT 20 77 #define SDHCI_DATA_0_LVL_MASK 0x00100000 78 #define SDHCI_CMD_LVL 0x01000000 79 80 #define SDHCI_HOST_CONTROL 0x28 81 #define SDHCI_CTRL_LED 0x01 82 #define SDHCI_CTRL_4BITBUS 0x02 83 #define SDHCI_CTRL_HISPD 0x04 84 #define SDHCI_CTRL_DMA_MASK 0x18 85 #define SDHCI_CTRL_SDMA 0x00 86 #define SDHCI_CTRL_ADMA1 0x08 87 #define SDHCI_CTRL_ADMA32 0x10 88 #define SDHCI_CTRL_ADMA64 0x18 89 #define SDHCI_CTRL_8BITBUS 0x20 90 #define SDHCI_CTRL_CDTEST_INS 0x40 91 #define SDHCI_CTRL_CDTEST_EN 0x80 92 93 #define SDHCI_POWER_CONTROL 0x29 94 #define SDHCI_POWER_ON 0x01 95 #define SDHCI_POWER_180 0x0A 96 #define SDHCI_POWER_300 0x0C 97 #define SDHCI_POWER_330 0x0E 98 99 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 100 101 #define SDHCI_WAKE_UP_CONTROL 0x2B 102 #define SDHCI_WAKE_ON_INT 0x01 103 #define SDHCI_WAKE_ON_INSERT 0x02 104 #define SDHCI_WAKE_ON_REMOVE 0x04 105 106 #define SDHCI_CLOCK_CONTROL 0x2C 107 #define SDHCI_DIVIDER_SHIFT 8 108 #define SDHCI_DIVIDER_HI_SHIFT 6 109 #define SDHCI_DIV_MASK 0xFF 110 #define SDHCI_DIV_MASK_LEN 8 111 #define SDHCI_DIV_HI_MASK 0x300 112 #define SDHCI_PROG_CLOCK_MODE 0x0020 113 #define SDHCI_CLOCK_CARD_EN 0x0004 114 #define SDHCI_CLOCK_INT_STABLE 0x0002 115 #define SDHCI_CLOCK_INT_EN 0x0001 116 117 #define SDHCI_TIMEOUT_CONTROL 0x2E 118 119 #define SDHCI_SOFTWARE_RESET 0x2F 120 #define SDHCI_RESET_ALL 0x01 121 #define SDHCI_RESET_CMD 0x02 122 #define SDHCI_RESET_DATA 0x04 123 124 #define SDHCI_INT_STATUS 0x30 125 #define SDHCI_INT_ENABLE 0x34 126 #define SDHCI_SIGNAL_ENABLE 0x38 127 #define SDHCI_INT_RESPONSE 0x00000001 128 #define SDHCI_INT_DATA_END 0x00000002 129 #define SDHCI_INT_BLK_GAP 0x00000004 130 #define SDHCI_INT_DMA_END 0x00000008 131 #define SDHCI_INT_SPACE_AVAIL 0x00000010 132 #define SDHCI_INT_DATA_AVAIL 0x00000020 133 #define SDHCI_INT_CARD_INSERT 0x00000040 134 #define SDHCI_INT_CARD_REMOVE 0x00000080 135 #define SDHCI_INT_CARD_INT 0x00000100 136 #define SDHCI_INT_RETUNE 0x00001000 137 #define SDHCI_INT_CQE 0x00004000 138 #define SDHCI_INT_ERROR 0x00008000 139 #define SDHCI_INT_TIMEOUT 0x00010000 140 #define SDHCI_INT_CRC 0x00020000 141 #define SDHCI_INT_END_BIT 0x00040000 142 #define SDHCI_INT_INDEX 0x00080000 143 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 144 #define SDHCI_INT_DATA_CRC 0x00200000 145 #define SDHCI_INT_DATA_END_BIT 0x00400000 146 #define SDHCI_INT_BUS_POWER 0x00800000 147 #define SDHCI_INT_ACMD12ERR 0x01000000 148 #define SDHCI_INT_ADMA_ERROR 0x02000000 149 150 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 151 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 152 153 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 154 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 155 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 156 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 157 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 158 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 159 SDHCI_INT_BLK_GAP) 160 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 161 162 #define SDHCI_CQE_INT_ERR_MASK ( \ 163 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 164 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 165 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 166 167 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 168 169 #define SDHCI_ACMD12_ERR 0x3C 170 171 #define SDHCI_HOST_CONTROL2 0x3E 172 #define SDHCI_CTRL_UHS_MASK 0x0007 173 #define SDHCI_CTRL_UHS_SDR12 0x0000 174 #define SDHCI_CTRL_UHS_SDR25 0x0001 175 #define SDHCI_CTRL_UHS_SDR50 0x0002 176 #define SDHCI_CTRL_UHS_SDR104 0x0003 177 #define SDHCI_CTRL_UHS_DDR50 0x0004 178 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 179 #define SDHCI_CTRL_VDD_180 0x0008 180 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 181 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 182 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 183 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 184 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 185 #define SDHCI_CTRL_EXEC_TUNING 0x0040 186 #define SDHCI_CTRL_TUNED_CLK 0x0080 187 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 188 189 #define SDHCI_CAPABILITIES 0x40 190 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 191 #define SDHCI_TIMEOUT_CLK_SHIFT 0 192 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 193 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 194 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 195 #define SDHCI_CLOCK_BASE_SHIFT 8 196 #define SDHCI_MAX_BLOCK_MASK 0x00030000 197 #define SDHCI_MAX_BLOCK_SHIFT 16 198 #define SDHCI_CAN_DO_8BIT 0x00040000 199 #define SDHCI_CAN_DO_ADMA2 0x00080000 200 #define SDHCI_CAN_DO_ADMA1 0x00100000 201 #define SDHCI_CAN_DO_HISPD 0x00200000 202 #define SDHCI_CAN_DO_SDMA 0x00400000 203 #define SDHCI_CAN_DO_SUSPEND 0x00800000 204 #define SDHCI_CAN_VDD_330 0x01000000 205 #define SDHCI_CAN_VDD_300 0x02000000 206 #define SDHCI_CAN_VDD_180 0x04000000 207 #define SDHCI_CAN_64BIT 0x10000000 208 209 #define SDHCI_SUPPORT_SDR50 0x00000001 210 #define SDHCI_SUPPORT_SDR104 0x00000002 211 #define SDHCI_SUPPORT_DDR50 0x00000004 212 #define SDHCI_DRIVER_TYPE_A 0x00000010 213 #define SDHCI_DRIVER_TYPE_C 0x00000020 214 #define SDHCI_DRIVER_TYPE_D 0x00000040 215 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 216 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 217 #define SDHCI_USE_SDR50_TUNING 0x00002000 218 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 219 #define SDHCI_RETUNING_MODE_SHIFT 14 220 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 221 #define SDHCI_CLOCK_MUL_SHIFT 16 222 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 223 224 #define SDHCI_CAPABILITIES_1 0x44 225 226 #define SDHCI_MAX_CURRENT 0x48 227 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 228 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 229 #define SDHCI_MAX_CURRENT_330_SHIFT 0 230 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 231 #define SDHCI_MAX_CURRENT_300_SHIFT 8 232 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 233 #define SDHCI_MAX_CURRENT_180_SHIFT 16 234 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 235 236 /* 4C-4F reserved for more max current */ 237 238 #define SDHCI_SET_ACMD12_ERROR 0x50 239 #define SDHCI_SET_INT_ERROR 0x52 240 241 #define SDHCI_ADMA_ERROR 0x54 242 243 /* 55-57 reserved */ 244 245 #define SDHCI_ADMA_ADDRESS 0x58 246 #define SDHCI_ADMA_ADDRESS_HI 0x5C 247 248 /* 60-FB reserved */ 249 250 #define SDHCI_PRESET_FOR_SDR12 0x66 251 #define SDHCI_PRESET_FOR_SDR25 0x68 252 #define SDHCI_PRESET_FOR_SDR50 0x6A 253 #define SDHCI_PRESET_FOR_SDR104 0x6C 254 #define SDHCI_PRESET_FOR_DDR50 0x6E 255 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 256 #define SDHCI_PRESET_DRV_MASK 0xC000 257 #define SDHCI_PRESET_DRV_SHIFT 14 258 #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 259 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 260 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 261 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 262 263 #define SDHCI_SLOT_INT_STATUS 0xFC 264 265 #define SDHCI_HOST_VERSION 0xFE 266 #define SDHCI_VENDOR_VER_MASK 0xFF00 267 #define SDHCI_VENDOR_VER_SHIFT 8 268 #define SDHCI_SPEC_VER_MASK 0x00FF 269 #define SDHCI_SPEC_VER_SHIFT 0 270 #define SDHCI_SPEC_100 0 271 #define SDHCI_SPEC_200 1 272 #define SDHCI_SPEC_300 2 273 274 /* 275 * End of controller registers. 276 */ 277 278 #define SDHCI_MAX_DIV_SPEC_200 256 279 #define SDHCI_MAX_DIV_SPEC_300 2046 280 281 /* 282 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 283 */ 284 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 285 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 286 287 /* ADMA2 32-bit DMA descriptor size */ 288 #define SDHCI_ADMA2_32_DESC_SZ 8 289 290 /* ADMA2 32-bit descriptor */ 291 struct sdhci_adma2_32_desc { 292 __le16 cmd; 293 __le16 len; 294 __le32 addr; 295 } __packed __aligned(4); 296 297 /* ADMA2 data alignment */ 298 #define SDHCI_ADMA2_ALIGN 4 299 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 300 301 /* 302 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 303 * alignment for the descriptor table even in 32-bit DMA mode. Memory 304 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 305 */ 306 #define SDHCI_ADMA2_DESC_ALIGN 8 307 308 /* ADMA2 64-bit DMA descriptor size */ 309 #define SDHCI_ADMA2_64_DESC_SZ 12 310 311 /* 312 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 313 * aligned. 314 */ 315 struct sdhci_adma2_64_desc { 316 __le16 cmd; 317 __le16 len; 318 __le32 addr_lo; 319 __le32 addr_hi; 320 } __packed __aligned(4); 321 322 #define ADMA2_TRAN_VALID 0x21 323 #define ADMA2_NOP_END_VALID 0x3 324 #define ADMA2_END 0x2 325 326 /* 327 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 328 * 4KiB page size. 329 */ 330 #define SDHCI_MAX_SEGS 128 331 332 /* Allow for a a command request and a data request at the same time */ 333 #define SDHCI_MAX_MRQS 2 334 335 /* 336 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 337 * However since the start time of the command, the time between 338 * command and response, and the time between response and start of data is 339 * not known, set the command transfer time to 10ms. 340 */ 341 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 342 343 enum sdhci_cookie { 344 COOKIE_UNMAPPED, 345 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 346 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 347 }; 348 349 struct sdhci_host { 350 /* Data set by hardware interface driver */ 351 const char *hw_name; /* Hardware bus name */ 352 353 unsigned int quirks; /* Deviations from spec. */ 354 355 /* Controller doesn't honor resets unless we touch the clock register */ 356 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 357 /* Controller has bad caps bits, but really supports DMA */ 358 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 359 /* Controller doesn't like to be reset when there is no card inserted. */ 360 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 361 /* Controller doesn't like clearing the power reg before a change */ 362 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 363 /* Controller has flaky internal state so reset it on each ios change */ 364 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 365 /* Controller has an unusable DMA engine */ 366 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 367 /* Controller has an unusable ADMA engine */ 368 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 369 /* Controller can only DMA from 32-bit aligned addresses */ 370 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 371 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 372 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 373 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 374 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 375 /* Controller needs to be reset after each request to stay stable */ 376 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 377 /* Controller needs voltage and power writes to happen separately */ 378 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 379 /* Controller provides an incorrect timeout value for transfers */ 380 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 381 /* Controller has an issue with buffer bits for small transfers */ 382 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 383 /* Controller does not provide transfer-complete interrupt when not busy */ 384 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 385 /* Controller has unreliable card detection */ 386 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 387 /* Controller reports inverted write-protect state */ 388 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 389 /* Controller does not like fast PIO transfers */ 390 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 391 /* Controller has to be forced to use block size of 2048 bytes */ 392 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 393 /* Controller cannot do multi-block transfers */ 394 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 395 /* Controller can only handle 1-bit data transfers */ 396 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 397 /* Controller needs 10ms delay between applying power and clock */ 398 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 399 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 400 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 401 /* Controller reports wrong base clock capability */ 402 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 403 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 404 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 405 /* Controller is missing device caps. Use caps provided by host */ 406 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 407 /* Controller uses Auto CMD12 command to stop the transfer */ 408 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 409 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 410 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 411 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 412 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 413 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 414 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 415 416 unsigned int quirks2; /* More deviations from spec. */ 417 418 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 419 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 420 /* The system physically doesn't support 1.8v, even if the host does */ 421 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 422 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 423 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 424 /* Controller has a non-standard host control register */ 425 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 426 /* Controller does not support HS200 */ 427 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 428 /* Controller does not support DDR50 */ 429 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 430 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 431 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 432 /* Controller does not support 64-bit DMA */ 433 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 434 /* need clear transfer mode register before send cmd */ 435 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 436 /* Capability register bit-63 indicates HS400 support */ 437 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 438 /* forced tuned clock */ 439 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 440 /* disable the block count for single block transactions */ 441 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 442 /* Controller broken with using ACMD23 */ 443 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 444 /* Broken Clock divider zero in controller */ 445 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 446 /* Controller has CRC in 136 bit Command Response */ 447 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 448 /* 449 * Disable HW timeout if the requested timeout is more than the maximum 450 * obtainable timeout. 451 */ 452 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 453 454 int irq; /* Device IRQ */ 455 void __iomem *ioaddr; /* Mapped address */ 456 char *bounce_buffer; /* For packing SDMA reads/writes */ 457 dma_addr_t bounce_addr; 458 unsigned int bounce_buffer_size; 459 460 const struct sdhci_ops *ops; /* Low level hw interface */ 461 462 /* Internal data */ 463 struct mmc_host *mmc; /* MMC structure */ 464 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 465 u64 dma_mask; /* custom DMA mask */ 466 467 #if IS_ENABLED(CONFIG_LEDS_CLASS) 468 struct led_classdev led; /* LED control */ 469 char led_name[32]; 470 #endif 471 472 spinlock_t lock; /* Mutex */ 473 474 int flags; /* Host attributes */ 475 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 476 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 477 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 478 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 479 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 480 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 481 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 482 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 483 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 484 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 485 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 486 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 487 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 488 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 489 490 unsigned int version; /* SDHCI spec. version */ 491 492 unsigned int max_clk; /* Max possible freq (MHz) */ 493 unsigned int timeout_clk; /* Timeout freq (KHz) */ 494 unsigned int clk_mul; /* Clock Muliplier value */ 495 496 unsigned int clock; /* Current clock (MHz) */ 497 u8 pwr; /* Current voltage */ 498 499 bool runtime_suspended; /* Host is runtime suspended */ 500 bool bus_on; /* Bus power prevents runtime suspend */ 501 bool preset_enabled; /* Preset is enabled */ 502 bool pending_reset; /* Cmd/data reset is pending */ 503 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 504 505 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 506 struct mmc_command *cmd; /* Current command */ 507 struct mmc_command *data_cmd; /* Current data command */ 508 struct mmc_data *data; /* Current data request */ 509 unsigned int data_early:1; /* Data finished before cmd */ 510 511 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 512 unsigned int blocks; /* remaining PIO blocks */ 513 514 int sg_count; /* Mapped sg entries */ 515 516 void *adma_table; /* ADMA descriptor table */ 517 void *align_buffer; /* Bounce buffer */ 518 519 size_t adma_table_sz; /* ADMA descriptor table size */ 520 size_t align_buffer_sz; /* Bounce buffer size */ 521 522 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 523 dma_addr_t align_addr; /* Mapped bounce buffer */ 524 525 unsigned int desc_sz; /* ADMA descriptor size */ 526 527 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 528 529 struct timer_list timer; /* Timer for timeouts */ 530 struct timer_list data_timer; /* Timer for data timeouts */ 531 532 u32 caps; /* CAPABILITY_0 */ 533 u32 caps1; /* CAPABILITY_1 */ 534 bool read_caps; /* Capability flags have been read */ 535 536 unsigned int ocr_avail_sdio; /* OCR bit masks */ 537 unsigned int ocr_avail_sd; 538 unsigned int ocr_avail_mmc; 539 u32 ocr_mask; /* available voltages */ 540 541 unsigned timing; /* Current timing */ 542 543 u32 thread_isr; 544 545 /* cached registers */ 546 u32 ier; 547 548 bool cqe_on; /* CQE is operating */ 549 u32 cqe_ier; /* CQE interrupt mask */ 550 u32 cqe_err_ier; /* CQE error interrupt mask */ 551 552 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 553 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 554 555 unsigned int tuning_count; /* Timer count for re-tuning */ 556 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 557 #define SDHCI_TUNING_MODE_1 0 558 #define SDHCI_TUNING_MODE_2 1 559 #define SDHCI_TUNING_MODE_3 2 560 /* Delay (ms) between tuning commands */ 561 int tuning_delay; 562 563 /* Host SDMA buffer boundary. */ 564 u32 sdma_boundary; 565 566 u64 data_timeout; 567 568 unsigned long private[0] ____cacheline_aligned; 569 }; 570 571 struct sdhci_ops { 572 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 573 u32 (*read_l)(struct sdhci_host *host, int reg); 574 u16 (*read_w)(struct sdhci_host *host, int reg); 575 u8 (*read_b)(struct sdhci_host *host, int reg); 576 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 577 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 578 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 579 #endif 580 581 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 582 void (*set_power)(struct sdhci_host *host, unsigned char mode, 583 unsigned short vdd); 584 585 u32 (*irq)(struct sdhci_host *host, u32 intmask); 586 587 int (*enable_dma)(struct sdhci_host *host); 588 unsigned int (*get_max_clock)(struct sdhci_host *host); 589 unsigned int (*get_min_clock)(struct sdhci_host *host); 590 /* get_timeout_clock should return clk rate in unit of Hz */ 591 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 592 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 593 void (*set_timeout)(struct sdhci_host *host, 594 struct mmc_command *cmd); 595 void (*set_bus_width)(struct sdhci_host *host, int width); 596 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 597 u8 power_mode); 598 unsigned int (*get_ro)(struct sdhci_host *host); 599 void (*reset)(struct sdhci_host *host, u8 mask); 600 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 601 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 602 void (*hw_reset)(struct sdhci_host *host); 603 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 604 void (*card_event)(struct sdhci_host *host); 605 void (*voltage_switch)(struct sdhci_host *host); 606 }; 607 608 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 609 610 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 611 { 612 if (unlikely(host->ops->write_l)) 613 host->ops->write_l(host, val, reg); 614 else 615 writel(val, host->ioaddr + reg); 616 } 617 618 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 619 { 620 if (unlikely(host->ops->write_w)) 621 host->ops->write_w(host, val, reg); 622 else 623 writew(val, host->ioaddr + reg); 624 } 625 626 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 627 { 628 if (unlikely(host->ops->write_b)) 629 host->ops->write_b(host, val, reg); 630 else 631 writeb(val, host->ioaddr + reg); 632 } 633 634 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 635 { 636 if (unlikely(host->ops->read_l)) 637 return host->ops->read_l(host, reg); 638 else 639 return readl(host->ioaddr + reg); 640 } 641 642 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 643 { 644 if (unlikely(host->ops->read_w)) 645 return host->ops->read_w(host, reg); 646 else 647 return readw(host->ioaddr + reg); 648 } 649 650 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 651 { 652 if (unlikely(host->ops->read_b)) 653 return host->ops->read_b(host, reg); 654 else 655 return readb(host->ioaddr + reg); 656 } 657 658 #else 659 660 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 661 { 662 writel(val, host->ioaddr + reg); 663 } 664 665 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 666 { 667 writew(val, host->ioaddr + reg); 668 } 669 670 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 671 { 672 writeb(val, host->ioaddr + reg); 673 } 674 675 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 676 { 677 return readl(host->ioaddr + reg); 678 } 679 680 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 681 { 682 return readw(host->ioaddr + reg); 683 } 684 685 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 686 { 687 return readb(host->ioaddr + reg); 688 } 689 690 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 691 692 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 693 void sdhci_free_host(struct sdhci_host *host); 694 695 static inline void *sdhci_priv(struct sdhci_host *host) 696 { 697 return host->private; 698 } 699 700 void sdhci_card_detect(struct sdhci_host *host); 701 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 702 u32 *caps1); 703 int sdhci_setup_host(struct sdhci_host *host); 704 void sdhci_cleanup_host(struct sdhci_host *host); 705 int __sdhci_add_host(struct sdhci_host *host); 706 int sdhci_add_host(struct sdhci_host *host); 707 void sdhci_remove_host(struct sdhci_host *host, int dead); 708 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 709 710 static inline void sdhci_read_caps(struct sdhci_host *host) 711 { 712 __sdhci_read_caps(host, NULL, NULL, NULL); 713 } 714 715 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 716 { 717 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 718 } 719 720 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 721 unsigned int *actual_clock); 722 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 723 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 724 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 725 unsigned short vdd); 726 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 727 unsigned short vdd); 728 void sdhci_set_bus_width(struct sdhci_host *host, int width); 729 void sdhci_reset(struct sdhci_host *host, u8 mask); 730 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 731 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 732 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 733 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 734 struct mmc_ios *ios); 735 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 736 737 #ifdef CONFIG_PM 738 int sdhci_suspend_host(struct sdhci_host *host); 739 int sdhci_resume_host(struct sdhci_host *host); 740 int sdhci_runtime_suspend_host(struct sdhci_host *host); 741 int sdhci_runtime_resume_host(struct sdhci_host *host); 742 #endif 743 744 void sdhci_cqe_enable(struct mmc_host *mmc); 745 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 746 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 747 int *data_error); 748 749 void sdhci_dumpregs(struct sdhci_host *host); 750 751 #endif /* __SDHCI_HW_H */ 752