1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 21 #include <linux/mmc/host.h> 22 23 /* 24 * Controller registers 25 */ 26 27 #define SDHCI_DMA_ADDRESS 0x00 28 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_READ 0x10 43 #define SDHCI_TRNS_MULTI 0x20 44 45 #define SDHCI_COMMAND 0x0E 46 #define SDHCI_CMD_RESP_MASK 0x03 47 #define SDHCI_CMD_CRC 0x08 48 #define SDHCI_CMD_INDEX 0x10 49 #define SDHCI_CMD_DATA 0x20 50 #define SDHCI_CMD_ABORTCMD 0xC0 51 52 #define SDHCI_CMD_RESP_NONE 0x00 53 #define SDHCI_CMD_RESP_LONG 0x01 54 #define SDHCI_CMD_RESP_SHORT 0x02 55 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 56 57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 59 60 #define SDHCI_RESPONSE 0x10 61 62 #define SDHCI_BUFFER 0x20 63 64 #define SDHCI_PRESENT_STATE 0x24 65 #define SDHCI_CMD_INHIBIT 0x00000001 66 #define SDHCI_DATA_INHIBIT 0x00000002 67 #define SDHCI_DOING_WRITE 0x00000100 68 #define SDHCI_DOING_READ 0x00000200 69 #define SDHCI_SPACE_AVAILABLE 0x00000400 70 #define SDHCI_DATA_AVAILABLE 0x00000800 71 #define SDHCI_CARD_PRESENT 0x00010000 72 #define SDHCI_WRITE_PROTECT 0x00080000 73 #define SDHCI_DATA_LVL_MASK 0x00F00000 74 #define SDHCI_DATA_LVL_SHIFT 20 75 #define SDHCI_DATA_0_LVL_MASK 0x00100000 76 #define SDHCI_CMD_LVL 0x01000000 77 78 #define SDHCI_HOST_CONTROL 0x28 79 #define SDHCI_CTRL_LED 0x01 80 #define SDHCI_CTRL_4BITBUS 0x02 81 #define SDHCI_CTRL_HISPD 0x04 82 #define SDHCI_CTRL_DMA_MASK 0x18 83 #define SDHCI_CTRL_SDMA 0x00 84 #define SDHCI_CTRL_ADMA1 0x08 85 #define SDHCI_CTRL_ADMA32 0x10 86 #define SDHCI_CTRL_ADMA64 0x18 87 #define SDHCI_CTRL_8BITBUS 0x20 88 #define SDHCI_CTRL_CDTEST_INS 0x40 89 #define SDHCI_CTRL_CDTEST_EN 0x80 90 91 #define SDHCI_POWER_CONTROL 0x29 92 #define SDHCI_POWER_ON 0x01 93 #define SDHCI_POWER_180 0x0A 94 #define SDHCI_POWER_300 0x0C 95 #define SDHCI_POWER_330 0x0E 96 97 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 98 99 #define SDHCI_WAKE_UP_CONTROL 0x2B 100 #define SDHCI_WAKE_ON_INT 0x01 101 #define SDHCI_WAKE_ON_INSERT 0x02 102 #define SDHCI_WAKE_ON_REMOVE 0x04 103 104 #define SDHCI_CLOCK_CONTROL 0x2C 105 #define SDHCI_DIVIDER_SHIFT 8 106 #define SDHCI_DIVIDER_HI_SHIFT 6 107 #define SDHCI_DIV_MASK 0xFF 108 #define SDHCI_DIV_MASK_LEN 8 109 #define SDHCI_DIV_HI_MASK 0x300 110 #define SDHCI_PROG_CLOCK_MODE 0x0020 111 #define SDHCI_CLOCK_CARD_EN 0x0004 112 #define SDHCI_CLOCK_INT_STABLE 0x0002 113 #define SDHCI_CLOCK_INT_EN 0x0001 114 115 #define SDHCI_TIMEOUT_CONTROL 0x2E 116 117 #define SDHCI_SOFTWARE_RESET 0x2F 118 #define SDHCI_RESET_ALL 0x01 119 #define SDHCI_RESET_CMD 0x02 120 #define SDHCI_RESET_DATA 0x04 121 122 #define SDHCI_INT_STATUS 0x30 123 #define SDHCI_INT_ENABLE 0x34 124 #define SDHCI_SIGNAL_ENABLE 0x38 125 #define SDHCI_INT_RESPONSE 0x00000001 126 #define SDHCI_INT_DATA_END 0x00000002 127 #define SDHCI_INT_BLK_GAP 0x00000004 128 #define SDHCI_INT_DMA_END 0x00000008 129 #define SDHCI_INT_SPACE_AVAIL 0x00000010 130 #define SDHCI_INT_DATA_AVAIL 0x00000020 131 #define SDHCI_INT_CARD_INSERT 0x00000040 132 #define SDHCI_INT_CARD_REMOVE 0x00000080 133 #define SDHCI_INT_CARD_INT 0x00000100 134 #define SDHCI_INT_RETUNE 0x00001000 135 #define SDHCI_INT_ERROR 0x00008000 136 #define SDHCI_INT_TIMEOUT 0x00010000 137 #define SDHCI_INT_CRC 0x00020000 138 #define SDHCI_INT_END_BIT 0x00040000 139 #define SDHCI_INT_INDEX 0x00080000 140 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 141 #define SDHCI_INT_DATA_CRC 0x00200000 142 #define SDHCI_INT_DATA_END_BIT 0x00400000 143 #define SDHCI_INT_BUS_POWER 0x00800000 144 #define SDHCI_INT_ACMD12ERR 0x01000000 145 #define SDHCI_INT_ADMA_ERROR 0x02000000 146 147 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 148 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 149 150 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 151 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 152 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 153 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 154 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 155 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 156 SDHCI_INT_BLK_GAP) 157 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 158 159 #define SDHCI_ACMD12_ERR 0x3C 160 161 #define SDHCI_HOST_CONTROL2 0x3E 162 #define SDHCI_CTRL_UHS_MASK 0x0007 163 #define SDHCI_CTRL_UHS_SDR12 0x0000 164 #define SDHCI_CTRL_UHS_SDR25 0x0001 165 #define SDHCI_CTRL_UHS_SDR50 0x0002 166 #define SDHCI_CTRL_UHS_SDR104 0x0003 167 #define SDHCI_CTRL_UHS_DDR50 0x0004 168 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 169 #define SDHCI_CTRL_VDD_180 0x0008 170 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 171 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 172 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 173 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 174 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 175 #define SDHCI_CTRL_EXEC_TUNING 0x0040 176 #define SDHCI_CTRL_TUNED_CLK 0x0080 177 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 178 179 #define SDHCI_CAPABILITIES 0x40 180 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 181 #define SDHCI_TIMEOUT_CLK_SHIFT 0 182 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 183 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 184 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 185 #define SDHCI_CLOCK_BASE_SHIFT 8 186 #define SDHCI_MAX_BLOCK_MASK 0x00030000 187 #define SDHCI_MAX_BLOCK_SHIFT 16 188 #define SDHCI_CAN_DO_8BIT 0x00040000 189 #define SDHCI_CAN_DO_ADMA2 0x00080000 190 #define SDHCI_CAN_DO_ADMA1 0x00100000 191 #define SDHCI_CAN_DO_HISPD 0x00200000 192 #define SDHCI_CAN_DO_SDMA 0x00400000 193 #define SDHCI_CAN_DO_SUSPEND 0x00800000 194 #define SDHCI_CAN_VDD_330 0x01000000 195 #define SDHCI_CAN_VDD_300 0x02000000 196 #define SDHCI_CAN_VDD_180 0x04000000 197 #define SDHCI_CAN_64BIT 0x10000000 198 199 #define SDHCI_SUPPORT_SDR50 0x00000001 200 #define SDHCI_SUPPORT_SDR104 0x00000002 201 #define SDHCI_SUPPORT_DDR50 0x00000004 202 #define SDHCI_DRIVER_TYPE_A 0x00000010 203 #define SDHCI_DRIVER_TYPE_C 0x00000020 204 #define SDHCI_DRIVER_TYPE_D 0x00000040 205 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 206 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 207 #define SDHCI_USE_SDR50_TUNING 0x00002000 208 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 209 #define SDHCI_RETUNING_MODE_SHIFT 14 210 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 211 #define SDHCI_CLOCK_MUL_SHIFT 16 212 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 213 214 #define SDHCI_CAPABILITIES_1 0x44 215 216 #define SDHCI_MAX_CURRENT 0x48 217 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 218 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 219 #define SDHCI_MAX_CURRENT_330_SHIFT 0 220 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 221 #define SDHCI_MAX_CURRENT_300_SHIFT 8 222 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 223 #define SDHCI_MAX_CURRENT_180_SHIFT 16 224 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 225 226 /* 4C-4F reserved for more max current */ 227 228 #define SDHCI_SET_ACMD12_ERROR 0x50 229 #define SDHCI_SET_INT_ERROR 0x52 230 231 #define SDHCI_ADMA_ERROR 0x54 232 233 /* 55-57 reserved */ 234 235 #define SDHCI_ADMA_ADDRESS 0x58 236 #define SDHCI_ADMA_ADDRESS_HI 0x5C 237 238 /* 60-FB reserved */ 239 240 #define SDHCI_PRESET_FOR_SDR12 0x66 241 #define SDHCI_PRESET_FOR_SDR25 0x68 242 #define SDHCI_PRESET_FOR_SDR50 0x6A 243 #define SDHCI_PRESET_FOR_SDR104 0x6C 244 #define SDHCI_PRESET_FOR_DDR50 0x6E 245 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 246 #define SDHCI_PRESET_DRV_MASK 0xC000 247 #define SDHCI_PRESET_DRV_SHIFT 14 248 #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 249 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 250 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 251 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 252 253 #define SDHCI_SLOT_INT_STATUS 0xFC 254 255 #define SDHCI_HOST_VERSION 0xFE 256 #define SDHCI_VENDOR_VER_MASK 0xFF00 257 #define SDHCI_VENDOR_VER_SHIFT 8 258 #define SDHCI_SPEC_VER_MASK 0x00FF 259 #define SDHCI_SPEC_VER_SHIFT 0 260 #define SDHCI_SPEC_100 0 261 #define SDHCI_SPEC_200 1 262 #define SDHCI_SPEC_300 2 263 264 /* 265 * End of controller registers. 266 */ 267 268 #define SDHCI_MAX_DIV_SPEC_200 256 269 #define SDHCI_MAX_DIV_SPEC_300 2046 270 271 /* 272 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 273 */ 274 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 275 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 276 277 /* ADMA2 32-bit DMA descriptor size */ 278 #define SDHCI_ADMA2_32_DESC_SZ 8 279 280 /* ADMA2 32-bit descriptor */ 281 struct sdhci_adma2_32_desc { 282 __le16 cmd; 283 __le16 len; 284 __le32 addr; 285 } __packed __aligned(4); 286 287 /* ADMA2 data alignment */ 288 #define SDHCI_ADMA2_ALIGN 4 289 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 290 291 /* 292 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 293 * alignment for the descriptor table even in 32-bit DMA mode. Memory 294 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 295 */ 296 #define SDHCI_ADMA2_DESC_ALIGN 8 297 298 /* ADMA2 64-bit DMA descriptor size */ 299 #define SDHCI_ADMA2_64_DESC_SZ 12 300 301 /* 302 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 303 * aligned. 304 */ 305 struct sdhci_adma2_64_desc { 306 __le16 cmd; 307 __le16 len; 308 __le32 addr_lo; 309 __le32 addr_hi; 310 } __packed __aligned(4); 311 312 #define ADMA2_TRAN_VALID 0x21 313 #define ADMA2_NOP_END_VALID 0x3 314 #define ADMA2_END 0x2 315 316 /* 317 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 318 * 4KiB page size. 319 */ 320 #define SDHCI_MAX_SEGS 128 321 322 /* Allow for a a command request and a data request at the same time */ 323 #define SDHCI_MAX_MRQS 2 324 325 enum sdhci_cookie { 326 COOKIE_UNMAPPED, 327 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 328 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 329 }; 330 331 struct sdhci_host { 332 /* Data set by hardware interface driver */ 333 const char *hw_name; /* Hardware bus name */ 334 335 unsigned int quirks; /* Deviations from spec. */ 336 337 /* Controller doesn't honor resets unless we touch the clock register */ 338 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 339 /* Controller has bad caps bits, but really supports DMA */ 340 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 341 /* Controller doesn't like to be reset when there is no card inserted. */ 342 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 343 /* Controller doesn't like clearing the power reg before a change */ 344 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 345 /* Controller has flaky internal state so reset it on each ios change */ 346 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 347 /* Controller has an unusable DMA engine */ 348 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 349 /* Controller has an unusable ADMA engine */ 350 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 351 /* Controller can only DMA from 32-bit aligned addresses */ 352 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 353 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 354 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 355 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 356 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 357 /* Controller needs to be reset after each request to stay stable */ 358 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 359 /* Controller needs voltage and power writes to happen separately */ 360 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 361 /* Controller provides an incorrect timeout value for transfers */ 362 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 363 /* Controller has an issue with buffer bits for small transfers */ 364 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 365 /* Controller does not provide transfer-complete interrupt when not busy */ 366 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 367 /* Controller has unreliable card detection */ 368 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 369 /* Controller reports inverted write-protect state */ 370 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 371 /* Controller does not like fast PIO transfers */ 372 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 373 /* Controller has to be forced to use block size of 2048 bytes */ 374 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 375 /* Controller cannot do multi-block transfers */ 376 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 377 /* Controller can only handle 1-bit data transfers */ 378 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 379 /* Controller needs 10ms delay between applying power and clock */ 380 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 381 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 382 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 383 /* Controller reports wrong base clock capability */ 384 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 385 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 386 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 387 /* Controller is missing device caps. Use caps provided by host */ 388 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 389 /* Controller uses Auto CMD12 command to stop the transfer */ 390 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 391 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 392 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 393 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 394 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 395 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 396 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 397 398 unsigned int quirks2; /* More deviations from spec. */ 399 400 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 401 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 402 /* The system physically doesn't support 1.8v, even if the host does */ 403 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 404 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 405 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 406 /* Controller has a non-standard host control register */ 407 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 408 /* Controller does not support HS200 */ 409 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 410 /* Controller does not support DDR50 */ 411 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 412 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 413 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 414 /* Controller does not support 64-bit DMA */ 415 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 416 /* need clear transfer mode register before send cmd */ 417 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 418 /* Capability register bit-63 indicates HS400 support */ 419 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 420 /* forced tuned clock */ 421 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 422 /* disable the block count for single block transactions */ 423 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 424 /* Controller broken with using ACMD23 */ 425 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 426 /* Broken Clock divider zero in controller */ 427 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 428 429 int irq; /* Device IRQ */ 430 void __iomem *ioaddr; /* Mapped address */ 431 432 const struct sdhci_ops *ops; /* Low level hw interface */ 433 434 /* Internal data */ 435 struct mmc_host *mmc; /* MMC structure */ 436 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 437 u64 dma_mask; /* custom DMA mask */ 438 439 #if IS_ENABLED(CONFIG_LEDS_CLASS) 440 struct led_classdev led; /* LED control */ 441 char led_name[32]; 442 #endif 443 444 spinlock_t lock; /* Mutex */ 445 446 int flags; /* Host attributes */ 447 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 448 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 449 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 450 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 451 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 452 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 453 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 454 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 455 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 456 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 457 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 458 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 459 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 460 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 461 462 unsigned int version; /* SDHCI spec. version */ 463 464 unsigned int max_clk; /* Max possible freq (MHz) */ 465 unsigned int timeout_clk; /* Timeout freq (KHz) */ 466 unsigned int clk_mul; /* Clock Muliplier value */ 467 468 unsigned int clock; /* Current clock (MHz) */ 469 u8 pwr; /* Current voltage */ 470 471 bool runtime_suspended; /* Host is runtime suspended */ 472 bool bus_on; /* Bus power prevents runtime suspend */ 473 bool preset_enabled; /* Preset is enabled */ 474 bool pending_reset; /* Cmd/data reset is pending */ 475 476 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 477 struct mmc_command *cmd; /* Current command */ 478 struct mmc_command *data_cmd; /* Current data command */ 479 struct mmc_data *data; /* Current data request */ 480 unsigned int data_early:1; /* Data finished before cmd */ 481 482 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 483 unsigned int blocks; /* remaining PIO blocks */ 484 485 int sg_count; /* Mapped sg entries */ 486 487 void *adma_table; /* ADMA descriptor table */ 488 void *align_buffer; /* Bounce buffer */ 489 490 size_t adma_table_sz; /* ADMA descriptor table size */ 491 size_t align_buffer_sz; /* Bounce buffer size */ 492 493 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 494 dma_addr_t align_addr; /* Mapped bounce buffer */ 495 496 unsigned int desc_sz; /* ADMA descriptor size */ 497 498 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 499 500 struct timer_list timer; /* Timer for timeouts */ 501 struct timer_list data_timer; /* Timer for data timeouts */ 502 503 u32 caps; /* CAPABILITY_0 */ 504 u32 caps1; /* CAPABILITY_1 */ 505 bool read_caps; /* Capability flags have been read */ 506 507 unsigned int ocr_avail_sdio; /* OCR bit masks */ 508 unsigned int ocr_avail_sd; 509 unsigned int ocr_avail_mmc; 510 u32 ocr_mask; /* available voltages */ 511 512 unsigned timing; /* Current timing */ 513 514 u32 thread_isr; 515 516 /* cached registers */ 517 u32 ier; 518 519 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 520 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 521 522 unsigned int tuning_count; /* Timer count for re-tuning */ 523 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 524 #define SDHCI_TUNING_MODE_1 0 525 #define SDHCI_TUNING_MODE_2 1 526 #define SDHCI_TUNING_MODE_3 2 527 528 unsigned long private[0] ____cacheline_aligned; 529 }; 530 531 struct sdhci_ops { 532 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 533 u32 (*read_l)(struct sdhci_host *host, int reg); 534 u16 (*read_w)(struct sdhci_host *host, int reg); 535 u8 (*read_b)(struct sdhci_host *host, int reg); 536 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 537 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 538 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 539 #endif 540 541 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 542 void (*set_power)(struct sdhci_host *host, unsigned char mode, 543 unsigned short vdd); 544 545 int (*enable_dma)(struct sdhci_host *host); 546 unsigned int (*get_max_clock)(struct sdhci_host *host); 547 unsigned int (*get_min_clock)(struct sdhci_host *host); 548 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 549 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 550 void (*set_timeout)(struct sdhci_host *host, 551 struct mmc_command *cmd); 552 void (*set_bus_width)(struct sdhci_host *host, int width); 553 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 554 u8 power_mode); 555 unsigned int (*get_ro)(struct sdhci_host *host); 556 void (*reset)(struct sdhci_host *host, u8 mask); 557 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 558 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 559 void (*hw_reset)(struct sdhci_host *host); 560 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 561 void (*card_event)(struct sdhci_host *host); 562 void (*voltage_switch)(struct sdhci_host *host); 563 int (*select_drive_strength)(struct sdhci_host *host, 564 struct mmc_card *card, 565 unsigned int max_dtr, int host_drv, 566 int card_drv, int *drv_type); 567 }; 568 569 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 570 571 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 572 { 573 if (unlikely(host->ops->write_l)) 574 host->ops->write_l(host, val, reg); 575 else 576 writel(val, host->ioaddr + reg); 577 } 578 579 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 580 { 581 if (unlikely(host->ops->write_w)) 582 host->ops->write_w(host, val, reg); 583 else 584 writew(val, host->ioaddr + reg); 585 } 586 587 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 588 { 589 if (unlikely(host->ops->write_b)) 590 host->ops->write_b(host, val, reg); 591 else 592 writeb(val, host->ioaddr + reg); 593 } 594 595 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 596 { 597 if (unlikely(host->ops->read_l)) 598 return host->ops->read_l(host, reg); 599 else 600 return readl(host->ioaddr + reg); 601 } 602 603 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 604 { 605 if (unlikely(host->ops->read_w)) 606 return host->ops->read_w(host, reg); 607 else 608 return readw(host->ioaddr + reg); 609 } 610 611 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 612 { 613 if (unlikely(host->ops->read_b)) 614 return host->ops->read_b(host, reg); 615 else 616 return readb(host->ioaddr + reg); 617 } 618 619 #else 620 621 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 622 { 623 writel(val, host->ioaddr + reg); 624 } 625 626 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 627 { 628 writew(val, host->ioaddr + reg); 629 } 630 631 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 632 { 633 writeb(val, host->ioaddr + reg); 634 } 635 636 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 637 { 638 return readl(host->ioaddr + reg); 639 } 640 641 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 642 { 643 return readw(host->ioaddr + reg); 644 } 645 646 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 647 { 648 return readb(host->ioaddr + reg); 649 } 650 651 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 652 653 extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 654 size_t priv_size); 655 extern void sdhci_free_host(struct sdhci_host *host); 656 657 static inline void *sdhci_priv(struct sdhci_host *host) 658 { 659 return host->private; 660 } 661 662 extern void sdhci_card_detect(struct sdhci_host *host); 663 extern void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 664 u32 *caps1); 665 extern int sdhci_setup_host(struct sdhci_host *host); 666 extern int __sdhci_add_host(struct sdhci_host *host); 667 extern int sdhci_add_host(struct sdhci_host *host); 668 extern void sdhci_remove_host(struct sdhci_host *host, int dead); 669 extern void sdhci_send_command(struct sdhci_host *host, 670 struct mmc_command *cmd); 671 672 static inline void sdhci_read_caps(struct sdhci_host *host) 673 { 674 __sdhci_read_caps(host, NULL, NULL, NULL); 675 } 676 677 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 678 { 679 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 680 } 681 682 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 683 unsigned int *actual_clock); 684 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 685 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 686 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 687 unsigned short vdd); 688 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 689 unsigned short vdd); 690 void sdhci_set_bus_width(struct sdhci_host *host, int width); 691 void sdhci_reset(struct sdhci_host *host, u8 mask); 692 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 693 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 694 695 #ifdef CONFIG_PM 696 extern int sdhci_suspend_host(struct sdhci_host *host); 697 extern int sdhci_resume_host(struct sdhci_host *host); 698 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 699 extern int sdhci_runtime_suspend_host(struct sdhci_host *host); 700 extern int sdhci_runtime_resume_host(struct sdhci_host *host); 701 #endif 702 703 #endif /* __SDHCI_HW_H */ 704