1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 21 #include <linux/mmc/host.h> 22 23 /* 24 * Controller registers 25 */ 26 27 #define SDHCI_DMA_ADDRESS 0x00 28 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_READ 0x10 43 #define SDHCI_TRNS_MULTI 0x20 44 45 #define SDHCI_COMMAND 0x0E 46 #define SDHCI_CMD_RESP_MASK 0x03 47 #define SDHCI_CMD_CRC 0x08 48 #define SDHCI_CMD_INDEX 0x10 49 #define SDHCI_CMD_DATA 0x20 50 #define SDHCI_CMD_ABORTCMD 0xC0 51 52 #define SDHCI_CMD_RESP_NONE 0x00 53 #define SDHCI_CMD_RESP_LONG 0x01 54 #define SDHCI_CMD_RESP_SHORT 0x02 55 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 56 57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 59 60 #define SDHCI_RESPONSE 0x10 61 62 #define SDHCI_BUFFER 0x20 63 64 #define SDHCI_PRESENT_STATE 0x24 65 #define SDHCI_CMD_INHIBIT 0x00000001 66 #define SDHCI_DATA_INHIBIT 0x00000002 67 #define SDHCI_DOING_WRITE 0x00000100 68 #define SDHCI_DOING_READ 0x00000200 69 #define SDHCI_SPACE_AVAILABLE 0x00000400 70 #define SDHCI_DATA_AVAILABLE 0x00000800 71 #define SDHCI_CARD_PRESENT 0x00010000 72 #define SDHCI_WRITE_PROTECT 0x00080000 73 #define SDHCI_DATA_LVL_MASK 0x00F00000 74 #define SDHCI_DATA_LVL_SHIFT 20 75 #define SDHCI_DATA_0_LVL_MASK 0x00100000 76 77 #define SDHCI_HOST_CONTROL 0x28 78 #define SDHCI_CTRL_LED 0x01 79 #define SDHCI_CTRL_4BITBUS 0x02 80 #define SDHCI_CTRL_HISPD 0x04 81 #define SDHCI_CTRL_DMA_MASK 0x18 82 #define SDHCI_CTRL_SDMA 0x00 83 #define SDHCI_CTRL_ADMA1 0x08 84 #define SDHCI_CTRL_ADMA32 0x10 85 #define SDHCI_CTRL_ADMA64 0x18 86 #define SDHCI_CTRL_8BITBUS 0x20 87 #define SDHCI_CTRL_CDTEST_INS 0x40 88 #define SDHCI_CTRL_CDTEST_EN 0x80 89 90 #define SDHCI_POWER_CONTROL 0x29 91 #define SDHCI_POWER_ON 0x01 92 #define SDHCI_POWER_180 0x0A 93 #define SDHCI_POWER_300 0x0C 94 #define SDHCI_POWER_330 0x0E 95 96 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 97 98 #define SDHCI_WAKE_UP_CONTROL 0x2B 99 #define SDHCI_WAKE_ON_INT 0x01 100 #define SDHCI_WAKE_ON_INSERT 0x02 101 #define SDHCI_WAKE_ON_REMOVE 0x04 102 103 #define SDHCI_CLOCK_CONTROL 0x2C 104 #define SDHCI_DIVIDER_SHIFT 8 105 #define SDHCI_DIVIDER_HI_SHIFT 6 106 #define SDHCI_DIV_MASK 0xFF 107 #define SDHCI_DIV_MASK_LEN 8 108 #define SDHCI_DIV_HI_MASK 0x300 109 #define SDHCI_PROG_CLOCK_MODE 0x0020 110 #define SDHCI_CLOCK_CARD_EN 0x0004 111 #define SDHCI_CLOCK_INT_STABLE 0x0002 112 #define SDHCI_CLOCK_INT_EN 0x0001 113 114 #define SDHCI_TIMEOUT_CONTROL 0x2E 115 116 #define SDHCI_SOFTWARE_RESET 0x2F 117 #define SDHCI_RESET_ALL 0x01 118 #define SDHCI_RESET_CMD 0x02 119 #define SDHCI_RESET_DATA 0x04 120 121 #define SDHCI_INT_STATUS 0x30 122 #define SDHCI_INT_ENABLE 0x34 123 #define SDHCI_SIGNAL_ENABLE 0x38 124 #define SDHCI_INT_RESPONSE 0x00000001 125 #define SDHCI_INT_DATA_END 0x00000002 126 #define SDHCI_INT_BLK_GAP 0x00000004 127 #define SDHCI_INT_DMA_END 0x00000008 128 #define SDHCI_INT_SPACE_AVAIL 0x00000010 129 #define SDHCI_INT_DATA_AVAIL 0x00000020 130 #define SDHCI_INT_CARD_INSERT 0x00000040 131 #define SDHCI_INT_CARD_REMOVE 0x00000080 132 #define SDHCI_INT_CARD_INT 0x00000100 133 #define SDHCI_INT_RETUNE 0x00001000 134 #define SDHCI_INT_ERROR 0x00008000 135 #define SDHCI_INT_TIMEOUT 0x00010000 136 #define SDHCI_INT_CRC 0x00020000 137 #define SDHCI_INT_END_BIT 0x00040000 138 #define SDHCI_INT_INDEX 0x00080000 139 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 140 #define SDHCI_INT_DATA_CRC 0x00200000 141 #define SDHCI_INT_DATA_END_BIT 0x00400000 142 #define SDHCI_INT_BUS_POWER 0x00800000 143 #define SDHCI_INT_ACMD12ERR 0x01000000 144 #define SDHCI_INT_ADMA_ERROR 0x02000000 145 146 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 147 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 148 149 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 150 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 151 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 152 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 153 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 154 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 155 SDHCI_INT_BLK_GAP) 156 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 157 158 #define SDHCI_ACMD12_ERR 0x3C 159 160 #define SDHCI_HOST_CONTROL2 0x3E 161 #define SDHCI_CTRL_UHS_MASK 0x0007 162 #define SDHCI_CTRL_UHS_SDR12 0x0000 163 #define SDHCI_CTRL_UHS_SDR25 0x0001 164 #define SDHCI_CTRL_UHS_SDR50 0x0002 165 #define SDHCI_CTRL_UHS_SDR104 0x0003 166 #define SDHCI_CTRL_UHS_DDR50 0x0004 167 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 168 #define SDHCI_CTRL_VDD_180 0x0008 169 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 170 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 171 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 172 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 173 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 174 #define SDHCI_CTRL_EXEC_TUNING 0x0040 175 #define SDHCI_CTRL_TUNED_CLK 0x0080 176 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 177 178 #define SDHCI_CAPABILITIES 0x40 179 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 180 #define SDHCI_TIMEOUT_CLK_SHIFT 0 181 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 182 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 183 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 184 #define SDHCI_CLOCK_BASE_SHIFT 8 185 #define SDHCI_MAX_BLOCK_MASK 0x00030000 186 #define SDHCI_MAX_BLOCK_SHIFT 16 187 #define SDHCI_CAN_DO_8BIT 0x00040000 188 #define SDHCI_CAN_DO_ADMA2 0x00080000 189 #define SDHCI_CAN_DO_ADMA1 0x00100000 190 #define SDHCI_CAN_DO_HISPD 0x00200000 191 #define SDHCI_CAN_DO_SDMA 0x00400000 192 #define SDHCI_CAN_DO_SUSPEND 0x00800000 193 #define SDHCI_CAN_VDD_330 0x01000000 194 #define SDHCI_CAN_VDD_300 0x02000000 195 #define SDHCI_CAN_VDD_180 0x04000000 196 #define SDHCI_CAN_64BIT 0x10000000 197 198 #define SDHCI_SUPPORT_SDR50 0x00000001 199 #define SDHCI_SUPPORT_SDR104 0x00000002 200 #define SDHCI_SUPPORT_DDR50 0x00000004 201 #define SDHCI_DRIVER_TYPE_A 0x00000010 202 #define SDHCI_DRIVER_TYPE_C 0x00000020 203 #define SDHCI_DRIVER_TYPE_D 0x00000040 204 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 205 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 206 #define SDHCI_USE_SDR50_TUNING 0x00002000 207 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 208 #define SDHCI_RETUNING_MODE_SHIFT 14 209 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 210 #define SDHCI_CLOCK_MUL_SHIFT 16 211 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 212 213 #define SDHCI_CAPABILITIES_1 0x44 214 215 #define SDHCI_MAX_CURRENT 0x48 216 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 217 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 218 #define SDHCI_MAX_CURRENT_330_SHIFT 0 219 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 220 #define SDHCI_MAX_CURRENT_300_SHIFT 8 221 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 222 #define SDHCI_MAX_CURRENT_180_SHIFT 16 223 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 224 225 /* 4C-4F reserved for more max current */ 226 227 #define SDHCI_SET_ACMD12_ERROR 0x50 228 #define SDHCI_SET_INT_ERROR 0x52 229 230 #define SDHCI_ADMA_ERROR 0x54 231 232 /* 55-57 reserved */ 233 234 #define SDHCI_ADMA_ADDRESS 0x58 235 #define SDHCI_ADMA_ADDRESS_HI 0x5C 236 237 /* 60-FB reserved */ 238 239 #define SDHCI_PRESET_FOR_SDR12 0x66 240 #define SDHCI_PRESET_FOR_SDR25 0x68 241 #define SDHCI_PRESET_FOR_SDR50 0x6A 242 #define SDHCI_PRESET_FOR_SDR104 0x6C 243 #define SDHCI_PRESET_FOR_DDR50 0x6E 244 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 245 #define SDHCI_PRESET_DRV_MASK 0xC000 246 #define SDHCI_PRESET_DRV_SHIFT 14 247 #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 248 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 249 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 250 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 251 252 #define SDHCI_SLOT_INT_STATUS 0xFC 253 254 #define SDHCI_HOST_VERSION 0xFE 255 #define SDHCI_VENDOR_VER_MASK 0xFF00 256 #define SDHCI_VENDOR_VER_SHIFT 8 257 #define SDHCI_SPEC_VER_MASK 0x00FF 258 #define SDHCI_SPEC_VER_SHIFT 0 259 #define SDHCI_SPEC_100 0 260 #define SDHCI_SPEC_200 1 261 #define SDHCI_SPEC_300 2 262 263 /* 264 * End of controller registers. 265 */ 266 267 #define SDHCI_MAX_DIV_SPEC_200 256 268 #define SDHCI_MAX_DIV_SPEC_300 2046 269 270 /* 271 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 272 */ 273 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 274 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 275 276 /* ADMA2 32-bit DMA descriptor size */ 277 #define SDHCI_ADMA2_32_DESC_SZ 8 278 279 /* ADMA2 32-bit descriptor */ 280 struct sdhci_adma2_32_desc { 281 __le16 cmd; 282 __le16 len; 283 __le32 addr; 284 } __packed __aligned(4); 285 286 /* ADMA2 data alignment */ 287 #define SDHCI_ADMA2_ALIGN 4 288 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 289 290 /* 291 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 292 * alignment for the descriptor table even in 32-bit DMA mode. Memory 293 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 294 */ 295 #define SDHCI_ADMA2_DESC_ALIGN 8 296 297 /* ADMA2 64-bit DMA descriptor size */ 298 #define SDHCI_ADMA2_64_DESC_SZ 12 299 300 /* 301 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 302 * aligned. 303 */ 304 struct sdhci_adma2_64_desc { 305 __le16 cmd; 306 __le16 len; 307 __le32 addr_lo; 308 __le32 addr_hi; 309 } __packed __aligned(4); 310 311 #define ADMA2_TRAN_VALID 0x21 312 #define ADMA2_NOP_END_VALID 0x3 313 #define ADMA2_END 0x2 314 315 /* 316 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 317 * 4KiB page size. 318 */ 319 #define SDHCI_MAX_SEGS 128 320 321 /* Allow for a a command request and a data request at the same time */ 322 #define SDHCI_MAX_MRQS 2 323 324 enum sdhci_cookie { 325 COOKIE_UNMAPPED, 326 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 327 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 328 }; 329 330 struct sdhci_host { 331 /* Data set by hardware interface driver */ 332 const char *hw_name; /* Hardware bus name */ 333 334 unsigned int quirks; /* Deviations from spec. */ 335 336 /* Controller doesn't honor resets unless we touch the clock register */ 337 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 338 /* Controller has bad caps bits, but really supports DMA */ 339 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 340 /* Controller doesn't like to be reset when there is no card inserted. */ 341 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 342 /* Controller doesn't like clearing the power reg before a change */ 343 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 344 /* Controller has flaky internal state so reset it on each ios change */ 345 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 346 /* Controller has an unusable DMA engine */ 347 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 348 /* Controller has an unusable ADMA engine */ 349 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 350 /* Controller can only DMA from 32-bit aligned addresses */ 351 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 352 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 353 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 354 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 355 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 356 /* Controller needs to be reset after each request to stay stable */ 357 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 358 /* Controller needs voltage and power writes to happen separately */ 359 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 360 /* Controller provides an incorrect timeout value for transfers */ 361 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 362 /* Controller has an issue with buffer bits for small transfers */ 363 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 364 /* Controller does not provide transfer-complete interrupt when not busy */ 365 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 366 /* Controller has unreliable card detection */ 367 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 368 /* Controller reports inverted write-protect state */ 369 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 370 /* Controller does not like fast PIO transfers */ 371 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 372 /* Controller has to be forced to use block size of 2048 bytes */ 373 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 374 /* Controller cannot do multi-block transfers */ 375 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 376 /* Controller can only handle 1-bit data transfers */ 377 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 378 /* Controller needs 10ms delay between applying power and clock */ 379 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 380 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 381 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 382 /* Controller reports wrong base clock capability */ 383 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 384 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 385 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 386 /* Controller is missing device caps. Use caps provided by host */ 387 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 388 /* Controller uses Auto CMD12 command to stop the transfer */ 389 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 390 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 391 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 392 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 393 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 394 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 395 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 396 397 unsigned int quirks2; /* More deviations from spec. */ 398 399 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 400 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 401 /* The system physically doesn't support 1.8v, even if the host does */ 402 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 403 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 404 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 405 /* Controller has a non-standard host control register */ 406 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 407 /* Controller does not support HS200 */ 408 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 409 /* Controller does not support DDR50 */ 410 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 411 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 412 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 413 /* Controller does not support 64-bit DMA */ 414 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 415 /* need clear transfer mode register before send cmd */ 416 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 417 /* Capability register bit-63 indicates HS400 support */ 418 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 419 /* forced tuned clock */ 420 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 421 /* disable the block count for single block transactions */ 422 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 423 /* Controller broken with using ACMD23 */ 424 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 425 /* Broken Clock divider zero in controller */ 426 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 427 428 int irq; /* Device IRQ */ 429 void __iomem *ioaddr; /* Mapped address */ 430 431 const struct sdhci_ops *ops; /* Low level hw interface */ 432 433 /* Internal data */ 434 struct mmc_host *mmc; /* MMC structure */ 435 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 436 u64 dma_mask; /* custom DMA mask */ 437 438 #if IS_ENABLED(CONFIG_LEDS_CLASS) 439 struct led_classdev led; /* LED control */ 440 char led_name[32]; 441 #endif 442 443 spinlock_t lock; /* Mutex */ 444 445 int flags; /* Host attributes */ 446 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 447 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 448 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 449 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 450 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 451 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 452 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 453 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 454 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 455 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 456 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 457 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 458 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 459 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 460 461 unsigned int version; /* SDHCI spec. version */ 462 463 unsigned int max_clk; /* Max possible freq (MHz) */ 464 unsigned int timeout_clk; /* Timeout freq (KHz) */ 465 unsigned int clk_mul; /* Clock Muliplier value */ 466 467 unsigned int clock; /* Current clock (MHz) */ 468 u8 pwr; /* Current voltage */ 469 470 bool runtime_suspended; /* Host is runtime suspended */ 471 bool bus_on; /* Bus power prevents runtime suspend */ 472 bool preset_enabled; /* Preset is enabled */ 473 bool pending_reset; /* Cmd/data reset is pending */ 474 475 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 476 struct mmc_command *cmd; /* Current command */ 477 struct mmc_command *data_cmd; /* Current data command */ 478 struct mmc_data *data; /* Current data request */ 479 unsigned int data_early:1; /* Data finished before cmd */ 480 481 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 482 unsigned int blocks; /* remaining PIO blocks */ 483 484 int sg_count; /* Mapped sg entries */ 485 486 void *adma_table; /* ADMA descriptor table */ 487 void *align_buffer; /* Bounce buffer */ 488 489 size_t adma_table_sz; /* ADMA descriptor table size */ 490 size_t align_buffer_sz; /* Bounce buffer size */ 491 492 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 493 dma_addr_t align_addr; /* Mapped bounce buffer */ 494 495 unsigned int desc_sz; /* ADMA descriptor size */ 496 497 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 498 499 struct timer_list timer; /* Timer for timeouts */ 500 struct timer_list data_timer; /* Timer for data timeouts */ 501 502 u32 caps; /* CAPABILITY_0 */ 503 u32 caps1; /* CAPABILITY_1 */ 504 bool read_caps; /* Capability flags have been read */ 505 506 unsigned int ocr_avail_sdio; /* OCR bit masks */ 507 unsigned int ocr_avail_sd; 508 unsigned int ocr_avail_mmc; 509 u32 ocr_mask; /* available voltages */ 510 511 unsigned timing; /* Current timing */ 512 513 u32 thread_isr; 514 515 /* cached registers */ 516 u32 ier; 517 518 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 519 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 520 521 unsigned int tuning_count; /* Timer count for re-tuning */ 522 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 523 #define SDHCI_TUNING_MODE_1 0 524 #define SDHCI_TUNING_MODE_2 1 525 #define SDHCI_TUNING_MODE_3 2 526 527 unsigned long private[0] ____cacheline_aligned; 528 }; 529 530 struct sdhci_ops { 531 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 532 u32 (*read_l)(struct sdhci_host *host, int reg); 533 u16 (*read_w)(struct sdhci_host *host, int reg); 534 u8 (*read_b)(struct sdhci_host *host, int reg); 535 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 536 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 537 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 538 #endif 539 540 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 541 void (*set_power)(struct sdhci_host *host, unsigned char mode, 542 unsigned short vdd); 543 544 int (*enable_dma)(struct sdhci_host *host); 545 unsigned int (*get_max_clock)(struct sdhci_host *host); 546 unsigned int (*get_min_clock)(struct sdhci_host *host); 547 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 548 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 549 void (*set_timeout)(struct sdhci_host *host, 550 struct mmc_command *cmd); 551 void (*set_bus_width)(struct sdhci_host *host, int width); 552 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 553 u8 power_mode); 554 unsigned int (*get_ro)(struct sdhci_host *host); 555 void (*reset)(struct sdhci_host *host, u8 mask); 556 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 557 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 558 void (*hw_reset)(struct sdhci_host *host); 559 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 560 void (*card_event)(struct sdhci_host *host); 561 void (*voltage_switch)(struct sdhci_host *host); 562 int (*select_drive_strength)(struct sdhci_host *host, 563 struct mmc_card *card, 564 unsigned int max_dtr, int host_drv, 565 int card_drv, int *drv_type); 566 }; 567 568 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 569 570 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 571 { 572 if (unlikely(host->ops->write_l)) 573 host->ops->write_l(host, val, reg); 574 else 575 writel(val, host->ioaddr + reg); 576 } 577 578 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 579 { 580 if (unlikely(host->ops->write_w)) 581 host->ops->write_w(host, val, reg); 582 else 583 writew(val, host->ioaddr + reg); 584 } 585 586 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 587 { 588 if (unlikely(host->ops->write_b)) 589 host->ops->write_b(host, val, reg); 590 else 591 writeb(val, host->ioaddr + reg); 592 } 593 594 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 595 { 596 if (unlikely(host->ops->read_l)) 597 return host->ops->read_l(host, reg); 598 else 599 return readl(host->ioaddr + reg); 600 } 601 602 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 603 { 604 if (unlikely(host->ops->read_w)) 605 return host->ops->read_w(host, reg); 606 else 607 return readw(host->ioaddr + reg); 608 } 609 610 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 611 { 612 if (unlikely(host->ops->read_b)) 613 return host->ops->read_b(host, reg); 614 else 615 return readb(host->ioaddr + reg); 616 } 617 618 #else 619 620 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 621 { 622 writel(val, host->ioaddr + reg); 623 } 624 625 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 626 { 627 writew(val, host->ioaddr + reg); 628 } 629 630 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 631 { 632 writeb(val, host->ioaddr + reg); 633 } 634 635 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 636 { 637 return readl(host->ioaddr + reg); 638 } 639 640 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 641 { 642 return readw(host->ioaddr + reg); 643 } 644 645 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 646 { 647 return readb(host->ioaddr + reg); 648 } 649 650 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 651 652 extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 653 size_t priv_size); 654 extern void sdhci_free_host(struct sdhci_host *host); 655 656 static inline void *sdhci_priv(struct sdhci_host *host) 657 { 658 return (void *)host->private; 659 } 660 661 extern void sdhci_card_detect(struct sdhci_host *host); 662 extern void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 663 u32 *caps1); 664 extern int sdhci_setup_host(struct sdhci_host *host); 665 extern int __sdhci_add_host(struct sdhci_host *host); 666 extern int sdhci_add_host(struct sdhci_host *host); 667 extern void sdhci_remove_host(struct sdhci_host *host, int dead); 668 extern void sdhci_send_command(struct sdhci_host *host, 669 struct mmc_command *cmd); 670 671 static inline void sdhci_read_caps(struct sdhci_host *host) 672 { 673 __sdhci_read_caps(host, NULL, NULL, NULL); 674 } 675 676 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 677 { 678 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 679 } 680 681 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 682 unsigned int *actual_clock); 683 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 684 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 685 unsigned short vdd); 686 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 687 unsigned short vdd); 688 void sdhci_set_bus_width(struct sdhci_host *host, int width); 689 void sdhci_reset(struct sdhci_host *host, u8 mask); 690 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 691 692 #ifdef CONFIG_PM 693 extern int sdhci_suspend_host(struct sdhci_host *host); 694 extern int sdhci_resume_host(struct sdhci_host *host); 695 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 696 extern int sdhci_runtime_suspend_host(struct sdhci_host *host); 697 extern int sdhci_runtime_resume_host(struct sdhci_host *host); 698 #endif 699 700 #endif /* __SDHCI_HW_H */ 701