1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 4 * 5 * Header file for Host Controller registers and I/O accessors. 6 * 7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 8 */ 9 #ifndef __SDHCI_HW_H 10 #define __SDHCI_HW_H 11 12 #include <linux/bits.h> 13 #include <linux/scatterlist.h> 14 #include <linux/compiler.h> 15 #include <linux/types.h> 16 #include <linux/io.h> 17 #include <linux/leds.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mmc/host.h> 21 22 /* 23 * Controller registers 24 */ 25 26 #define SDHCI_DMA_ADDRESS 0x00 27 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 28 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_AUTO_SEL 0x0C 43 #define SDHCI_TRNS_READ 0x10 44 #define SDHCI_TRNS_MULTI 0x20 45 46 #define SDHCI_COMMAND 0x0E 47 #define SDHCI_CMD_RESP_MASK 0x03 48 #define SDHCI_CMD_CRC 0x08 49 #define SDHCI_CMD_INDEX 0x10 50 #define SDHCI_CMD_DATA 0x20 51 #define SDHCI_CMD_ABORTCMD 0xC0 52 53 #define SDHCI_CMD_RESP_NONE 0x00 54 #define SDHCI_CMD_RESP_LONG 0x01 55 #define SDHCI_CMD_RESP_SHORT 0x02 56 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 57 58 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 59 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 60 61 #define SDHCI_RESPONSE 0x10 62 63 #define SDHCI_BUFFER 0x20 64 65 #define SDHCI_PRESENT_STATE 0x24 66 #define SDHCI_CMD_INHIBIT 0x00000001 67 #define SDHCI_DATA_INHIBIT 0x00000002 68 #define SDHCI_DOING_WRITE 0x00000100 69 #define SDHCI_DOING_READ 0x00000200 70 #define SDHCI_SPACE_AVAILABLE 0x00000400 71 #define SDHCI_DATA_AVAILABLE 0x00000800 72 #define SDHCI_CARD_PRESENT 0x00010000 73 #define SDHCI_CARD_PRES_SHIFT 16 74 #define SDHCI_CD_STABLE 0x00020000 75 #define SDHCI_CD_LVL 0x00040000 76 #define SDHCI_CD_LVL_SHIFT 18 77 #define SDHCI_WRITE_PROTECT 0x00080000 78 #define SDHCI_DATA_LVL_MASK 0x00F00000 79 #define SDHCI_DATA_LVL_SHIFT 20 80 #define SDHCI_DATA_0_LVL_MASK 0x00100000 81 #define SDHCI_CMD_LVL 0x01000000 82 83 #define SDHCI_HOST_CONTROL 0x28 84 #define SDHCI_CTRL_LED 0x01 85 #define SDHCI_CTRL_4BITBUS 0x02 86 #define SDHCI_CTRL_HISPD 0x04 87 #define SDHCI_CTRL_DMA_MASK 0x18 88 #define SDHCI_CTRL_SDMA 0x00 89 #define SDHCI_CTRL_ADMA1 0x08 90 #define SDHCI_CTRL_ADMA32 0x10 91 #define SDHCI_CTRL_ADMA64 0x18 92 #define SDHCI_CTRL_ADMA3 0x18 93 #define SDHCI_CTRL_8BITBUS 0x20 94 #define SDHCI_CTRL_CDTEST_INS 0x40 95 #define SDHCI_CTRL_CDTEST_EN 0x80 96 97 #define SDHCI_POWER_CONTROL 0x29 98 #define SDHCI_POWER_ON 0x01 99 #define SDHCI_POWER_180 0x0A 100 #define SDHCI_POWER_300 0x0C 101 #define SDHCI_POWER_330 0x0E 102 103 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 104 105 #define SDHCI_WAKE_UP_CONTROL 0x2B 106 #define SDHCI_WAKE_ON_INT 0x01 107 #define SDHCI_WAKE_ON_INSERT 0x02 108 #define SDHCI_WAKE_ON_REMOVE 0x04 109 110 #define SDHCI_CLOCK_CONTROL 0x2C 111 #define SDHCI_DIVIDER_SHIFT 8 112 #define SDHCI_DIVIDER_HI_SHIFT 6 113 #define SDHCI_DIV_MASK 0xFF 114 #define SDHCI_DIV_MASK_LEN 8 115 #define SDHCI_DIV_HI_MASK 0x300 116 #define SDHCI_PROG_CLOCK_MODE 0x0020 117 #define SDHCI_CLOCK_CARD_EN 0x0004 118 #define SDHCI_CLOCK_PLL_EN 0x0008 119 #define SDHCI_CLOCK_INT_STABLE 0x0002 120 #define SDHCI_CLOCK_INT_EN 0x0001 121 122 #define SDHCI_TIMEOUT_CONTROL 0x2E 123 124 #define SDHCI_SOFTWARE_RESET 0x2F 125 #define SDHCI_RESET_ALL 0x01 126 #define SDHCI_RESET_CMD 0x02 127 #define SDHCI_RESET_DATA 0x04 128 129 #define SDHCI_INT_STATUS 0x30 130 #define SDHCI_INT_ENABLE 0x34 131 #define SDHCI_SIGNAL_ENABLE 0x38 132 #define SDHCI_INT_RESPONSE 0x00000001 133 #define SDHCI_INT_DATA_END 0x00000002 134 #define SDHCI_INT_BLK_GAP 0x00000004 135 #define SDHCI_INT_DMA_END 0x00000008 136 #define SDHCI_INT_SPACE_AVAIL 0x00000010 137 #define SDHCI_INT_DATA_AVAIL 0x00000020 138 #define SDHCI_INT_CARD_INSERT 0x00000040 139 #define SDHCI_INT_CARD_REMOVE 0x00000080 140 #define SDHCI_INT_CARD_INT 0x00000100 141 #define SDHCI_INT_RETUNE 0x00001000 142 #define SDHCI_INT_CQE 0x00004000 143 #define SDHCI_INT_ERROR 0x00008000 144 #define SDHCI_INT_TIMEOUT 0x00010000 145 #define SDHCI_INT_CRC 0x00020000 146 #define SDHCI_INT_END_BIT 0x00040000 147 #define SDHCI_INT_INDEX 0x00080000 148 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 149 #define SDHCI_INT_DATA_CRC 0x00200000 150 #define SDHCI_INT_DATA_END_BIT 0x00400000 151 #define SDHCI_INT_BUS_POWER 0x00800000 152 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 153 #define SDHCI_INT_ADMA_ERROR 0x02000000 154 155 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 156 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 157 158 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 159 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 160 SDHCI_INT_AUTO_CMD_ERR) 161 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 162 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 163 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 164 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 165 SDHCI_INT_BLK_GAP) 166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 167 168 #define SDHCI_CQE_INT_ERR_MASK ( \ 169 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 170 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 171 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 172 173 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 174 175 #define SDHCI_AUTO_CMD_STATUS 0x3C 176 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 177 #define SDHCI_AUTO_CMD_CRC 0x00000004 178 #define SDHCI_AUTO_CMD_END_BIT 0x00000008 179 #define SDHCI_AUTO_CMD_INDEX 0x00000010 180 181 #define SDHCI_HOST_CONTROL2 0x3E 182 #define SDHCI_CTRL_UHS_MASK 0x0007 183 #define SDHCI_CTRL_UHS_SDR12 0x0000 184 #define SDHCI_CTRL_UHS_SDR25 0x0001 185 #define SDHCI_CTRL_UHS_SDR50 0x0002 186 #define SDHCI_CTRL_UHS_SDR104 0x0003 187 #define SDHCI_CTRL_UHS_DDR50 0x0004 188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 189 #define SDHCI_CTRL_VDD_180 0x0008 190 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 191 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 192 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 193 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 194 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 195 #define SDHCI_CTRL_EXEC_TUNING 0x0040 196 #define SDHCI_CTRL_TUNED_CLK 0x0080 197 #define SDHCI_CMD23_ENABLE 0x0800 198 #define SDHCI_CTRL_V4_MODE 0x1000 199 #define SDHCI_CTRL_64BIT_ADDR 0x2000 200 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 201 202 #define SDHCI_CAPABILITIES 0x40 203 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 204 #define SDHCI_TIMEOUT_CLK_SHIFT 0 205 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 206 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 207 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 208 #define SDHCI_CLOCK_BASE_SHIFT 8 209 #define SDHCI_MAX_BLOCK_MASK 0x00030000 210 #define SDHCI_MAX_BLOCK_SHIFT 16 211 #define SDHCI_CAN_DO_8BIT 0x00040000 212 #define SDHCI_CAN_DO_ADMA2 0x00080000 213 #define SDHCI_CAN_DO_ADMA1 0x00100000 214 #define SDHCI_CAN_DO_HISPD 0x00200000 215 #define SDHCI_CAN_DO_SDMA 0x00400000 216 #define SDHCI_CAN_DO_SUSPEND 0x00800000 217 #define SDHCI_CAN_VDD_330 0x01000000 218 #define SDHCI_CAN_VDD_300 0x02000000 219 #define SDHCI_CAN_VDD_180 0x04000000 220 #define SDHCI_CAN_64BIT_V4 0x08000000 221 #define SDHCI_CAN_64BIT 0x10000000 222 223 #define SDHCI_SUPPORT_SDR50 0x00000001 224 #define SDHCI_SUPPORT_SDR104 0x00000002 225 #define SDHCI_SUPPORT_DDR50 0x00000004 226 #define SDHCI_DRIVER_TYPE_A 0x00000010 227 #define SDHCI_DRIVER_TYPE_C 0x00000020 228 #define SDHCI_DRIVER_TYPE_D 0x00000040 229 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 230 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 231 #define SDHCI_USE_SDR50_TUNING 0x00002000 232 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 233 #define SDHCI_RETUNING_MODE_SHIFT 14 234 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 235 #define SDHCI_CLOCK_MUL_SHIFT 16 236 #define SDHCI_CAN_DO_ADMA3 0x08000000 237 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 238 239 #define SDHCI_CAPABILITIES_1 0x44 240 241 #define SDHCI_MAX_CURRENT 0x48 242 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 243 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 244 #define SDHCI_MAX_CURRENT_330_SHIFT 0 245 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 246 #define SDHCI_MAX_CURRENT_300_SHIFT 8 247 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 248 #define SDHCI_MAX_CURRENT_180_SHIFT 16 249 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 250 251 /* 4C-4F reserved for more max current */ 252 253 #define SDHCI_SET_ACMD12_ERROR 0x50 254 #define SDHCI_SET_INT_ERROR 0x52 255 256 #define SDHCI_ADMA_ERROR 0x54 257 258 /* 55-57 reserved */ 259 260 #define SDHCI_ADMA_ADDRESS 0x58 261 #define SDHCI_ADMA_ADDRESS_HI 0x5C 262 263 /* 60-FB reserved */ 264 265 #define SDHCI_PRESET_FOR_SDR12 0x66 266 #define SDHCI_PRESET_FOR_SDR25 0x68 267 #define SDHCI_PRESET_FOR_SDR50 0x6A 268 #define SDHCI_PRESET_FOR_SDR104 0x6C 269 #define SDHCI_PRESET_FOR_DDR50 0x6E 270 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 271 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) 272 #define SDHCI_PRESET_CLKGEN_SEL BIT(10) 273 #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) 274 275 #define SDHCI_SLOT_INT_STATUS 0xFC 276 277 #define SDHCI_HOST_VERSION 0xFE 278 #define SDHCI_VENDOR_VER_MASK 0xFF00 279 #define SDHCI_VENDOR_VER_SHIFT 8 280 #define SDHCI_SPEC_VER_MASK 0x00FF 281 #define SDHCI_SPEC_VER_SHIFT 0 282 #define SDHCI_SPEC_100 0 283 #define SDHCI_SPEC_200 1 284 #define SDHCI_SPEC_300 2 285 #define SDHCI_SPEC_400 3 286 #define SDHCI_SPEC_410 4 287 #define SDHCI_SPEC_420 5 288 289 /* 290 * End of controller registers. 291 */ 292 293 #define SDHCI_MAX_DIV_SPEC_200 256 294 #define SDHCI_MAX_DIV_SPEC_300 2046 295 296 /* 297 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 298 */ 299 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 300 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 301 302 /* ADMA2 32-bit DMA descriptor size */ 303 #define SDHCI_ADMA2_32_DESC_SZ 8 304 305 /* ADMA2 32-bit descriptor */ 306 struct sdhci_adma2_32_desc { 307 __le16 cmd; 308 __le16 len; 309 __le32 addr; 310 } __packed __aligned(4); 311 312 /* ADMA2 data alignment */ 313 #define SDHCI_ADMA2_ALIGN 4 314 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 315 316 /* 317 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 318 * alignment for the descriptor table even in 32-bit DMA mode. Memory 319 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 320 */ 321 #define SDHCI_ADMA2_DESC_ALIGN 8 322 323 /* 324 * ADMA2 64-bit DMA descriptor size 325 * According to SD Host Controller spec v4.10, there are two kinds of 326 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 327 * Descriptor, if Host Version 4 Enable is set in the Host Control 2 328 * register, 128-bit Descriptor will be selected. 329 */ 330 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 331 332 /* 333 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 334 * aligned. 335 */ 336 struct sdhci_adma2_64_desc { 337 __le16 cmd; 338 __le16 len; 339 __le32 addr_lo; 340 __le32 addr_hi; 341 } __packed __aligned(4); 342 343 #define ADMA2_TRAN_VALID 0x21 344 #define ADMA2_NOP_END_VALID 0x3 345 #define ADMA2_END 0x2 346 347 /* 348 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 349 * 4KiB page size. 350 */ 351 #define SDHCI_MAX_SEGS 128 352 353 /* Allow for a a command request and a data request at the same time */ 354 #define SDHCI_MAX_MRQS 2 355 356 /* 357 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 358 * However since the start time of the command, the time between 359 * command and response, and the time between response and start of data is 360 * not known, set the command transfer time to 10ms. 361 */ 362 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 363 364 enum sdhci_cookie { 365 COOKIE_UNMAPPED, 366 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 367 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 368 }; 369 370 struct sdhci_host { 371 /* Data set by hardware interface driver */ 372 const char *hw_name; /* Hardware bus name */ 373 374 unsigned int quirks; /* Deviations from spec. */ 375 376 /* Controller doesn't honor resets unless we touch the clock register */ 377 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 378 /* Controller has bad caps bits, but really supports DMA */ 379 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 380 /* Controller doesn't like to be reset when there is no card inserted. */ 381 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 382 /* Controller doesn't like clearing the power reg before a change */ 383 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 384 /* Controller has flaky internal state so reset it on each ios change */ 385 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 386 /* Controller has an unusable DMA engine */ 387 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 388 /* Controller has an unusable ADMA engine */ 389 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 390 /* Controller can only DMA from 32-bit aligned addresses */ 391 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 392 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 393 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 394 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 395 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 396 /* Controller needs to be reset after each request to stay stable */ 397 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 398 /* Controller needs voltage and power writes to happen separately */ 399 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 400 /* Controller provides an incorrect timeout value for transfers */ 401 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 402 /* Controller has an issue with buffer bits for small transfers */ 403 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 404 /* Controller does not provide transfer-complete interrupt when not busy */ 405 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 406 /* Controller has unreliable card detection */ 407 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 408 /* Controller reports inverted write-protect state */ 409 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 410 /* Controller has unusable command queue engine */ 411 #define SDHCI_QUIRK_BROKEN_CQE (1<<17) 412 /* Controller does not like fast PIO transfers */ 413 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 414 /* Controller does not have a LED */ 415 #define SDHCI_QUIRK_NO_LED (1<<19) 416 /* Controller has to be forced to use block size of 2048 bytes */ 417 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 418 /* Controller cannot do multi-block transfers */ 419 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 420 /* Controller can only handle 1-bit data transfers */ 421 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 422 /* Controller needs 10ms delay between applying power and clock */ 423 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 424 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 425 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 426 /* Controller reports wrong base clock capability */ 427 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 428 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 429 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 430 /* Controller is missing device caps. Use caps provided by host */ 431 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 432 /* Controller uses Auto CMD12 command to stop the transfer */ 433 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 434 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 435 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 436 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 437 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 438 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 439 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 440 441 unsigned int quirks2; /* More deviations from spec. */ 442 443 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 444 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 445 /* The system physically doesn't support 1.8v, even if the host does */ 446 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 447 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 448 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 449 /* Controller has a non-standard host control register */ 450 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 451 /* Controller does not support HS200 */ 452 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 453 /* Controller does not support DDR50 */ 454 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 455 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 456 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 457 /* Controller does not support 64-bit DMA */ 458 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 459 /* need clear transfer mode register before send cmd */ 460 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 461 /* Capability register bit-63 indicates HS400 support */ 462 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 463 /* forced tuned clock */ 464 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 465 /* disable the block count for single block transactions */ 466 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 467 /* Controller broken with using ACMD23 */ 468 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 469 /* Broken Clock divider zero in controller */ 470 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 471 /* Controller has CRC in 136 bit Command Response */ 472 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 473 /* 474 * Disable HW timeout if the requested timeout is more than the maximum 475 * obtainable timeout. 476 */ 477 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 478 /* 479 * 32-bit block count may not support eMMC where upper bits of CMD23 are used 480 * for other purposes. Consequently we support 16-bit block count by default. 481 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 482 * block count. 483 */ 484 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 485 486 int irq; /* Device IRQ */ 487 void __iomem *ioaddr; /* Mapped address */ 488 phys_addr_t mapbase; /* physical address base */ 489 char *bounce_buffer; /* For packing SDMA reads/writes */ 490 dma_addr_t bounce_addr; 491 unsigned int bounce_buffer_size; 492 493 const struct sdhci_ops *ops; /* Low level hw interface */ 494 495 /* Internal data */ 496 struct mmc_host *mmc; /* MMC structure */ 497 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 498 u64 dma_mask; /* custom DMA mask */ 499 500 #if IS_ENABLED(CONFIG_LEDS_CLASS) 501 struct led_classdev led; /* LED control */ 502 char led_name[32]; 503 #endif 504 505 spinlock_t lock; /* Mutex */ 506 507 int flags; /* Host attributes */ 508 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 509 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 510 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 511 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 512 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 513 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 514 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 515 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 516 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 517 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 518 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 519 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 520 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 521 522 unsigned int version; /* SDHCI spec. version */ 523 524 unsigned int max_clk; /* Max possible freq (MHz) */ 525 unsigned int timeout_clk; /* Timeout freq (KHz) */ 526 unsigned int clk_mul; /* Clock Muliplier value */ 527 528 unsigned int clock; /* Current clock (MHz) */ 529 u8 pwr; /* Current voltage */ 530 531 bool runtime_suspended; /* Host is runtime suspended */ 532 bool bus_on; /* Bus power prevents runtime suspend */ 533 bool preset_enabled; /* Preset is enabled */ 534 bool pending_reset; /* Cmd/data reset is pending */ 535 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 536 bool v4_mode; /* Host Version 4 Enable */ 537 bool use_external_dma; /* Host selects to use external DMA */ 538 bool always_defer_done; /* Always defer to complete requests */ 539 540 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 541 struct mmc_command *cmd; /* Current command */ 542 struct mmc_command *data_cmd; /* Current data command */ 543 struct mmc_data *data; /* Current data request */ 544 unsigned int data_early:1; /* Data finished before cmd */ 545 546 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 547 unsigned int blocks; /* remaining PIO blocks */ 548 549 int sg_count; /* Mapped sg entries */ 550 551 void *adma_table; /* ADMA descriptor table */ 552 void *align_buffer; /* Bounce buffer */ 553 554 size_t adma_table_sz; /* ADMA descriptor table size */ 555 size_t align_buffer_sz; /* Bounce buffer size */ 556 557 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 558 dma_addr_t align_addr; /* Mapped bounce buffer */ 559 560 unsigned int desc_sz; /* ADMA current descriptor size */ 561 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ 562 563 struct workqueue_struct *complete_wq; /* Request completion wq */ 564 struct work_struct complete_work; /* Request completion work */ 565 566 struct timer_list timer; /* Timer for timeouts */ 567 struct timer_list data_timer; /* Timer for data timeouts */ 568 569 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) 570 struct dma_chan *rx_chan; 571 struct dma_chan *tx_chan; 572 #endif 573 574 u32 caps; /* CAPABILITY_0 */ 575 u32 caps1; /* CAPABILITY_1 */ 576 bool read_caps; /* Capability flags have been read */ 577 578 unsigned int ocr_avail_sdio; /* OCR bit masks */ 579 unsigned int ocr_avail_sd; 580 unsigned int ocr_avail_mmc; 581 u32 ocr_mask; /* available voltages */ 582 583 unsigned timing; /* Current timing */ 584 585 u32 thread_isr; 586 587 /* cached registers */ 588 u32 ier; 589 590 bool cqe_on; /* CQE is operating */ 591 u32 cqe_ier; /* CQE interrupt mask */ 592 u32 cqe_err_ier; /* CQE error interrupt mask */ 593 594 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 595 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 596 597 unsigned int tuning_count; /* Timer count for re-tuning */ 598 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 599 unsigned int tuning_err; /* Error code for re-tuning */ 600 #define SDHCI_TUNING_MODE_1 0 601 #define SDHCI_TUNING_MODE_2 1 602 #define SDHCI_TUNING_MODE_3 2 603 /* Delay (ms) between tuning commands */ 604 int tuning_delay; 605 int tuning_loop_count; 606 607 /* Host SDMA buffer boundary. */ 608 u32 sdma_boundary; 609 610 /* Host ADMA table count */ 611 u32 adma_table_cnt; 612 613 u64 data_timeout; 614 615 unsigned long private[] ____cacheline_aligned; 616 }; 617 618 struct sdhci_ops { 619 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 620 u32 (*read_l)(struct sdhci_host *host, int reg); 621 u16 (*read_w)(struct sdhci_host *host, int reg); 622 u8 (*read_b)(struct sdhci_host *host, int reg); 623 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 624 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 625 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 626 #endif 627 628 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 629 void (*set_power)(struct sdhci_host *host, unsigned char mode, 630 unsigned short vdd); 631 632 u32 (*irq)(struct sdhci_host *host, u32 intmask); 633 634 int (*set_dma_mask)(struct sdhci_host *host); 635 int (*enable_dma)(struct sdhci_host *host); 636 unsigned int (*get_max_clock)(struct sdhci_host *host); 637 unsigned int (*get_min_clock)(struct sdhci_host *host); 638 /* get_timeout_clock should return clk rate in unit of Hz */ 639 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 640 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 641 void (*set_timeout)(struct sdhci_host *host, 642 struct mmc_command *cmd); 643 void (*set_bus_width)(struct sdhci_host *host, int width); 644 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 645 u8 power_mode); 646 unsigned int (*get_ro)(struct sdhci_host *host); 647 void (*reset)(struct sdhci_host *host, u8 mask); 648 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 649 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 650 void (*hw_reset)(struct sdhci_host *host); 651 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 652 void (*card_event)(struct sdhci_host *host); 653 void (*voltage_switch)(struct sdhci_host *host); 654 void (*adma_write_desc)(struct sdhci_host *host, void **desc, 655 dma_addr_t addr, int len, unsigned int cmd); 656 void (*request_done)(struct sdhci_host *host, 657 struct mmc_request *mrq); 658 }; 659 660 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 661 662 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 663 { 664 if (unlikely(host->ops->write_l)) 665 host->ops->write_l(host, val, reg); 666 else 667 writel(val, host->ioaddr + reg); 668 } 669 670 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 671 { 672 if (unlikely(host->ops->write_w)) 673 host->ops->write_w(host, val, reg); 674 else 675 writew(val, host->ioaddr + reg); 676 } 677 678 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 679 { 680 if (unlikely(host->ops->write_b)) 681 host->ops->write_b(host, val, reg); 682 else 683 writeb(val, host->ioaddr + reg); 684 } 685 686 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 687 { 688 if (unlikely(host->ops->read_l)) 689 return host->ops->read_l(host, reg); 690 else 691 return readl(host->ioaddr + reg); 692 } 693 694 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 695 { 696 if (unlikely(host->ops->read_w)) 697 return host->ops->read_w(host, reg); 698 else 699 return readw(host->ioaddr + reg); 700 } 701 702 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 703 { 704 if (unlikely(host->ops->read_b)) 705 return host->ops->read_b(host, reg); 706 else 707 return readb(host->ioaddr + reg); 708 } 709 710 #else 711 712 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 713 { 714 writel(val, host->ioaddr + reg); 715 } 716 717 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 718 { 719 writew(val, host->ioaddr + reg); 720 } 721 722 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 723 { 724 writeb(val, host->ioaddr + reg); 725 } 726 727 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 728 { 729 return readl(host->ioaddr + reg); 730 } 731 732 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 733 { 734 return readw(host->ioaddr + reg); 735 } 736 737 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 738 { 739 return readb(host->ioaddr + reg); 740 } 741 742 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 743 744 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 745 void sdhci_free_host(struct sdhci_host *host); 746 747 static inline void *sdhci_priv(struct sdhci_host *host) 748 { 749 return host->private; 750 } 751 752 void sdhci_card_detect(struct sdhci_host *host); 753 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 754 const u32 *caps, const u32 *caps1); 755 int sdhci_setup_host(struct sdhci_host *host); 756 void sdhci_cleanup_host(struct sdhci_host *host); 757 int __sdhci_add_host(struct sdhci_host *host); 758 int sdhci_add_host(struct sdhci_host *host); 759 void sdhci_remove_host(struct sdhci_host *host, int dead); 760 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 761 762 static inline void sdhci_read_caps(struct sdhci_host *host) 763 { 764 __sdhci_read_caps(host, NULL, NULL, NULL); 765 } 766 767 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 768 unsigned int *actual_clock); 769 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 770 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 771 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 772 unsigned short vdd); 773 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, 774 unsigned char mode, 775 unsigned short vdd); 776 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 777 unsigned short vdd); 778 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 779 void sdhci_set_bus_width(struct sdhci_host *host, int width); 780 void sdhci_reset(struct sdhci_host *host, u8 mask); 781 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 782 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 783 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 784 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 785 struct mmc_ios *ios); 786 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 787 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 788 dma_addr_t addr, int len, unsigned int cmd); 789 790 #ifdef CONFIG_PM 791 int sdhci_suspend_host(struct sdhci_host *host); 792 int sdhci_resume_host(struct sdhci_host *host); 793 int sdhci_runtime_suspend_host(struct sdhci_host *host); 794 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 795 #endif 796 797 void sdhci_cqe_enable(struct mmc_host *mmc); 798 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 799 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 800 int *data_error); 801 802 void sdhci_dumpregs(struct sdhci_host *host); 803 void sdhci_enable_v4_mode(struct sdhci_host *host); 804 805 void sdhci_start_tuning(struct sdhci_host *host); 806 void sdhci_end_tuning(struct sdhci_host *host); 807 void sdhci_reset_tuning(struct sdhci_host *host); 808 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 809 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); 810 void sdhci_switch_external_dma(struct sdhci_host *host, bool en); 811 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); 812 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); 813 814 #endif /* __SDHCI_HW_H */ 815