1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 4 * 5 * Header file for Host Controller registers and I/O accessors. 6 * 7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 8 */ 9 #ifndef __SDHCI_HW_H 10 #define __SDHCI_HW_H 11 12 #include <linux/bits.h> 13 #include <linux/scatterlist.h> 14 #include <linux/compiler.h> 15 #include <linux/types.h> 16 #include <linux/io.h> 17 #include <linux/leds.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mmc/host.h> 21 22 /* 23 * Controller registers 24 */ 25 26 #define SDHCI_DMA_ADDRESS 0x00 27 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 28 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_AUTO_SEL 0x0C 43 #define SDHCI_TRNS_READ 0x10 44 #define SDHCI_TRNS_MULTI 0x20 45 46 #define SDHCI_COMMAND 0x0E 47 #define SDHCI_CMD_RESP_MASK 0x03 48 #define SDHCI_CMD_CRC 0x08 49 #define SDHCI_CMD_INDEX 0x10 50 #define SDHCI_CMD_DATA 0x20 51 #define SDHCI_CMD_ABORTCMD 0xC0 52 53 #define SDHCI_CMD_RESP_NONE 0x00 54 #define SDHCI_CMD_RESP_LONG 0x01 55 #define SDHCI_CMD_RESP_SHORT 0x02 56 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 57 58 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 59 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 60 61 #define SDHCI_RESPONSE 0x10 62 63 #define SDHCI_BUFFER 0x20 64 65 #define SDHCI_PRESENT_STATE 0x24 66 #define SDHCI_CMD_INHIBIT 0x00000001 67 #define SDHCI_DATA_INHIBIT 0x00000002 68 #define SDHCI_DOING_WRITE 0x00000100 69 #define SDHCI_DOING_READ 0x00000200 70 #define SDHCI_SPACE_AVAILABLE 0x00000400 71 #define SDHCI_DATA_AVAILABLE 0x00000800 72 #define SDHCI_CARD_PRESENT 0x00010000 73 #define SDHCI_CARD_PRES_SHIFT 16 74 #define SDHCI_CD_STABLE 0x00020000 75 #define SDHCI_CD_LVL 0x00040000 76 #define SDHCI_CD_LVL_SHIFT 18 77 #define SDHCI_WRITE_PROTECT 0x00080000 78 #define SDHCI_DATA_LVL_MASK 0x00F00000 79 #define SDHCI_DATA_LVL_SHIFT 20 80 #define SDHCI_DATA_0_LVL_MASK 0x00100000 81 #define SDHCI_CMD_LVL 0x01000000 82 83 #define SDHCI_HOST_CONTROL 0x28 84 #define SDHCI_CTRL_LED 0x01 85 #define SDHCI_CTRL_4BITBUS 0x02 86 #define SDHCI_CTRL_HISPD 0x04 87 #define SDHCI_CTRL_DMA_MASK 0x18 88 #define SDHCI_CTRL_SDMA 0x00 89 #define SDHCI_CTRL_ADMA1 0x08 90 #define SDHCI_CTRL_ADMA32 0x10 91 #define SDHCI_CTRL_ADMA64 0x18 92 #define SDHCI_CTRL_ADMA3 0x18 93 #define SDHCI_CTRL_8BITBUS 0x20 94 #define SDHCI_CTRL_CDTEST_INS 0x40 95 #define SDHCI_CTRL_CDTEST_EN 0x80 96 97 #define SDHCI_POWER_CONTROL 0x29 98 #define SDHCI_POWER_ON 0x01 99 #define SDHCI_POWER_180 0x0A 100 #define SDHCI_POWER_300 0x0C 101 #define SDHCI_POWER_330 0x0E 102 /* 103 * VDD2 - UHS2 or PCIe/NVMe 104 * VDD2 power on/off and voltage select 105 */ 106 #define SDHCI_VDD2_POWER_ON 0x10 107 #define SDHCI_VDD2_POWER_120 0x80 108 #define SDHCI_VDD2_POWER_180 0xA0 109 110 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 111 112 #define SDHCI_WAKE_UP_CONTROL 0x2B 113 #define SDHCI_WAKE_ON_INT 0x01 114 #define SDHCI_WAKE_ON_INSERT 0x02 115 #define SDHCI_WAKE_ON_REMOVE 0x04 116 117 #define SDHCI_CLOCK_CONTROL 0x2C 118 #define SDHCI_DIVIDER_SHIFT 8 119 #define SDHCI_DIVIDER_HI_SHIFT 6 120 #define SDHCI_DIV_MASK 0xFF 121 #define SDHCI_DIV_MASK_LEN 8 122 #define SDHCI_DIV_HI_MASK 0x300 123 #define SDHCI_PROG_CLOCK_MODE 0x0020 124 #define SDHCI_CLOCK_CARD_EN 0x0004 125 #define SDHCI_CLOCK_PLL_EN 0x0008 126 #define SDHCI_CLOCK_INT_STABLE 0x0002 127 #define SDHCI_CLOCK_INT_EN 0x0001 128 129 #define SDHCI_TIMEOUT_CONTROL 0x2E 130 131 #define SDHCI_SOFTWARE_RESET 0x2F 132 #define SDHCI_RESET_ALL 0x01 133 #define SDHCI_RESET_CMD 0x02 134 #define SDHCI_RESET_DATA 0x04 135 136 #define SDHCI_INT_STATUS 0x30 137 #define SDHCI_INT_ENABLE 0x34 138 #define SDHCI_SIGNAL_ENABLE 0x38 139 #define SDHCI_INT_RESPONSE 0x00000001 140 #define SDHCI_INT_DATA_END 0x00000002 141 #define SDHCI_INT_BLK_GAP 0x00000004 142 #define SDHCI_INT_DMA_END 0x00000008 143 #define SDHCI_INT_SPACE_AVAIL 0x00000010 144 #define SDHCI_INT_DATA_AVAIL 0x00000020 145 #define SDHCI_INT_CARD_INSERT 0x00000040 146 #define SDHCI_INT_CARD_REMOVE 0x00000080 147 #define SDHCI_INT_CARD_INT 0x00000100 148 #define SDHCI_INT_RETUNE 0x00001000 149 #define SDHCI_INT_CQE 0x00004000 150 #define SDHCI_INT_ERROR 0x00008000 151 #define SDHCI_INT_TIMEOUT 0x00010000 152 #define SDHCI_INT_CRC 0x00020000 153 #define SDHCI_INT_END_BIT 0x00040000 154 #define SDHCI_INT_INDEX 0x00080000 155 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 156 #define SDHCI_INT_DATA_CRC 0x00200000 157 #define SDHCI_INT_DATA_END_BIT 0x00400000 158 #define SDHCI_INT_BUS_POWER 0x00800000 159 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 160 #define SDHCI_INT_ADMA_ERROR 0x02000000 161 #define SDHCI_INT_TUNING_ERROR 0x04000000 162 163 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 164 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 165 166 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 167 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 168 SDHCI_INT_AUTO_CMD_ERR) 169 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 170 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 171 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 172 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 173 SDHCI_INT_BLK_GAP | SDHCI_INT_TUNING_ERROR) 174 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 175 176 #define SDHCI_CQE_INT_ERR_MASK ( \ 177 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 178 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 179 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 180 181 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 182 183 #define SDHCI_AUTO_CMD_STATUS 0x3C 184 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 185 #define SDHCI_AUTO_CMD_CRC 0x00000004 186 #define SDHCI_AUTO_CMD_END_BIT 0x00000008 187 #define SDHCI_AUTO_CMD_INDEX 0x00000010 188 189 #define SDHCI_HOST_CONTROL2 0x3E 190 #define SDHCI_CTRL_UHS_MASK 0x0007 191 #define SDHCI_CTRL_UHS_SDR12 0x0000 192 #define SDHCI_CTRL_UHS_SDR25 0x0001 193 #define SDHCI_CTRL_UHS_SDR50 0x0002 194 #define SDHCI_CTRL_UHS_SDR104 0x0003 195 #define SDHCI_CTRL_UHS_DDR50 0x0004 196 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 197 #define SDHCI_CTRL_VDD_180 0x0008 198 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 199 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 200 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 201 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 202 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 203 #define SDHCI_CTRL_EXEC_TUNING 0x0040 204 #define SDHCI_CTRL_TUNED_CLK 0x0080 205 #define SDHCI_CMD23_ENABLE 0x0800 206 #define SDHCI_CTRL_V4_MODE 0x1000 207 #define SDHCI_CTRL_64BIT_ADDR 0x2000 208 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 209 210 #define SDHCI_CAPABILITIES 0x40 211 #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) 212 #define SDHCI_TIMEOUT_CLK_SHIFT 0 213 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 214 #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) 215 #define SDHCI_CLOCK_BASE_SHIFT 8 216 #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) 217 #define SDHCI_MAX_BLOCK_MASK 0x00030000 218 #define SDHCI_MAX_BLOCK_SHIFT 16 219 #define SDHCI_CAN_DO_8BIT 0x00040000 220 #define SDHCI_CAN_DO_ADMA2 0x00080000 221 #define SDHCI_CAN_DO_ADMA1 0x00100000 222 #define SDHCI_CAN_DO_HISPD 0x00200000 223 #define SDHCI_CAN_DO_SDMA 0x00400000 224 #define SDHCI_CAN_DO_SUSPEND 0x00800000 225 #define SDHCI_CAN_VDD_330 0x01000000 226 #define SDHCI_CAN_VDD_300 0x02000000 227 #define SDHCI_CAN_VDD_180 0x04000000 228 #define SDHCI_CAN_64BIT_V4 0x08000000 229 #define SDHCI_CAN_64BIT 0x10000000 230 231 #define SDHCI_CAPABILITIES_1 0x44 232 #define SDHCI_SUPPORT_SDR50 0x00000001 233 #define SDHCI_SUPPORT_SDR104 0x00000002 234 #define SDHCI_SUPPORT_DDR50 0x00000004 235 #define SDHCI_DRIVER_TYPE_A 0x00000010 236 #define SDHCI_DRIVER_TYPE_C 0x00000020 237 #define SDHCI_DRIVER_TYPE_D 0x00000040 238 #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) 239 #define SDHCI_USE_SDR50_TUNING 0x00002000 240 #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) 241 #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) 242 #define SDHCI_CAN_DO_ADMA3 0x08000000 243 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 244 245 #define SDHCI_MAX_CURRENT 0x48 246 #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) 247 #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) 248 #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) 249 #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) 250 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 251 252 /* 4C-4F reserved for more max current */ 253 254 #define SDHCI_SET_ACMD12_ERROR 0x50 255 #define SDHCI_SET_INT_ERROR 0x52 256 257 #define SDHCI_ADMA_ERROR 0x54 258 259 /* 55-57 reserved */ 260 261 #define SDHCI_ADMA_ADDRESS 0x58 262 #define SDHCI_ADMA_ADDRESS_HI 0x5C 263 264 /* 60-FB reserved */ 265 266 #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 267 #define SDHCI_PRESET_FOR_SDR12 0x66 268 #define SDHCI_PRESET_FOR_SDR25 0x68 269 #define SDHCI_PRESET_FOR_SDR50 0x6A 270 #define SDHCI_PRESET_FOR_SDR104 0x6C 271 #define SDHCI_PRESET_FOR_DDR50 0x6E 272 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 273 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) 274 #define SDHCI_PRESET_CLKGEN_SEL BIT(10) 275 #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) 276 277 #define SDHCI_SLOT_INT_STATUS 0xFC 278 279 #define SDHCI_HOST_VERSION 0xFE 280 #define SDHCI_VENDOR_VER_MASK 0xFF00 281 #define SDHCI_VENDOR_VER_SHIFT 8 282 #define SDHCI_SPEC_VER_MASK 0x00FF 283 #define SDHCI_SPEC_VER_SHIFT 0 284 #define SDHCI_SPEC_100 0 285 #define SDHCI_SPEC_200 1 286 #define SDHCI_SPEC_300 2 287 #define SDHCI_SPEC_400 3 288 #define SDHCI_SPEC_410 4 289 #define SDHCI_SPEC_420 5 290 291 /* 292 * End of controller registers. 293 */ 294 295 #define SDHCI_MAX_DIV_SPEC_200 256 296 #define SDHCI_MAX_DIV_SPEC_300 2046 297 298 /* 299 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 300 */ 301 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 302 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 303 304 /* ADMA2 32-bit DMA descriptor size */ 305 #define SDHCI_ADMA2_32_DESC_SZ 8 306 307 /* ADMA2 32-bit descriptor */ 308 struct sdhci_adma2_32_desc { 309 __le16 cmd; 310 __le16 len; 311 __le32 addr; 312 } __packed __aligned(4); 313 314 /* ADMA2 data alignment */ 315 #define SDHCI_ADMA2_ALIGN 4 316 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 317 318 /* 319 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 320 * alignment for the descriptor table even in 32-bit DMA mode. Memory 321 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 322 */ 323 #define SDHCI_ADMA2_DESC_ALIGN 8 324 325 /* 326 * ADMA2 64-bit DMA descriptor size 327 * According to SD Host Controller spec v4.10, there are two kinds of 328 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 329 * Descriptor, if Host Version 4 Enable is set in the Host Control 2 330 * register, 128-bit Descriptor will be selected. 331 */ 332 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 333 334 /* 335 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 336 * aligned. 337 */ 338 struct sdhci_adma2_64_desc { 339 __le16 cmd; 340 __le16 len; 341 __le32 addr_lo; 342 __le32 addr_hi; 343 } __packed __aligned(4); 344 345 #define ADMA2_TRAN_VALID 0x21 346 #define ADMA2_NOP_END_VALID 0x3 347 #define ADMA2_END 0x2 348 349 /* 350 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 351 * 4KiB page size. Note this also allows enough for multiple descriptors in 352 * case of PAGE_SIZE >= 64KiB. 353 */ 354 #define SDHCI_MAX_SEGS 128 355 356 /* Allow for a command request and a data request at the same time */ 357 #define SDHCI_MAX_MRQS 2 358 359 /* 360 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 361 * However since the start time of the command, the time between 362 * command and response, and the time between response and start of data is 363 * not known, set the command transfer time to 10ms. 364 */ 365 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 366 367 #define sdhci_err_stats_inc(host, err_name) \ 368 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name) 369 370 enum sdhci_cookie { 371 COOKIE_UNMAPPED, 372 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 373 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 374 }; 375 376 struct sdhci_host { 377 /* Data set by hardware interface driver */ 378 const char *hw_name; /* Hardware bus name */ 379 380 unsigned int quirks; /* Deviations from spec. */ 381 382 /* Controller doesn't honor resets unless we touch the clock register */ 383 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 384 /* Controller has bad caps bits, but really supports DMA */ 385 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 386 /* Controller doesn't like to be reset when there is no card inserted. */ 387 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 388 /* Controller doesn't like clearing the power reg before a change */ 389 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 390 /* Controller has an unusable DMA engine */ 391 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 392 /* Controller has an unusable ADMA engine */ 393 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 394 /* Controller can only DMA from 32-bit aligned addresses */ 395 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 396 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 397 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 398 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 399 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 400 /* Controller needs to be reset after each request to stay stable */ 401 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 402 /* Controller needs voltage and power writes to happen separately */ 403 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 404 /* Controller provides an incorrect timeout value for transfers */ 405 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 406 /* Controller has an issue with buffer bits for small transfers */ 407 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 408 /* Controller does not provide transfer-complete interrupt when not busy */ 409 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 410 /* Controller has unreliable card detection */ 411 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 412 /* Controller reports inverted write-protect state */ 413 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 414 /* Controller has unusable command queue engine */ 415 #define SDHCI_QUIRK_BROKEN_CQE (1<<17) 416 /* Controller does not like fast PIO transfers */ 417 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 418 /* Controller does not have a LED */ 419 #define SDHCI_QUIRK_NO_LED (1<<19) 420 /* Controller has to be forced to use block size of 2048 bytes */ 421 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 422 /* Controller cannot do multi-block transfers */ 423 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 424 /* Controller can only handle 1-bit data transfers */ 425 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 426 /* Controller needs 10ms delay between applying power and clock */ 427 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 428 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 429 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 430 /* Controller reports wrong base clock capability */ 431 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 432 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 433 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 434 /* Controller uses Auto CMD12 command to stop the transfer */ 435 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 436 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 437 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 438 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 439 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 440 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 441 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 442 443 unsigned int quirks2; /* More deviations from spec. */ 444 445 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 446 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 447 /* The system physically doesn't support 1.8v, even if the host does */ 448 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 449 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 450 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 451 /* Controller has a non-standard host control register */ 452 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 453 /* Controller does not support HS200 */ 454 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 455 /* Controller does not support DDR50 */ 456 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 457 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 458 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 459 /* Controller does not support 64-bit DMA */ 460 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 461 /* need clear transfer mode register before send cmd */ 462 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 463 /* Capability register bit-63 indicates HS400 support */ 464 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 465 /* forced tuned clock */ 466 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 467 /* disable the block count for single block transactions */ 468 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 469 /* Controller broken with using ACMD23 */ 470 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 471 /* Broken Clock divider zero in controller */ 472 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 473 /* Controller has CRC in 136 bit Command Response */ 474 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 475 /* 476 * Disable HW timeout if the requested timeout is more than the maximum 477 * obtainable timeout. 478 */ 479 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 480 /* 481 * 32-bit block count may not support eMMC where upper bits of CMD23 are used 482 * for other purposes. Consequently we support 16-bit block count by default. 483 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 484 * block count. 485 */ 486 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 487 /* Issue CMD and DATA reset together */ 488 #define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) 489 490 int irq; /* Device IRQ */ 491 void __iomem *ioaddr; /* Mapped address */ 492 phys_addr_t mapbase; /* physical address base */ 493 char *bounce_buffer; /* For packing SDMA reads/writes */ 494 dma_addr_t bounce_addr; 495 unsigned int bounce_buffer_size; 496 497 const struct sdhci_ops *ops; /* Low level hw interface */ 498 499 /* Internal data */ 500 struct mmc_host *mmc; /* MMC structure */ 501 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 502 u64 dma_mask; /* custom DMA mask */ 503 504 #if IS_ENABLED(CONFIG_LEDS_CLASS) 505 struct led_classdev led; /* LED control */ 506 char led_name[32]; 507 #endif 508 509 spinlock_t lock; /* Mutex */ 510 511 int flags; /* Host attributes */ 512 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 513 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 514 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 515 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 516 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 517 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 518 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 519 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 520 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 521 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 522 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 523 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 524 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 525 526 unsigned int version; /* SDHCI spec. version */ 527 528 unsigned int max_clk; /* Max possible freq (MHz) */ 529 unsigned int timeout_clk; /* Timeout freq (KHz) */ 530 u8 max_timeout_count; /* Vendor specific max timeout count */ 531 unsigned int clk_mul; /* Clock Muliplier value */ 532 533 unsigned int clock; /* Current clock (MHz) */ 534 u8 pwr; /* Current voltage */ 535 u8 drv_type; /* Current UHS-I driver type */ 536 bool reinit_uhs; /* Force UHS-related re-initialization */ 537 538 bool runtime_suspended; /* Host is runtime suspended */ 539 bool bus_on; /* Bus power prevents runtime suspend */ 540 bool preset_enabled; /* Preset is enabled */ 541 bool pending_reset; /* Cmd/data reset is pending */ 542 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 543 bool v4_mode; /* Host Version 4 Enable */ 544 bool use_external_dma; /* Host selects to use external DMA */ 545 bool always_defer_done; /* Always defer to complete requests */ 546 547 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 548 struct mmc_command *cmd; /* Current command */ 549 struct mmc_command *data_cmd; /* Current data command */ 550 struct mmc_command *deferred_cmd; /* Deferred command */ 551 struct mmc_data *data; /* Current data request */ 552 unsigned int data_early:1; /* Data finished before cmd */ 553 554 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 555 unsigned int blocks; /* remaining PIO blocks */ 556 557 int sg_count; /* Mapped sg entries */ 558 int max_adma; /* Max. length in ADMA descriptor */ 559 560 void *adma_table; /* ADMA descriptor table */ 561 void *align_buffer; /* Bounce buffer */ 562 563 size_t adma_table_sz; /* ADMA descriptor table size */ 564 size_t align_buffer_sz; /* Bounce buffer size */ 565 566 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 567 dma_addr_t align_addr; /* Mapped bounce buffer */ 568 569 unsigned int desc_sz; /* ADMA current descriptor size */ 570 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ 571 572 struct workqueue_struct *complete_wq; /* Request completion wq */ 573 struct work_struct complete_work; /* Request completion work */ 574 575 struct timer_list timer; /* Timer for timeouts */ 576 struct timer_list data_timer; /* Timer for data timeouts */ 577 578 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) 579 struct dma_chan *rx_chan; 580 struct dma_chan *tx_chan; 581 #endif 582 583 u32 caps; /* CAPABILITY_0 */ 584 u32 caps1; /* CAPABILITY_1 */ 585 bool read_caps; /* Capability flags have been read */ 586 587 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ 588 unsigned int ocr_avail_sdio; /* OCR bit masks */ 589 unsigned int ocr_avail_sd; 590 unsigned int ocr_avail_mmc; 591 u32 ocr_mask; /* available voltages */ 592 593 unsigned timing; /* Current timing */ 594 595 u32 thread_isr; 596 597 /* cached registers */ 598 u32 ier; 599 600 bool cqe_on; /* CQE is operating */ 601 u32 cqe_ier; /* CQE interrupt mask */ 602 u32 cqe_err_ier; /* CQE error interrupt mask */ 603 604 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 605 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 606 607 unsigned int tuning_count; /* Timer count for re-tuning */ 608 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 609 unsigned int tuning_err; /* Error code for re-tuning */ 610 #define SDHCI_TUNING_MODE_1 0 611 #define SDHCI_TUNING_MODE_2 1 612 #define SDHCI_TUNING_MODE_3 2 613 /* Delay (ms) between tuning commands */ 614 int tuning_delay; 615 int tuning_loop_count; 616 617 /* Host SDMA buffer boundary. */ 618 u32 sdma_boundary; 619 620 /* Host ADMA table count */ 621 u32 adma_table_cnt; 622 623 u64 data_timeout; 624 625 unsigned long private[] ____cacheline_aligned; 626 }; 627 628 struct sdhci_ops { 629 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 630 u32 (*read_l)(struct sdhci_host *host, int reg); 631 u16 (*read_w)(struct sdhci_host *host, int reg); 632 u8 (*read_b)(struct sdhci_host *host, int reg); 633 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 634 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 635 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 636 #endif 637 638 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 639 void (*set_power)(struct sdhci_host *host, unsigned char mode, 640 unsigned short vdd); 641 642 u32 (*irq)(struct sdhci_host *host, u32 intmask); 643 644 int (*set_dma_mask)(struct sdhci_host *host); 645 int (*enable_dma)(struct sdhci_host *host); 646 unsigned int (*get_max_clock)(struct sdhci_host *host); 647 unsigned int (*get_min_clock)(struct sdhci_host *host); 648 /* get_timeout_clock should return clk rate in unit of Hz */ 649 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 650 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 651 void (*set_timeout)(struct sdhci_host *host, 652 struct mmc_command *cmd); 653 void (*set_bus_width)(struct sdhci_host *host, int width); 654 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 655 u8 power_mode); 656 unsigned int (*get_ro)(struct sdhci_host *host); 657 void (*reset)(struct sdhci_host *host, u8 mask); 658 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 659 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 660 void (*hw_reset)(struct sdhci_host *host); 661 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 662 void (*card_event)(struct sdhci_host *host); 663 void (*voltage_switch)(struct sdhci_host *host); 664 void (*adma_write_desc)(struct sdhci_host *host, void **desc, 665 dma_addr_t addr, int len, unsigned int cmd); 666 void (*copy_to_bounce_buffer)(struct sdhci_host *host, 667 struct mmc_data *data, 668 unsigned int length); 669 void (*request_done)(struct sdhci_host *host, 670 struct mmc_request *mrq); 671 void (*dump_vendor_regs)(struct sdhci_host *host); 672 }; 673 674 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 675 676 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 677 { 678 if (unlikely(host->ops->write_l)) 679 host->ops->write_l(host, val, reg); 680 else 681 writel(val, host->ioaddr + reg); 682 } 683 684 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 685 { 686 if (unlikely(host->ops->write_w)) 687 host->ops->write_w(host, val, reg); 688 else 689 writew(val, host->ioaddr + reg); 690 } 691 692 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 693 { 694 if (unlikely(host->ops->write_b)) 695 host->ops->write_b(host, val, reg); 696 else 697 writeb(val, host->ioaddr + reg); 698 } 699 700 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 701 { 702 if (unlikely(host->ops->read_l)) 703 return host->ops->read_l(host, reg); 704 else 705 return readl(host->ioaddr + reg); 706 } 707 708 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 709 { 710 if (unlikely(host->ops->read_w)) 711 return host->ops->read_w(host, reg); 712 else 713 return readw(host->ioaddr + reg); 714 } 715 716 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 717 { 718 if (unlikely(host->ops->read_b)) 719 return host->ops->read_b(host, reg); 720 else 721 return readb(host->ioaddr + reg); 722 } 723 724 #else 725 726 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 727 { 728 writel(val, host->ioaddr + reg); 729 } 730 731 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 732 { 733 writew(val, host->ioaddr + reg); 734 } 735 736 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 737 { 738 writeb(val, host->ioaddr + reg); 739 } 740 741 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 742 { 743 return readl(host->ioaddr + reg); 744 } 745 746 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 747 { 748 return readw(host->ioaddr + reg); 749 } 750 751 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 752 { 753 return readb(host->ioaddr + reg); 754 } 755 756 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 757 758 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 759 void sdhci_free_host(struct sdhci_host *host); 760 761 static inline void *sdhci_priv(struct sdhci_host *host) 762 { 763 return host->private; 764 } 765 766 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 767 const u32 *caps, const u32 *caps1); 768 int sdhci_setup_host(struct sdhci_host *host); 769 void sdhci_cleanup_host(struct sdhci_host *host); 770 int __sdhci_add_host(struct sdhci_host *host); 771 int sdhci_add_host(struct sdhci_host *host); 772 void sdhci_remove_host(struct sdhci_host *host, int dead); 773 774 static inline void sdhci_read_caps(struct sdhci_host *host) 775 { 776 __sdhci_read_caps(host, NULL, NULL, NULL); 777 } 778 779 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 780 unsigned int *actual_clock); 781 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 782 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 783 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 784 unsigned short vdd); 785 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, 786 unsigned char mode, 787 unsigned short vdd); 788 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 789 unsigned short vdd); 790 int sdhci_get_cd_nogpio(struct mmc_host *mmc); 791 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 792 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); 793 void sdhci_set_bus_width(struct sdhci_host *host, int width); 794 void sdhci_reset(struct sdhci_host *host, u8 mask); 795 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 796 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 797 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 798 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 799 struct mmc_ios *ios); 800 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 801 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 802 dma_addr_t addr, int len, unsigned int cmd); 803 804 #ifdef CONFIG_PM 805 int sdhci_suspend_host(struct sdhci_host *host); 806 int sdhci_resume_host(struct sdhci_host *host); 807 int sdhci_runtime_suspend_host(struct sdhci_host *host); 808 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 809 #endif 810 811 void sdhci_cqe_enable(struct mmc_host *mmc); 812 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 813 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 814 int *data_error); 815 816 void sdhci_dumpregs(struct sdhci_host *host); 817 void sdhci_enable_v4_mode(struct sdhci_host *host); 818 819 void sdhci_start_tuning(struct sdhci_host *host); 820 void sdhci_end_tuning(struct sdhci_host *host); 821 void sdhci_reset_tuning(struct sdhci_host *host); 822 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 823 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); 824 void sdhci_switch_external_dma(struct sdhci_host *host, bool en); 825 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); 826 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); 827 828 #endif /* __SDHCI_HW_H */ 829