1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/leds.h> 21 #include <linux/interrupt.h> 22 23 #include <linux/mmc/host.h> 24 25 /* 26 * Controller registers 27 */ 28 29 #define SDHCI_DMA_ADDRESS 0x00 30 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 31 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 32 33 #define SDHCI_BLOCK_SIZE 0x04 34 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 35 36 #define SDHCI_BLOCK_COUNT 0x06 37 38 #define SDHCI_ARGUMENT 0x08 39 40 #define SDHCI_TRANSFER_MODE 0x0C 41 #define SDHCI_TRNS_DMA 0x01 42 #define SDHCI_TRNS_BLK_CNT_EN 0x02 43 #define SDHCI_TRNS_AUTO_CMD12 0x04 44 #define SDHCI_TRNS_AUTO_CMD23 0x08 45 #define SDHCI_TRNS_AUTO_SEL 0x0C 46 #define SDHCI_TRNS_READ 0x10 47 #define SDHCI_TRNS_MULTI 0x20 48 49 #define SDHCI_COMMAND 0x0E 50 #define SDHCI_CMD_RESP_MASK 0x03 51 #define SDHCI_CMD_CRC 0x08 52 #define SDHCI_CMD_INDEX 0x10 53 #define SDHCI_CMD_DATA 0x20 54 #define SDHCI_CMD_ABORTCMD 0xC0 55 56 #define SDHCI_CMD_RESP_NONE 0x00 57 #define SDHCI_CMD_RESP_LONG 0x01 58 #define SDHCI_CMD_RESP_SHORT 0x02 59 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 60 61 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 62 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 63 64 #define SDHCI_RESPONSE 0x10 65 66 #define SDHCI_BUFFER 0x20 67 68 #define SDHCI_PRESENT_STATE 0x24 69 #define SDHCI_CMD_INHIBIT 0x00000001 70 #define SDHCI_DATA_INHIBIT 0x00000002 71 #define SDHCI_DOING_WRITE 0x00000100 72 #define SDHCI_DOING_READ 0x00000200 73 #define SDHCI_SPACE_AVAILABLE 0x00000400 74 #define SDHCI_DATA_AVAILABLE 0x00000800 75 #define SDHCI_CARD_PRESENT 0x00010000 76 #define SDHCI_CARD_PRES_SHIFT 16 77 #define SDHCI_CD_STABLE 0x00020000 78 #define SDHCI_CD_LVL 0x00040000 79 #define SDHCI_CD_LVL_SHIFT 18 80 #define SDHCI_WRITE_PROTECT 0x00080000 81 #define SDHCI_DATA_LVL_MASK 0x00F00000 82 #define SDHCI_DATA_LVL_SHIFT 20 83 #define SDHCI_DATA_0_LVL_MASK 0x00100000 84 #define SDHCI_CMD_LVL 0x01000000 85 86 #define SDHCI_HOST_CONTROL 0x28 87 #define SDHCI_CTRL_LED 0x01 88 #define SDHCI_CTRL_4BITBUS 0x02 89 #define SDHCI_CTRL_HISPD 0x04 90 #define SDHCI_CTRL_DMA_MASK 0x18 91 #define SDHCI_CTRL_SDMA 0x00 92 #define SDHCI_CTRL_ADMA1 0x08 93 #define SDHCI_CTRL_ADMA32 0x10 94 #define SDHCI_CTRL_ADMA64 0x18 95 #define SDHCI_CTRL_ADMA3 0x18 96 #define SDHCI_CTRL_8BITBUS 0x20 97 #define SDHCI_CTRL_CDTEST_INS 0x40 98 #define SDHCI_CTRL_CDTEST_EN 0x80 99 100 #define SDHCI_POWER_CONTROL 0x29 101 #define SDHCI_POWER_ON 0x01 102 #define SDHCI_POWER_180 0x0A 103 #define SDHCI_POWER_300 0x0C 104 #define SDHCI_POWER_330 0x0E 105 106 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 107 108 #define SDHCI_WAKE_UP_CONTROL 0x2B 109 #define SDHCI_WAKE_ON_INT 0x01 110 #define SDHCI_WAKE_ON_INSERT 0x02 111 #define SDHCI_WAKE_ON_REMOVE 0x04 112 113 #define SDHCI_CLOCK_CONTROL 0x2C 114 #define SDHCI_DIVIDER_SHIFT 8 115 #define SDHCI_DIVIDER_HI_SHIFT 6 116 #define SDHCI_DIV_MASK 0xFF 117 #define SDHCI_DIV_MASK_LEN 8 118 #define SDHCI_DIV_HI_MASK 0x300 119 #define SDHCI_PROG_CLOCK_MODE 0x0020 120 #define SDHCI_CLOCK_CARD_EN 0x0004 121 #define SDHCI_CLOCK_INT_STABLE 0x0002 122 #define SDHCI_CLOCK_INT_EN 0x0001 123 124 #define SDHCI_TIMEOUT_CONTROL 0x2E 125 126 #define SDHCI_SOFTWARE_RESET 0x2F 127 #define SDHCI_RESET_ALL 0x01 128 #define SDHCI_RESET_CMD 0x02 129 #define SDHCI_RESET_DATA 0x04 130 131 #define SDHCI_INT_STATUS 0x30 132 #define SDHCI_INT_ENABLE 0x34 133 #define SDHCI_SIGNAL_ENABLE 0x38 134 #define SDHCI_INT_RESPONSE 0x00000001 135 #define SDHCI_INT_DATA_END 0x00000002 136 #define SDHCI_INT_BLK_GAP 0x00000004 137 #define SDHCI_INT_DMA_END 0x00000008 138 #define SDHCI_INT_SPACE_AVAIL 0x00000010 139 #define SDHCI_INT_DATA_AVAIL 0x00000020 140 #define SDHCI_INT_CARD_INSERT 0x00000040 141 #define SDHCI_INT_CARD_REMOVE 0x00000080 142 #define SDHCI_INT_CARD_INT 0x00000100 143 #define SDHCI_INT_RETUNE 0x00001000 144 #define SDHCI_INT_CQE 0x00004000 145 #define SDHCI_INT_ERROR 0x00008000 146 #define SDHCI_INT_TIMEOUT 0x00010000 147 #define SDHCI_INT_CRC 0x00020000 148 #define SDHCI_INT_END_BIT 0x00040000 149 #define SDHCI_INT_INDEX 0x00080000 150 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 151 #define SDHCI_INT_DATA_CRC 0x00200000 152 #define SDHCI_INT_DATA_END_BIT 0x00400000 153 #define SDHCI_INT_BUS_POWER 0x00800000 154 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 155 #define SDHCI_INT_ADMA_ERROR 0x02000000 156 157 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 158 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 159 160 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 161 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 162 SDHCI_INT_AUTO_CMD_ERR) 163 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 164 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 165 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 166 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 167 SDHCI_INT_BLK_GAP) 168 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 169 170 #define SDHCI_CQE_INT_ERR_MASK ( \ 171 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 172 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 173 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 174 175 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 176 177 #define SDHCI_AUTO_CMD_STATUS 0x3C 178 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 179 #define SDHCI_AUTO_CMD_CRC 0x00000004 180 #define SDHCI_AUTO_CMD_END_BIT 0x00000008 181 #define SDHCI_AUTO_CMD_INDEX 0x00000010 182 183 #define SDHCI_HOST_CONTROL2 0x3E 184 #define SDHCI_CTRL_UHS_MASK 0x0007 185 #define SDHCI_CTRL_UHS_SDR12 0x0000 186 #define SDHCI_CTRL_UHS_SDR25 0x0001 187 #define SDHCI_CTRL_UHS_SDR50 0x0002 188 #define SDHCI_CTRL_UHS_SDR104 0x0003 189 #define SDHCI_CTRL_UHS_DDR50 0x0004 190 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 191 #define SDHCI_CTRL_VDD_180 0x0008 192 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 193 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 194 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 195 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 196 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 197 #define SDHCI_CTRL_EXEC_TUNING 0x0040 198 #define SDHCI_CTRL_TUNED_CLK 0x0080 199 #define SDHCI_CMD23_ENABLE 0x0800 200 #define SDHCI_CTRL_V4_MODE 0x1000 201 #define SDHCI_CTRL_64BIT_ADDR 0x2000 202 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 203 204 #define SDHCI_CAPABILITIES 0x40 205 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 206 #define SDHCI_TIMEOUT_CLK_SHIFT 0 207 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 208 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 209 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 210 #define SDHCI_CLOCK_BASE_SHIFT 8 211 #define SDHCI_MAX_BLOCK_MASK 0x00030000 212 #define SDHCI_MAX_BLOCK_SHIFT 16 213 #define SDHCI_CAN_DO_8BIT 0x00040000 214 #define SDHCI_CAN_DO_ADMA2 0x00080000 215 #define SDHCI_CAN_DO_ADMA1 0x00100000 216 #define SDHCI_CAN_DO_HISPD 0x00200000 217 #define SDHCI_CAN_DO_SDMA 0x00400000 218 #define SDHCI_CAN_DO_SUSPEND 0x00800000 219 #define SDHCI_CAN_VDD_330 0x01000000 220 #define SDHCI_CAN_VDD_300 0x02000000 221 #define SDHCI_CAN_VDD_180 0x04000000 222 #define SDHCI_CAN_64BIT_V4 0x08000000 223 #define SDHCI_CAN_64BIT 0x10000000 224 225 #define SDHCI_SUPPORT_SDR50 0x00000001 226 #define SDHCI_SUPPORT_SDR104 0x00000002 227 #define SDHCI_SUPPORT_DDR50 0x00000004 228 #define SDHCI_DRIVER_TYPE_A 0x00000010 229 #define SDHCI_DRIVER_TYPE_C 0x00000020 230 #define SDHCI_DRIVER_TYPE_D 0x00000040 231 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 232 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 233 #define SDHCI_USE_SDR50_TUNING 0x00002000 234 #define SDHCI_RETUNING_MODE_MASK 0x0000C000 235 #define SDHCI_RETUNING_MODE_SHIFT 14 236 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 237 #define SDHCI_CLOCK_MUL_SHIFT 16 238 #define SDHCI_CAN_DO_ADMA3 0x08000000 239 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 240 241 #define SDHCI_CAPABILITIES_1 0x44 242 243 #define SDHCI_MAX_CURRENT 0x48 244 #define SDHCI_MAX_CURRENT_LIMIT 0xFF 245 #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 246 #define SDHCI_MAX_CURRENT_330_SHIFT 0 247 #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 248 #define SDHCI_MAX_CURRENT_300_SHIFT 8 249 #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 250 #define SDHCI_MAX_CURRENT_180_SHIFT 16 251 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 252 253 /* 4C-4F reserved for more max current */ 254 255 #define SDHCI_SET_ACMD12_ERROR 0x50 256 #define SDHCI_SET_INT_ERROR 0x52 257 258 #define SDHCI_ADMA_ERROR 0x54 259 260 /* 55-57 reserved */ 261 262 #define SDHCI_ADMA_ADDRESS 0x58 263 #define SDHCI_ADMA_ADDRESS_HI 0x5C 264 265 /* 60-FB reserved */ 266 267 #define SDHCI_PRESET_FOR_SDR12 0x66 268 #define SDHCI_PRESET_FOR_SDR25 0x68 269 #define SDHCI_PRESET_FOR_SDR50 0x6A 270 #define SDHCI_PRESET_FOR_SDR104 0x6C 271 #define SDHCI_PRESET_FOR_DDR50 0x6E 272 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 273 #define SDHCI_PRESET_DRV_MASK 0xC000 274 #define SDHCI_PRESET_DRV_SHIFT 14 275 #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 276 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 277 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 278 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 279 280 #define SDHCI_SLOT_INT_STATUS 0xFC 281 282 #define SDHCI_HOST_VERSION 0xFE 283 #define SDHCI_VENDOR_VER_MASK 0xFF00 284 #define SDHCI_VENDOR_VER_SHIFT 8 285 #define SDHCI_SPEC_VER_MASK 0x00FF 286 #define SDHCI_SPEC_VER_SHIFT 0 287 #define SDHCI_SPEC_100 0 288 #define SDHCI_SPEC_200 1 289 #define SDHCI_SPEC_300 2 290 #define SDHCI_SPEC_400 3 291 #define SDHCI_SPEC_410 4 292 #define SDHCI_SPEC_420 5 293 294 /* 295 * End of controller registers. 296 */ 297 298 #define SDHCI_MAX_DIV_SPEC_200 256 299 #define SDHCI_MAX_DIV_SPEC_300 2046 300 301 /* 302 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 303 */ 304 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 305 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 306 307 /* ADMA2 32-bit DMA descriptor size */ 308 #define SDHCI_ADMA2_32_DESC_SZ 8 309 310 /* ADMA2 32-bit descriptor */ 311 struct sdhci_adma2_32_desc { 312 __le16 cmd; 313 __le16 len; 314 __le32 addr; 315 } __packed __aligned(4); 316 317 /* ADMA2 data alignment */ 318 #define SDHCI_ADMA2_ALIGN 4 319 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 320 321 /* 322 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 323 * alignment for the descriptor table even in 32-bit DMA mode. Memory 324 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 325 */ 326 #define SDHCI_ADMA2_DESC_ALIGN 8 327 328 /* 329 * ADMA2 64-bit DMA descriptor size 330 * According to SD Host Controller spec v4.10, there are two kinds of 331 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 332 * Descriptor, if Host Version 4 Enable is set in the Host Control 2 333 * register, 128-bit Descriptor will be selected. 334 */ 335 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 336 337 /* 338 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 339 * aligned. 340 */ 341 struct sdhci_adma2_64_desc { 342 __le16 cmd; 343 __le16 len; 344 __le32 addr_lo; 345 __le32 addr_hi; 346 } __packed __aligned(4); 347 348 #define ADMA2_TRAN_VALID 0x21 349 #define ADMA2_NOP_END_VALID 0x3 350 #define ADMA2_END 0x2 351 352 /* 353 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 354 * 4KiB page size. 355 */ 356 #define SDHCI_MAX_SEGS 128 357 358 /* Allow for a a command request and a data request at the same time */ 359 #define SDHCI_MAX_MRQS 2 360 361 /* 362 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 363 * However since the start time of the command, the time between 364 * command and response, and the time between response and start of data is 365 * not known, set the command transfer time to 10ms. 366 */ 367 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 368 369 enum sdhci_cookie { 370 COOKIE_UNMAPPED, 371 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 372 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 373 }; 374 375 struct sdhci_host { 376 /* Data set by hardware interface driver */ 377 const char *hw_name; /* Hardware bus name */ 378 379 unsigned int quirks; /* Deviations from spec. */ 380 381 /* Controller doesn't honor resets unless we touch the clock register */ 382 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 383 /* Controller has bad caps bits, but really supports DMA */ 384 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 385 /* Controller doesn't like to be reset when there is no card inserted. */ 386 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 387 /* Controller doesn't like clearing the power reg before a change */ 388 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 389 /* Controller has flaky internal state so reset it on each ios change */ 390 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 391 /* Controller has an unusable DMA engine */ 392 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 393 /* Controller has an unusable ADMA engine */ 394 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 395 /* Controller can only DMA from 32-bit aligned addresses */ 396 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 397 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 398 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 399 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 400 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 401 /* Controller needs to be reset after each request to stay stable */ 402 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 403 /* Controller needs voltage and power writes to happen separately */ 404 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 405 /* Controller provides an incorrect timeout value for transfers */ 406 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 407 /* Controller has an issue with buffer bits for small transfers */ 408 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 409 /* Controller does not provide transfer-complete interrupt when not busy */ 410 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 411 /* Controller has unreliable card detection */ 412 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 413 /* Controller reports inverted write-protect state */ 414 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 415 /* Controller does not like fast PIO transfers */ 416 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 417 /* Controller does not have a LED */ 418 #define SDHCI_QUIRK_NO_LED (1<<19) 419 /* Controller has to be forced to use block size of 2048 bytes */ 420 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 421 /* Controller cannot do multi-block transfers */ 422 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 423 /* Controller can only handle 1-bit data transfers */ 424 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 425 /* Controller needs 10ms delay between applying power and clock */ 426 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 427 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 428 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 429 /* Controller reports wrong base clock capability */ 430 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 431 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 432 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 433 /* Controller is missing device caps. Use caps provided by host */ 434 #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 435 /* Controller uses Auto CMD12 command to stop the transfer */ 436 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 437 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 438 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 439 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 440 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 441 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 442 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 443 444 unsigned int quirks2; /* More deviations from spec. */ 445 446 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 447 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 448 /* The system physically doesn't support 1.8v, even if the host does */ 449 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 450 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 451 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 452 /* Controller has a non-standard host control register */ 453 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 454 /* Controller does not support HS200 */ 455 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 456 /* Controller does not support DDR50 */ 457 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 458 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 459 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 460 /* Controller does not support 64-bit DMA */ 461 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 462 /* need clear transfer mode register before send cmd */ 463 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 464 /* Capability register bit-63 indicates HS400 support */ 465 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 466 /* forced tuned clock */ 467 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 468 /* disable the block count for single block transactions */ 469 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 470 /* Controller broken with using ACMD23 */ 471 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 472 /* Broken Clock divider zero in controller */ 473 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 474 /* Controller has CRC in 136 bit Command Response */ 475 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 476 /* 477 * Disable HW timeout if the requested timeout is more than the maximum 478 * obtainable timeout. 479 */ 480 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 481 /* 482 * 32-bit block count may not support eMMC where upper bits of CMD23 are used 483 * for other purposes. Consequently we support 16-bit block count by default. 484 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 485 * block count. 486 */ 487 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 488 489 int irq; /* Device IRQ */ 490 void __iomem *ioaddr; /* Mapped address */ 491 char *bounce_buffer; /* For packing SDMA reads/writes */ 492 dma_addr_t bounce_addr; 493 unsigned int bounce_buffer_size; 494 495 const struct sdhci_ops *ops; /* Low level hw interface */ 496 497 /* Internal data */ 498 struct mmc_host *mmc; /* MMC structure */ 499 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 500 u64 dma_mask; /* custom DMA mask */ 501 502 #if IS_ENABLED(CONFIG_LEDS_CLASS) 503 struct led_classdev led; /* LED control */ 504 char led_name[32]; 505 #endif 506 507 spinlock_t lock; /* Mutex */ 508 509 int flags; /* Host attributes */ 510 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 511 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 512 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 513 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 514 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 515 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 516 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 517 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 518 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 519 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 520 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 521 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 522 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 523 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 524 525 unsigned int version; /* SDHCI spec. version */ 526 527 unsigned int max_clk; /* Max possible freq (MHz) */ 528 unsigned int timeout_clk; /* Timeout freq (KHz) */ 529 unsigned int clk_mul; /* Clock Muliplier value */ 530 531 unsigned int clock; /* Current clock (MHz) */ 532 u8 pwr; /* Current voltage */ 533 534 bool runtime_suspended; /* Host is runtime suspended */ 535 bool bus_on; /* Bus power prevents runtime suspend */ 536 bool preset_enabled; /* Preset is enabled */ 537 bool pending_reset; /* Cmd/data reset is pending */ 538 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 539 bool v4_mode; /* Host Version 4 Enable */ 540 541 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 542 struct mmc_command *cmd; /* Current command */ 543 struct mmc_command *data_cmd; /* Current data command */ 544 struct mmc_data *data; /* Current data request */ 545 unsigned int data_early:1; /* Data finished before cmd */ 546 547 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 548 unsigned int blocks; /* remaining PIO blocks */ 549 550 int sg_count; /* Mapped sg entries */ 551 552 void *adma_table; /* ADMA descriptor table */ 553 void *align_buffer; /* Bounce buffer */ 554 555 size_t adma_table_sz; /* ADMA descriptor table size */ 556 size_t align_buffer_sz; /* Bounce buffer size */ 557 558 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 559 dma_addr_t align_addr; /* Mapped bounce buffer */ 560 561 unsigned int desc_sz; /* ADMA descriptor size */ 562 563 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 564 565 struct timer_list timer; /* Timer for timeouts */ 566 struct timer_list data_timer; /* Timer for data timeouts */ 567 568 u32 caps; /* CAPABILITY_0 */ 569 u32 caps1; /* CAPABILITY_1 */ 570 bool read_caps; /* Capability flags have been read */ 571 572 unsigned int ocr_avail_sdio; /* OCR bit masks */ 573 unsigned int ocr_avail_sd; 574 unsigned int ocr_avail_mmc; 575 u32 ocr_mask; /* available voltages */ 576 577 unsigned timing; /* Current timing */ 578 579 u32 thread_isr; 580 581 /* cached registers */ 582 u32 ier; 583 584 bool cqe_on; /* CQE is operating */ 585 u32 cqe_ier; /* CQE interrupt mask */ 586 u32 cqe_err_ier; /* CQE error interrupt mask */ 587 588 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 589 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 590 591 unsigned int tuning_count; /* Timer count for re-tuning */ 592 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 593 unsigned int tuning_err; /* Error code for re-tuning */ 594 #define SDHCI_TUNING_MODE_1 0 595 #define SDHCI_TUNING_MODE_2 1 596 #define SDHCI_TUNING_MODE_3 2 597 /* Delay (ms) between tuning commands */ 598 int tuning_delay; 599 600 /* Host SDMA buffer boundary. */ 601 u32 sdma_boundary; 602 603 /* Host ADMA table count */ 604 u32 adma_table_cnt; 605 606 u64 data_timeout; 607 608 unsigned long private[0] ____cacheline_aligned; 609 }; 610 611 struct sdhci_ops { 612 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 613 u32 (*read_l)(struct sdhci_host *host, int reg); 614 u16 (*read_w)(struct sdhci_host *host, int reg); 615 u8 (*read_b)(struct sdhci_host *host, int reg); 616 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 617 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 618 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 619 #endif 620 621 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 622 void (*set_power)(struct sdhci_host *host, unsigned char mode, 623 unsigned short vdd); 624 625 u32 (*irq)(struct sdhci_host *host, u32 intmask); 626 627 int (*enable_dma)(struct sdhci_host *host); 628 unsigned int (*get_max_clock)(struct sdhci_host *host); 629 unsigned int (*get_min_clock)(struct sdhci_host *host); 630 /* get_timeout_clock should return clk rate in unit of Hz */ 631 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 632 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 633 void (*set_timeout)(struct sdhci_host *host, 634 struct mmc_command *cmd); 635 void (*set_bus_width)(struct sdhci_host *host, int width); 636 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 637 u8 power_mode); 638 unsigned int (*get_ro)(struct sdhci_host *host); 639 void (*reset)(struct sdhci_host *host, u8 mask); 640 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 641 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 642 void (*hw_reset)(struct sdhci_host *host); 643 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 644 void (*card_event)(struct sdhci_host *host); 645 void (*voltage_switch)(struct sdhci_host *host); 646 void (*adma_write_desc)(struct sdhci_host *host, void **desc, 647 dma_addr_t addr, int len, unsigned int cmd); 648 }; 649 650 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 651 652 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 653 { 654 if (unlikely(host->ops->write_l)) 655 host->ops->write_l(host, val, reg); 656 else 657 writel(val, host->ioaddr + reg); 658 } 659 660 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 661 { 662 if (unlikely(host->ops->write_w)) 663 host->ops->write_w(host, val, reg); 664 else 665 writew(val, host->ioaddr + reg); 666 } 667 668 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 669 { 670 if (unlikely(host->ops->write_b)) 671 host->ops->write_b(host, val, reg); 672 else 673 writeb(val, host->ioaddr + reg); 674 } 675 676 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 677 { 678 if (unlikely(host->ops->read_l)) 679 return host->ops->read_l(host, reg); 680 else 681 return readl(host->ioaddr + reg); 682 } 683 684 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 685 { 686 if (unlikely(host->ops->read_w)) 687 return host->ops->read_w(host, reg); 688 else 689 return readw(host->ioaddr + reg); 690 } 691 692 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 693 { 694 if (unlikely(host->ops->read_b)) 695 return host->ops->read_b(host, reg); 696 else 697 return readb(host->ioaddr + reg); 698 } 699 700 #else 701 702 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 703 { 704 writel(val, host->ioaddr + reg); 705 } 706 707 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 708 { 709 writew(val, host->ioaddr + reg); 710 } 711 712 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 713 { 714 writeb(val, host->ioaddr + reg); 715 } 716 717 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 718 { 719 return readl(host->ioaddr + reg); 720 } 721 722 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 723 { 724 return readw(host->ioaddr + reg); 725 } 726 727 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 728 { 729 return readb(host->ioaddr + reg); 730 } 731 732 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 733 734 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 735 void sdhci_free_host(struct sdhci_host *host); 736 737 static inline void *sdhci_priv(struct sdhci_host *host) 738 { 739 return host->private; 740 } 741 742 void sdhci_card_detect(struct sdhci_host *host); 743 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 744 u32 *caps1); 745 int sdhci_setup_host(struct sdhci_host *host); 746 void sdhci_cleanup_host(struct sdhci_host *host); 747 int __sdhci_add_host(struct sdhci_host *host); 748 int sdhci_add_host(struct sdhci_host *host); 749 void sdhci_remove_host(struct sdhci_host *host, int dead); 750 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 751 752 static inline void sdhci_read_caps(struct sdhci_host *host) 753 { 754 __sdhci_read_caps(host, NULL, NULL, NULL); 755 } 756 757 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 758 { 759 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 760 } 761 762 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 763 unsigned int *actual_clock); 764 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 765 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 766 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 767 unsigned short vdd); 768 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 769 unsigned short vdd); 770 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 771 void sdhci_set_bus_width(struct sdhci_host *host, int width); 772 void sdhci_reset(struct sdhci_host *host, u8 mask); 773 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 774 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 775 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 776 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 777 struct mmc_ios *ios); 778 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 779 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 780 dma_addr_t addr, int len, unsigned int cmd); 781 782 #ifdef CONFIG_PM 783 int sdhci_suspend_host(struct sdhci_host *host); 784 int sdhci_resume_host(struct sdhci_host *host); 785 int sdhci_runtime_suspend_host(struct sdhci_host *host); 786 int sdhci_runtime_resume_host(struct sdhci_host *host); 787 #endif 788 789 void sdhci_cqe_enable(struct mmc_host *mmc); 790 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 791 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 792 int *data_error); 793 794 void sdhci_dumpregs(struct sdhci_host *host); 795 void sdhci_enable_v4_mode(struct sdhci_host *host); 796 797 void sdhci_start_tuning(struct sdhci_host *host); 798 void sdhci_end_tuning(struct sdhci_host *host); 799 void sdhci_reset_tuning(struct sdhci_host *host); 800 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 801 802 #endif /* __SDHCI_HW_H */ 803