11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 41978fda8SGiuseppe Cavallaro * Header file for Host Controller registers and I/O accessors. 51978fda8SGiuseppe Cavallaro * 6b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 71c6a0718SPierre Ossman * 81c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 91c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 101c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 111c6a0718SPierre Ossman * your option) any later version. 121c6a0718SPierre Ossman */ 131978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H 141978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H 151c6a0718SPierre Ossman 160c7ad106SAndrew Morton #include <linux/scatterlist.h> 174e4141a5SAnton Vorontsov #include <linux/compiler.h> 184e4141a5SAnton Vorontsov #include <linux/types.h> 194e4141a5SAnton Vorontsov #include <linux/io.h> 200c7ad106SAndrew Morton 211978fda8SGiuseppe Cavallaro #include <linux/mmc/sdhci.h> 221978fda8SGiuseppe Cavallaro 231c6a0718SPierre Ossman /* 241c6a0718SPierre Ossman * Controller registers 251c6a0718SPierre Ossman */ 261c6a0718SPierre Ossman 271c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 281c6a0718SPierre Ossman 291c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 301c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 311c6a0718SPierre Ossman 321c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 351c6a0718SPierre Ossman 361c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 371c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 381c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 391c6a0718SPierre Ossman #define SDHCI_TRNS_ACMD12 0x04 401c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 411c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 441c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 451c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 461c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 471c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 48574e3f56SRichard Zhu #define SDHCI_CMD_ABORTCMD 0xC0 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 511c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 521c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 531c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 541c6a0718SPierre Ossman 551c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 5622113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 571c6a0718SPierre Ossman 581c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 591c6a0718SPierre Ossman 601c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 611c6a0718SPierre Ossman 621c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 631c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 641c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 651c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 661c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 671c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 681c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 691c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 701c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 71f2119df6SArindam Nath #define SDHCI_DATA_LVL_MASK 0x00F00000 72f2119df6SArindam Nath #define SDHCI_DATA_LVL_SHIFT 20 731c6a0718SPierre Ossman 741c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 751c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 761c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 771c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 782134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 792134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 802134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 812134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 822134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 83ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 841c6a0718SPierre Ossman 851c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 861c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 871c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 881c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 891c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 901c6a0718SPierre Ossman 911c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 921c6a0718SPierre Ossman 932df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 945f619704SDaniel Drake #define SDHCI_WAKE_ON_INT 0x01 955f619704SDaniel Drake #define SDHCI_WAKE_ON_INSERT 0x02 965f619704SDaniel Drake #define SDHCI_WAKE_ON_REMOVE 0x04 971c6a0718SPierre Ossman 981c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 991c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 10085105c53SZhangfei Gao #define SDHCI_DIVIDER_HI_SHIFT 6 10185105c53SZhangfei Gao #define SDHCI_DIV_MASK 0xFF 10285105c53SZhangfei Gao #define SDHCI_DIV_MASK_LEN 8 10385105c53SZhangfei Gao #define SDHCI_DIV_HI_MASK 0x300 104c3ed3877SArindam Nath #define SDHCI_PROG_CLOCK_MODE 0x0020 1051c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 1061c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 1071c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 1081c6a0718SPierre Ossman 1091c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 1101c6a0718SPierre Ossman 1111c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 1121c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 1131c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 1141c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 1151c6a0718SPierre Ossman 1161c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1171c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1181c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1191c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1201c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 1211c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1221c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1231c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1241c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1251c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1261c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 127964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1281c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1291c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1301c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1311c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1321c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1331c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1341c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1351c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 1361c6a0718SPierre Ossman #define SDHCI_INT_ACMD12ERR 0x01000000 1372134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1381c6a0718SPierre Ossman 1391c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1401c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1411c6a0718SPierre Ossman 1421c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 1431c6a0718SPierre Ossman SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 1441c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1451c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1461c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 147a751a7d6SZhangfei Gao SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 1487260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1491c6a0718SPierre Ossman 1501c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR 0x3C 1511c6a0718SPierre Ossman 152f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2 0x3E 15349c468fcSArindam Nath #define SDHCI_CTRL_UHS_MASK 0x0007 15449c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR12 0x0000 15549c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR25 0x0001 15649c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR50 0x0002 15749c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR104 0x0003 15849c468fcSArindam Nath #define SDHCI_CTRL_UHS_DDR50 0x0004 159f2119df6SArindam Nath #define SDHCI_CTRL_VDD_180 0x0008 160d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 161d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_B 0x0000 162d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_A 0x0010 163d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_C 0x0020 164d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_D 0x0030 165b513ea25SArindam Nath #define SDHCI_CTRL_EXEC_TUNING 0x0040 166b513ea25SArindam Nath #define SDHCI_CTRL_TUNED_CLK 0x0080 167d6d50a15SArindam Nath #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 1681c6a0718SPierre Ossman 1691c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 1701c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 1711c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 1721c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 1731c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 174c4687d5fSZhangfei Gao #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 1751c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 1761c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 1771c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 17815ec4461SPhilip Rakity #define SDHCI_CAN_DO_8BIT 0x00040000 1792134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 1802134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 1811c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 182a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 1831c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 1841c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 1851c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 1862134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 1871c6a0718SPierre Ossman 188f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR50 0x00000001 189f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR104 0x00000002 190f2119df6SArindam Nath #define SDHCI_SUPPORT_DDR50 0x00000004 191d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_A 0x00000010 192d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_C 0x00000020 193d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_D 0x00000040 194cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 195cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 196b513ea25SArindam Nath #define SDHCI_USE_SDR50_TUNING 0x00002000 197cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_MASK 0x0000C000 198cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_SHIFT 14 199c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 200c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_SHIFT 16 201f2119df6SArindam Nath 202e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1 0x44 2031c6a0718SPierre Ossman 2041c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 205f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 206f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_SHIFT 0 207f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 208f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_SHIFT 8 209f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 210f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_SHIFT 16 211f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_MULTIPLIER 4 2121c6a0718SPierre Ossman 2131c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 2141c6a0718SPierre Ossman 2152134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 2162134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 2172134a922SPierre Ossman 2182134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 2192134a922SPierre Ossman 2202134a922SPierre Ossman /* 55-57 reserved */ 2212134a922SPierre Ossman 2222134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 2232134a922SPierre Ossman 2242134a922SPierre Ossman /* 60-FB reserved */ 2251c6a0718SPierre Ossman 2261c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 2271c6a0718SPierre Ossman 2281c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 2291c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 2301c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 2311c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 2321c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 2332134a922SPierre Ossman #define SDHCI_SPEC_100 0 2342134a922SPierre Ossman #define SDHCI_SPEC_200 1 23585105c53SZhangfei Gao #define SDHCI_SPEC_300 2 2361c6a0718SPierre Ossman 2370397526dSZhangfei Gao /* 2380397526dSZhangfei Gao * End of controller registers. 2390397526dSZhangfei Gao */ 2400397526dSZhangfei Gao 2410397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200 256 2420397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300 2046 2430397526dSZhangfei Gao 244f6a03cbfSMikko Vinni /* 245f6a03cbfSMikko Vinni * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 246f6a03cbfSMikko Vinni */ 247f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 248f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 249f6a03cbfSMikko Vinni 250b8c86fc5SPierre Ossman struct sdhci_ops { 2514e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 252dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 253dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 254dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 255dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 256dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 257dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 2584e4141a5SAnton Vorontsov #endif 2594e4141a5SAnton Vorontsov 2608114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 2618114634cSAnton Vorontsov 262b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 2634240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 264a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 2654240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 26615ec4461SPhilip Rakity int (*platform_8bit_width)(struct sdhci_host *host, 26715ec4461SPhilip Rakity int width); 268643a81ffSPhilip Rakity void (*platform_send_init_74_clocks)(struct sdhci_host *host, 269643a81ffSPhilip Rakity u8 power_mode); 2702dfb579cSWolfram Sang unsigned int (*get_ro)(struct sdhci_host *host); 271393c1a34SPhilip Rakity void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); 272393c1a34SPhilip Rakity void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); 2731c6a0718SPierre Ossman }; 274b8c86fc5SPierre Ossman 2754e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 2764e4141a5SAnton Vorontsov 2774e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 2784e4141a5SAnton Vorontsov { 279dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 280dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 2814e4141a5SAnton Vorontsov else 2824e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 2834e4141a5SAnton Vorontsov } 2844e4141a5SAnton Vorontsov 2854e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 2864e4141a5SAnton Vorontsov { 287dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 288dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 2894e4141a5SAnton Vorontsov else 2904e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 2914e4141a5SAnton Vorontsov } 2924e4141a5SAnton Vorontsov 2934e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 2944e4141a5SAnton Vorontsov { 295dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 296dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 2974e4141a5SAnton Vorontsov else 2984e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 2994e4141a5SAnton Vorontsov } 3004e4141a5SAnton Vorontsov 3014e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3024e4141a5SAnton Vorontsov { 303dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 304dc297c92SMatt Fleming return host->ops->read_l(host, reg); 3054e4141a5SAnton Vorontsov else 3064e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3074e4141a5SAnton Vorontsov } 3084e4141a5SAnton Vorontsov 3094e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3104e4141a5SAnton Vorontsov { 311dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 312dc297c92SMatt Fleming return host->ops->read_w(host, reg); 3134e4141a5SAnton Vorontsov else 3144e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3154e4141a5SAnton Vorontsov } 3164e4141a5SAnton Vorontsov 3174e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3184e4141a5SAnton Vorontsov { 319dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 320dc297c92SMatt Fleming return host->ops->read_b(host, reg); 3214e4141a5SAnton Vorontsov else 3224e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3234e4141a5SAnton Vorontsov } 3244e4141a5SAnton Vorontsov 3254e4141a5SAnton Vorontsov #else 3264e4141a5SAnton Vorontsov 3274e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 3284e4141a5SAnton Vorontsov { 3294e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 3304e4141a5SAnton Vorontsov } 3314e4141a5SAnton Vorontsov 3324e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 3334e4141a5SAnton Vorontsov { 3344e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 3354e4141a5SAnton Vorontsov } 3364e4141a5SAnton Vorontsov 3374e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 3384e4141a5SAnton Vorontsov { 3394e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3404e4141a5SAnton Vorontsov } 3414e4141a5SAnton Vorontsov 3424e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3434e4141a5SAnton Vorontsov { 3444e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3454e4141a5SAnton Vorontsov } 3464e4141a5SAnton Vorontsov 3474e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3484e4141a5SAnton Vorontsov { 3494e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3504e4141a5SAnton Vorontsov } 3514e4141a5SAnton Vorontsov 3524e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3534e4141a5SAnton Vorontsov { 3544e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3554e4141a5SAnton Vorontsov } 3564e4141a5SAnton Vorontsov 3574e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 358b8c86fc5SPierre Ossman 359b8c86fc5SPierre Ossman extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 360b8c86fc5SPierre Ossman size_t priv_size); 361b8c86fc5SPierre Ossman extern void sdhci_free_host(struct sdhci_host *host); 362b8c86fc5SPierre Ossman 363b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 364b8c86fc5SPierre Ossman { 365b8c86fc5SPierre Ossman return (void *)host->private; 366b8c86fc5SPierre Ossman } 367b8c86fc5SPierre Ossman 36817866e14SMarek Szyprowski extern void sdhci_card_detect(struct sdhci_host *host); 369b8c86fc5SPierre Ossman extern int sdhci_add_host(struct sdhci_host *host); 3701e72859eSPierre Ossman extern void sdhci_remove_host(struct sdhci_host *host, int dead); 371b8c86fc5SPierre Ossman 372b8c86fc5SPierre Ossman #ifdef CONFIG_PM 373b8c86fc5SPierre Ossman extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state); 374b8c86fc5SPierre Ossman extern int sdhci_resume_host(struct sdhci_host *host); 3755f619704SDaniel Drake extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 376b8c86fc5SPierre Ossman #endif 377c0bba0d2SAlbert Herranz 3781978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */ 379