12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 41c6a0718SPierre Ossman * 51978fda8SGiuseppe Cavallaro * Header file for Host Controller registers and I/O accessors. 61978fda8SGiuseppe Cavallaro * 7b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 81c6a0718SPierre Ossman */ 91978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H 101978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H 111c6a0718SPierre Ossman 120c7ad106SAndrew Morton #include <linux/scatterlist.h> 134e4141a5SAnton Vorontsov #include <linux/compiler.h> 144e4141a5SAnton Vorontsov #include <linux/types.h> 154e4141a5SAnton Vorontsov #include <linux/io.h> 16210583f4SUlf Hansson #include <linux/leds.h> 17b8789ec4SUlf Hansson #include <linux/interrupt.h> 180c7ad106SAndrew Morton 1983f13cc9SUlf Hansson #include <linux/mmc/host.h> 201978fda8SGiuseppe Cavallaro 211c6a0718SPierre Ossman /* 221c6a0718SPierre Ossman * Controller registers 231c6a0718SPierre Ossman */ 241c6a0718SPierre Ossman 251c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 268edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 27e65953d4SChunyan Zhang #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 281c6a0718SPierre Ossman 291c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 301c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 311c6a0718SPierre Ossman 321c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 351c6a0718SPierre Ossman 361c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 371c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 381c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 39e89d456fSAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD12 0x04 408edf6371SAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD23 0x08 41427b6514SChunyan Zhang #define SDHCI_TRNS_AUTO_SEL 0x0C 421c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 431c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 461c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 471c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 481c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 491c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 50574e3f56SRichard Zhu #define SDHCI_CMD_ABORTCMD 0xC0 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 531c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 541c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 551c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 561c6a0718SPierre Ossman 571c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 5822113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 591c6a0718SPierre Ossman 601c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 611c6a0718SPierre Ossman 621c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 631c6a0718SPierre Ossman 641c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 651c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 661c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 671c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 681c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 691c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 701c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 711c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 7269d91ed1SErnest Zhang(WH) #define SDHCI_CARD_PRES_SHIFT 16 7369d91ed1SErnest Zhang(WH) #define SDHCI_CD_STABLE 0x00020000 7469d91ed1SErnest Zhang(WH) #define SDHCI_CD_LVL 0x00040000 7569d91ed1SErnest Zhang(WH) #define SDHCI_CD_LVL_SHIFT 18 761c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 77f2119df6SArindam Nath #define SDHCI_DATA_LVL_MASK 0x00F00000 78f2119df6SArindam Nath #define SDHCI_DATA_LVL_SHIFT 20 797756a96dSYi Sun #define SDHCI_DATA_0_LVL_MASK 0x00100000 80b0921d5cSMichael Walle #define SDHCI_CMD_LVL 0x01000000 811c6a0718SPierre Ossman 821c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 831c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 841c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 851c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 862134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 872134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 882134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 892134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 902134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 914c4faff6SSowjanya Komatineni #define SDHCI_CTRL_ADMA3 0x18 92ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 933794c542SZach Brown #define SDHCI_CTRL_CDTEST_INS 0x40 943794c542SZach Brown #define SDHCI_CTRL_CDTEST_EN 0x80 951c6a0718SPierre Ossman 961c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 971c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 981c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 991c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 1001c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 1011c6a0718SPierre Ossman 1021c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 1031c6a0718SPierre Ossman 1042df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 1055f619704SDaniel Drake #define SDHCI_WAKE_ON_INT 0x01 1065f619704SDaniel Drake #define SDHCI_WAKE_ON_INSERT 0x02 1075f619704SDaniel Drake #define SDHCI_WAKE_ON_REMOVE 0x04 1081c6a0718SPierre Ossman 1091c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 1101c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 11185105c53SZhangfei Gao #define SDHCI_DIVIDER_HI_SHIFT 6 11285105c53SZhangfei Gao #define SDHCI_DIV_MASK 0xFF 11385105c53SZhangfei Gao #define SDHCI_DIV_MASK_LEN 8 11485105c53SZhangfei Gao #define SDHCI_DIV_HI_MASK 0x300 115c3ed3877SArindam Nath #define SDHCI_PROG_CLOCK_MODE 0x0020 1161c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 1171c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 1181c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 1191c6a0718SPierre Ossman 1201c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 1211c6a0718SPierre Ossman 1221c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 1231c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 1241c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 1251c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 1261c6a0718SPierre Ossman 1271c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1281c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1291c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1301c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1311c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 132a4071fbbSHaijun Zhang #define SDHCI_INT_BLK_GAP 0x00000004 1331c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1341c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1351c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1361c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1371c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1381c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 139f37b20ebSDong Aisheng #define SDHCI_INT_RETUNE 0x00001000 140f12e39dbSAdrian Hunter #define SDHCI_INT_CQE 0x00004000 141964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1421c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1431c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1441c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1451c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1461c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1471c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1481c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1491c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 150869f8a69SAdrian Hunter #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 1512134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1521c6a0718SPierre Ossman 1531c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1541c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1551c6a0718SPierre Ossman 1561c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 157af849c86SAdrian Hunter SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 158af849c86SAdrian Hunter SDHCI_INT_AUTO_CMD_ERR) 1591c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1601c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1611c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 162a4071fbbSHaijun Zhang SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 163a4071fbbSHaijun Zhang SDHCI_INT_BLK_GAP) 1647260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1651c6a0718SPierre Ossman 166f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_ERR_MASK ( \ 167f12e39dbSAdrian Hunter SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 168f12e39dbSAdrian Hunter SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 169f12e39dbSAdrian Hunter SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 170f12e39dbSAdrian Hunter 171f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 172f12e39dbSAdrian Hunter 173869f8a69SAdrian Hunter #define SDHCI_AUTO_CMD_STATUS 0x3C 174af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 175af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_CRC 0x00000004 176af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_END_BIT 0x00000008 177af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_INDEX 0x00000010 1781c6a0718SPierre Ossman 179f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2 0x3E 18049c468fcSArindam Nath #define SDHCI_CTRL_UHS_MASK 0x0007 18149c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR12 0x0000 18249c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR25 0x0001 18349c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR50 0x0002 18449c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR104 0x0003 18549c468fcSArindam Nath #define SDHCI_CTRL_UHS_DDR50 0x0004 186e9fb05d5SAdrian Hunter #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 187f2119df6SArindam Nath #define SDHCI_CTRL_VDD_180 0x0008 188d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 189d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_B 0x0000 190d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_A 0x0010 191d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_C 0x0020 192d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_D 0x0030 193b513ea25SArindam Nath #define SDHCI_CTRL_EXEC_TUNING 0x0040 194b513ea25SArindam Nath #define SDHCI_CTRL_TUNED_CLK 0x0080 195427b6514SChunyan Zhang #define SDHCI_CMD23_ENABLE 0x0800 196b3f80b43SChunyan Zhang #define SDHCI_CTRL_V4_MODE 0x1000 197685e444bSChunyan Zhang #define SDHCI_CTRL_64BIT_ADDR 0x2000 198d6d50a15SArindam Nath #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 1991c6a0718SPierre Ossman 2001c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 2011c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 2021c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 2031c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 2041c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 205c4687d5fSZhangfei Gao #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 2061c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 2071c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 2081c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 20915ec4461SPhilip Rakity #define SDHCI_CAN_DO_8BIT 0x00040000 2102134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 2112134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 2121c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 213a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 214e71d4b81SStefan Wahren #define SDHCI_CAN_DO_SUSPEND 0x00800000 2151c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 2161c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 2171c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 218685e444bSChunyan Zhang #define SDHCI_CAN_64BIT_V4 0x08000000 2192134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 2201c6a0718SPierre Ossman 221f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR50 0x00000001 222f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR104 0x00000002 223f2119df6SArindam Nath #define SDHCI_SUPPORT_DDR50 0x00000004 224d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_A 0x00000010 225d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_C 0x00000020 226d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_D 0x00000040 227cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 228cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 229b513ea25SArindam Nath #define SDHCI_USE_SDR50_TUNING 0x00002000 230cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_MASK 0x0000C000 231cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_SHIFT 14 232c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 233c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_SHIFT 16 2344c4faff6SSowjanya Komatineni #define SDHCI_CAN_DO_ADMA3 0x08000000 235e9fb05d5SAdrian Hunter #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 236f2119df6SArindam Nath 237e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1 0x44 2381c6a0718SPierre Ossman 2391c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 240bad37e1aSPhilip Rakity #define SDHCI_MAX_CURRENT_LIMIT 0xFF 241f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 242f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_SHIFT 0 243f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 244f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_SHIFT 8 245f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 246f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_SHIFT 16 247f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_MULTIPLIER 4 2481c6a0718SPierre Ossman 2491c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 2501c6a0718SPierre Ossman 2512134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 2522134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 2532134a922SPierre Ossman 2542134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 2552134a922SPierre Ossman 2562134a922SPierre Ossman /* 55-57 reserved */ 2572134a922SPierre Ossman 2582134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 259e57a5f61SAdrian Hunter #define SDHCI_ADMA_ADDRESS_HI 0x5C 2602134a922SPierre Ossman 2612134a922SPierre Ossman /* 60-FB reserved */ 2621c6a0718SPierre Ossman 26352983382SKevin Liu #define SDHCI_PRESET_FOR_SDR12 0x66 26452983382SKevin Liu #define SDHCI_PRESET_FOR_SDR25 0x68 26552983382SKevin Liu #define SDHCI_PRESET_FOR_SDR50 0x6A 26652983382SKevin Liu #define SDHCI_PRESET_FOR_SDR104 0x6C 26752983382SKevin Liu #define SDHCI_PRESET_FOR_DDR50 0x6E 268e9fb05d5SAdrian Hunter #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 26952983382SKevin Liu #define SDHCI_PRESET_DRV_MASK 0xC000 27052983382SKevin Liu #define SDHCI_PRESET_DRV_SHIFT 14 27152983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 27252983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 27352983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 27452983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 27552983382SKevin Liu 2761c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 2771c6a0718SPierre Ossman 2781c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 2791c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 2801c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 2811c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 2821c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 2832134a922SPierre Ossman #define SDHCI_SPEC_100 0 2842134a922SPierre Ossman #define SDHCI_SPEC_200 1 28585105c53SZhangfei Gao #define SDHCI_SPEC_300 2 28618da1990SChunyan Zhang #define SDHCI_SPEC_400 3 28718da1990SChunyan Zhang #define SDHCI_SPEC_410 4 28818da1990SChunyan Zhang #define SDHCI_SPEC_420 5 2891c6a0718SPierre Ossman 2900397526dSZhangfei Gao /* 2910397526dSZhangfei Gao * End of controller registers. 2920397526dSZhangfei Gao */ 2930397526dSZhangfei Gao 2940397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200 256 2950397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300 2046 2960397526dSZhangfei Gao 297f6a03cbfSMikko Vinni /* 298f6a03cbfSMikko Vinni * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 299f6a03cbfSMikko Vinni */ 300f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 301f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 302f6a03cbfSMikko Vinni 303739d46dcSAdrian Hunter /* ADMA2 32-bit DMA descriptor size */ 304739d46dcSAdrian Hunter #define SDHCI_ADMA2_32_DESC_SZ 8 305739d46dcSAdrian Hunter 3060545230fSAdrian Hunter /* ADMA2 32-bit descriptor */ 3070545230fSAdrian Hunter struct sdhci_adma2_32_desc { 3080545230fSAdrian Hunter __le16 cmd; 3090545230fSAdrian Hunter __le16 len; 3100545230fSAdrian Hunter __le32 addr; 31104a5ae6fSAdrian Hunter } __packed __aligned(4); 31204a5ae6fSAdrian Hunter 31304a5ae6fSAdrian Hunter /* ADMA2 data alignment */ 31404a5ae6fSAdrian Hunter #define SDHCI_ADMA2_ALIGN 4 31504a5ae6fSAdrian Hunter #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 31604a5ae6fSAdrian Hunter 31704a5ae6fSAdrian Hunter /* 31804a5ae6fSAdrian Hunter * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 31904a5ae6fSAdrian Hunter * alignment for the descriptor table even in 32-bit DMA mode. Memory 32004a5ae6fSAdrian Hunter * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 32104a5ae6fSAdrian Hunter */ 32204a5ae6fSAdrian Hunter #define SDHCI_ADMA2_DESC_ALIGN 8 3230545230fSAdrian Hunter 324685e444bSChunyan Zhang /* 325685e444bSChunyan Zhang * ADMA2 64-bit DMA descriptor size 326685e444bSChunyan Zhang * According to SD Host Controller spec v4.10, there are two kinds of 327685e444bSChunyan Zhang * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 328685e444bSChunyan Zhang * Descriptor, if Host Version 4 Enable is set in the Host Control 2 329685e444bSChunyan Zhang * register, 128-bit Descriptor will be selected. 330685e444bSChunyan Zhang */ 331685e444bSChunyan Zhang #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 332e57a5f61SAdrian Hunter 333e57a5f61SAdrian Hunter /* 334e57a5f61SAdrian Hunter * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 335e57a5f61SAdrian Hunter * aligned. 336e57a5f61SAdrian Hunter */ 337e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc { 338e57a5f61SAdrian Hunter __le16 cmd; 339e57a5f61SAdrian Hunter __le16 len; 340e57a5f61SAdrian Hunter __le32 addr_lo; 341e57a5f61SAdrian Hunter __le32 addr_hi; 342e57a5f61SAdrian Hunter } __packed __aligned(4); 343e57a5f61SAdrian Hunter 344739d46dcSAdrian Hunter #define ADMA2_TRAN_VALID 0x21 345739d46dcSAdrian Hunter #define ADMA2_NOP_END_VALID 0x3 346739d46dcSAdrian Hunter #define ADMA2_END 0x2 347739d46dcSAdrian Hunter 3484fb213f8SAdrian Hunter /* 3494fb213f8SAdrian Hunter * Maximum segments assuming a 512KiB maximum requisition size and a minimum 3504fb213f8SAdrian Hunter * 4KiB page size. 3514fb213f8SAdrian Hunter */ 3524fb213f8SAdrian Hunter #define SDHCI_MAX_SEGS 128 3534fb213f8SAdrian Hunter 3544e9f8fe5SAdrian Hunter /* Allow for a a command request and a data request at the same time */ 3554e9f8fe5SAdrian Hunter #define SDHCI_MAX_MRQS 2 3564e9f8fe5SAdrian Hunter 357fc1fa1b7SKishon Vijay Abraham I /* 358fc1fa1b7SKishon Vijay Abraham I * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 359fc1fa1b7SKishon Vijay Abraham I * However since the start time of the command, the time between 360fc1fa1b7SKishon Vijay Abraham I * command and response, and the time between response and start of data is 361fc1fa1b7SKishon Vijay Abraham I * not known, set the command transfer time to 10ms. 362fc1fa1b7SKishon Vijay Abraham I */ 363fc1fa1b7SKishon Vijay Abraham I #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 364fc1fa1b7SKishon Vijay Abraham I 365d31911b9SHaibo Chen enum sdhci_cookie { 366d31911b9SHaibo Chen COOKIE_UNMAPPED, 36794538e51SRussell King COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 36894538e51SRussell King COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 36983f13cc9SUlf Hansson }; 37083f13cc9SUlf Hansson 37183f13cc9SUlf Hansson struct sdhci_host { 37283f13cc9SUlf Hansson /* Data set by hardware interface driver */ 37383f13cc9SUlf Hansson const char *hw_name; /* Hardware bus name */ 37483f13cc9SUlf Hansson 37583f13cc9SUlf Hansson unsigned int quirks; /* Deviations from spec. */ 37683f13cc9SUlf Hansson 37783f13cc9SUlf Hansson /* Controller doesn't honor resets unless we touch the clock register */ 37883f13cc9SUlf Hansson #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 37983f13cc9SUlf Hansson /* Controller has bad caps bits, but really supports DMA */ 38083f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_DMA (1<<1) 38183f13cc9SUlf Hansson /* Controller doesn't like to be reset when there is no card inserted. */ 38283f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 38383f13cc9SUlf Hansson /* Controller doesn't like clearing the power reg before a change */ 38483f13cc9SUlf Hansson #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 38583f13cc9SUlf Hansson /* Controller has flaky internal state so reset it on each ios change */ 38683f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 38783f13cc9SUlf Hansson /* Controller has an unusable DMA engine */ 38883f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 38983f13cc9SUlf Hansson /* Controller has an unusable ADMA engine */ 39083f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 39183f13cc9SUlf Hansson /* Controller can only DMA from 32-bit aligned addresses */ 39283f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 39383f13cc9SUlf Hansson /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 39483f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 39583f13cc9SUlf Hansson /* Controller can only ADMA chunks that are a multiple of 32 bits */ 39683f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 39783f13cc9SUlf Hansson /* Controller needs to be reset after each request to stay stable */ 39883f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 39983f13cc9SUlf Hansson /* Controller needs voltage and power writes to happen separately */ 40083f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 40183f13cc9SUlf Hansson /* Controller provides an incorrect timeout value for transfers */ 40283f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 40383f13cc9SUlf Hansson /* Controller has an issue with buffer bits for small transfers */ 40483f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 40583f13cc9SUlf Hansson /* Controller does not provide transfer-complete interrupt when not busy */ 40683f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 40783f13cc9SUlf Hansson /* Controller has unreliable card detection */ 40883f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 40983f13cc9SUlf Hansson /* Controller reports inverted write-protect state */ 41083f13cc9SUlf Hansson #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 41183f13cc9SUlf Hansson /* Controller does not like fast PIO transfers */ 41283f13cc9SUlf Hansson #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 413bd29f58bSAdrian Hunter /* Controller does not have a LED */ 414bd29f58bSAdrian Hunter #define SDHCI_QUIRK_NO_LED (1<<19) 41583f13cc9SUlf Hansson /* Controller has to be forced to use block size of 2048 bytes */ 41683f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 41783f13cc9SUlf Hansson /* Controller cannot do multi-block transfers */ 41883f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 41983f13cc9SUlf Hansson /* Controller can only handle 1-bit data transfers */ 42083f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 42183f13cc9SUlf Hansson /* Controller needs 10ms delay between applying power and clock */ 42283f13cc9SUlf Hansson #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 42383f13cc9SUlf Hansson /* Controller uses SDCLK instead of TMCLK for data timeouts */ 42483f13cc9SUlf Hansson #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 42583f13cc9SUlf Hansson /* Controller reports wrong base clock capability */ 42683f13cc9SUlf Hansson #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 42783f13cc9SUlf Hansson /* Controller cannot support End Attribute in NOP ADMA descriptor */ 42883f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 42983f13cc9SUlf Hansson /* Controller is missing device caps. Use caps provided by host */ 43083f13cc9SUlf Hansson #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 43183f13cc9SUlf Hansson /* Controller uses Auto CMD12 command to stop the transfer */ 43283f13cc9SUlf Hansson #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 43383f13cc9SUlf Hansson /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 43483f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 43583f13cc9SUlf Hansson /* Controller treats ADMA descriptors with length 0000h incorrectly */ 43683f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 43783f13cc9SUlf Hansson /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 43883f13cc9SUlf Hansson #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 43983f13cc9SUlf Hansson 44083f13cc9SUlf Hansson unsigned int quirks2; /* More deviations from spec. */ 44183f13cc9SUlf Hansson 44283f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 44383f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 44483f13cc9SUlf Hansson /* The system physically doesn't support 1.8v, even if the host does */ 44583f13cc9SUlf Hansson #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 44683f13cc9SUlf Hansson #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 44783f13cc9SUlf Hansson #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 44883f13cc9SUlf Hansson /* Controller has a non-standard host control register */ 44983f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 45083f13cc9SUlf Hansson /* Controller does not support HS200 */ 45183f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 45283f13cc9SUlf Hansson /* Controller does not support DDR50 */ 45383f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 45483f13cc9SUlf Hansson /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 45583f13cc9SUlf Hansson #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 45683f13cc9SUlf Hansson /* Controller does not support 64-bit DMA */ 45783f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 45883f13cc9SUlf Hansson /* need clear transfer mode register before send cmd */ 45983f13cc9SUlf Hansson #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 46083f13cc9SUlf Hansson /* Capability register bit-63 indicates HS400 support */ 46183f13cc9SUlf Hansson #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 46283f13cc9SUlf Hansson /* forced tuned clock */ 46383f13cc9SUlf Hansson #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 46483f13cc9SUlf Hansson /* disable the block count for single block transactions */ 46583f13cc9SUlf Hansson #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 46683f13cc9SUlf Hansson /* Controller broken with using ACMD23 */ 46783f13cc9SUlf Hansson #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 468d1955c3aSSuneel Garapati /* Broken Clock divider zero in controller */ 469d1955c3aSSuneel Garapati #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 4701284c248SKishon Vijay Abraham I /* Controller has CRC in 136 bit Command Response */ 4711284c248SKishon Vijay Abraham I #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 472a999fd93SAdrian Hunter /* 473a999fd93SAdrian Hunter * Disable HW timeout if the requested timeout is more than the maximum 474a999fd93SAdrian Hunter * obtainable timeout. 475a999fd93SAdrian Hunter */ 476a999fd93SAdrian Hunter #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 477e65953d4SChunyan Zhang /* 478e65953d4SChunyan Zhang * 32-bit block count may not support eMMC where upper bits of CMD23 are used 479e65953d4SChunyan Zhang * for other purposes. Consequently we support 16-bit block count by default. 480e65953d4SChunyan Zhang * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 481e65953d4SChunyan Zhang * block count. 482e65953d4SChunyan Zhang */ 483e65953d4SChunyan Zhang #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 48483f13cc9SUlf Hansson 48583f13cc9SUlf Hansson int irq; /* Device IRQ */ 48683f13cc9SUlf Hansson void __iomem *ioaddr; /* Mapped address */ 487bd9b9027SLinus Walleij char *bounce_buffer; /* For packing SDMA reads/writes */ 488bd9b9027SLinus Walleij dma_addr_t bounce_addr; 489bd9b9027SLinus Walleij unsigned int bounce_buffer_size; 49083f13cc9SUlf Hansson 49183f13cc9SUlf Hansson const struct sdhci_ops *ops; /* Low level hw interface */ 49283f13cc9SUlf Hansson 49383f13cc9SUlf Hansson /* Internal data */ 49483f13cc9SUlf Hansson struct mmc_host *mmc; /* MMC structure */ 495bf60e592SAdrian Hunter struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 49683f13cc9SUlf Hansson u64 dma_mask; /* custom DMA mask */ 49783f13cc9SUlf Hansson 49874479c5dSMasahiro Yamada #if IS_ENABLED(CONFIG_LEDS_CLASS) 49983f13cc9SUlf Hansson struct led_classdev led; /* LED control */ 50083f13cc9SUlf Hansson char led_name[32]; 50183f13cc9SUlf Hansson #endif 50283f13cc9SUlf Hansson 50383f13cc9SUlf Hansson spinlock_t lock; /* Mutex */ 50483f13cc9SUlf Hansson 50583f13cc9SUlf Hansson int flags; /* Host attributes */ 50683f13cc9SUlf Hansson #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 50783f13cc9SUlf Hansson #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 50883f13cc9SUlf Hansson #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 50983f13cc9SUlf Hansson #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 51083f13cc9SUlf Hansson #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 51183f13cc9SUlf Hansson #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 51283f13cc9SUlf Hansson #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 51383f13cc9SUlf Hansson #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 51483f13cc9SUlf Hansson #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 51583f13cc9SUlf Hansson #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 51683f13cc9SUlf Hansson #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 5178cb851a4SAdrian Hunter #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 5188cb851a4SAdrian Hunter #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 5198cb851a4SAdrian Hunter #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 52083f13cc9SUlf Hansson 52183f13cc9SUlf Hansson unsigned int version; /* SDHCI spec. version */ 52283f13cc9SUlf Hansson 52383f13cc9SUlf Hansson unsigned int max_clk; /* Max possible freq (MHz) */ 52483f13cc9SUlf Hansson unsigned int timeout_clk; /* Timeout freq (KHz) */ 52583f13cc9SUlf Hansson unsigned int clk_mul; /* Clock Muliplier value */ 52683f13cc9SUlf Hansson 52783f13cc9SUlf Hansson unsigned int clock; /* Current clock (MHz) */ 52883f13cc9SUlf Hansson u8 pwr; /* Current voltage */ 52983f13cc9SUlf Hansson 53083f13cc9SUlf Hansson bool runtime_suspended; /* Host is runtime suspended */ 53183f13cc9SUlf Hansson bool bus_on; /* Bus power prevents runtime suspend */ 53283f13cc9SUlf Hansson bool preset_enabled; /* Preset is enabled */ 533ed1563deSAdrian Hunter bool pending_reset; /* Cmd/data reset is pending */ 53458e79b60SAdrian Hunter bool irq_wake_enabled; /* IRQ wakeup is enabled */ 535b3f80b43SChunyan Zhang bool v4_mode; /* Host Version 4 Enable */ 53683f13cc9SUlf Hansson 5374e9f8fe5SAdrian Hunter struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 53883f13cc9SUlf Hansson struct mmc_command *cmd; /* Current command */ 5397c89a3d9SAdrian Hunter struct mmc_command *data_cmd; /* Current data command */ 54083f13cc9SUlf Hansson struct mmc_data *data; /* Current data request */ 54183f13cc9SUlf Hansson unsigned int data_early:1; /* Data finished before cmd */ 54283f13cc9SUlf Hansson 54383f13cc9SUlf Hansson struct sg_mapping_iter sg_miter; /* SG state for PIO */ 54483f13cc9SUlf Hansson unsigned int blocks; /* remaining PIO blocks */ 54583f13cc9SUlf Hansson 54683f13cc9SUlf Hansson int sg_count; /* Mapped sg entries */ 54783f13cc9SUlf Hansson 54883f13cc9SUlf Hansson void *adma_table; /* ADMA descriptor table */ 54983f13cc9SUlf Hansson void *align_buffer; /* Bounce buffer */ 55083f13cc9SUlf Hansson 55183f13cc9SUlf Hansson size_t adma_table_sz; /* ADMA descriptor table size */ 55283f13cc9SUlf Hansson size_t align_buffer_sz; /* Bounce buffer size */ 55383f13cc9SUlf Hansson 55483f13cc9SUlf Hansson dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 55583f13cc9SUlf Hansson dma_addr_t align_addr; /* Mapped bounce buffer */ 55683f13cc9SUlf Hansson 55783f13cc9SUlf Hansson unsigned int desc_sz; /* ADMA descriptor size */ 55883f13cc9SUlf Hansson 559c07a48c2SAdrian Hunter struct workqueue_struct *complete_wq; /* Request completion wq */ 560c07a48c2SAdrian Hunter struct work_struct complete_work; /* Request completion work */ 56183f13cc9SUlf Hansson 56283f13cc9SUlf Hansson struct timer_list timer; /* Timer for timeouts */ 563d7422fb4SAdrian Hunter struct timer_list data_timer; /* Timer for data timeouts */ 56483f13cc9SUlf Hansson 56528da3589SAdrian Hunter u32 caps; /* CAPABILITY_0 */ 56628da3589SAdrian Hunter u32 caps1; /* CAPABILITY_1 */ 5676132a3bfSAdrian Hunter bool read_caps; /* Capability flags have been read */ 56883f13cc9SUlf Hansson 56983f13cc9SUlf Hansson unsigned int ocr_avail_sdio; /* OCR bit masks */ 57083f13cc9SUlf Hansson unsigned int ocr_avail_sd; 57183f13cc9SUlf Hansson unsigned int ocr_avail_mmc; 57283f13cc9SUlf Hansson u32 ocr_mask; /* available voltages */ 57383f13cc9SUlf Hansson 57483f13cc9SUlf Hansson unsigned timing; /* Current timing */ 57583f13cc9SUlf Hansson 57683f13cc9SUlf Hansson u32 thread_isr; 57783f13cc9SUlf Hansson 57883f13cc9SUlf Hansson /* cached registers */ 57983f13cc9SUlf Hansson u32 ier; 58083f13cc9SUlf Hansson 581f12e39dbSAdrian Hunter bool cqe_on; /* CQE is operating */ 582f12e39dbSAdrian Hunter u32 cqe_ier; /* CQE interrupt mask */ 583f12e39dbSAdrian Hunter u32 cqe_err_ier; /* CQE error interrupt mask */ 584f12e39dbSAdrian Hunter 58583f13cc9SUlf Hansson wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 58683f13cc9SUlf Hansson unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 58783f13cc9SUlf Hansson 58883f13cc9SUlf Hansson unsigned int tuning_count; /* Timer count for re-tuning */ 58983f13cc9SUlf Hansson unsigned int tuning_mode; /* Re-tuning mode supported by host */ 5907d8bb1f4SYinbo Zhu unsigned int tuning_err; /* Error code for re-tuning */ 59183f13cc9SUlf Hansson #define SDHCI_TUNING_MODE_1 0 592f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_2 1 593f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_3 2 59483b600b8SAdrian Hunter /* Delay (ms) between tuning commands */ 59583b600b8SAdrian Hunter int tuning_delay; 5961d8cd065SSowjanya Komatineni int tuning_loop_count; 59783f13cc9SUlf Hansson 598c846a00fSSrinivas Kandagatla /* Host SDMA buffer boundary. */ 599c846a00fSSrinivas Kandagatla u32 sdma_boundary; 600c846a00fSSrinivas Kandagatla 601e93be38aSJisheng Zhang /* Host ADMA table count */ 602e93be38aSJisheng Zhang u32 adma_table_cnt; 603e93be38aSJisheng Zhang 604fc1fa1b7SKishon Vijay Abraham I u64 data_timeout; 605fc1fa1b7SKishon Vijay Abraham I 60683f13cc9SUlf Hansson unsigned long private[0] ____cacheline_aligned; 60783f13cc9SUlf Hansson }; 60883f13cc9SUlf Hansson 609b8c86fc5SPierre Ossman struct sdhci_ops { 6104e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 611dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 612dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 613dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 614dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 615dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 616dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 6174e4141a5SAnton Vorontsov #endif 6184e4141a5SAnton Vorontsov 6198114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 6201dceb041SAdrian Hunter void (*set_power)(struct sdhci_host *host, unsigned char mode, 6211dceb041SAdrian Hunter unsigned short vdd); 6228114634cSAnton Vorontsov 623f12e39dbSAdrian Hunter u32 (*irq)(struct sdhci_host *host, u32 intmask); 624f12e39dbSAdrian Hunter 625b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 6264240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 627a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 6288cc35289SShawn Lin /* get_timeout_clock should return clk rate in unit of Hz */ 6294240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 630a6ff5aebSAisheng Dong unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 631b45e668aSAisheng Dong void (*set_timeout)(struct sdhci_host *host, 632b45e668aSAisheng Dong struct mmc_command *cmd); 6332317f56cSRussell King void (*set_bus_width)(struct sdhci_host *host, int width); 634643a81ffSPhilip Rakity void (*platform_send_init_74_clocks)(struct sdhci_host *host, 635643a81ffSPhilip Rakity u8 power_mode); 6362dfb579cSWolfram Sang unsigned int (*get_ro)(struct sdhci_host *host); 63703231f9bSRussell King void (*reset)(struct sdhci_host *host, u8 mask); 63845251812SDong Aisheng int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 63913e64501SRussell King void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 64020758b66SAdrian Hunter void (*hw_reset)(struct sdhci_host *host); 641a4071fbbSHaijun Zhang void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 642722e1280SChristian Daudt void (*card_event)(struct sdhci_host *host); 6439d967a61SVincent Yang void (*voltage_switch)(struct sdhci_host *host); 64454552e49SJisheng Zhang void (*adma_write_desc)(struct sdhci_host *host, void **desc, 64554552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd); 6461c6a0718SPierre Ossman }; 647b8c86fc5SPierre Ossman 6484e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 6494e4141a5SAnton Vorontsov 6504e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 6514e4141a5SAnton Vorontsov { 652dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 653dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 6544e4141a5SAnton Vorontsov else 6554e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 6564e4141a5SAnton Vorontsov } 6574e4141a5SAnton Vorontsov 6584e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 6594e4141a5SAnton Vorontsov { 660dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 661dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 6624e4141a5SAnton Vorontsov else 6634e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 6644e4141a5SAnton Vorontsov } 6654e4141a5SAnton Vorontsov 6664e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 6674e4141a5SAnton Vorontsov { 668dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 669dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 6704e4141a5SAnton Vorontsov else 6714e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 6724e4141a5SAnton Vorontsov } 6734e4141a5SAnton Vorontsov 6744e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 6754e4141a5SAnton Vorontsov { 676dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 677dc297c92SMatt Fleming return host->ops->read_l(host, reg); 6784e4141a5SAnton Vorontsov else 6794e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 6804e4141a5SAnton Vorontsov } 6814e4141a5SAnton Vorontsov 6824e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 6834e4141a5SAnton Vorontsov { 684dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 685dc297c92SMatt Fleming return host->ops->read_w(host, reg); 6864e4141a5SAnton Vorontsov else 6874e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 6884e4141a5SAnton Vorontsov } 6894e4141a5SAnton Vorontsov 6904e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 6914e4141a5SAnton Vorontsov { 692dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 693dc297c92SMatt Fleming return host->ops->read_b(host, reg); 6944e4141a5SAnton Vorontsov else 6954e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 6964e4141a5SAnton Vorontsov } 6974e4141a5SAnton Vorontsov 6984e4141a5SAnton Vorontsov #else 6994e4141a5SAnton Vorontsov 7004e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 7014e4141a5SAnton Vorontsov { 7024e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 7034e4141a5SAnton Vorontsov } 7044e4141a5SAnton Vorontsov 7054e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 7064e4141a5SAnton Vorontsov { 7074e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 7084e4141a5SAnton Vorontsov } 7094e4141a5SAnton Vorontsov 7104e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 7114e4141a5SAnton Vorontsov { 7124e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 7134e4141a5SAnton Vorontsov } 7144e4141a5SAnton Vorontsov 7154e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 7164e4141a5SAnton Vorontsov { 7174e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 7184e4141a5SAnton Vorontsov } 7194e4141a5SAnton Vorontsov 7204e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 7214e4141a5SAnton Vorontsov { 7224e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 7234e4141a5SAnton Vorontsov } 7244e4141a5SAnton Vorontsov 7254e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 7264e4141a5SAnton Vorontsov { 7274e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 7284e4141a5SAnton Vorontsov } 7294e4141a5SAnton Vorontsov 7304e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 731b8c86fc5SPierre Ossman 73215becf68SAdrian Hunter struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 73315becf68SAdrian Hunter void sdhci_free_host(struct sdhci_host *host); 734b8c86fc5SPierre Ossman 735b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 736b8c86fc5SPierre Ossman { 737178b0fa0SMasahiro Yamada return host->private; 738b8c86fc5SPierre Ossman } 739b8c86fc5SPierre Ossman 74015becf68SAdrian Hunter void sdhci_card_detect(struct sdhci_host *host); 74115becf68SAdrian Hunter void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 7426132a3bfSAdrian Hunter u32 *caps1); 74315becf68SAdrian Hunter int sdhci_setup_host(struct sdhci_host *host); 7444180ffa8SAdrian Hunter void sdhci_cleanup_host(struct sdhci_host *host); 74515becf68SAdrian Hunter int __sdhci_add_host(struct sdhci_host *host); 74615becf68SAdrian Hunter int sdhci_add_host(struct sdhci_host *host); 74715becf68SAdrian Hunter void sdhci_remove_host(struct sdhci_host *host, int dead); 74815becf68SAdrian Hunter void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 749b8c86fc5SPierre Ossman 7506132a3bfSAdrian Hunter static inline void sdhci_read_caps(struct sdhci_host *host) 7516132a3bfSAdrian Hunter { 7526132a3bfSAdrian Hunter __sdhci_read_caps(host, NULL, NULL, NULL); 7536132a3bfSAdrian Hunter } 7546132a3bfSAdrian Hunter 755be138554SRussell King static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 756be138554SRussell King { 757be138554SRussell King return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 758be138554SRussell King } 759be138554SRussell King 760fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 761fb9ee047SLudovic Desroches unsigned int *actual_clock); 7621771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 763fec79673SRitesh Harjani void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 7641dceb041SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 7651dceb041SAdrian Hunter unsigned short vdd); 766606d3131SAdrian Hunter void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 767606d3131SAdrian Hunter unsigned short vdd); 768d462c1b4SAapo Vienamo void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 7692317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width); 77003231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask); 77196d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 77285a882c2SMasahiro Yamada int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 7736a6d4cebSHu Ziji void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 774c376ea9eSHu Ziji int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 775c376ea9eSHu Ziji struct mmc_ios *ios); 7762f05b6abSHu Ziji void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 77754552e49SJisheng Zhang void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 77854552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd); 7792317f56cSRussell King 780b8c86fc5SPierre Ossman #ifdef CONFIG_PM 78115becf68SAdrian Hunter int sdhci_suspend_host(struct sdhci_host *host); 78215becf68SAdrian Hunter int sdhci_resume_host(struct sdhci_host *host); 78315becf68SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host); 784c6303c5dSBaolin Wang int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 78566fd8ad5SAdrian Hunter #endif 78666fd8ad5SAdrian Hunter 787f12e39dbSAdrian Hunter void sdhci_cqe_enable(struct mmc_host *mmc); 788f12e39dbSAdrian Hunter void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 789f12e39dbSAdrian Hunter bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 790f12e39dbSAdrian Hunter int *data_error); 791f12e39dbSAdrian Hunter 792d2898172SAdrian Hunter void sdhci_dumpregs(struct sdhci_host *host); 793b3f80b43SChunyan Zhang void sdhci_enable_v4_mode(struct sdhci_host *host); 794d2898172SAdrian Hunter 7956663c419Sernest.zhang void sdhci_start_tuning(struct sdhci_host *host); 7966663c419Sernest.zhang void sdhci_end_tuning(struct sdhci_host *host); 7976663c419Sernest.zhang void sdhci_reset_tuning(struct sdhci_host *host); 7986663c419Sernest.zhang void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 7996663c419Sernest.zhang 8001978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */ 801