11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 4b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 81c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 91c6a0718SPierre Ossman * your option) any later version. 101c6a0718SPierre Ossman */ 11c0bba0d2SAlbert Herranz #ifndef __SDHCI_H 12c0bba0d2SAlbert Herranz #define __SDHCI_H 131c6a0718SPierre Ossman 140c7ad106SAndrew Morton #include <linux/scatterlist.h> 154e4141a5SAnton Vorontsov #include <linux/compiler.h> 164e4141a5SAnton Vorontsov #include <linux/types.h> 174e4141a5SAnton Vorontsov #include <linux/io.h> 180c7ad106SAndrew Morton 191c6a0718SPierre Ossman /* 201c6a0718SPierre Ossman * Controller registers 211c6a0718SPierre Ossman */ 221c6a0718SPierre Ossman 231c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 241c6a0718SPierre Ossman 251c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 261c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 271c6a0718SPierre Ossman 281c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 291c6a0718SPierre Ossman 301c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 311c6a0718SPierre Ossman 321c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 331c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 341c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 351c6a0718SPierre Ossman #define SDHCI_TRNS_ACMD12 0x04 361c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 371c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 381c6a0718SPierre Ossman 391c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 401c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 411c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 421c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 431c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 461c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 471c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 481c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 531c6a0718SPierre Ossman 541c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 551c6a0718SPierre Ossman 561c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 571c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 581c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 591c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 601c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 611c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 621c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 631c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 641c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 651c6a0718SPierre Ossman 661c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 671c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 681c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 691c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 702134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 712134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 722134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 732134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 742134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 75ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 761c6a0718SPierre Ossman 771c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 781c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 791c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 801c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 811c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 821c6a0718SPierre Ossman 831c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 841c6a0718SPierre Ossman 852df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 861c6a0718SPierre Ossman 871c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 881c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 891c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 901c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 911c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 921c6a0718SPierre Ossman 931c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 941c6a0718SPierre Ossman 951c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 961c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 971c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 981c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 991c6a0718SPierre Ossman 1001c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1011c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1021c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1031c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1041c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 1051c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1061c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1071c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1081c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1091c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1101c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 111964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1121c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1131c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1141c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1151c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1161c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1171c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1181c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1191c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 1201c6a0718SPierre Ossman #define SDHCI_INT_ACMD12ERR 0x01000000 1212134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1221c6a0718SPierre Ossman 1231c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1241c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1251c6a0718SPierre Ossman 1261c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 1271c6a0718SPierre Ossman SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 1281c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1291c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1301c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 131a751a7d6SZhangfei Gao SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 1327260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1331c6a0718SPierre Ossman 1341c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR 0x3C 1351c6a0718SPierre Ossman 1361c6a0718SPierre Ossman /* 3E-3F reserved */ 1371c6a0718SPierre Ossman 1381c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 1391c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 1401c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 1411c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 1421c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 1431c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 1441c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 1451c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 1462134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 1472134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 1481c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 149a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 1501c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 1511c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 1521c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 1532134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 1541c6a0718SPierre Ossman 1551c6a0718SPierre Ossman /* 44-47 reserved for more caps */ 1561c6a0718SPierre Ossman 1571c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 1581c6a0718SPierre Ossman 1591c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 1601c6a0718SPierre Ossman 1612134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 1622134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 1632134a922SPierre Ossman 1642134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 1652134a922SPierre Ossman 1662134a922SPierre Ossman /* 55-57 reserved */ 1672134a922SPierre Ossman 1682134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 1692134a922SPierre Ossman 1702134a922SPierre Ossman /* 60-FB reserved */ 1711c6a0718SPierre Ossman 1721c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 1731c6a0718SPierre Ossman 1741c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 1751c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 1761c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 1771c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 1781c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 1792134a922SPierre Ossman #define SDHCI_SPEC_100 0 1802134a922SPierre Ossman #define SDHCI_SPEC_200 1 1811c6a0718SPierre Ossman 182b8c86fc5SPierre Ossman struct sdhci_ops; 1831c6a0718SPierre Ossman 1841c6a0718SPierre Ossman struct sdhci_host { 185b8c86fc5SPierre Ossman /* Data set by hardware interface driver */ 186b8c86fc5SPierre Ossman const char *hw_name; /* Hardware bus name */ 187b8c86fc5SPierre Ossman 188b8c86fc5SPierre Ossman unsigned int quirks; /* Deviations from spec. */ 189b8c86fc5SPierre Ossman 190b8c86fc5SPierre Ossman /* Controller doesn't honor resets unless we touch the clock register */ 191b8c86fc5SPierre Ossman #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 192b8c86fc5SPierre Ossman /* Controller has bad caps bits, but really supports DMA */ 193b8c86fc5SPierre Ossman #define SDHCI_QUIRK_FORCE_DMA (1<<1) 194b8c86fc5SPierre Ossman /* Controller doesn't like to be reset when there is no card inserted. */ 195b8c86fc5SPierre Ossman #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 196b8c86fc5SPierre Ossman /* Controller doesn't like clearing the power reg before a change */ 197b8c86fc5SPierre Ossman #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 198b8c86fc5SPierre Ossman /* Controller has flaky internal state so reset it on each ios change */ 199b8c86fc5SPierre Ossman #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 200b8c86fc5SPierre Ossman /* Controller has an unusable DMA engine */ 201b8c86fc5SPierre Ossman #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 2022134a922SPierre Ossman /* Controller has an unusable ADMA engine */ 2032134a922SPierre Ossman #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 204b8c86fc5SPierre Ossman /* Controller can only DMA from 32-bit aligned addresses */ 2052134a922SPierre Ossman #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 206b8c86fc5SPierre Ossman /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 2072134a922SPierre Ossman #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 2082134a922SPierre Ossman /* Controller can only ADMA chunks that are a multiple of 32 bits */ 2092134a922SPierre Ossman #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 210b8c86fc5SPierre Ossman /* Controller needs to be reset after each request to stay stable */ 2112134a922SPierre Ossman #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 212b8c86fc5SPierre Ossman /* Controller needs voltage and power writes to happen separately */ 2132134a922SPierre Ossman #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 214ee53ab5dSPierre Ossman /* Controller provides an incorrect timeout value for transfers */ 2152134a922SPierre Ossman #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 2164a3cba32SPierre Ossman /* Controller has an issue with buffer bits for small transfers */ 2174a3cba32SPierre Ossman #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 218f945405cSBen Dooks /* Controller does not provide transfer-complete interrupt when not busy */ 219f945405cSBen Dooks #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 22068d1fb7eSAnton Vorontsov /* Controller has unreliable card detection */ 22168d1fb7eSAnton Vorontsov #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 222c5075a10SAnton Vorontsov /* Controller reports inverted write-protect state */ 223c5075a10SAnton Vorontsov #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 2248114634cSAnton Vorontsov /* Controller has nonstandard clock management */ 2258114634cSAnton Vorontsov #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17) 2263e3bf207SAnton Vorontsov /* Controller does not like fast PIO transfers */ 2273e3bf207SAnton Vorontsov #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 228063a9dbbSAnton Vorontsov /* Controller losing signal/interrupt enable states after reset */ 229063a9dbbSAnton Vorontsov #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) 2300633f654SAnton Vorontsov /* Controller has to be forced to use block size of 2048 bytes */ 2310633f654SAnton Vorontsov #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 2321388eefdSBen Dooks /* Controller cannot do multi-block transfers */ 2331388eefdSBen Dooks #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 2345fe23c7fSAnton Vorontsov /* Controller can only handle 1-bit data transfers */ 2355fe23c7fSAnton Vorontsov #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 236557b0697SHarald Welte /* Controller needs 10ms delay between applying power and clock */ 237557b0697SHarald Welte #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 23881b39802SAnton Vorontsov /* Controller uses SDCLK instead of TMCLK for data timeouts */ 23981b39802SAnton Vorontsov #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 240f27f47efSAnton Vorontsov /* Controller reports wrong base clock capability */ 241f27f47efSAnton Vorontsov #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 24270764a90SThomas Abraham /* Controller cannot support End Attribute in NOP ADMA descriptor */ 24370764a90SThomas Abraham #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 244ccc92c23SMaxim Levitsky /* Controller is missing device caps. Use caps provided by host */ 245ccc92c23SMaxim Levitsky #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 246b8c86fc5SPierre Ossman 247b8c86fc5SPierre Ossman int irq; /* Device IRQ */ 248b8c86fc5SPierre Ossman void __iomem * ioaddr; /* Mapped address */ 249b8c86fc5SPierre Ossman 250b8c86fc5SPierre Ossman const struct sdhci_ops *ops; /* Low level hw interface */ 251b8c86fc5SPierre Ossman 252b8c86fc5SPierre Ossman /* Internal data */ 2531c6a0718SPierre Ossman struct mmc_host *mmc; /* MMC structure */ 2547659150cSPierre Ossman u64 dma_mask; /* custom DMA mask */ 2551c6a0718SPierre Ossman 25635ff8554SÉric Piel #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 2572f730fecSPierre Ossman struct led_classdev led; /* LED control */ 2585dbace0cSHelmut Schaa char led_name[32]; 2592f730fecSPierre Ossman #endif 2602f730fecSPierre Ossman 2611c6a0718SPierre Ossman spinlock_t lock; /* Mutex */ 2621c6a0718SPierre Ossman 2631c6a0718SPierre Ossman int flags; /* Host attributes */ 264a13abc7bSRichard Röjfors #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 2652134a922SPierre Ossman #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 2662134a922SPierre Ossman #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 2672134a922SPierre Ossman #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 2682134a922SPierre Ossman 2692134a922SPierre Ossman unsigned int version; /* SDHCI spec. version */ 2701c6a0718SPierre Ossman 2711c6a0718SPierre Ossman unsigned int max_clk; /* Max possible freq (MHz) */ 2721c6a0718SPierre Ossman unsigned int timeout_clk; /* Timeout freq (KHz) */ 2731c6a0718SPierre Ossman 2741c6a0718SPierre Ossman unsigned int clock; /* Current clock (MHz) */ 275ae628903SPierre Ossman u8 pwr; /* Current voltage */ 2761c6a0718SPierre Ossman 2771c6a0718SPierre Ossman struct mmc_request *mrq; /* Current request */ 2781c6a0718SPierre Ossman struct mmc_command *cmd; /* Current command */ 2791c6a0718SPierre Ossman struct mmc_data *data; /* Current data request */ 28055654be9SHarvey Harrison unsigned int data_early:1; /* Data finished before cmd */ 2811c6a0718SPierre Ossman 2827659150cSPierre Ossman struct sg_mapping_iter sg_miter; /* SG state for PIO */ 2837659150cSPierre Ossman unsigned int blocks; /* remaining PIO blocks */ 2841c6a0718SPierre Ossman 2852134a922SPierre Ossman int sg_count; /* Mapped sg entries */ 2862134a922SPierre Ossman 2872134a922SPierre Ossman u8 *adma_desc; /* ADMA descriptor table */ 2882134a922SPierre Ossman u8 *align_buffer; /* Bounce buffer */ 2892134a922SPierre Ossman 2902134a922SPierre Ossman dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 2912134a922SPierre Ossman dma_addr_t align_addr; /* Mapped bounce buffer */ 2922134a922SPierre Ossman 2931c6a0718SPierre Ossman struct tasklet_struct card_tasklet; /* Tasklet structures */ 2941c6a0718SPierre Ossman struct tasklet_struct finish_tasklet; 2951c6a0718SPierre Ossman 2961c6a0718SPierre Ossman struct timer_list timer; /* Timer for timeouts */ 297b8c86fc5SPierre Ossman 298ccc92c23SMaxim Levitsky unsigned int caps; /* Alternative capabilities */ 299ccc92c23SMaxim Levitsky 300b8c86fc5SPierre Ossman unsigned long private[0] ____cacheline_aligned; 3011c6a0718SPierre Ossman }; 3021c6a0718SPierre Ossman 3031c6a0718SPierre Ossman 304b8c86fc5SPierre Ossman struct sdhci_ops { 3054e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 306dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 307dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 308dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 309dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 310dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 311dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 3124e4141a5SAnton Vorontsov #endif 3134e4141a5SAnton Vorontsov 3148114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 3158114634cSAnton Vorontsov 316b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 3174240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 318a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 3194240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 3201c6a0718SPierre Ossman }; 321b8c86fc5SPierre Ossman 3224e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 3234e4141a5SAnton Vorontsov 3244e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 3254e4141a5SAnton Vorontsov { 326dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 327dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 3284e4141a5SAnton Vorontsov else 3294e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 3304e4141a5SAnton Vorontsov } 3314e4141a5SAnton Vorontsov 3324e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 3334e4141a5SAnton Vorontsov { 334dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 335dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 3364e4141a5SAnton Vorontsov else 3374e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 3384e4141a5SAnton Vorontsov } 3394e4141a5SAnton Vorontsov 3404e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 3414e4141a5SAnton Vorontsov { 342dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 343dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 3444e4141a5SAnton Vorontsov else 3454e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3464e4141a5SAnton Vorontsov } 3474e4141a5SAnton Vorontsov 3484e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3494e4141a5SAnton Vorontsov { 350dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 351dc297c92SMatt Fleming return host->ops->read_l(host, reg); 3524e4141a5SAnton Vorontsov else 3534e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3544e4141a5SAnton Vorontsov } 3554e4141a5SAnton Vorontsov 3564e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3574e4141a5SAnton Vorontsov { 358dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 359dc297c92SMatt Fleming return host->ops->read_w(host, reg); 3604e4141a5SAnton Vorontsov else 3614e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3624e4141a5SAnton Vorontsov } 3634e4141a5SAnton Vorontsov 3644e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3654e4141a5SAnton Vorontsov { 366dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 367dc297c92SMatt Fleming return host->ops->read_b(host, reg); 3684e4141a5SAnton Vorontsov else 3694e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3704e4141a5SAnton Vorontsov } 3714e4141a5SAnton Vorontsov 3724e4141a5SAnton Vorontsov #else 3734e4141a5SAnton Vorontsov 3744e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 3754e4141a5SAnton Vorontsov { 3764e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 3774e4141a5SAnton Vorontsov } 3784e4141a5SAnton Vorontsov 3794e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 3804e4141a5SAnton Vorontsov { 3814e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 3824e4141a5SAnton Vorontsov } 3834e4141a5SAnton Vorontsov 3844e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 3854e4141a5SAnton Vorontsov { 3864e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3874e4141a5SAnton Vorontsov } 3884e4141a5SAnton Vorontsov 3894e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3904e4141a5SAnton Vorontsov { 3914e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3924e4141a5SAnton Vorontsov } 3934e4141a5SAnton Vorontsov 3944e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3954e4141a5SAnton Vorontsov { 3964e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3974e4141a5SAnton Vorontsov } 3984e4141a5SAnton Vorontsov 3994e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 4004e4141a5SAnton Vorontsov { 4014e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 4024e4141a5SAnton Vorontsov } 4034e4141a5SAnton Vorontsov 4044e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 405b8c86fc5SPierre Ossman 406b8c86fc5SPierre Ossman extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 407b8c86fc5SPierre Ossman size_t priv_size); 408b8c86fc5SPierre Ossman extern void sdhci_free_host(struct sdhci_host *host); 409b8c86fc5SPierre Ossman 410b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 411b8c86fc5SPierre Ossman { 412b8c86fc5SPierre Ossman return (void *)host->private; 413b8c86fc5SPierre Ossman } 414b8c86fc5SPierre Ossman 415b8c86fc5SPierre Ossman extern int sdhci_add_host(struct sdhci_host *host); 4161e72859eSPierre Ossman extern void sdhci_remove_host(struct sdhci_host *host, int dead); 417b8c86fc5SPierre Ossman 418b8c86fc5SPierre Ossman #ifdef CONFIG_PM 419b8c86fc5SPierre Ossman extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state); 420b8c86fc5SPierre Ossman extern int sdhci_resume_host(struct sdhci_host *host); 421b8c86fc5SPierre Ossman #endif 422c0bba0d2SAlbert Herranz 423c0bba0d2SAlbert Herranz #endif /* __SDHCI_H */ 424