11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 41978fda8SGiuseppe Cavallaro * Header file for Host Controller registers and I/O accessors. 51978fda8SGiuseppe Cavallaro * 6b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 71c6a0718SPierre Ossman * 81c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 91c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 101c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 111c6a0718SPierre Ossman * your option) any later version. 121c6a0718SPierre Ossman */ 131978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H 141978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H 151c6a0718SPierre Ossman 160c7ad106SAndrew Morton #include <linux/scatterlist.h> 174e4141a5SAnton Vorontsov #include <linux/compiler.h> 184e4141a5SAnton Vorontsov #include <linux/types.h> 194e4141a5SAnton Vorontsov #include <linux/io.h> 20210583f4SUlf Hansson #include <linux/leds.h> 21b8789ec4SUlf Hansson #include <linux/interrupt.h> 220c7ad106SAndrew Morton 2383f13cc9SUlf Hansson #include <linux/mmc/host.h> 241978fda8SGiuseppe Cavallaro 251c6a0718SPierre Ossman /* 261c6a0718SPierre Ossman * Controller registers 271c6a0718SPierre Ossman */ 281c6a0718SPierre Ossman 291c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 308edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 311c6a0718SPierre Ossman 321c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 331c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 381c6a0718SPierre Ossman 391c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 401c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 411c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 42e89d456fSAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD12 0x04 438edf6371SAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD23 0x08 441c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 451c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 461c6a0718SPierre Ossman 471c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 481c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 491c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 501c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 511c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 52574e3f56SRichard Zhu #define SDHCI_CMD_ABORTCMD 0xC0 531c6a0718SPierre Ossman 541c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 551c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 561c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 571c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 581c6a0718SPierre Ossman 591c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 6022113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 611c6a0718SPierre Ossman 621c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 631c6a0718SPierre Ossman 641c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 651c6a0718SPierre Ossman 661c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 671c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 681c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 691c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 701c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 711c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 721c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 731c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 741c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 75f2119df6SArindam Nath #define SDHCI_DATA_LVL_MASK 0x00F00000 76f2119df6SArindam Nath #define SDHCI_DATA_LVL_SHIFT 20 777756a96dSYi Sun #define SDHCI_DATA_0_LVL_MASK 0x00100000 78b0921d5cSMichael Walle #define SDHCI_CMD_LVL 0x01000000 791c6a0718SPierre Ossman 801c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 811c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 821c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 831c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 842134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 852134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 862134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 872134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 882134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 89ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 903794c542SZach Brown #define SDHCI_CTRL_CDTEST_INS 0x40 913794c542SZach Brown #define SDHCI_CTRL_CDTEST_EN 0x80 921c6a0718SPierre Ossman 931c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 941c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 951c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 961c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 971c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 981c6a0718SPierre Ossman 991c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 1001c6a0718SPierre Ossman 1012df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 1025f619704SDaniel Drake #define SDHCI_WAKE_ON_INT 0x01 1035f619704SDaniel Drake #define SDHCI_WAKE_ON_INSERT 0x02 1045f619704SDaniel Drake #define SDHCI_WAKE_ON_REMOVE 0x04 1051c6a0718SPierre Ossman 1061c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 1071c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 10885105c53SZhangfei Gao #define SDHCI_DIVIDER_HI_SHIFT 6 10985105c53SZhangfei Gao #define SDHCI_DIV_MASK 0xFF 11085105c53SZhangfei Gao #define SDHCI_DIV_MASK_LEN 8 11185105c53SZhangfei Gao #define SDHCI_DIV_HI_MASK 0x300 112c3ed3877SArindam Nath #define SDHCI_PROG_CLOCK_MODE 0x0020 1131c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 1141c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 1151c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 1161c6a0718SPierre Ossman 1171c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 1181c6a0718SPierre Ossman 1191c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 1201c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 1211c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 1221c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 1231c6a0718SPierre Ossman 1241c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1251c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1261c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1271c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1281c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 129a4071fbbSHaijun Zhang #define SDHCI_INT_BLK_GAP 0x00000004 1301c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1311c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1321c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1331c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1341c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1351c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 136f37b20ebSDong Aisheng #define SDHCI_INT_RETUNE 0x00001000 137f12e39dbSAdrian Hunter #define SDHCI_INT_CQE 0x00004000 138964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1391c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1401c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1411c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1421c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1431c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1441c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1451c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1461c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 1471c6a0718SPierre Ossman #define SDHCI_INT_ACMD12ERR 0x01000000 1482134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1491c6a0718SPierre Ossman 1501c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1511c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1521c6a0718SPierre Ossman 1531c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 1541c6a0718SPierre Ossman SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 1551c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1561c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1571c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 158a4071fbbSHaijun Zhang SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 159a4071fbbSHaijun Zhang SDHCI_INT_BLK_GAP) 1607260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1611c6a0718SPierre Ossman 162f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_ERR_MASK ( \ 163f12e39dbSAdrian Hunter SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 164f12e39dbSAdrian Hunter SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 165f12e39dbSAdrian Hunter SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 166f12e39dbSAdrian Hunter 167f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 168f12e39dbSAdrian Hunter 1691c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR 0x3C 1701c6a0718SPierre Ossman 171f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2 0x3E 17249c468fcSArindam Nath #define SDHCI_CTRL_UHS_MASK 0x0007 17349c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR12 0x0000 17449c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR25 0x0001 17549c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR50 0x0002 17649c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR104 0x0003 17749c468fcSArindam Nath #define SDHCI_CTRL_UHS_DDR50 0x0004 178e9fb05d5SAdrian Hunter #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 179f2119df6SArindam Nath #define SDHCI_CTRL_VDD_180 0x0008 180d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 181d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_B 0x0000 182d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_A 0x0010 183d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_C 0x0020 184d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_D 0x0030 185b513ea25SArindam Nath #define SDHCI_CTRL_EXEC_TUNING 0x0040 186b513ea25SArindam Nath #define SDHCI_CTRL_TUNED_CLK 0x0080 187d6d50a15SArindam Nath #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 1881c6a0718SPierre Ossman 1891c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 1901c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 1911c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 1921c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 1931c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 194c4687d5fSZhangfei Gao #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 1951c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 1961c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 1971c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 19815ec4461SPhilip Rakity #define SDHCI_CAN_DO_8BIT 0x00040000 1992134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 2002134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 2011c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 202a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 203e71d4b81SStefan Wahren #define SDHCI_CAN_DO_SUSPEND 0x00800000 2041c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 2051c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 2061c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 2072134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 2081c6a0718SPierre Ossman 209f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR50 0x00000001 210f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR104 0x00000002 211f2119df6SArindam Nath #define SDHCI_SUPPORT_DDR50 0x00000004 212d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_A 0x00000010 213d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_C 0x00000020 214d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_D 0x00000040 215cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 216cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 217b513ea25SArindam Nath #define SDHCI_USE_SDR50_TUNING 0x00002000 218cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_MASK 0x0000C000 219cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_SHIFT 14 220c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 221c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_SHIFT 16 222e9fb05d5SAdrian Hunter #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 223f2119df6SArindam Nath 224e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1 0x44 2251c6a0718SPierre Ossman 2261c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 227bad37e1aSPhilip Rakity #define SDHCI_MAX_CURRENT_LIMIT 0xFF 228f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 229f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_SHIFT 0 230f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 231f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_SHIFT 8 232f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 233f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_SHIFT 16 234f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_MULTIPLIER 4 2351c6a0718SPierre Ossman 2361c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 2371c6a0718SPierre Ossman 2382134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 2392134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 2402134a922SPierre Ossman 2412134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 2422134a922SPierre Ossman 2432134a922SPierre Ossman /* 55-57 reserved */ 2442134a922SPierre Ossman 2452134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 246e57a5f61SAdrian Hunter #define SDHCI_ADMA_ADDRESS_HI 0x5C 2472134a922SPierre Ossman 2482134a922SPierre Ossman /* 60-FB reserved */ 2491c6a0718SPierre Ossman 25052983382SKevin Liu #define SDHCI_PRESET_FOR_SDR12 0x66 25152983382SKevin Liu #define SDHCI_PRESET_FOR_SDR25 0x68 25252983382SKevin Liu #define SDHCI_PRESET_FOR_SDR50 0x6A 25352983382SKevin Liu #define SDHCI_PRESET_FOR_SDR104 0x6C 25452983382SKevin Liu #define SDHCI_PRESET_FOR_DDR50 0x6E 255e9fb05d5SAdrian Hunter #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 25652983382SKevin Liu #define SDHCI_PRESET_DRV_MASK 0xC000 25752983382SKevin Liu #define SDHCI_PRESET_DRV_SHIFT 14 25852983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 25952983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 26052983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 26152983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 26252983382SKevin Liu 2631c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 2641c6a0718SPierre Ossman 2651c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 2661c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 2671c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 2681c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 2691c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 2702134a922SPierre Ossman #define SDHCI_SPEC_100 0 2712134a922SPierre Ossman #define SDHCI_SPEC_200 1 27285105c53SZhangfei Gao #define SDHCI_SPEC_300 2 2731c6a0718SPierre Ossman 2740397526dSZhangfei Gao /* 2750397526dSZhangfei Gao * End of controller registers. 2760397526dSZhangfei Gao */ 2770397526dSZhangfei Gao 2780397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200 256 2790397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300 2046 2800397526dSZhangfei Gao 281f6a03cbfSMikko Vinni /* 282f6a03cbfSMikko Vinni * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 283f6a03cbfSMikko Vinni */ 284f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 285f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 286f6a03cbfSMikko Vinni 287739d46dcSAdrian Hunter /* ADMA2 32-bit DMA descriptor size */ 288739d46dcSAdrian Hunter #define SDHCI_ADMA2_32_DESC_SZ 8 289739d46dcSAdrian Hunter 2900545230fSAdrian Hunter /* ADMA2 32-bit descriptor */ 2910545230fSAdrian Hunter struct sdhci_adma2_32_desc { 2920545230fSAdrian Hunter __le16 cmd; 2930545230fSAdrian Hunter __le16 len; 2940545230fSAdrian Hunter __le32 addr; 29504a5ae6fSAdrian Hunter } __packed __aligned(4); 29604a5ae6fSAdrian Hunter 29704a5ae6fSAdrian Hunter /* ADMA2 data alignment */ 29804a5ae6fSAdrian Hunter #define SDHCI_ADMA2_ALIGN 4 29904a5ae6fSAdrian Hunter #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 30004a5ae6fSAdrian Hunter 30104a5ae6fSAdrian Hunter /* 30204a5ae6fSAdrian Hunter * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 30304a5ae6fSAdrian Hunter * alignment for the descriptor table even in 32-bit DMA mode. Memory 30404a5ae6fSAdrian Hunter * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 30504a5ae6fSAdrian Hunter */ 30604a5ae6fSAdrian Hunter #define SDHCI_ADMA2_DESC_ALIGN 8 3070545230fSAdrian Hunter 308e57a5f61SAdrian Hunter /* ADMA2 64-bit DMA descriptor size */ 309e57a5f61SAdrian Hunter #define SDHCI_ADMA2_64_DESC_SZ 12 310e57a5f61SAdrian Hunter 311e57a5f61SAdrian Hunter /* 312e57a5f61SAdrian Hunter * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 313e57a5f61SAdrian Hunter * aligned. 314e57a5f61SAdrian Hunter */ 315e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc { 316e57a5f61SAdrian Hunter __le16 cmd; 317e57a5f61SAdrian Hunter __le16 len; 318e57a5f61SAdrian Hunter __le32 addr_lo; 319e57a5f61SAdrian Hunter __le32 addr_hi; 320e57a5f61SAdrian Hunter } __packed __aligned(4); 321e57a5f61SAdrian Hunter 322739d46dcSAdrian Hunter #define ADMA2_TRAN_VALID 0x21 323739d46dcSAdrian Hunter #define ADMA2_NOP_END_VALID 0x3 324739d46dcSAdrian Hunter #define ADMA2_END 0x2 325739d46dcSAdrian Hunter 3264fb213f8SAdrian Hunter /* 3274fb213f8SAdrian Hunter * Maximum segments assuming a 512KiB maximum requisition size and a minimum 3284fb213f8SAdrian Hunter * 4KiB page size. 3294fb213f8SAdrian Hunter */ 3304fb213f8SAdrian Hunter #define SDHCI_MAX_SEGS 128 3314fb213f8SAdrian Hunter 3324e9f8fe5SAdrian Hunter /* Allow for a a command request and a data request at the same time */ 3334e9f8fe5SAdrian Hunter #define SDHCI_MAX_MRQS 2 3344e9f8fe5SAdrian Hunter 335d31911b9SHaibo Chen enum sdhci_cookie { 336d31911b9SHaibo Chen COOKIE_UNMAPPED, 33794538e51SRussell King COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 33894538e51SRussell King COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 33983f13cc9SUlf Hansson }; 34083f13cc9SUlf Hansson 34183f13cc9SUlf Hansson struct sdhci_host { 34283f13cc9SUlf Hansson /* Data set by hardware interface driver */ 34383f13cc9SUlf Hansson const char *hw_name; /* Hardware bus name */ 34483f13cc9SUlf Hansson 34583f13cc9SUlf Hansson unsigned int quirks; /* Deviations from spec. */ 34683f13cc9SUlf Hansson 34783f13cc9SUlf Hansson /* Controller doesn't honor resets unless we touch the clock register */ 34883f13cc9SUlf Hansson #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 34983f13cc9SUlf Hansson /* Controller has bad caps bits, but really supports DMA */ 35083f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_DMA (1<<1) 35183f13cc9SUlf Hansson /* Controller doesn't like to be reset when there is no card inserted. */ 35283f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 35383f13cc9SUlf Hansson /* Controller doesn't like clearing the power reg before a change */ 35483f13cc9SUlf Hansson #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 35583f13cc9SUlf Hansson /* Controller has flaky internal state so reset it on each ios change */ 35683f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 35783f13cc9SUlf Hansson /* Controller has an unusable DMA engine */ 35883f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 35983f13cc9SUlf Hansson /* Controller has an unusable ADMA engine */ 36083f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 36183f13cc9SUlf Hansson /* Controller can only DMA from 32-bit aligned addresses */ 36283f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 36383f13cc9SUlf Hansson /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 36483f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 36583f13cc9SUlf Hansson /* Controller can only ADMA chunks that are a multiple of 32 bits */ 36683f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 36783f13cc9SUlf Hansson /* Controller needs to be reset after each request to stay stable */ 36883f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 36983f13cc9SUlf Hansson /* Controller needs voltage and power writes to happen separately */ 37083f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 37183f13cc9SUlf Hansson /* Controller provides an incorrect timeout value for transfers */ 37283f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 37383f13cc9SUlf Hansson /* Controller has an issue with buffer bits for small transfers */ 37483f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 37583f13cc9SUlf Hansson /* Controller does not provide transfer-complete interrupt when not busy */ 37683f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 37783f13cc9SUlf Hansson /* Controller has unreliable card detection */ 37883f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 37983f13cc9SUlf Hansson /* Controller reports inverted write-protect state */ 38083f13cc9SUlf Hansson #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 38183f13cc9SUlf Hansson /* Controller does not like fast PIO transfers */ 38283f13cc9SUlf Hansson #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 38383f13cc9SUlf Hansson /* Controller has to be forced to use block size of 2048 bytes */ 38483f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 38583f13cc9SUlf Hansson /* Controller cannot do multi-block transfers */ 38683f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 38783f13cc9SUlf Hansson /* Controller can only handle 1-bit data transfers */ 38883f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 38983f13cc9SUlf Hansson /* Controller needs 10ms delay between applying power and clock */ 39083f13cc9SUlf Hansson #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 39183f13cc9SUlf Hansson /* Controller uses SDCLK instead of TMCLK for data timeouts */ 39283f13cc9SUlf Hansson #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 39383f13cc9SUlf Hansson /* Controller reports wrong base clock capability */ 39483f13cc9SUlf Hansson #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 39583f13cc9SUlf Hansson /* Controller cannot support End Attribute in NOP ADMA descriptor */ 39683f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 39783f13cc9SUlf Hansson /* Controller is missing device caps. Use caps provided by host */ 39883f13cc9SUlf Hansson #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 39983f13cc9SUlf Hansson /* Controller uses Auto CMD12 command to stop the transfer */ 40083f13cc9SUlf Hansson #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 40183f13cc9SUlf Hansson /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 40283f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 40383f13cc9SUlf Hansson /* Controller treats ADMA descriptors with length 0000h incorrectly */ 40483f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 40583f13cc9SUlf Hansson /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 40683f13cc9SUlf Hansson #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 40783f13cc9SUlf Hansson 40883f13cc9SUlf Hansson unsigned int quirks2; /* More deviations from spec. */ 40983f13cc9SUlf Hansson 41083f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 41183f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 41283f13cc9SUlf Hansson /* The system physically doesn't support 1.8v, even if the host does */ 41383f13cc9SUlf Hansson #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 41483f13cc9SUlf Hansson #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 41583f13cc9SUlf Hansson #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 41683f13cc9SUlf Hansson /* Controller has a non-standard host control register */ 41783f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 41883f13cc9SUlf Hansson /* Controller does not support HS200 */ 41983f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 42083f13cc9SUlf Hansson /* Controller does not support DDR50 */ 42183f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 42283f13cc9SUlf Hansson /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 42383f13cc9SUlf Hansson #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 42483f13cc9SUlf Hansson /* Controller does not support 64-bit DMA */ 42583f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 42683f13cc9SUlf Hansson /* need clear transfer mode register before send cmd */ 42783f13cc9SUlf Hansson #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 42883f13cc9SUlf Hansson /* Capability register bit-63 indicates HS400 support */ 42983f13cc9SUlf Hansson #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 43083f13cc9SUlf Hansson /* forced tuned clock */ 43183f13cc9SUlf Hansson #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 43283f13cc9SUlf Hansson /* disable the block count for single block transactions */ 43383f13cc9SUlf Hansson #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 43483f13cc9SUlf Hansson /* Controller broken with using ACMD23 */ 43583f13cc9SUlf Hansson #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 436d1955c3aSSuneel Garapati /* Broken Clock divider zero in controller */ 437d1955c3aSSuneel Garapati #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 43883f13cc9SUlf Hansson 43983f13cc9SUlf Hansson int irq; /* Device IRQ */ 44083f13cc9SUlf Hansson void __iomem *ioaddr; /* Mapped address */ 44183f13cc9SUlf Hansson 44283f13cc9SUlf Hansson const struct sdhci_ops *ops; /* Low level hw interface */ 44383f13cc9SUlf Hansson 44483f13cc9SUlf Hansson /* Internal data */ 44583f13cc9SUlf Hansson struct mmc_host *mmc; /* MMC structure */ 446bf60e592SAdrian Hunter struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 44783f13cc9SUlf Hansson u64 dma_mask; /* custom DMA mask */ 44883f13cc9SUlf Hansson 44974479c5dSMasahiro Yamada #if IS_ENABLED(CONFIG_LEDS_CLASS) 45083f13cc9SUlf Hansson struct led_classdev led; /* LED control */ 45183f13cc9SUlf Hansson char led_name[32]; 45283f13cc9SUlf Hansson #endif 45383f13cc9SUlf Hansson 45483f13cc9SUlf Hansson spinlock_t lock; /* Mutex */ 45583f13cc9SUlf Hansson 45683f13cc9SUlf Hansson int flags; /* Host attributes */ 45783f13cc9SUlf Hansson #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 45883f13cc9SUlf Hansson #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 45983f13cc9SUlf Hansson #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 46083f13cc9SUlf Hansson #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 46183f13cc9SUlf Hansson #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 46283f13cc9SUlf Hansson #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 46383f13cc9SUlf Hansson #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 46483f13cc9SUlf Hansson #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 46583f13cc9SUlf Hansson #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 46683f13cc9SUlf Hansson #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 46783f13cc9SUlf Hansson #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 4688cb851a4SAdrian Hunter #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 4698cb851a4SAdrian Hunter #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 4708cb851a4SAdrian Hunter #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 47183f13cc9SUlf Hansson 47283f13cc9SUlf Hansson unsigned int version; /* SDHCI spec. version */ 47383f13cc9SUlf Hansson 47483f13cc9SUlf Hansson unsigned int max_clk; /* Max possible freq (MHz) */ 47583f13cc9SUlf Hansson unsigned int timeout_clk; /* Timeout freq (KHz) */ 47683f13cc9SUlf Hansson unsigned int clk_mul; /* Clock Muliplier value */ 47783f13cc9SUlf Hansson 47883f13cc9SUlf Hansson unsigned int clock; /* Current clock (MHz) */ 47983f13cc9SUlf Hansson u8 pwr; /* Current voltage */ 48083f13cc9SUlf Hansson 48183f13cc9SUlf Hansson bool runtime_suspended; /* Host is runtime suspended */ 48283f13cc9SUlf Hansson bool bus_on; /* Bus power prevents runtime suspend */ 48383f13cc9SUlf Hansson bool preset_enabled; /* Preset is enabled */ 484ed1563deSAdrian Hunter bool pending_reset; /* Cmd/data reset is pending */ 48583f13cc9SUlf Hansson 4864e9f8fe5SAdrian Hunter struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 48783f13cc9SUlf Hansson struct mmc_command *cmd; /* Current command */ 4887c89a3d9SAdrian Hunter struct mmc_command *data_cmd; /* Current data command */ 48983f13cc9SUlf Hansson struct mmc_data *data; /* Current data request */ 49083f13cc9SUlf Hansson unsigned int data_early:1; /* Data finished before cmd */ 49183f13cc9SUlf Hansson 49283f13cc9SUlf Hansson struct sg_mapping_iter sg_miter; /* SG state for PIO */ 49383f13cc9SUlf Hansson unsigned int blocks; /* remaining PIO blocks */ 49483f13cc9SUlf Hansson 49583f13cc9SUlf Hansson int sg_count; /* Mapped sg entries */ 49683f13cc9SUlf Hansson 49783f13cc9SUlf Hansson void *adma_table; /* ADMA descriptor table */ 49883f13cc9SUlf Hansson void *align_buffer; /* Bounce buffer */ 49983f13cc9SUlf Hansson 50083f13cc9SUlf Hansson size_t adma_table_sz; /* ADMA descriptor table size */ 50183f13cc9SUlf Hansson size_t align_buffer_sz; /* Bounce buffer size */ 50283f13cc9SUlf Hansson 50383f13cc9SUlf Hansson dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 50483f13cc9SUlf Hansson dma_addr_t align_addr; /* Mapped bounce buffer */ 50583f13cc9SUlf Hansson 50683f13cc9SUlf Hansson unsigned int desc_sz; /* ADMA descriptor size */ 50783f13cc9SUlf Hansson 50883f13cc9SUlf Hansson struct tasklet_struct finish_tasklet; /* Tasklet structures */ 50983f13cc9SUlf Hansson 51083f13cc9SUlf Hansson struct timer_list timer; /* Timer for timeouts */ 511d7422fb4SAdrian Hunter struct timer_list data_timer; /* Timer for data timeouts */ 51283f13cc9SUlf Hansson 51328da3589SAdrian Hunter u32 caps; /* CAPABILITY_0 */ 51428da3589SAdrian Hunter u32 caps1; /* CAPABILITY_1 */ 5156132a3bfSAdrian Hunter bool read_caps; /* Capability flags have been read */ 51683f13cc9SUlf Hansson 51783f13cc9SUlf Hansson unsigned int ocr_avail_sdio; /* OCR bit masks */ 51883f13cc9SUlf Hansson unsigned int ocr_avail_sd; 51983f13cc9SUlf Hansson unsigned int ocr_avail_mmc; 52083f13cc9SUlf Hansson u32 ocr_mask; /* available voltages */ 52183f13cc9SUlf Hansson 52283f13cc9SUlf Hansson unsigned timing; /* Current timing */ 52383f13cc9SUlf Hansson 52483f13cc9SUlf Hansson u32 thread_isr; 52583f13cc9SUlf Hansson 52683f13cc9SUlf Hansson /* cached registers */ 52783f13cc9SUlf Hansson u32 ier; 52883f13cc9SUlf Hansson 529f12e39dbSAdrian Hunter bool cqe_on; /* CQE is operating */ 530f12e39dbSAdrian Hunter u32 cqe_ier; /* CQE interrupt mask */ 531f12e39dbSAdrian Hunter u32 cqe_err_ier; /* CQE error interrupt mask */ 532f12e39dbSAdrian Hunter 53383f13cc9SUlf Hansson wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 53483f13cc9SUlf Hansson unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 53583f13cc9SUlf Hansson 53683f13cc9SUlf Hansson unsigned int tuning_count; /* Timer count for re-tuning */ 53783f13cc9SUlf Hansson unsigned int tuning_mode; /* Re-tuning mode supported by host */ 53883f13cc9SUlf Hansson #define SDHCI_TUNING_MODE_1 0 539f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_2 1 540f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_3 2 54183f13cc9SUlf Hansson 54283f13cc9SUlf Hansson unsigned long private[0] ____cacheline_aligned; 54383f13cc9SUlf Hansson }; 54483f13cc9SUlf Hansson 545b8c86fc5SPierre Ossman struct sdhci_ops { 5464e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 547dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 548dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 549dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 550dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 551dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 552dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 5534e4141a5SAnton Vorontsov #endif 5544e4141a5SAnton Vorontsov 5558114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 5561dceb041SAdrian Hunter void (*set_power)(struct sdhci_host *host, unsigned char mode, 5571dceb041SAdrian Hunter unsigned short vdd); 5588114634cSAnton Vorontsov 559f12e39dbSAdrian Hunter u32 (*irq)(struct sdhci_host *host, u32 intmask); 560f12e39dbSAdrian Hunter 561b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 5624240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 563a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 5648cc35289SShawn Lin /* get_timeout_clock should return clk rate in unit of Hz */ 5654240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 566a6ff5aebSAisheng Dong unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 567b45e668aSAisheng Dong void (*set_timeout)(struct sdhci_host *host, 568b45e668aSAisheng Dong struct mmc_command *cmd); 5692317f56cSRussell King void (*set_bus_width)(struct sdhci_host *host, int width); 570643a81ffSPhilip Rakity void (*platform_send_init_74_clocks)(struct sdhci_host *host, 571643a81ffSPhilip Rakity u8 power_mode); 5722dfb579cSWolfram Sang unsigned int (*get_ro)(struct sdhci_host *host); 57303231f9bSRussell King void (*reset)(struct sdhci_host *host, u8 mask); 57445251812SDong Aisheng int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 57513e64501SRussell King void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 57620758b66SAdrian Hunter void (*hw_reset)(struct sdhci_host *host); 577a4071fbbSHaijun Zhang void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 578722e1280SChristian Daudt void (*card_event)(struct sdhci_host *host); 5799d967a61SVincent Yang void (*voltage_switch)(struct sdhci_host *host); 5801c6a0718SPierre Ossman }; 581b8c86fc5SPierre Ossman 5824e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 5834e4141a5SAnton Vorontsov 5844e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 5854e4141a5SAnton Vorontsov { 586dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 587dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 5884e4141a5SAnton Vorontsov else 5894e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 5904e4141a5SAnton Vorontsov } 5914e4141a5SAnton Vorontsov 5924e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 5934e4141a5SAnton Vorontsov { 594dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 595dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 5964e4141a5SAnton Vorontsov else 5974e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 5984e4141a5SAnton Vorontsov } 5994e4141a5SAnton Vorontsov 6004e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 6014e4141a5SAnton Vorontsov { 602dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 603dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 6044e4141a5SAnton Vorontsov else 6054e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 6064e4141a5SAnton Vorontsov } 6074e4141a5SAnton Vorontsov 6084e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 6094e4141a5SAnton Vorontsov { 610dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 611dc297c92SMatt Fleming return host->ops->read_l(host, reg); 6124e4141a5SAnton Vorontsov else 6134e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 6144e4141a5SAnton Vorontsov } 6154e4141a5SAnton Vorontsov 6164e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 6174e4141a5SAnton Vorontsov { 618dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 619dc297c92SMatt Fleming return host->ops->read_w(host, reg); 6204e4141a5SAnton Vorontsov else 6214e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 6224e4141a5SAnton Vorontsov } 6234e4141a5SAnton Vorontsov 6244e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 6254e4141a5SAnton Vorontsov { 626dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 627dc297c92SMatt Fleming return host->ops->read_b(host, reg); 6284e4141a5SAnton Vorontsov else 6294e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 6304e4141a5SAnton Vorontsov } 6314e4141a5SAnton Vorontsov 6324e4141a5SAnton Vorontsov #else 6334e4141a5SAnton Vorontsov 6344e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 6354e4141a5SAnton Vorontsov { 6364e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 6374e4141a5SAnton Vorontsov } 6384e4141a5SAnton Vorontsov 6394e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 6404e4141a5SAnton Vorontsov { 6414e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 6424e4141a5SAnton Vorontsov } 6434e4141a5SAnton Vorontsov 6444e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 6454e4141a5SAnton Vorontsov { 6464e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 6474e4141a5SAnton Vorontsov } 6484e4141a5SAnton Vorontsov 6494e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 6504e4141a5SAnton Vorontsov { 6514e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 6524e4141a5SAnton Vorontsov } 6534e4141a5SAnton Vorontsov 6544e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 6554e4141a5SAnton Vorontsov { 6564e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 6574e4141a5SAnton Vorontsov } 6584e4141a5SAnton Vorontsov 6594e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 6604e4141a5SAnton Vorontsov { 6614e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 6624e4141a5SAnton Vorontsov } 6634e4141a5SAnton Vorontsov 6644e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 665b8c86fc5SPierre Ossman 66615becf68SAdrian Hunter struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 66715becf68SAdrian Hunter void sdhci_free_host(struct sdhci_host *host); 668b8c86fc5SPierre Ossman 669b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 670b8c86fc5SPierre Ossman { 671178b0fa0SMasahiro Yamada return host->private; 672b8c86fc5SPierre Ossman } 673b8c86fc5SPierre Ossman 67415becf68SAdrian Hunter void sdhci_card_detect(struct sdhci_host *host); 67515becf68SAdrian Hunter void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 6766132a3bfSAdrian Hunter u32 *caps1); 67715becf68SAdrian Hunter int sdhci_setup_host(struct sdhci_host *host); 6784180ffa8SAdrian Hunter void sdhci_cleanup_host(struct sdhci_host *host); 67915becf68SAdrian Hunter int __sdhci_add_host(struct sdhci_host *host); 68015becf68SAdrian Hunter int sdhci_add_host(struct sdhci_host *host); 68115becf68SAdrian Hunter void sdhci_remove_host(struct sdhci_host *host, int dead); 68215becf68SAdrian Hunter void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 683b8c86fc5SPierre Ossman 6846132a3bfSAdrian Hunter static inline void sdhci_read_caps(struct sdhci_host *host) 6856132a3bfSAdrian Hunter { 6866132a3bfSAdrian Hunter __sdhci_read_caps(host, NULL, NULL, NULL); 6876132a3bfSAdrian Hunter } 6886132a3bfSAdrian Hunter 689be138554SRussell King static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 690be138554SRussell King { 691be138554SRussell King return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 692be138554SRussell King } 693be138554SRussell King 694fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 695fb9ee047SLudovic Desroches unsigned int *actual_clock); 6961771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 697fec79673SRitesh Harjani void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 6981dceb041SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 6991dceb041SAdrian Hunter unsigned short vdd); 700606d3131SAdrian Hunter void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 701606d3131SAdrian Hunter unsigned short vdd); 7022317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width); 70303231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask); 70496d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 70585a882c2SMasahiro Yamada int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 7062317f56cSRussell King 707b8c86fc5SPierre Ossman #ifdef CONFIG_PM 70815becf68SAdrian Hunter int sdhci_suspend_host(struct sdhci_host *host); 70915becf68SAdrian Hunter int sdhci_resume_host(struct sdhci_host *host); 71015becf68SAdrian Hunter void sdhci_enable_irq_wakeups(struct sdhci_host *host); 71115becf68SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host); 71215becf68SAdrian Hunter int sdhci_runtime_resume_host(struct sdhci_host *host); 71366fd8ad5SAdrian Hunter #endif 71466fd8ad5SAdrian Hunter 715f12e39dbSAdrian Hunter void sdhci_cqe_enable(struct mmc_host *mmc); 716f12e39dbSAdrian Hunter void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 717f12e39dbSAdrian Hunter bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 718f12e39dbSAdrian Hunter int *data_error); 719f12e39dbSAdrian Hunter 720d2898172SAdrian Hunter void sdhci_dumpregs(struct sdhci_host *host); 721d2898172SAdrian Hunter 7221978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */ 723