xref: /openbmc/linux/drivers/mmc/host/sdhci.h (revision 7756a96d)
11c6a0718SPierre Ossman /*
270f10482SPierre Ossman  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
31c6a0718SPierre Ossman  *
41978fda8SGiuseppe Cavallaro  * Header file for Host Controller registers and I/O accessors.
51978fda8SGiuseppe Cavallaro  *
6b69c9058SPierre Ossman  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
71c6a0718SPierre Ossman  *
81c6a0718SPierre Ossman  * This program is free software; you can redistribute it and/or modify
91c6a0718SPierre Ossman  * it under the terms of the GNU General Public License as published by
101c6a0718SPierre Ossman  * the Free Software Foundation; either version 2 of the License, or (at
111c6a0718SPierre Ossman  * your option) any later version.
121c6a0718SPierre Ossman  */
131978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H
141978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H
151c6a0718SPierre Ossman 
160c7ad106SAndrew Morton #include <linux/scatterlist.h>
174e4141a5SAnton Vorontsov #include <linux/compiler.h>
184e4141a5SAnton Vorontsov #include <linux/types.h>
194e4141a5SAnton Vorontsov #include <linux/io.h>
200c7ad106SAndrew Morton 
211978fda8SGiuseppe Cavallaro #include <linux/mmc/sdhci.h>
221978fda8SGiuseppe Cavallaro 
231c6a0718SPierre Ossman /*
241c6a0718SPierre Ossman  * Controller registers
251c6a0718SPierre Ossman  */
261c6a0718SPierre Ossman 
271c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS	0x00
288edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2		SDHCI_DMA_ADDRESS
291c6a0718SPierre Ossman 
301c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE	0x04
311c6a0718SPierre Ossman #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
321c6a0718SPierre Ossman 
331c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT	0x06
341c6a0718SPierre Ossman 
351c6a0718SPierre Ossman #define SDHCI_ARGUMENT		0x08
361c6a0718SPierre Ossman 
371c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE	0x0C
381c6a0718SPierre Ossman #define  SDHCI_TRNS_DMA		0x01
391c6a0718SPierre Ossman #define  SDHCI_TRNS_BLK_CNT_EN	0x02
40e89d456fSAndrei Warkentin #define  SDHCI_TRNS_AUTO_CMD12	0x04
418edf6371SAndrei Warkentin #define  SDHCI_TRNS_AUTO_CMD23	0x08
421c6a0718SPierre Ossman #define  SDHCI_TRNS_READ	0x10
431c6a0718SPierre Ossman #define  SDHCI_TRNS_MULTI	0x20
441c6a0718SPierre Ossman 
451c6a0718SPierre Ossman #define SDHCI_COMMAND		0x0E
461c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_MASK	0x03
471c6a0718SPierre Ossman #define  SDHCI_CMD_CRC		0x08
481c6a0718SPierre Ossman #define  SDHCI_CMD_INDEX	0x10
491c6a0718SPierre Ossman #define  SDHCI_CMD_DATA		0x20
50574e3f56SRichard Zhu #define  SDHCI_CMD_ABORTCMD	0xC0
511c6a0718SPierre Ossman 
521c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_NONE	0x00
531c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_LONG	0x01
541c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_SHORT	0x02
551c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
561c6a0718SPierre Ossman 
571c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
5822113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
591c6a0718SPierre Ossman 
601c6a0718SPierre Ossman #define SDHCI_RESPONSE		0x10
611c6a0718SPierre Ossman 
621c6a0718SPierre Ossman #define SDHCI_BUFFER		0x20
631c6a0718SPierre Ossman 
641c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE	0x24
651c6a0718SPierre Ossman #define  SDHCI_CMD_INHIBIT	0x00000001
661c6a0718SPierre Ossman #define  SDHCI_DATA_INHIBIT	0x00000002
671c6a0718SPierre Ossman #define  SDHCI_DOING_WRITE	0x00000100
681c6a0718SPierre Ossman #define  SDHCI_DOING_READ	0x00000200
691c6a0718SPierre Ossman #define  SDHCI_SPACE_AVAILABLE	0x00000400
701c6a0718SPierre Ossman #define  SDHCI_DATA_AVAILABLE	0x00000800
711c6a0718SPierre Ossman #define  SDHCI_CARD_PRESENT	0x00010000
721c6a0718SPierre Ossman #define  SDHCI_WRITE_PROTECT	0x00080000
73f2119df6SArindam Nath #define  SDHCI_DATA_LVL_MASK	0x00F00000
74f2119df6SArindam Nath #define   SDHCI_DATA_LVL_SHIFT	20
757756a96dSYi Sun #define   SDHCI_DATA_0_LVL_MASK	0x00100000
761c6a0718SPierre Ossman 
771c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL	0x28
781c6a0718SPierre Ossman #define  SDHCI_CTRL_LED		0x01
791c6a0718SPierre Ossman #define  SDHCI_CTRL_4BITBUS	0x02
801c6a0718SPierre Ossman #define  SDHCI_CTRL_HISPD	0x04
812134a922SPierre Ossman #define  SDHCI_CTRL_DMA_MASK	0x18
822134a922SPierre Ossman #define   SDHCI_CTRL_SDMA	0x00
832134a922SPierre Ossman #define   SDHCI_CTRL_ADMA1	0x08
842134a922SPierre Ossman #define   SDHCI_CTRL_ADMA32	0x10
852134a922SPierre Ossman #define   SDHCI_CTRL_ADMA64	0x18
86ae6d6c92SKyungmin Park #define   SDHCI_CTRL_8BITBUS	0x20
871c6a0718SPierre Ossman 
881c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL	0x29
891c6a0718SPierre Ossman #define  SDHCI_POWER_ON		0x01
901c6a0718SPierre Ossman #define  SDHCI_POWER_180	0x0A
911c6a0718SPierre Ossman #define  SDHCI_POWER_300	0x0C
921c6a0718SPierre Ossman #define  SDHCI_POWER_330	0x0E
931c6a0718SPierre Ossman 
941c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL	0x2A
951c6a0718SPierre Ossman 
962df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL	0x2B
975f619704SDaniel Drake #define  SDHCI_WAKE_ON_INT	0x01
985f619704SDaniel Drake #define  SDHCI_WAKE_ON_INSERT	0x02
995f619704SDaniel Drake #define  SDHCI_WAKE_ON_REMOVE	0x04
1001c6a0718SPierre Ossman 
1011c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL	0x2C
1021c6a0718SPierre Ossman #define  SDHCI_DIVIDER_SHIFT	8
10385105c53SZhangfei Gao #define  SDHCI_DIVIDER_HI_SHIFT	6
10485105c53SZhangfei Gao #define  SDHCI_DIV_MASK	0xFF
10585105c53SZhangfei Gao #define  SDHCI_DIV_MASK_LEN	8
10685105c53SZhangfei Gao #define  SDHCI_DIV_HI_MASK	0x300
107c3ed3877SArindam Nath #define  SDHCI_PROG_CLOCK_MODE	0x0020
1081c6a0718SPierre Ossman #define  SDHCI_CLOCK_CARD_EN	0x0004
1091c6a0718SPierre Ossman #define  SDHCI_CLOCK_INT_STABLE	0x0002
1101c6a0718SPierre Ossman #define  SDHCI_CLOCK_INT_EN	0x0001
1111c6a0718SPierre Ossman 
1121c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL	0x2E
1131c6a0718SPierre Ossman 
1141c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET	0x2F
1151c6a0718SPierre Ossman #define  SDHCI_RESET_ALL	0x01
1161c6a0718SPierre Ossman #define  SDHCI_RESET_CMD	0x02
1171c6a0718SPierre Ossman #define  SDHCI_RESET_DATA	0x04
1181c6a0718SPierre Ossman 
1191c6a0718SPierre Ossman #define SDHCI_INT_STATUS	0x30
1201c6a0718SPierre Ossman #define SDHCI_INT_ENABLE	0x34
1211c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE	0x38
1221c6a0718SPierre Ossman #define  SDHCI_INT_RESPONSE	0x00000001
1231c6a0718SPierre Ossman #define  SDHCI_INT_DATA_END	0x00000002
124a4071fbbSHaijun Zhang #define  SDHCI_INT_BLK_GAP	0x00000004
1251c6a0718SPierre Ossman #define  SDHCI_INT_DMA_END	0x00000008
1261c6a0718SPierre Ossman #define  SDHCI_INT_SPACE_AVAIL	0x00000010
1271c6a0718SPierre Ossman #define  SDHCI_INT_DATA_AVAIL	0x00000020
1281c6a0718SPierre Ossman #define  SDHCI_INT_CARD_INSERT	0x00000040
1291c6a0718SPierre Ossman #define  SDHCI_INT_CARD_REMOVE	0x00000080
1301c6a0718SPierre Ossman #define  SDHCI_INT_CARD_INT	0x00000100
131964f9ce2SPierre Ossman #define  SDHCI_INT_ERROR	0x00008000
1321c6a0718SPierre Ossman #define  SDHCI_INT_TIMEOUT	0x00010000
1331c6a0718SPierre Ossman #define  SDHCI_INT_CRC		0x00020000
1341c6a0718SPierre Ossman #define  SDHCI_INT_END_BIT	0x00040000
1351c6a0718SPierre Ossman #define  SDHCI_INT_INDEX	0x00080000
1361c6a0718SPierre Ossman #define  SDHCI_INT_DATA_TIMEOUT	0x00100000
1371c6a0718SPierre Ossman #define  SDHCI_INT_DATA_CRC	0x00200000
1381c6a0718SPierre Ossman #define  SDHCI_INT_DATA_END_BIT	0x00400000
1391c6a0718SPierre Ossman #define  SDHCI_INT_BUS_POWER	0x00800000
1401c6a0718SPierre Ossman #define  SDHCI_INT_ACMD12ERR	0x01000000
1412134a922SPierre Ossman #define  SDHCI_INT_ADMA_ERROR	0x02000000
1421c6a0718SPierre Ossman 
1431c6a0718SPierre Ossman #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
1441c6a0718SPierre Ossman #define  SDHCI_INT_ERROR_MASK	0xFFFF8000
1451c6a0718SPierre Ossman 
1461c6a0718SPierre Ossman #define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
1471c6a0718SPierre Ossman 		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
1481c6a0718SPierre Ossman #define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
1491c6a0718SPierre Ossman 		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
1501c6a0718SPierre Ossman 		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
151a4071fbbSHaijun Zhang 		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
152a4071fbbSHaijun Zhang 		SDHCI_INT_BLK_GAP)
1537260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
1541c6a0718SPierre Ossman 
1551c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR	0x3C
1561c6a0718SPierre Ossman 
157f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2		0x3E
15849c468fcSArindam Nath #define  SDHCI_CTRL_UHS_MASK		0x0007
15949c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR12		0x0000
16049c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR25		0x0001
16149c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR50		0x0002
16249c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR104		0x0003
16349c468fcSArindam Nath #define   SDHCI_CTRL_UHS_DDR50		0x0004
164069c9f14SGirish K S #define   SDHCI_CTRL_HS_SDR200		0x0005 /* reserved value in SDIO spec */
165f2119df6SArindam Nath #define  SDHCI_CTRL_VDD_180		0x0008
166d6d50a15SArindam Nath #define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
167d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_B		0x0000
168d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_A		0x0010
169d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_C		0x0020
170d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_D		0x0030
171b513ea25SArindam Nath #define  SDHCI_CTRL_EXEC_TUNING		0x0040
172b513ea25SArindam Nath #define  SDHCI_CTRL_TUNED_CLK		0x0080
173d6d50a15SArindam Nath #define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000
1741c6a0718SPierre Ossman 
1751c6a0718SPierre Ossman #define SDHCI_CAPABILITIES	0x40
1761c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
1771c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_SHIFT 0
1781c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
1791c6a0718SPierre Ossman #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
180c4687d5fSZhangfei Gao #define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
1811c6a0718SPierre Ossman #define  SDHCI_CLOCK_BASE_SHIFT	8
1821c6a0718SPierre Ossman #define  SDHCI_MAX_BLOCK_MASK	0x00030000
1831c6a0718SPierre Ossman #define  SDHCI_MAX_BLOCK_SHIFT  16
18415ec4461SPhilip Rakity #define  SDHCI_CAN_DO_8BIT	0x00040000
1852134a922SPierre Ossman #define  SDHCI_CAN_DO_ADMA2	0x00080000
1862134a922SPierre Ossman #define  SDHCI_CAN_DO_ADMA1	0x00100000
1871c6a0718SPierre Ossman #define  SDHCI_CAN_DO_HISPD	0x00200000
188a13abc7bSRichard Röjfors #define  SDHCI_CAN_DO_SDMA	0x00400000
1891c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_330	0x01000000
1901c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_300	0x02000000
1911c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_180	0x04000000
1922134a922SPierre Ossman #define  SDHCI_CAN_64BIT	0x10000000
1931c6a0718SPierre Ossman 
194f2119df6SArindam Nath #define  SDHCI_SUPPORT_SDR50	0x00000001
195f2119df6SArindam Nath #define  SDHCI_SUPPORT_SDR104	0x00000002
196f2119df6SArindam Nath #define  SDHCI_SUPPORT_DDR50	0x00000004
197d6d50a15SArindam Nath #define  SDHCI_DRIVER_TYPE_A	0x00000010
198d6d50a15SArindam Nath #define  SDHCI_DRIVER_TYPE_C	0x00000020
199d6d50a15SArindam Nath #define  SDHCI_DRIVER_TYPE_D	0x00000040
200cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_TIMER_COUNT_MASK	0x00000F00
201cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT	8
202b513ea25SArindam Nath #define  SDHCI_USE_SDR50_TUNING			0x00002000
203cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_MODE_MASK		0x0000C000
204cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_MODE_SHIFT		14
205c3ed3877SArindam Nath #define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
206c3ed3877SArindam Nath #define  SDHCI_CLOCK_MUL_SHIFT	16
207f2119df6SArindam Nath 
208e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1	0x44
2091c6a0718SPierre Ossman 
2101c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT		0x48
211bad37e1aSPhilip Rakity #define  SDHCI_MAX_CURRENT_LIMIT	0xFF
212f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_330_MASK	0x0000FF
213f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_330_SHIFT	0
214f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_300_MASK	0x00FF00
215f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_300_SHIFT	8
216f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_180_MASK	0xFF0000
217f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_180_SHIFT	16
218f2119df6SArindam Nath #define   SDHCI_MAX_CURRENT_MULTIPLIER	4
2191c6a0718SPierre Ossman 
2201c6a0718SPierre Ossman /* 4C-4F reserved for more max current */
2211c6a0718SPierre Ossman 
2222134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR	0x50
2232134a922SPierre Ossman #define SDHCI_SET_INT_ERROR	0x52
2242134a922SPierre Ossman 
2252134a922SPierre Ossman #define SDHCI_ADMA_ERROR	0x54
2262134a922SPierre Ossman 
2272134a922SPierre Ossman /* 55-57 reserved */
2282134a922SPierre Ossman 
2292134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS	0x58
2302134a922SPierre Ossman 
2312134a922SPierre Ossman /* 60-FB reserved */
2321c6a0718SPierre Ossman 
23352983382SKevin Liu #define SDHCI_PRESET_FOR_SDR12 0x66
23452983382SKevin Liu #define SDHCI_PRESET_FOR_SDR25 0x68
23552983382SKevin Liu #define SDHCI_PRESET_FOR_SDR50 0x6A
23652983382SKevin Liu #define SDHCI_PRESET_FOR_SDR104        0x6C
23752983382SKevin Liu #define SDHCI_PRESET_FOR_DDR50 0x6E
23852983382SKevin Liu #define SDHCI_PRESET_DRV_MASK  0xC000
23952983382SKevin Liu #define SDHCI_PRESET_DRV_SHIFT  14
24052983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
24152983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_SHIFT	10
24252983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
24352983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_SHIFT	0
24452983382SKevin Liu 
2451c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS	0xFC
2461c6a0718SPierre Ossman 
2471c6a0718SPierre Ossman #define SDHCI_HOST_VERSION	0xFE
2481c6a0718SPierre Ossman #define  SDHCI_VENDOR_VER_MASK	0xFF00
2491c6a0718SPierre Ossman #define  SDHCI_VENDOR_VER_SHIFT	8
2501c6a0718SPierre Ossman #define  SDHCI_SPEC_VER_MASK	0x00FF
2511c6a0718SPierre Ossman #define  SDHCI_SPEC_VER_SHIFT	0
2522134a922SPierre Ossman #define   SDHCI_SPEC_100	0
2532134a922SPierre Ossman #define   SDHCI_SPEC_200	1
25485105c53SZhangfei Gao #define   SDHCI_SPEC_300	2
2551c6a0718SPierre Ossman 
2560397526dSZhangfei Gao /*
2570397526dSZhangfei Gao  * End of controller registers.
2580397526dSZhangfei Gao  */
2590397526dSZhangfei Gao 
2600397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200	256
2610397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300	2046
2620397526dSZhangfei Gao 
263f6a03cbfSMikko Vinni /*
264f6a03cbfSMikko Vinni  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
265f6a03cbfSMikko Vinni  */
266f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
267f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
268f6a03cbfSMikko Vinni 
269b8c86fc5SPierre Ossman struct sdhci_ops {
2704e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
271dc297c92SMatt Fleming 	u32		(*read_l)(struct sdhci_host *host, int reg);
272dc297c92SMatt Fleming 	u16		(*read_w)(struct sdhci_host *host, int reg);
273dc297c92SMatt Fleming 	u8		(*read_b)(struct sdhci_host *host, int reg);
274dc297c92SMatt Fleming 	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
275dc297c92SMatt Fleming 	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
276dc297c92SMatt Fleming 	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
2774e4141a5SAnton Vorontsov #endif
2784e4141a5SAnton Vorontsov 
2798114634cSAnton Vorontsov 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);
2808114634cSAnton Vorontsov 
281b8c86fc5SPierre Ossman 	int		(*enable_dma)(struct sdhci_host *host);
2824240ff0aSBen Dooks 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
283a9e58f25SAnton Vorontsov 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
2844240ff0aSBen Dooks 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
285a6ff5aebSAisheng Dong 	unsigned int	(*get_max_timeout_count)(struct sdhci_host *host);
286b45e668aSAisheng Dong 	void		(*set_timeout)(struct sdhci_host *host,
287b45e668aSAisheng Dong 				       struct mmc_command *cmd);
2882317f56cSRussell King 	void		(*set_bus_width)(struct sdhci_host *host, int width);
289643a81ffSPhilip Rakity 	void (*platform_send_init_74_clocks)(struct sdhci_host *host,
290643a81ffSPhilip Rakity 					     u8 power_mode);
2912dfb579cSWolfram Sang 	unsigned int    (*get_ro)(struct sdhci_host *host);
29203231f9bSRussell King 	void		(*reset)(struct sdhci_host *host, u8 mask);
29345251812SDong Aisheng 	int	(*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
29413e64501SRussell King 	void	(*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
29520758b66SAdrian Hunter 	void	(*hw_reset)(struct sdhci_host *host);
296a4071fbbSHaijun Zhang 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
29763ef5d8cSJerry Huang 	void	(*platform_init)(struct sdhci_host *host);
298722e1280SChristian Daudt 	void    (*card_event)(struct sdhci_host *host);
2991c6a0718SPierre Ossman };
300b8c86fc5SPierre Ossman 
3014e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
3024e4141a5SAnton Vorontsov 
3034e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
3044e4141a5SAnton Vorontsov {
305dc297c92SMatt Fleming 	if (unlikely(host->ops->write_l))
306dc297c92SMatt Fleming 		host->ops->write_l(host, val, reg);
3074e4141a5SAnton Vorontsov 	else
3084e4141a5SAnton Vorontsov 		writel(val, host->ioaddr + reg);
3094e4141a5SAnton Vorontsov }
3104e4141a5SAnton Vorontsov 
3114e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
3124e4141a5SAnton Vorontsov {
313dc297c92SMatt Fleming 	if (unlikely(host->ops->write_w))
314dc297c92SMatt Fleming 		host->ops->write_w(host, val, reg);
3154e4141a5SAnton Vorontsov 	else
3164e4141a5SAnton Vorontsov 		writew(val, host->ioaddr + reg);
3174e4141a5SAnton Vorontsov }
3184e4141a5SAnton Vorontsov 
3194e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
3204e4141a5SAnton Vorontsov {
321dc297c92SMatt Fleming 	if (unlikely(host->ops->write_b))
322dc297c92SMatt Fleming 		host->ops->write_b(host, val, reg);
3234e4141a5SAnton Vorontsov 	else
3244e4141a5SAnton Vorontsov 		writeb(val, host->ioaddr + reg);
3254e4141a5SAnton Vorontsov }
3264e4141a5SAnton Vorontsov 
3274e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
3284e4141a5SAnton Vorontsov {
329dc297c92SMatt Fleming 	if (unlikely(host->ops->read_l))
330dc297c92SMatt Fleming 		return host->ops->read_l(host, reg);
3314e4141a5SAnton Vorontsov 	else
3324e4141a5SAnton Vorontsov 		return readl(host->ioaddr + reg);
3334e4141a5SAnton Vorontsov }
3344e4141a5SAnton Vorontsov 
3354e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
3364e4141a5SAnton Vorontsov {
337dc297c92SMatt Fleming 	if (unlikely(host->ops->read_w))
338dc297c92SMatt Fleming 		return host->ops->read_w(host, reg);
3394e4141a5SAnton Vorontsov 	else
3404e4141a5SAnton Vorontsov 		return readw(host->ioaddr + reg);
3414e4141a5SAnton Vorontsov }
3424e4141a5SAnton Vorontsov 
3434e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
3444e4141a5SAnton Vorontsov {
345dc297c92SMatt Fleming 	if (unlikely(host->ops->read_b))
346dc297c92SMatt Fleming 		return host->ops->read_b(host, reg);
3474e4141a5SAnton Vorontsov 	else
3484e4141a5SAnton Vorontsov 		return readb(host->ioaddr + reg);
3494e4141a5SAnton Vorontsov }
3504e4141a5SAnton Vorontsov 
3514e4141a5SAnton Vorontsov #else
3524e4141a5SAnton Vorontsov 
3534e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
3544e4141a5SAnton Vorontsov {
3554e4141a5SAnton Vorontsov 	writel(val, host->ioaddr + reg);
3564e4141a5SAnton Vorontsov }
3574e4141a5SAnton Vorontsov 
3584e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
3594e4141a5SAnton Vorontsov {
3604e4141a5SAnton Vorontsov 	writew(val, host->ioaddr + reg);
3614e4141a5SAnton Vorontsov }
3624e4141a5SAnton Vorontsov 
3634e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
3644e4141a5SAnton Vorontsov {
3654e4141a5SAnton Vorontsov 	writeb(val, host->ioaddr + reg);
3664e4141a5SAnton Vorontsov }
3674e4141a5SAnton Vorontsov 
3684e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
3694e4141a5SAnton Vorontsov {
3704e4141a5SAnton Vorontsov 	return readl(host->ioaddr + reg);
3714e4141a5SAnton Vorontsov }
3724e4141a5SAnton Vorontsov 
3734e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
3744e4141a5SAnton Vorontsov {
3754e4141a5SAnton Vorontsov 	return readw(host->ioaddr + reg);
3764e4141a5SAnton Vorontsov }
3774e4141a5SAnton Vorontsov 
3784e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
3794e4141a5SAnton Vorontsov {
3804e4141a5SAnton Vorontsov 	return readb(host->ioaddr + reg);
3814e4141a5SAnton Vorontsov }
3824e4141a5SAnton Vorontsov 
3834e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
384b8c86fc5SPierre Ossman 
385b8c86fc5SPierre Ossman extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
386b8c86fc5SPierre Ossman 	size_t priv_size);
387b8c86fc5SPierre Ossman extern void sdhci_free_host(struct sdhci_host *host);
388b8c86fc5SPierre Ossman 
389b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host)
390b8c86fc5SPierre Ossman {
391b8c86fc5SPierre Ossman 	return (void *)host->private;
392b8c86fc5SPierre Ossman }
393b8c86fc5SPierre Ossman 
39417866e14SMarek Szyprowski extern void sdhci_card_detect(struct sdhci_host *host);
395b8c86fc5SPierre Ossman extern int sdhci_add_host(struct sdhci_host *host);
3961e72859eSPierre Ossman extern void sdhci_remove_host(struct sdhci_host *host, int dead);
397c0e55129SDong Aisheng extern void sdhci_send_command(struct sdhci_host *host,
398c0e55129SDong Aisheng 				struct mmc_command *cmd);
399b8c86fc5SPierre Ossman 
400be138554SRussell King static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
401be138554SRussell King {
402be138554SRussell King 	return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
403be138554SRussell King }
404be138554SRussell King 
4051771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
4062317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width);
40703231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask);
40896d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
4092317f56cSRussell King 
410b8c86fc5SPierre Ossman #ifdef CONFIG_PM
41129495aa0SManuel Lauss extern int sdhci_suspend_host(struct sdhci_host *host);
412b8c86fc5SPierre Ossman extern int sdhci_resume_host(struct sdhci_host *host);
4135f619704SDaniel Drake extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
414b8c86fc5SPierre Ossman #endif
415c0bba0d2SAlbert Herranz 
41666fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME
41766fd8ad5SAdrian Hunter extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
41866fd8ad5SAdrian Hunter extern int sdhci_runtime_resume_host(struct sdhci_host *host);
41966fd8ad5SAdrian Hunter #endif
42066fd8ad5SAdrian Hunter 
4211978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */
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