xref: /openbmc/linux/drivers/mmc/host/sdhci.h (revision 55654be9)
11c6a0718SPierre Ossman /*
270f10482SPierre Ossman  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
31c6a0718SPierre Ossman  *
4b69c9058SPierre Ossman  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
51c6a0718SPierre Ossman  *
61c6a0718SPierre Ossman  * This program is free software; you can redistribute it and/or modify
71c6a0718SPierre Ossman  * it under the terms of the GNU General Public License as published by
81c6a0718SPierre Ossman  * the Free Software Foundation; either version 2 of the License, or (at
91c6a0718SPierre Ossman  * your option) any later version.
101c6a0718SPierre Ossman  */
111c6a0718SPierre Ossman 
121c6a0718SPierre Ossman /*
131c6a0718SPierre Ossman  * PCI registers
141c6a0718SPierre Ossman  */
151c6a0718SPierre Ossman 
161c6a0718SPierre Ossman #define PCI_SDHCI_IFPIO			0x00
171c6a0718SPierre Ossman #define PCI_SDHCI_IFDMA			0x01
181c6a0718SPierre Ossman #define PCI_SDHCI_IFVENDOR		0x02
191c6a0718SPierre Ossman 
201c6a0718SPierre Ossman #define PCI_SLOT_INFO			0x40	/* 8 bits */
211c6a0718SPierre Ossman #define  PCI_SLOT_INFO_SLOTS(x)		((x >> 4) & 7)
221c6a0718SPierre Ossman #define  PCI_SLOT_INFO_FIRST_BAR_MASK	0x07
231c6a0718SPierre Ossman 
241c6a0718SPierre Ossman /*
251c6a0718SPierre Ossman  * Controller registers
261c6a0718SPierre Ossman  */
271c6a0718SPierre Ossman 
281c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS	0x00
291c6a0718SPierre Ossman 
301c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE	0x04
311c6a0718SPierre Ossman #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
321c6a0718SPierre Ossman 
331c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT	0x06
341c6a0718SPierre Ossman 
351c6a0718SPierre Ossman #define SDHCI_ARGUMENT		0x08
361c6a0718SPierre Ossman 
371c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE	0x0C
381c6a0718SPierre Ossman #define  SDHCI_TRNS_DMA		0x01
391c6a0718SPierre Ossman #define  SDHCI_TRNS_BLK_CNT_EN	0x02
401c6a0718SPierre Ossman #define  SDHCI_TRNS_ACMD12	0x04
411c6a0718SPierre Ossman #define  SDHCI_TRNS_READ	0x10
421c6a0718SPierre Ossman #define  SDHCI_TRNS_MULTI	0x20
431c6a0718SPierre Ossman 
441c6a0718SPierre Ossman #define SDHCI_COMMAND		0x0E
451c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_MASK	0x03
461c6a0718SPierre Ossman #define  SDHCI_CMD_CRC		0x08
471c6a0718SPierre Ossman #define  SDHCI_CMD_INDEX	0x10
481c6a0718SPierre Ossman #define  SDHCI_CMD_DATA		0x20
491c6a0718SPierre Ossman 
501c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_NONE	0x00
511c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_LONG	0x01
521c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_SHORT	0x02
531c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
541c6a0718SPierre Ossman 
551c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
561c6a0718SPierre Ossman 
571c6a0718SPierre Ossman #define SDHCI_RESPONSE		0x10
581c6a0718SPierre Ossman 
591c6a0718SPierre Ossman #define SDHCI_BUFFER		0x20
601c6a0718SPierre Ossman 
611c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE	0x24
621c6a0718SPierre Ossman #define  SDHCI_CMD_INHIBIT	0x00000001
631c6a0718SPierre Ossman #define  SDHCI_DATA_INHIBIT	0x00000002
641c6a0718SPierre Ossman #define  SDHCI_DOING_WRITE	0x00000100
651c6a0718SPierre Ossman #define  SDHCI_DOING_READ	0x00000200
661c6a0718SPierre Ossman #define  SDHCI_SPACE_AVAILABLE	0x00000400
671c6a0718SPierre Ossman #define  SDHCI_DATA_AVAILABLE	0x00000800
681c6a0718SPierre Ossman #define  SDHCI_CARD_PRESENT	0x00010000
691c6a0718SPierre Ossman #define  SDHCI_WRITE_PROTECT	0x00080000
701c6a0718SPierre Ossman 
711c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 	0x28
721c6a0718SPierre Ossman #define  SDHCI_CTRL_LED		0x01
731c6a0718SPierre Ossman #define  SDHCI_CTRL_4BITBUS	0x02
741c6a0718SPierre Ossman #define  SDHCI_CTRL_HISPD	0x04
751c6a0718SPierre Ossman 
761c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL	0x29
771c6a0718SPierre Ossman #define  SDHCI_POWER_ON		0x01
781c6a0718SPierre Ossman #define  SDHCI_POWER_180	0x0A
791c6a0718SPierre Ossman #define  SDHCI_POWER_300	0x0C
801c6a0718SPierre Ossman #define  SDHCI_POWER_330	0x0E
811c6a0718SPierre Ossman 
821c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL	0x2A
831c6a0718SPierre Ossman 
842df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL	0x2B
851c6a0718SPierre Ossman 
861c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL	0x2C
871c6a0718SPierre Ossman #define  SDHCI_DIVIDER_SHIFT	8
881c6a0718SPierre Ossman #define  SDHCI_CLOCK_CARD_EN	0x0004
891c6a0718SPierre Ossman #define  SDHCI_CLOCK_INT_STABLE	0x0002
901c6a0718SPierre Ossman #define  SDHCI_CLOCK_INT_EN	0x0001
911c6a0718SPierre Ossman 
921c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL	0x2E
931c6a0718SPierre Ossman 
941c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET	0x2F
951c6a0718SPierre Ossman #define  SDHCI_RESET_ALL	0x01
961c6a0718SPierre Ossman #define  SDHCI_RESET_CMD	0x02
971c6a0718SPierre Ossman #define  SDHCI_RESET_DATA	0x04
981c6a0718SPierre Ossman 
991c6a0718SPierre Ossman #define SDHCI_INT_STATUS	0x30
1001c6a0718SPierre Ossman #define SDHCI_INT_ENABLE	0x34
1011c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE	0x38
1021c6a0718SPierre Ossman #define  SDHCI_INT_RESPONSE	0x00000001
1031c6a0718SPierre Ossman #define  SDHCI_INT_DATA_END	0x00000002
1041c6a0718SPierre Ossman #define  SDHCI_INT_DMA_END	0x00000008
1051c6a0718SPierre Ossman #define  SDHCI_INT_SPACE_AVAIL	0x00000010
1061c6a0718SPierre Ossman #define  SDHCI_INT_DATA_AVAIL	0x00000020
1071c6a0718SPierre Ossman #define  SDHCI_INT_CARD_INSERT	0x00000040
1081c6a0718SPierre Ossman #define  SDHCI_INT_CARD_REMOVE	0x00000080
1091c6a0718SPierre Ossman #define  SDHCI_INT_CARD_INT	0x00000100
110964f9ce2SPierre Ossman #define  SDHCI_INT_ERROR	0x00008000
1111c6a0718SPierre Ossman #define  SDHCI_INT_TIMEOUT	0x00010000
1121c6a0718SPierre Ossman #define  SDHCI_INT_CRC		0x00020000
1131c6a0718SPierre Ossman #define  SDHCI_INT_END_BIT	0x00040000
1141c6a0718SPierre Ossman #define  SDHCI_INT_INDEX	0x00080000
1151c6a0718SPierre Ossman #define  SDHCI_INT_DATA_TIMEOUT	0x00100000
1161c6a0718SPierre Ossman #define  SDHCI_INT_DATA_CRC	0x00200000
1171c6a0718SPierre Ossman #define  SDHCI_INT_DATA_END_BIT	0x00400000
1181c6a0718SPierre Ossman #define  SDHCI_INT_BUS_POWER	0x00800000
1191c6a0718SPierre Ossman #define  SDHCI_INT_ACMD12ERR	0x01000000
1201c6a0718SPierre Ossman 
1211c6a0718SPierre Ossman #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
1221c6a0718SPierre Ossman #define  SDHCI_INT_ERROR_MASK	0xFFFF8000
1231c6a0718SPierre Ossman 
1241c6a0718SPierre Ossman #define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
1251c6a0718SPierre Ossman 		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
1261c6a0718SPierre Ossman #define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
1271c6a0718SPierre Ossman 		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
1281c6a0718SPierre Ossman 		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
1291c6a0718SPierre Ossman 		SDHCI_INT_DATA_END_BIT)
1301c6a0718SPierre Ossman 
1311c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR	0x3C
1321c6a0718SPierre Ossman 
1331c6a0718SPierre Ossman /* 3E-3F reserved */
1341c6a0718SPierre Ossman 
1351c6a0718SPierre Ossman #define SDHCI_CAPABILITIES	0x40
1361c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
1371c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_SHIFT 0
1381c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
1391c6a0718SPierre Ossman #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
1401c6a0718SPierre Ossman #define  SDHCI_CLOCK_BASE_SHIFT	8
1411c6a0718SPierre Ossman #define  SDHCI_MAX_BLOCK_MASK	0x00030000
1421c6a0718SPierre Ossman #define  SDHCI_MAX_BLOCK_SHIFT  16
1431c6a0718SPierre Ossman #define  SDHCI_CAN_DO_HISPD	0x00200000
1441c6a0718SPierre Ossman #define  SDHCI_CAN_DO_DMA	0x00400000
1451c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_330	0x01000000
1461c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_300	0x02000000
1471c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_180	0x04000000
1481c6a0718SPierre Ossman 
1491c6a0718SPierre Ossman /* 44-47 reserved for more caps */
1501c6a0718SPierre Ossman 
1511c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT	0x48
1521c6a0718SPierre Ossman 
1531c6a0718SPierre Ossman /* 4C-4F reserved for more max current */
1541c6a0718SPierre Ossman 
1551c6a0718SPierre Ossman /* 50-FB reserved */
1561c6a0718SPierre Ossman 
1571c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS	0xFC
1581c6a0718SPierre Ossman 
1591c6a0718SPierre Ossman #define SDHCI_HOST_VERSION	0xFE
1601c6a0718SPierre Ossman #define  SDHCI_VENDOR_VER_MASK	0xFF00
1611c6a0718SPierre Ossman #define  SDHCI_VENDOR_VER_SHIFT	8
1621c6a0718SPierre Ossman #define  SDHCI_SPEC_VER_MASK	0x00FF
1631c6a0718SPierre Ossman #define  SDHCI_SPEC_VER_SHIFT	0
1641c6a0718SPierre Ossman 
1651c6a0718SPierre Ossman struct sdhci_chip;
1661c6a0718SPierre Ossman 
1671c6a0718SPierre Ossman struct sdhci_host {
1681c6a0718SPierre Ossman 	struct sdhci_chip	*chip;
1691c6a0718SPierre Ossman 	struct mmc_host		*mmc;		/* MMC structure */
1701c6a0718SPierre Ossman 
1712f730fecSPierre Ossman #ifdef CONFIG_LEDS_CLASS
1722f730fecSPierre Ossman 	struct led_classdev	led;		/* LED control */
1732f730fecSPierre Ossman #endif
1742f730fecSPierre Ossman 
1751c6a0718SPierre Ossman 	spinlock_t		lock;		/* Mutex */
1761c6a0718SPierre Ossman 
1771c6a0718SPierre Ossman 	int			flags;		/* Host attributes */
178c9fddbc4SPierre Ossman #define SDHCI_USE_DMA		(1<<0)		/* Host is DMA capable */
179c9fddbc4SPierre Ossman #define SDHCI_REQ_USE_DMA	(1<<1)		/* Use DMA for this req. */
1801c6a0718SPierre Ossman 
1811c6a0718SPierre Ossman 	unsigned int		max_clk;	/* Max possible freq (MHz) */
1821c6a0718SPierre Ossman 	unsigned int		timeout_clk;	/* Timeout freq (KHz) */
1831c6a0718SPierre Ossman 
1841c6a0718SPierre Ossman 	unsigned int		clock;		/* Current clock (MHz) */
1851c6a0718SPierre Ossman 	unsigned short		power;		/* Current voltage */
1861c6a0718SPierre Ossman 
1871c6a0718SPierre Ossman 	struct mmc_request	*mrq;		/* Current request */
1881c6a0718SPierre Ossman 	struct mmc_command	*cmd;		/* Current command */
1891c6a0718SPierre Ossman 	struct mmc_data		*data;		/* Current data request */
19055654be9SHarvey Harrison 	unsigned int		data_early:1;	/* Data finished before cmd */
1911c6a0718SPierre Ossman 
1921c6a0718SPierre Ossman 	struct scatterlist	*cur_sg;	/* We're working on this */
1931c6a0718SPierre Ossman 	int			num_sg;		/* Entries left */
1941c6a0718SPierre Ossman 	int			offset;		/* Offset into current sg */
1951c6a0718SPierre Ossman 	int			remain;		/* Bytes left in current */
1961c6a0718SPierre Ossman 
1971c6a0718SPierre Ossman 	int			irq;		/* Device IRQ */
1981c6a0718SPierre Ossman 	int			bar;		/* PCI BAR index */
1991c6a0718SPierre Ossman 	unsigned long		addr;		/* Bus address */
2001c6a0718SPierre Ossman 	void __iomem *		ioaddr;		/* Mapped address */
2011c6a0718SPierre Ossman 
2021c6a0718SPierre Ossman 	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
2031c6a0718SPierre Ossman 	struct tasklet_struct	finish_tasklet;
2041c6a0718SPierre Ossman 
2051c6a0718SPierre Ossman 	struct timer_list	timer;		/* Timer for timeouts */
2061c6a0718SPierre Ossman };
2071c6a0718SPierre Ossman 
2081c6a0718SPierre Ossman struct sdhci_chip {
2091c6a0718SPierre Ossman 	struct pci_dev		*pdev;
2101c6a0718SPierre Ossman 
2111c6a0718SPierre Ossman 	unsigned long		quirks;
2121c6a0718SPierre Ossman 
2131c6a0718SPierre Ossman 	int			num_slots;	/* Slots on controller */
2141c6a0718SPierre Ossman 	struct sdhci_host	*hosts[0];	/* Pointers to hosts */
2151c6a0718SPierre Ossman };
216