11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 4b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 81c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 91c6a0718SPierre Ossman * your option) any later version. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman 120c7ad106SAndrew Morton #include <linux/scatterlist.h> 134e4141a5SAnton Vorontsov #include <linux/compiler.h> 144e4141a5SAnton Vorontsov #include <linux/types.h> 154e4141a5SAnton Vorontsov #include <linux/io.h> 160c7ad106SAndrew Morton 171c6a0718SPierre Ossman /* 181c6a0718SPierre Ossman * Controller registers 191c6a0718SPierre Ossman */ 201c6a0718SPierre Ossman 211c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 221c6a0718SPierre Ossman 231c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 241c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 251c6a0718SPierre Ossman 261c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 271c6a0718SPierre Ossman 281c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 291c6a0718SPierre Ossman 301c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 311c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 321c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 331c6a0718SPierre Ossman #define SDHCI_TRNS_ACMD12 0x04 341c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 351c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 381c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 391c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 401c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 411c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 441c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 451c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 461c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 471c6a0718SPierre Ossman 481c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 531c6a0718SPierre Ossman 541c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 551c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 561c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 571c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 581c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 591c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 601c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 611c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 621c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 631c6a0718SPierre Ossman 641c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 651c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 661c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 671c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 682134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 692134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 702134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 712134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 722134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 731c6a0718SPierre Ossman 741c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 751c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 761c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 771c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 781c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 791c6a0718SPierre Ossman 801c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 811c6a0718SPierre Ossman 822df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 831c6a0718SPierre Ossman 841c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 851c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 861c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 871c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 881c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 891c6a0718SPierre Ossman 901c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 911c6a0718SPierre Ossman 921c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 931c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 941c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 951c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 961c6a0718SPierre Ossman 971c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 981c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 991c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1001c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1011c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 1021c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1031c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1041c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1051c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1061c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1071c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 108964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1091c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1101c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1111c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1121c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1131c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1141c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1151c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1161c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 1171c6a0718SPierre Ossman #define SDHCI_INT_ACMD12ERR 0x01000000 1182134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1191c6a0718SPierre Ossman 1201c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1211c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1221c6a0718SPierre Ossman 1231c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 1241c6a0718SPierre Ossman SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 1251c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1261c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1271c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 1281c6a0718SPierre Ossman SDHCI_INT_DATA_END_BIT) 1291c6a0718SPierre Ossman 1301c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR 0x3C 1311c6a0718SPierre Ossman 1321c6a0718SPierre Ossman /* 3E-3F reserved */ 1331c6a0718SPierre Ossman 1341c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 1351c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 1361c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 1371c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 1381c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 1391c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 1401c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 1411c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 1422134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 1432134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 1441c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 1451c6a0718SPierre Ossman #define SDHCI_CAN_DO_DMA 0x00400000 1461c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 1471c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 1481c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 1492134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 1501c6a0718SPierre Ossman 1511c6a0718SPierre Ossman /* 44-47 reserved for more caps */ 1521c6a0718SPierre Ossman 1531c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 1541c6a0718SPierre Ossman 1551c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 1561c6a0718SPierre Ossman 1572134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 1582134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 1592134a922SPierre Ossman 1602134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 1612134a922SPierre Ossman 1622134a922SPierre Ossman /* 55-57 reserved */ 1632134a922SPierre Ossman 1642134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 1652134a922SPierre Ossman 1662134a922SPierre Ossman /* 60-FB reserved */ 1671c6a0718SPierre Ossman 1681c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 1691c6a0718SPierre Ossman 1701c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 1711c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 1721c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 1731c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 1741c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 1752134a922SPierre Ossman #define SDHCI_SPEC_100 0 1762134a922SPierre Ossman #define SDHCI_SPEC_200 1 1771c6a0718SPierre Ossman 178b8c86fc5SPierre Ossman struct sdhci_ops; 1791c6a0718SPierre Ossman 1801c6a0718SPierre Ossman struct sdhci_host { 181b8c86fc5SPierre Ossman /* Data set by hardware interface driver */ 182b8c86fc5SPierre Ossman const char *hw_name; /* Hardware bus name */ 183b8c86fc5SPierre Ossman 184b8c86fc5SPierre Ossman unsigned int quirks; /* Deviations from spec. */ 185b8c86fc5SPierre Ossman 186b8c86fc5SPierre Ossman /* Controller doesn't honor resets unless we touch the clock register */ 187b8c86fc5SPierre Ossman #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 188b8c86fc5SPierre Ossman /* Controller has bad caps bits, but really supports DMA */ 189b8c86fc5SPierre Ossman #define SDHCI_QUIRK_FORCE_DMA (1<<1) 190b8c86fc5SPierre Ossman /* Controller doesn't like to be reset when there is no card inserted. */ 191b8c86fc5SPierre Ossman #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 192b8c86fc5SPierre Ossman /* Controller doesn't like clearing the power reg before a change */ 193b8c86fc5SPierre Ossman #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 194b8c86fc5SPierre Ossman /* Controller has flaky internal state so reset it on each ios change */ 195b8c86fc5SPierre Ossman #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 196b8c86fc5SPierre Ossman /* Controller has an unusable DMA engine */ 197b8c86fc5SPierre Ossman #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 1982134a922SPierre Ossman /* Controller has an unusable ADMA engine */ 1992134a922SPierre Ossman #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 200b8c86fc5SPierre Ossman /* Controller can only DMA from 32-bit aligned addresses */ 2012134a922SPierre Ossman #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 202b8c86fc5SPierre Ossman /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 2032134a922SPierre Ossman #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 2042134a922SPierre Ossman /* Controller can only ADMA chunks that are a multiple of 32 bits */ 2052134a922SPierre Ossman #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 206b8c86fc5SPierre Ossman /* Controller needs to be reset after each request to stay stable */ 2072134a922SPierre Ossman #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 208b8c86fc5SPierre Ossman /* Controller needs voltage and power writes to happen separately */ 2092134a922SPierre Ossman #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 210ee53ab5dSPierre Ossman /* Controller provides an incorrect timeout value for transfers */ 2112134a922SPierre Ossman #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 2124a3cba32SPierre Ossman /* Controller has an issue with buffer bits for small transfers */ 2134a3cba32SPierre Ossman #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 214f945405cSBen Dooks /* Controller does not provide transfer-complete interrupt when not busy */ 215f945405cSBen Dooks #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 216b8c86fc5SPierre Ossman 217b8c86fc5SPierre Ossman int irq; /* Device IRQ */ 218b8c86fc5SPierre Ossman void __iomem * ioaddr; /* Mapped address */ 219b8c86fc5SPierre Ossman 220b8c86fc5SPierre Ossman const struct sdhci_ops *ops; /* Low level hw interface */ 221b8c86fc5SPierre Ossman 222b8c86fc5SPierre Ossman /* Internal data */ 2231c6a0718SPierre Ossman struct mmc_host *mmc; /* MMC structure */ 2247659150cSPierre Ossman u64 dma_mask; /* custom DMA mask */ 2251c6a0718SPierre Ossman 22635ff8554SÉric Piel #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 2272f730fecSPierre Ossman struct led_classdev led; /* LED control */ 2285dbace0cSHelmut Schaa char led_name[32]; 2292f730fecSPierre Ossman #endif 2302f730fecSPierre Ossman 2311c6a0718SPierre Ossman spinlock_t lock; /* Mutex */ 2321c6a0718SPierre Ossman 2331c6a0718SPierre Ossman int flags; /* Host attributes */ 234c9fddbc4SPierre Ossman #define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */ 2352134a922SPierre Ossman #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 2362134a922SPierre Ossman #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 2372134a922SPierre Ossman #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 2382134a922SPierre Ossman 2392134a922SPierre Ossman unsigned int version; /* SDHCI spec. version */ 2401c6a0718SPierre Ossman 2411c6a0718SPierre Ossman unsigned int max_clk; /* Max possible freq (MHz) */ 2421c6a0718SPierre Ossman unsigned int timeout_clk; /* Timeout freq (KHz) */ 2431c6a0718SPierre Ossman 2441c6a0718SPierre Ossman unsigned int clock; /* Current clock (MHz) */ 2451c6a0718SPierre Ossman unsigned short power; /* Current voltage */ 2461c6a0718SPierre Ossman 2471c6a0718SPierre Ossman struct mmc_request *mrq; /* Current request */ 2481c6a0718SPierre Ossman struct mmc_command *cmd; /* Current command */ 2491c6a0718SPierre Ossman struct mmc_data *data; /* Current data request */ 25055654be9SHarvey Harrison unsigned int data_early:1; /* Data finished before cmd */ 2511c6a0718SPierre Ossman 2527659150cSPierre Ossman struct sg_mapping_iter sg_miter; /* SG state for PIO */ 2537659150cSPierre Ossman unsigned int blocks; /* remaining PIO blocks */ 2541c6a0718SPierre Ossman 2552134a922SPierre Ossman int sg_count; /* Mapped sg entries */ 2562134a922SPierre Ossman 2572134a922SPierre Ossman u8 *adma_desc; /* ADMA descriptor table */ 2582134a922SPierre Ossman u8 *align_buffer; /* Bounce buffer */ 2592134a922SPierre Ossman 2602134a922SPierre Ossman dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 2612134a922SPierre Ossman dma_addr_t align_addr; /* Mapped bounce buffer */ 2622134a922SPierre Ossman 2631c6a0718SPierre Ossman struct tasklet_struct card_tasklet; /* Tasklet structures */ 2641c6a0718SPierre Ossman struct tasklet_struct finish_tasklet; 2651c6a0718SPierre Ossman 2661c6a0718SPierre Ossman struct timer_list timer; /* Timer for timeouts */ 267b8c86fc5SPierre Ossman 268b8c86fc5SPierre Ossman unsigned long private[0] ____cacheline_aligned; 2691c6a0718SPierre Ossman }; 2701c6a0718SPierre Ossman 2711c6a0718SPierre Ossman 272b8c86fc5SPierre Ossman struct sdhci_ops { 2734e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 2744e4141a5SAnton Vorontsov u32 (*readl)(struct sdhci_host *host, int reg); 2754e4141a5SAnton Vorontsov u16 (*readw)(struct sdhci_host *host, int reg); 2764e4141a5SAnton Vorontsov u8 (*readb)(struct sdhci_host *host, int reg); 2774e4141a5SAnton Vorontsov void (*writel)(struct sdhci_host *host, u32 val, int reg); 2784e4141a5SAnton Vorontsov void (*writew)(struct sdhci_host *host, u16 val, int reg); 2794e4141a5SAnton Vorontsov void (*writeb)(struct sdhci_host *host, u8 val, int reg); 2804e4141a5SAnton Vorontsov #endif 2814e4141a5SAnton Vorontsov 282b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 2831c6a0718SPierre Ossman }; 284b8c86fc5SPierre Ossman 2854e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 2864e4141a5SAnton Vorontsov 2874e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 2884e4141a5SAnton Vorontsov { 2894e4141a5SAnton Vorontsov if (unlikely(host->ops->writel)) 2904e4141a5SAnton Vorontsov host->ops->writel(host, val, reg); 2914e4141a5SAnton Vorontsov else 2924e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 2934e4141a5SAnton Vorontsov } 2944e4141a5SAnton Vorontsov 2954e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 2964e4141a5SAnton Vorontsov { 2974e4141a5SAnton Vorontsov if (unlikely(host->ops->writew)) 2984e4141a5SAnton Vorontsov host->ops->writew(host, val, reg); 2994e4141a5SAnton Vorontsov else 3004e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 3014e4141a5SAnton Vorontsov } 3024e4141a5SAnton Vorontsov 3034e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 3044e4141a5SAnton Vorontsov { 3054e4141a5SAnton Vorontsov if (unlikely(host->ops->writeb)) 3064e4141a5SAnton Vorontsov host->ops->writeb(host, val, reg); 3074e4141a5SAnton Vorontsov else 3084e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3094e4141a5SAnton Vorontsov } 3104e4141a5SAnton Vorontsov 3114e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3124e4141a5SAnton Vorontsov { 3134e4141a5SAnton Vorontsov if (unlikely(host->ops->readl)) 3144e4141a5SAnton Vorontsov return host->ops->readl(host, reg); 3154e4141a5SAnton Vorontsov else 3164e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3174e4141a5SAnton Vorontsov } 3184e4141a5SAnton Vorontsov 3194e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3204e4141a5SAnton Vorontsov { 3214e4141a5SAnton Vorontsov if (unlikely(host->ops->readw)) 3224e4141a5SAnton Vorontsov return host->ops->readw(host, reg); 3234e4141a5SAnton Vorontsov else 3244e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3254e4141a5SAnton Vorontsov } 3264e4141a5SAnton Vorontsov 3274e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3284e4141a5SAnton Vorontsov { 3294e4141a5SAnton Vorontsov if (unlikely(host->ops->readb)) 3304e4141a5SAnton Vorontsov return host->ops->readb(host, reg); 3314e4141a5SAnton Vorontsov else 3324e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3334e4141a5SAnton Vorontsov } 3344e4141a5SAnton Vorontsov 3354e4141a5SAnton Vorontsov #else 3364e4141a5SAnton Vorontsov 3374e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 3384e4141a5SAnton Vorontsov { 3394e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 3404e4141a5SAnton Vorontsov } 3414e4141a5SAnton Vorontsov 3424e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 3434e4141a5SAnton Vorontsov { 3444e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 3454e4141a5SAnton Vorontsov } 3464e4141a5SAnton Vorontsov 3474e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 3484e4141a5SAnton Vorontsov { 3494e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3504e4141a5SAnton Vorontsov } 3514e4141a5SAnton Vorontsov 3524e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3534e4141a5SAnton Vorontsov { 3544e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3554e4141a5SAnton Vorontsov } 3564e4141a5SAnton Vorontsov 3574e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3584e4141a5SAnton Vorontsov { 3594e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3604e4141a5SAnton Vorontsov } 3614e4141a5SAnton Vorontsov 3624e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3634e4141a5SAnton Vorontsov { 3644e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3654e4141a5SAnton Vorontsov } 3664e4141a5SAnton Vorontsov 3674e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 368b8c86fc5SPierre Ossman 369b8c86fc5SPierre Ossman extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 370b8c86fc5SPierre Ossman size_t priv_size); 371b8c86fc5SPierre Ossman extern void sdhci_free_host(struct sdhci_host *host); 372b8c86fc5SPierre Ossman 373b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 374b8c86fc5SPierre Ossman { 375b8c86fc5SPierre Ossman return (void *)host->private; 376b8c86fc5SPierre Ossman } 377b8c86fc5SPierre Ossman 378b8c86fc5SPierre Ossman extern int sdhci_add_host(struct sdhci_host *host); 3791e72859eSPierre Ossman extern void sdhci_remove_host(struct sdhci_host *host, int dead); 380b8c86fc5SPierre Ossman 381b8c86fc5SPierre Ossman #ifdef CONFIG_PM 382b8c86fc5SPierre Ossman extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state); 383b8c86fc5SPierre Ossman extern int sdhci_resume_host(struct sdhci_host *host); 384b8c86fc5SPierre Ossman #endif 385