11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 41978fda8SGiuseppe Cavallaro * Header file for Host Controller registers and I/O accessors. 51978fda8SGiuseppe Cavallaro * 6b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 71c6a0718SPierre Ossman * 81c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 91c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 101c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 111c6a0718SPierre Ossman * your option) any later version. 121c6a0718SPierre Ossman */ 131978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H 141978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H 151c6a0718SPierre Ossman 160c7ad106SAndrew Morton #include <linux/scatterlist.h> 174e4141a5SAnton Vorontsov #include <linux/compiler.h> 184e4141a5SAnton Vorontsov #include <linux/types.h> 194e4141a5SAnton Vorontsov #include <linux/io.h> 20210583f4SUlf Hansson #include <linux/leds.h> 21b8789ec4SUlf Hansson #include <linux/interrupt.h> 220c7ad106SAndrew Morton 2383f13cc9SUlf Hansson #include <linux/mmc/host.h> 241978fda8SGiuseppe Cavallaro 251c6a0718SPierre Ossman /* 261c6a0718SPierre Ossman * Controller registers 271c6a0718SPierre Ossman */ 281c6a0718SPierre Ossman 291c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 308edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 31e65953d4SChunyan Zhang #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 341c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 351c6a0718SPierre Ossman 361c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 391c6a0718SPierre Ossman 401c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 411c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 421c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 43e89d456fSAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD12 0x04 448edf6371SAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD23 0x08 45427b6514SChunyan Zhang #define SDHCI_TRNS_AUTO_SEL 0x0C 461c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 471c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 481c6a0718SPierre Ossman 491c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 501c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 511c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 521c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 531c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 54574e3f56SRichard Zhu #define SDHCI_CMD_ABORTCMD 0xC0 551c6a0718SPierre Ossman 561c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 571c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 581c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 591c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 601c6a0718SPierre Ossman 611c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 6222113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 631c6a0718SPierre Ossman 641c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 651c6a0718SPierre Ossman 661c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 671c6a0718SPierre Ossman 681c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 691c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 701c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 711c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 721c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 731c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 741c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 751c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 761c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 77f2119df6SArindam Nath #define SDHCI_DATA_LVL_MASK 0x00F00000 78f2119df6SArindam Nath #define SDHCI_DATA_LVL_SHIFT 20 797756a96dSYi Sun #define SDHCI_DATA_0_LVL_MASK 0x00100000 80b0921d5cSMichael Walle #define SDHCI_CMD_LVL 0x01000000 811c6a0718SPierre Ossman 821c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 831c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 841c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 851c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 862134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 872134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 882134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 892134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 902134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 91ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 923794c542SZach Brown #define SDHCI_CTRL_CDTEST_INS 0x40 933794c542SZach Brown #define SDHCI_CTRL_CDTEST_EN 0x80 941c6a0718SPierre Ossman 951c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 961c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 971c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 981c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 991c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 1001c6a0718SPierre Ossman 1011c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 1021c6a0718SPierre Ossman 1032df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 1045f619704SDaniel Drake #define SDHCI_WAKE_ON_INT 0x01 1055f619704SDaniel Drake #define SDHCI_WAKE_ON_INSERT 0x02 1065f619704SDaniel Drake #define SDHCI_WAKE_ON_REMOVE 0x04 1071c6a0718SPierre Ossman 1081c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 1091c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 11085105c53SZhangfei Gao #define SDHCI_DIVIDER_HI_SHIFT 6 11185105c53SZhangfei Gao #define SDHCI_DIV_MASK 0xFF 11285105c53SZhangfei Gao #define SDHCI_DIV_MASK_LEN 8 11385105c53SZhangfei Gao #define SDHCI_DIV_HI_MASK 0x300 114c3ed3877SArindam Nath #define SDHCI_PROG_CLOCK_MODE 0x0020 1151c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 1161c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 1171c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 1181c6a0718SPierre Ossman 1191c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 1201c6a0718SPierre Ossman 1211c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 1221c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 1231c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 1241c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 1251c6a0718SPierre Ossman 1261c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1271c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1281c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1291c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1301c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 131a4071fbbSHaijun Zhang #define SDHCI_INT_BLK_GAP 0x00000004 1321c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1331c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1341c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1351c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1361c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1371c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 138f37b20ebSDong Aisheng #define SDHCI_INT_RETUNE 0x00001000 139f12e39dbSAdrian Hunter #define SDHCI_INT_CQE 0x00004000 140964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1411c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1421c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1431c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1441c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1451c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1461c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1471c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1481c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 1491c6a0718SPierre Ossman #define SDHCI_INT_ACMD12ERR 0x01000000 1502134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1511c6a0718SPierre Ossman 1521c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1531c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1541c6a0718SPierre Ossman 1551c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 1561c6a0718SPierre Ossman SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 1571c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1581c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1591c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 160a4071fbbSHaijun Zhang SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 161a4071fbbSHaijun Zhang SDHCI_INT_BLK_GAP) 1627260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1631c6a0718SPierre Ossman 164f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_ERR_MASK ( \ 165f12e39dbSAdrian Hunter SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 166f12e39dbSAdrian Hunter SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 167f12e39dbSAdrian Hunter SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 168f12e39dbSAdrian Hunter 169f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 170f12e39dbSAdrian Hunter 1711c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR 0x3C 1721c6a0718SPierre Ossman 173f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2 0x3E 17449c468fcSArindam Nath #define SDHCI_CTRL_UHS_MASK 0x0007 17549c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR12 0x0000 17649c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR25 0x0001 17749c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR50 0x0002 17849c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR104 0x0003 17949c468fcSArindam Nath #define SDHCI_CTRL_UHS_DDR50 0x0004 180e9fb05d5SAdrian Hunter #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 181f2119df6SArindam Nath #define SDHCI_CTRL_VDD_180 0x0008 182d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 183d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_B 0x0000 184d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_A 0x0010 185d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_C 0x0020 186d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_D 0x0030 187b513ea25SArindam Nath #define SDHCI_CTRL_EXEC_TUNING 0x0040 188b513ea25SArindam Nath #define SDHCI_CTRL_TUNED_CLK 0x0080 189427b6514SChunyan Zhang #define SDHCI_CMD23_ENABLE 0x0800 190b3f80b43SChunyan Zhang #define SDHCI_CTRL_V4_MODE 0x1000 191685e444bSChunyan Zhang #define SDHCI_CTRL_64BIT_ADDR 0x2000 192d6d50a15SArindam Nath #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 1931c6a0718SPierre Ossman 1941c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 1951c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 1961c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 1971c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 1981c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 199c4687d5fSZhangfei Gao #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 2001c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 2011c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 2021c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 20315ec4461SPhilip Rakity #define SDHCI_CAN_DO_8BIT 0x00040000 2042134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 2052134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 2061c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 207a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 208e71d4b81SStefan Wahren #define SDHCI_CAN_DO_SUSPEND 0x00800000 2091c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 2101c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 2111c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 212685e444bSChunyan Zhang #define SDHCI_CAN_64BIT_V4 0x08000000 2132134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 2141c6a0718SPierre Ossman 215f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR50 0x00000001 216f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR104 0x00000002 217f2119df6SArindam Nath #define SDHCI_SUPPORT_DDR50 0x00000004 218d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_A 0x00000010 219d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_C 0x00000020 220d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_D 0x00000040 221cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 222cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 223b513ea25SArindam Nath #define SDHCI_USE_SDR50_TUNING 0x00002000 224cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_MASK 0x0000C000 225cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_SHIFT 14 226c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 227c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_SHIFT 16 228e9fb05d5SAdrian Hunter #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 229f2119df6SArindam Nath 230e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1 0x44 2311c6a0718SPierre Ossman 2321c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 233bad37e1aSPhilip Rakity #define SDHCI_MAX_CURRENT_LIMIT 0xFF 234f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 235f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_SHIFT 0 236f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 237f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_SHIFT 8 238f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 239f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_SHIFT 16 240f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_MULTIPLIER 4 2411c6a0718SPierre Ossman 2421c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 2431c6a0718SPierre Ossman 2442134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 2452134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 2462134a922SPierre Ossman 2472134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 2482134a922SPierre Ossman 2492134a922SPierre Ossman /* 55-57 reserved */ 2502134a922SPierre Ossman 2512134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 252e57a5f61SAdrian Hunter #define SDHCI_ADMA_ADDRESS_HI 0x5C 2532134a922SPierre Ossman 2542134a922SPierre Ossman /* 60-FB reserved */ 2551c6a0718SPierre Ossman 25652983382SKevin Liu #define SDHCI_PRESET_FOR_SDR12 0x66 25752983382SKevin Liu #define SDHCI_PRESET_FOR_SDR25 0x68 25852983382SKevin Liu #define SDHCI_PRESET_FOR_SDR50 0x6A 25952983382SKevin Liu #define SDHCI_PRESET_FOR_SDR104 0x6C 26052983382SKevin Liu #define SDHCI_PRESET_FOR_DDR50 0x6E 261e9fb05d5SAdrian Hunter #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 26252983382SKevin Liu #define SDHCI_PRESET_DRV_MASK 0xC000 26352983382SKevin Liu #define SDHCI_PRESET_DRV_SHIFT 14 26452983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 26552983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 26652983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 26752983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 26852983382SKevin Liu 2691c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 2701c6a0718SPierre Ossman 2711c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 2721c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 2731c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 2741c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 2751c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 2762134a922SPierre Ossman #define SDHCI_SPEC_100 0 2772134a922SPierre Ossman #define SDHCI_SPEC_200 1 27885105c53SZhangfei Gao #define SDHCI_SPEC_300 2 27918da1990SChunyan Zhang #define SDHCI_SPEC_400 3 28018da1990SChunyan Zhang #define SDHCI_SPEC_410 4 28118da1990SChunyan Zhang #define SDHCI_SPEC_420 5 2821c6a0718SPierre Ossman 2830397526dSZhangfei Gao /* 2840397526dSZhangfei Gao * End of controller registers. 2850397526dSZhangfei Gao */ 2860397526dSZhangfei Gao 2870397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200 256 2880397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300 2046 2890397526dSZhangfei Gao 290f6a03cbfSMikko Vinni /* 291f6a03cbfSMikko Vinni * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 292f6a03cbfSMikko Vinni */ 293f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 294f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 295f6a03cbfSMikko Vinni 296739d46dcSAdrian Hunter /* ADMA2 32-bit DMA descriptor size */ 297739d46dcSAdrian Hunter #define SDHCI_ADMA2_32_DESC_SZ 8 298739d46dcSAdrian Hunter 2990545230fSAdrian Hunter /* ADMA2 32-bit descriptor */ 3000545230fSAdrian Hunter struct sdhci_adma2_32_desc { 3010545230fSAdrian Hunter __le16 cmd; 3020545230fSAdrian Hunter __le16 len; 3030545230fSAdrian Hunter __le32 addr; 30404a5ae6fSAdrian Hunter } __packed __aligned(4); 30504a5ae6fSAdrian Hunter 30604a5ae6fSAdrian Hunter /* ADMA2 data alignment */ 30704a5ae6fSAdrian Hunter #define SDHCI_ADMA2_ALIGN 4 30804a5ae6fSAdrian Hunter #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 30904a5ae6fSAdrian Hunter 31004a5ae6fSAdrian Hunter /* 31104a5ae6fSAdrian Hunter * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 31204a5ae6fSAdrian Hunter * alignment for the descriptor table even in 32-bit DMA mode. Memory 31304a5ae6fSAdrian Hunter * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 31404a5ae6fSAdrian Hunter */ 31504a5ae6fSAdrian Hunter #define SDHCI_ADMA2_DESC_ALIGN 8 3160545230fSAdrian Hunter 317685e444bSChunyan Zhang /* 318685e444bSChunyan Zhang * ADMA2 64-bit DMA descriptor size 319685e444bSChunyan Zhang * According to SD Host Controller spec v4.10, there are two kinds of 320685e444bSChunyan Zhang * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 321685e444bSChunyan Zhang * Descriptor, if Host Version 4 Enable is set in the Host Control 2 322685e444bSChunyan Zhang * register, 128-bit Descriptor will be selected. 323685e444bSChunyan Zhang */ 324685e444bSChunyan Zhang #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 325e57a5f61SAdrian Hunter 326e57a5f61SAdrian Hunter /* 327e57a5f61SAdrian Hunter * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 328e57a5f61SAdrian Hunter * aligned. 329e57a5f61SAdrian Hunter */ 330e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc { 331e57a5f61SAdrian Hunter __le16 cmd; 332e57a5f61SAdrian Hunter __le16 len; 333e57a5f61SAdrian Hunter __le32 addr_lo; 334e57a5f61SAdrian Hunter __le32 addr_hi; 335e57a5f61SAdrian Hunter } __packed __aligned(4); 336e57a5f61SAdrian Hunter 337739d46dcSAdrian Hunter #define ADMA2_TRAN_VALID 0x21 338739d46dcSAdrian Hunter #define ADMA2_NOP_END_VALID 0x3 339739d46dcSAdrian Hunter #define ADMA2_END 0x2 340739d46dcSAdrian Hunter 3414fb213f8SAdrian Hunter /* 3424fb213f8SAdrian Hunter * Maximum segments assuming a 512KiB maximum requisition size and a minimum 3434fb213f8SAdrian Hunter * 4KiB page size. 3444fb213f8SAdrian Hunter */ 3454fb213f8SAdrian Hunter #define SDHCI_MAX_SEGS 128 3464fb213f8SAdrian Hunter 3474e9f8fe5SAdrian Hunter /* Allow for a a command request and a data request at the same time */ 3484e9f8fe5SAdrian Hunter #define SDHCI_MAX_MRQS 2 3494e9f8fe5SAdrian Hunter 350fc1fa1b7SKishon Vijay Abraham I /* 351fc1fa1b7SKishon Vijay Abraham I * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 352fc1fa1b7SKishon Vijay Abraham I * However since the start time of the command, the time between 353fc1fa1b7SKishon Vijay Abraham I * command and response, and the time between response and start of data is 354fc1fa1b7SKishon Vijay Abraham I * not known, set the command transfer time to 10ms. 355fc1fa1b7SKishon Vijay Abraham I */ 356fc1fa1b7SKishon Vijay Abraham I #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 357fc1fa1b7SKishon Vijay Abraham I 358d31911b9SHaibo Chen enum sdhci_cookie { 359d31911b9SHaibo Chen COOKIE_UNMAPPED, 36094538e51SRussell King COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 36194538e51SRussell King COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 36283f13cc9SUlf Hansson }; 36383f13cc9SUlf Hansson 36483f13cc9SUlf Hansson struct sdhci_host { 36583f13cc9SUlf Hansson /* Data set by hardware interface driver */ 36683f13cc9SUlf Hansson const char *hw_name; /* Hardware bus name */ 36783f13cc9SUlf Hansson 36883f13cc9SUlf Hansson unsigned int quirks; /* Deviations from spec. */ 36983f13cc9SUlf Hansson 37083f13cc9SUlf Hansson /* Controller doesn't honor resets unless we touch the clock register */ 37183f13cc9SUlf Hansson #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 37283f13cc9SUlf Hansson /* Controller has bad caps bits, but really supports DMA */ 37383f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_DMA (1<<1) 37483f13cc9SUlf Hansson /* Controller doesn't like to be reset when there is no card inserted. */ 37583f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 37683f13cc9SUlf Hansson /* Controller doesn't like clearing the power reg before a change */ 37783f13cc9SUlf Hansson #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 37883f13cc9SUlf Hansson /* Controller has flaky internal state so reset it on each ios change */ 37983f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 38083f13cc9SUlf Hansson /* Controller has an unusable DMA engine */ 38183f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 38283f13cc9SUlf Hansson /* Controller has an unusable ADMA engine */ 38383f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 38483f13cc9SUlf Hansson /* Controller can only DMA from 32-bit aligned addresses */ 38583f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 38683f13cc9SUlf Hansson /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 38783f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 38883f13cc9SUlf Hansson /* Controller can only ADMA chunks that are a multiple of 32 bits */ 38983f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 39083f13cc9SUlf Hansson /* Controller needs to be reset after each request to stay stable */ 39183f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 39283f13cc9SUlf Hansson /* Controller needs voltage and power writes to happen separately */ 39383f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 39483f13cc9SUlf Hansson /* Controller provides an incorrect timeout value for transfers */ 39583f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 39683f13cc9SUlf Hansson /* Controller has an issue with buffer bits for small transfers */ 39783f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 39883f13cc9SUlf Hansson /* Controller does not provide transfer-complete interrupt when not busy */ 39983f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 40083f13cc9SUlf Hansson /* Controller has unreliable card detection */ 40183f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 40283f13cc9SUlf Hansson /* Controller reports inverted write-protect state */ 40383f13cc9SUlf Hansson #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 40483f13cc9SUlf Hansson /* Controller does not like fast PIO transfers */ 40583f13cc9SUlf Hansson #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 40683f13cc9SUlf Hansson /* Controller has to be forced to use block size of 2048 bytes */ 40783f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 40883f13cc9SUlf Hansson /* Controller cannot do multi-block transfers */ 40983f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 41083f13cc9SUlf Hansson /* Controller can only handle 1-bit data transfers */ 41183f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 41283f13cc9SUlf Hansson /* Controller needs 10ms delay between applying power and clock */ 41383f13cc9SUlf Hansson #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 41483f13cc9SUlf Hansson /* Controller uses SDCLK instead of TMCLK for data timeouts */ 41583f13cc9SUlf Hansson #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 41683f13cc9SUlf Hansson /* Controller reports wrong base clock capability */ 41783f13cc9SUlf Hansson #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 41883f13cc9SUlf Hansson /* Controller cannot support End Attribute in NOP ADMA descriptor */ 41983f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 42083f13cc9SUlf Hansson /* Controller is missing device caps. Use caps provided by host */ 42183f13cc9SUlf Hansson #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 42283f13cc9SUlf Hansson /* Controller uses Auto CMD12 command to stop the transfer */ 42383f13cc9SUlf Hansson #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 42483f13cc9SUlf Hansson /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 42583f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 42683f13cc9SUlf Hansson /* Controller treats ADMA descriptors with length 0000h incorrectly */ 42783f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 42883f13cc9SUlf Hansson /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 42983f13cc9SUlf Hansson #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 43083f13cc9SUlf Hansson 43183f13cc9SUlf Hansson unsigned int quirks2; /* More deviations from spec. */ 43283f13cc9SUlf Hansson 43383f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 43483f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 43583f13cc9SUlf Hansson /* The system physically doesn't support 1.8v, even if the host does */ 43683f13cc9SUlf Hansson #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 43783f13cc9SUlf Hansson #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 43883f13cc9SUlf Hansson #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 43983f13cc9SUlf Hansson /* Controller has a non-standard host control register */ 44083f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 44183f13cc9SUlf Hansson /* Controller does not support HS200 */ 44283f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 44383f13cc9SUlf Hansson /* Controller does not support DDR50 */ 44483f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 44583f13cc9SUlf Hansson /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 44683f13cc9SUlf Hansson #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 44783f13cc9SUlf Hansson /* Controller does not support 64-bit DMA */ 44883f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 44983f13cc9SUlf Hansson /* need clear transfer mode register before send cmd */ 45083f13cc9SUlf Hansson #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 45183f13cc9SUlf Hansson /* Capability register bit-63 indicates HS400 support */ 45283f13cc9SUlf Hansson #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 45383f13cc9SUlf Hansson /* forced tuned clock */ 45483f13cc9SUlf Hansson #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 45583f13cc9SUlf Hansson /* disable the block count for single block transactions */ 45683f13cc9SUlf Hansson #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 45783f13cc9SUlf Hansson /* Controller broken with using ACMD23 */ 45883f13cc9SUlf Hansson #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 459d1955c3aSSuneel Garapati /* Broken Clock divider zero in controller */ 460d1955c3aSSuneel Garapati #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 4611284c248SKishon Vijay Abraham I /* Controller has CRC in 136 bit Command Response */ 4621284c248SKishon Vijay Abraham I #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 463a999fd93SAdrian Hunter /* 464a999fd93SAdrian Hunter * Disable HW timeout if the requested timeout is more than the maximum 465a999fd93SAdrian Hunter * obtainable timeout. 466a999fd93SAdrian Hunter */ 467a999fd93SAdrian Hunter #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 468e65953d4SChunyan Zhang /* 469e65953d4SChunyan Zhang * 32-bit block count may not support eMMC where upper bits of CMD23 are used 470e65953d4SChunyan Zhang * for other purposes. Consequently we support 16-bit block count by default. 471e65953d4SChunyan Zhang * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 472e65953d4SChunyan Zhang * block count. 473e65953d4SChunyan Zhang */ 474e65953d4SChunyan Zhang #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 47583f13cc9SUlf Hansson 47683f13cc9SUlf Hansson int irq; /* Device IRQ */ 47783f13cc9SUlf Hansson void __iomem *ioaddr; /* Mapped address */ 478bd9b9027SLinus Walleij char *bounce_buffer; /* For packing SDMA reads/writes */ 479bd9b9027SLinus Walleij dma_addr_t bounce_addr; 480bd9b9027SLinus Walleij unsigned int bounce_buffer_size; 48183f13cc9SUlf Hansson 48283f13cc9SUlf Hansson const struct sdhci_ops *ops; /* Low level hw interface */ 48383f13cc9SUlf Hansson 48483f13cc9SUlf Hansson /* Internal data */ 48583f13cc9SUlf Hansson struct mmc_host *mmc; /* MMC structure */ 486bf60e592SAdrian Hunter struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 48783f13cc9SUlf Hansson u64 dma_mask; /* custom DMA mask */ 48883f13cc9SUlf Hansson 48974479c5dSMasahiro Yamada #if IS_ENABLED(CONFIG_LEDS_CLASS) 49083f13cc9SUlf Hansson struct led_classdev led; /* LED control */ 49183f13cc9SUlf Hansson char led_name[32]; 49283f13cc9SUlf Hansson #endif 49383f13cc9SUlf Hansson 49483f13cc9SUlf Hansson spinlock_t lock; /* Mutex */ 49583f13cc9SUlf Hansson 49683f13cc9SUlf Hansson int flags; /* Host attributes */ 49783f13cc9SUlf Hansson #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 49883f13cc9SUlf Hansson #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 49983f13cc9SUlf Hansson #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 50083f13cc9SUlf Hansson #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 50183f13cc9SUlf Hansson #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 50283f13cc9SUlf Hansson #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 50383f13cc9SUlf Hansson #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 50483f13cc9SUlf Hansson #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 50583f13cc9SUlf Hansson #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 50683f13cc9SUlf Hansson #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 50783f13cc9SUlf Hansson #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 5088cb851a4SAdrian Hunter #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 5098cb851a4SAdrian Hunter #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 5108cb851a4SAdrian Hunter #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 51183f13cc9SUlf Hansson 51283f13cc9SUlf Hansson unsigned int version; /* SDHCI spec. version */ 51383f13cc9SUlf Hansson 51483f13cc9SUlf Hansson unsigned int max_clk; /* Max possible freq (MHz) */ 51583f13cc9SUlf Hansson unsigned int timeout_clk; /* Timeout freq (KHz) */ 51683f13cc9SUlf Hansson unsigned int clk_mul; /* Clock Muliplier value */ 51783f13cc9SUlf Hansson 51883f13cc9SUlf Hansson unsigned int clock; /* Current clock (MHz) */ 51983f13cc9SUlf Hansson u8 pwr; /* Current voltage */ 52083f13cc9SUlf Hansson 52183f13cc9SUlf Hansson bool runtime_suspended; /* Host is runtime suspended */ 52283f13cc9SUlf Hansson bool bus_on; /* Bus power prevents runtime suspend */ 52383f13cc9SUlf Hansson bool preset_enabled; /* Preset is enabled */ 524ed1563deSAdrian Hunter bool pending_reset; /* Cmd/data reset is pending */ 52558e79b60SAdrian Hunter bool irq_wake_enabled; /* IRQ wakeup is enabled */ 526b3f80b43SChunyan Zhang bool v4_mode; /* Host Version 4 Enable */ 52783f13cc9SUlf Hansson 5284e9f8fe5SAdrian Hunter struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 52983f13cc9SUlf Hansson struct mmc_command *cmd; /* Current command */ 5307c89a3d9SAdrian Hunter struct mmc_command *data_cmd; /* Current data command */ 53183f13cc9SUlf Hansson struct mmc_data *data; /* Current data request */ 53283f13cc9SUlf Hansson unsigned int data_early:1; /* Data finished before cmd */ 53383f13cc9SUlf Hansson 53483f13cc9SUlf Hansson struct sg_mapping_iter sg_miter; /* SG state for PIO */ 53583f13cc9SUlf Hansson unsigned int blocks; /* remaining PIO blocks */ 53683f13cc9SUlf Hansson 53783f13cc9SUlf Hansson int sg_count; /* Mapped sg entries */ 53883f13cc9SUlf Hansson 53983f13cc9SUlf Hansson void *adma_table; /* ADMA descriptor table */ 54083f13cc9SUlf Hansson void *align_buffer; /* Bounce buffer */ 54183f13cc9SUlf Hansson 54283f13cc9SUlf Hansson size_t adma_table_sz; /* ADMA descriptor table size */ 54383f13cc9SUlf Hansson size_t align_buffer_sz; /* Bounce buffer size */ 54483f13cc9SUlf Hansson 54583f13cc9SUlf Hansson dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 54683f13cc9SUlf Hansson dma_addr_t align_addr; /* Mapped bounce buffer */ 54783f13cc9SUlf Hansson 54883f13cc9SUlf Hansson unsigned int desc_sz; /* ADMA descriptor size */ 54983f13cc9SUlf Hansson 55083f13cc9SUlf Hansson struct tasklet_struct finish_tasklet; /* Tasklet structures */ 55183f13cc9SUlf Hansson 55283f13cc9SUlf Hansson struct timer_list timer; /* Timer for timeouts */ 553d7422fb4SAdrian Hunter struct timer_list data_timer; /* Timer for data timeouts */ 55483f13cc9SUlf Hansson 55528da3589SAdrian Hunter u32 caps; /* CAPABILITY_0 */ 55628da3589SAdrian Hunter u32 caps1; /* CAPABILITY_1 */ 5576132a3bfSAdrian Hunter bool read_caps; /* Capability flags have been read */ 55883f13cc9SUlf Hansson 55983f13cc9SUlf Hansson unsigned int ocr_avail_sdio; /* OCR bit masks */ 56083f13cc9SUlf Hansson unsigned int ocr_avail_sd; 56183f13cc9SUlf Hansson unsigned int ocr_avail_mmc; 56283f13cc9SUlf Hansson u32 ocr_mask; /* available voltages */ 56383f13cc9SUlf Hansson 56483f13cc9SUlf Hansson unsigned timing; /* Current timing */ 56583f13cc9SUlf Hansson 56683f13cc9SUlf Hansson u32 thread_isr; 56783f13cc9SUlf Hansson 56883f13cc9SUlf Hansson /* cached registers */ 56983f13cc9SUlf Hansson u32 ier; 57083f13cc9SUlf Hansson 571f12e39dbSAdrian Hunter bool cqe_on; /* CQE is operating */ 572f12e39dbSAdrian Hunter u32 cqe_ier; /* CQE interrupt mask */ 573f12e39dbSAdrian Hunter u32 cqe_err_ier; /* CQE error interrupt mask */ 574f12e39dbSAdrian Hunter 57583f13cc9SUlf Hansson wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 57683f13cc9SUlf Hansson unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 57783f13cc9SUlf Hansson 57883f13cc9SUlf Hansson unsigned int tuning_count; /* Timer count for re-tuning */ 57983f13cc9SUlf Hansson unsigned int tuning_mode; /* Re-tuning mode supported by host */ 5807d8bb1f4SYinbo Zhu unsigned int tuning_err; /* Error code for re-tuning */ 58183f13cc9SUlf Hansson #define SDHCI_TUNING_MODE_1 0 582f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_2 1 583f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_3 2 58483b600b8SAdrian Hunter /* Delay (ms) between tuning commands */ 58583b600b8SAdrian Hunter int tuning_delay; 58683f13cc9SUlf Hansson 587c846a00fSSrinivas Kandagatla /* Host SDMA buffer boundary. */ 588c846a00fSSrinivas Kandagatla u32 sdma_boundary; 589c846a00fSSrinivas Kandagatla 590e93be38aSJisheng Zhang /* Host ADMA table count */ 591e93be38aSJisheng Zhang u32 adma_table_cnt; 592e93be38aSJisheng Zhang 593fc1fa1b7SKishon Vijay Abraham I u64 data_timeout; 594fc1fa1b7SKishon Vijay Abraham I 59583f13cc9SUlf Hansson unsigned long private[0] ____cacheline_aligned; 59683f13cc9SUlf Hansson }; 59783f13cc9SUlf Hansson 598b8c86fc5SPierre Ossman struct sdhci_ops { 5994e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 600dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 601dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 602dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 603dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 604dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 605dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 6064e4141a5SAnton Vorontsov #endif 6074e4141a5SAnton Vorontsov 6088114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 6091dceb041SAdrian Hunter void (*set_power)(struct sdhci_host *host, unsigned char mode, 6101dceb041SAdrian Hunter unsigned short vdd); 6118114634cSAnton Vorontsov 612f12e39dbSAdrian Hunter u32 (*irq)(struct sdhci_host *host, u32 intmask); 613f12e39dbSAdrian Hunter 614b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 6154240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 616a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 6178cc35289SShawn Lin /* get_timeout_clock should return clk rate in unit of Hz */ 6184240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 619a6ff5aebSAisheng Dong unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 620b45e668aSAisheng Dong void (*set_timeout)(struct sdhci_host *host, 621b45e668aSAisheng Dong struct mmc_command *cmd); 6222317f56cSRussell King void (*set_bus_width)(struct sdhci_host *host, int width); 623643a81ffSPhilip Rakity void (*platform_send_init_74_clocks)(struct sdhci_host *host, 624643a81ffSPhilip Rakity u8 power_mode); 6252dfb579cSWolfram Sang unsigned int (*get_ro)(struct sdhci_host *host); 62603231f9bSRussell King void (*reset)(struct sdhci_host *host, u8 mask); 62745251812SDong Aisheng int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 62813e64501SRussell King void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 62920758b66SAdrian Hunter void (*hw_reset)(struct sdhci_host *host); 630a4071fbbSHaijun Zhang void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 631722e1280SChristian Daudt void (*card_event)(struct sdhci_host *host); 6329d967a61SVincent Yang void (*voltage_switch)(struct sdhci_host *host); 63354552e49SJisheng Zhang void (*adma_write_desc)(struct sdhci_host *host, void **desc, 63454552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd); 6351c6a0718SPierre Ossman }; 636b8c86fc5SPierre Ossman 6374e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 6384e4141a5SAnton Vorontsov 6394e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 6404e4141a5SAnton Vorontsov { 641dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 642dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 6434e4141a5SAnton Vorontsov else 6444e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 6454e4141a5SAnton Vorontsov } 6464e4141a5SAnton Vorontsov 6474e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 6484e4141a5SAnton Vorontsov { 649dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 650dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 6514e4141a5SAnton Vorontsov else 6524e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 6534e4141a5SAnton Vorontsov } 6544e4141a5SAnton Vorontsov 6554e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 6564e4141a5SAnton Vorontsov { 657dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 658dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 6594e4141a5SAnton Vorontsov else 6604e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 6614e4141a5SAnton Vorontsov } 6624e4141a5SAnton Vorontsov 6634e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 6644e4141a5SAnton Vorontsov { 665dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 666dc297c92SMatt Fleming return host->ops->read_l(host, reg); 6674e4141a5SAnton Vorontsov else 6684e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 6694e4141a5SAnton Vorontsov } 6704e4141a5SAnton Vorontsov 6714e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 6724e4141a5SAnton Vorontsov { 673dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 674dc297c92SMatt Fleming return host->ops->read_w(host, reg); 6754e4141a5SAnton Vorontsov else 6764e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 6774e4141a5SAnton Vorontsov } 6784e4141a5SAnton Vorontsov 6794e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 6804e4141a5SAnton Vorontsov { 681dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 682dc297c92SMatt Fleming return host->ops->read_b(host, reg); 6834e4141a5SAnton Vorontsov else 6844e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 6854e4141a5SAnton Vorontsov } 6864e4141a5SAnton Vorontsov 6874e4141a5SAnton Vorontsov #else 6884e4141a5SAnton Vorontsov 6894e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 6904e4141a5SAnton Vorontsov { 6914e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 6924e4141a5SAnton Vorontsov } 6934e4141a5SAnton Vorontsov 6944e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 6954e4141a5SAnton Vorontsov { 6964e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 6974e4141a5SAnton Vorontsov } 6984e4141a5SAnton Vorontsov 6994e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 7004e4141a5SAnton Vorontsov { 7014e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 7024e4141a5SAnton Vorontsov } 7034e4141a5SAnton Vorontsov 7044e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 7054e4141a5SAnton Vorontsov { 7064e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 7074e4141a5SAnton Vorontsov } 7084e4141a5SAnton Vorontsov 7094e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 7104e4141a5SAnton Vorontsov { 7114e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 7124e4141a5SAnton Vorontsov } 7134e4141a5SAnton Vorontsov 7144e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 7154e4141a5SAnton Vorontsov { 7164e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 7174e4141a5SAnton Vorontsov } 7184e4141a5SAnton Vorontsov 7194e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 720b8c86fc5SPierre Ossman 72115becf68SAdrian Hunter struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 72215becf68SAdrian Hunter void sdhci_free_host(struct sdhci_host *host); 723b8c86fc5SPierre Ossman 724b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 725b8c86fc5SPierre Ossman { 726178b0fa0SMasahiro Yamada return host->private; 727b8c86fc5SPierre Ossman } 728b8c86fc5SPierre Ossman 72915becf68SAdrian Hunter void sdhci_card_detect(struct sdhci_host *host); 73015becf68SAdrian Hunter void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, 7316132a3bfSAdrian Hunter u32 *caps1); 73215becf68SAdrian Hunter int sdhci_setup_host(struct sdhci_host *host); 7334180ffa8SAdrian Hunter void sdhci_cleanup_host(struct sdhci_host *host); 73415becf68SAdrian Hunter int __sdhci_add_host(struct sdhci_host *host); 73515becf68SAdrian Hunter int sdhci_add_host(struct sdhci_host *host); 73615becf68SAdrian Hunter void sdhci_remove_host(struct sdhci_host *host, int dead); 73715becf68SAdrian Hunter void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); 738b8c86fc5SPierre Ossman 7396132a3bfSAdrian Hunter static inline void sdhci_read_caps(struct sdhci_host *host) 7406132a3bfSAdrian Hunter { 7416132a3bfSAdrian Hunter __sdhci_read_caps(host, NULL, NULL, NULL); 7426132a3bfSAdrian Hunter } 7436132a3bfSAdrian Hunter 744be138554SRussell King static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 745be138554SRussell King { 746be138554SRussell King return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 747be138554SRussell King } 748be138554SRussell King 749fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 750fb9ee047SLudovic Desroches unsigned int *actual_clock); 7511771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 752fec79673SRitesh Harjani void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 7531dceb041SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 7541dceb041SAdrian Hunter unsigned short vdd); 755606d3131SAdrian Hunter void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 756606d3131SAdrian Hunter unsigned short vdd); 757d462c1b4SAapo Vienamo void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 7582317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width); 75903231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask); 76096d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 76185a882c2SMasahiro Yamada int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 7626a6d4cebSHu Ziji void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 763c376ea9eSHu Ziji int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 764c376ea9eSHu Ziji struct mmc_ios *ios); 7652f05b6abSHu Ziji void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 76654552e49SJisheng Zhang void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 76754552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd); 7682317f56cSRussell King 769b8c86fc5SPierre Ossman #ifdef CONFIG_PM 77015becf68SAdrian Hunter int sdhci_suspend_host(struct sdhci_host *host); 77115becf68SAdrian Hunter int sdhci_resume_host(struct sdhci_host *host); 77215becf68SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host); 77315becf68SAdrian Hunter int sdhci_runtime_resume_host(struct sdhci_host *host); 77466fd8ad5SAdrian Hunter #endif 77566fd8ad5SAdrian Hunter 776f12e39dbSAdrian Hunter void sdhci_cqe_enable(struct mmc_host *mmc); 777f12e39dbSAdrian Hunter void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 778f12e39dbSAdrian Hunter bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 779f12e39dbSAdrian Hunter int *data_error); 780f12e39dbSAdrian Hunter 781d2898172SAdrian Hunter void sdhci_dumpregs(struct sdhci_host *host); 782b3f80b43SChunyan Zhang void sdhci_enable_v4_mode(struct sdhci_host *host); 783d2898172SAdrian Hunter 7846663c419Sernest.zhang void sdhci_start_tuning(struct sdhci_host *host); 7856663c419Sernest.zhang void sdhci_end_tuning(struct sdhci_host *host); 7866663c419Sernest.zhang void sdhci_reset_tuning(struct sdhci_host *host); 7876663c419Sernest.zhang void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 7886663c419Sernest.zhang 7891978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */ 790