xref: /openbmc/linux/drivers/mmc/host/sdhci.h (revision 3794c542)
11c6a0718SPierre Ossman /*
270f10482SPierre Ossman  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
31c6a0718SPierre Ossman  *
41978fda8SGiuseppe Cavallaro  * Header file for Host Controller registers and I/O accessors.
51978fda8SGiuseppe Cavallaro  *
6b69c9058SPierre Ossman  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
71c6a0718SPierre Ossman  *
81c6a0718SPierre Ossman  * This program is free software; you can redistribute it and/or modify
91c6a0718SPierre Ossman  * it under the terms of the GNU General Public License as published by
101c6a0718SPierre Ossman  * the Free Software Foundation; either version 2 of the License, or (at
111c6a0718SPierre Ossman  * your option) any later version.
121c6a0718SPierre Ossman  */
131978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H
141978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H
151c6a0718SPierre Ossman 
160c7ad106SAndrew Morton #include <linux/scatterlist.h>
174e4141a5SAnton Vorontsov #include <linux/compiler.h>
184e4141a5SAnton Vorontsov #include <linux/types.h>
194e4141a5SAnton Vorontsov #include <linux/io.h>
200c7ad106SAndrew Morton 
2183f13cc9SUlf Hansson #include <linux/mmc/host.h>
221978fda8SGiuseppe Cavallaro 
231c6a0718SPierre Ossman /*
241c6a0718SPierre Ossman  * Controller registers
251c6a0718SPierre Ossman  */
261c6a0718SPierre Ossman 
271c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS	0x00
288edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2		SDHCI_DMA_ADDRESS
291c6a0718SPierre Ossman 
301c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE	0x04
311c6a0718SPierre Ossman #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
321c6a0718SPierre Ossman 
331c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT	0x06
341c6a0718SPierre Ossman 
351c6a0718SPierre Ossman #define SDHCI_ARGUMENT		0x08
361c6a0718SPierre Ossman 
371c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE	0x0C
381c6a0718SPierre Ossman #define  SDHCI_TRNS_DMA		0x01
391c6a0718SPierre Ossman #define  SDHCI_TRNS_BLK_CNT_EN	0x02
40e89d456fSAndrei Warkentin #define  SDHCI_TRNS_AUTO_CMD12	0x04
418edf6371SAndrei Warkentin #define  SDHCI_TRNS_AUTO_CMD23	0x08
421c6a0718SPierre Ossman #define  SDHCI_TRNS_READ	0x10
431c6a0718SPierre Ossman #define  SDHCI_TRNS_MULTI	0x20
441c6a0718SPierre Ossman 
451c6a0718SPierre Ossman #define SDHCI_COMMAND		0x0E
461c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_MASK	0x03
471c6a0718SPierre Ossman #define  SDHCI_CMD_CRC		0x08
481c6a0718SPierre Ossman #define  SDHCI_CMD_INDEX	0x10
491c6a0718SPierre Ossman #define  SDHCI_CMD_DATA		0x20
50574e3f56SRichard Zhu #define  SDHCI_CMD_ABORTCMD	0xC0
511c6a0718SPierre Ossman 
521c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_NONE	0x00
531c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_LONG	0x01
541c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_SHORT	0x02
551c6a0718SPierre Ossman #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
561c6a0718SPierre Ossman 
571c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
5822113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
591c6a0718SPierre Ossman 
601c6a0718SPierre Ossman #define SDHCI_RESPONSE		0x10
611c6a0718SPierre Ossman 
621c6a0718SPierre Ossman #define SDHCI_BUFFER		0x20
631c6a0718SPierre Ossman 
641c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE	0x24
651c6a0718SPierre Ossman #define  SDHCI_CMD_INHIBIT	0x00000001
661c6a0718SPierre Ossman #define  SDHCI_DATA_INHIBIT	0x00000002
671c6a0718SPierre Ossman #define  SDHCI_DOING_WRITE	0x00000100
681c6a0718SPierre Ossman #define  SDHCI_DOING_READ	0x00000200
691c6a0718SPierre Ossman #define  SDHCI_SPACE_AVAILABLE	0x00000400
701c6a0718SPierre Ossman #define  SDHCI_DATA_AVAILABLE	0x00000800
711c6a0718SPierre Ossman #define  SDHCI_CARD_PRESENT	0x00010000
721c6a0718SPierre Ossman #define  SDHCI_WRITE_PROTECT	0x00080000
73f2119df6SArindam Nath #define  SDHCI_DATA_LVL_MASK	0x00F00000
74f2119df6SArindam Nath #define   SDHCI_DATA_LVL_SHIFT	20
757756a96dSYi Sun #define   SDHCI_DATA_0_LVL_MASK	0x00100000
761c6a0718SPierre Ossman 
771c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL	0x28
781c6a0718SPierre Ossman #define  SDHCI_CTRL_LED		0x01
791c6a0718SPierre Ossman #define  SDHCI_CTRL_4BITBUS	0x02
801c6a0718SPierre Ossman #define  SDHCI_CTRL_HISPD	0x04
812134a922SPierre Ossman #define  SDHCI_CTRL_DMA_MASK	0x18
822134a922SPierre Ossman #define   SDHCI_CTRL_SDMA	0x00
832134a922SPierre Ossman #define   SDHCI_CTRL_ADMA1	0x08
842134a922SPierre Ossman #define   SDHCI_CTRL_ADMA32	0x10
852134a922SPierre Ossman #define   SDHCI_CTRL_ADMA64	0x18
86ae6d6c92SKyungmin Park #define   SDHCI_CTRL_8BITBUS	0x20
873794c542SZach Brown #define  SDHCI_CTRL_CDTEST_INS	0x40
883794c542SZach Brown #define  SDHCI_CTRL_CDTEST_EN	0x80
891c6a0718SPierre Ossman 
901c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL	0x29
911c6a0718SPierre Ossman #define  SDHCI_POWER_ON		0x01
921c6a0718SPierre Ossman #define  SDHCI_POWER_180	0x0A
931c6a0718SPierre Ossman #define  SDHCI_POWER_300	0x0C
941c6a0718SPierre Ossman #define  SDHCI_POWER_330	0x0E
951c6a0718SPierre Ossman 
961c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL	0x2A
971c6a0718SPierre Ossman 
982df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL	0x2B
995f619704SDaniel Drake #define  SDHCI_WAKE_ON_INT	0x01
1005f619704SDaniel Drake #define  SDHCI_WAKE_ON_INSERT	0x02
1015f619704SDaniel Drake #define  SDHCI_WAKE_ON_REMOVE	0x04
1021c6a0718SPierre Ossman 
1031c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL	0x2C
1041c6a0718SPierre Ossman #define  SDHCI_DIVIDER_SHIFT	8
10585105c53SZhangfei Gao #define  SDHCI_DIVIDER_HI_SHIFT	6
10685105c53SZhangfei Gao #define  SDHCI_DIV_MASK	0xFF
10785105c53SZhangfei Gao #define  SDHCI_DIV_MASK_LEN	8
10885105c53SZhangfei Gao #define  SDHCI_DIV_HI_MASK	0x300
109c3ed3877SArindam Nath #define  SDHCI_PROG_CLOCK_MODE	0x0020
1101c6a0718SPierre Ossman #define  SDHCI_CLOCK_CARD_EN	0x0004
1111c6a0718SPierre Ossman #define  SDHCI_CLOCK_INT_STABLE	0x0002
1121c6a0718SPierre Ossman #define  SDHCI_CLOCK_INT_EN	0x0001
1131c6a0718SPierre Ossman 
1141c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL	0x2E
1151c6a0718SPierre Ossman 
1161c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET	0x2F
1171c6a0718SPierre Ossman #define  SDHCI_RESET_ALL	0x01
1181c6a0718SPierre Ossman #define  SDHCI_RESET_CMD	0x02
1191c6a0718SPierre Ossman #define  SDHCI_RESET_DATA	0x04
1201c6a0718SPierre Ossman 
1211c6a0718SPierre Ossman #define SDHCI_INT_STATUS	0x30
1221c6a0718SPierre Ossman #define SDHCI_INT_ENABLE	0x34
1231c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE	0x38
1241c6a0718SPierre Ossman #define  SDHCI_INT_RESPONSE	0x00000001
1251c6a0718SPierre Ossman #define  SDHCI_INT_DATA_END	0x00000002
126a4071fbbSHaijun Zhang #define  SDHCI_INT_BLK_GAP	0x00000004
1271c6a0718SPierre Ossman #define  SDHCI_INT_DMA_END	0x00000008
1281c6a0718SPierre Ossman #define  SDHCI_INT_SPACE_AVAIL	0x00000010
1291c6a0718SPierre Ossman #define  SDHCI_INT_DATA_AVAIL	0x00000020
1301c6a0718SPierre Ossman #define  SDHCI_INT_CARD_INSERT	0x00000040
1311c6a0718SPierre Ossman #define  SDHCI_INT_CARD_REMOVE	0x00000080
1321c6a0718SPierre Ossman #define  SDHCI_INT_CARD_INT	0x00000100
133f37b20ebSDong Aisheng #define  SDHCI_INT_RETUNE	0x00001000
134964f9ce2SPierre Ossman #define  SDHCI_INT_ERROR	0x00008000
1351c6a0718SPierre Ossman #define  SDHCI_INT_TIMEOUT	0x00010000
1361c6a0718SPierre Ossman #define  SDHCI_INT_CRC		0x00020000
1371c6a0718SPierre Ossman #define  SDHCI_INT_END_BIT	0x00040000
1381c6a0718SPierre Ossman #define  SDHCI_INT_INDEX	0x00080000
1391c6a0718SPierre Ossman #define  SDHCI_INT_DATA_TIMEOUT	0x00100000
1401c6a0718SPierre Ossman #define  SDHCI_INT_DATA_CRC	0x00200000
1411c6a0718SPierre Ossman #define  SDHCI_INT_DATA_END_BIT	0x00400000
1421c6a0718SPierre Ossman #define  SDHCI_INT_BUS_POWER	0x00800000
1431c6a0718SPierre Ossman #define  SDHCI_INT_ACMD12ERR	0x01000000
1442134a922SPierre Ossman #define  SDHCI_INT_ADMA_ERROR	0x02000000
1451c6a0718SPierre Ossman 
1461c6a0718SPierre Ossman #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
1471c6a0718SPierre Ossman #define  SDHCI_INT_ERROR_MASK	0xFFFF8000
1481c6a0718SPierre Ossman 
1491c6a0718SPierre Ossman #define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
1501c6a0718SPierre Ossman 		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
1511c6a0718SPierre Ossman #define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
1521c6a0718SPierre Ossman 		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
1531c6a0718SPierre Ossman 		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
154a4071fbbSHaijun Zhang 		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
155a4071fbbSHaijun Zhang 		SDHCI_INT_BLK_GAP)
1567260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
1571c6a0718SPierre Ossman 
1581c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR	0x3C
1591c6a0718SPierre Ossman 
160f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2		0x3E
16149c468fcSArindam Nath #define  SDHCI_CTRL_UHS_MASK		0x0007
16249c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR12		0x0000
16349c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR25		0x0001
16449c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR50		0x0002
16549c468fcSArindam Nath #define   SDHCI_CTRL_UHS_SDR104		0x0003
16649c468fcSArindam Nath #define   SDHCI_CTRL_UHS_DDR50		0x0004
167e9fb05d5SAdrian Hunter #define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
168f2119df6SArindam Nath #define  SDHCI_CTRL_VDD_180		0x0008
169d6d50a15SArindam Nath #define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
170d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_B		0x0000
171d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_A		0x0010
172d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_C		0x0020
173d6d50a15SArindam Nath #define   SDHCI_CTRL_DRV_TYPE_D		0x0030
174b513ea25SArindam Nath #define  SDHCI_CTRL_EXEC_TUNING		0x0040
175b513ea25SArindam Nath #define  SDHCI_CTRL_TUNED_CLK		0x0080
176d6d50a15SArindam Nath #define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000
1771c6a0718SPierre Ossman 
1781c6a0718SPierre Ossman #define SDHCI_CAPABILITIES	0x40
1791c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
1801c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_SHIFT 0
1811c6a0718SPierre Ossman #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
1821c6a0718SPierre Ossman #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
183c4687d5fSZhangfei Gao #define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
1841c6a0718SPierre Ossman #define  SDHCI_CLOCK_BASE_SHIFT	8
1851c6a0718SPierre Ossman #define  SDHCI_MAX_BLOCK_MASK	0x00030000
1861c6a0718SPierre Ossman #define  SDHCI_MAX_BLOCK_SHIFT  16
18715ec4461SPhilip Rakity #define  SDHCI_CAN_DO_8BIT	0x00040000
1882134a922SPierre Ossman #define  SDHCI_CAN_DO_ADMA2	0x00080000
1892134a922SPierre Ossman #define  SDHCI_CAN_DO_ADMA1	0x00100000
1901c6a0718SPierre Ossman #define  SDHCI_CAN_DO_HISPD	0x00200000
191a13abc7bSRichard Röjfors #define  SDHCI_CAN_DO_SDMA	0x00400000
192e71d4b81SStefan Wahren #define  SDHCI_CAN_DO_SUSPEND	0x00800000
1931c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_330	0x01000000
1941c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_300	0x02000000
1951c6a0718SPierre Ossman #define  SDHCI_CAN_VDD_180	0x04000000
1962134a922SPierre Ossman #define  SDHCI_CAN_64BIT	0x10000000
1971c6a0718SPierre Ossman 
198f2119df6SArindam Nath #define  SDHCI_SUPPORT_SDR50	0x00000001
199f2119df6SArindam Nath #define  SDHCI_SUPPORT_SDR104	0x00000002
200f2119df6SArindam Nath #define  SDHCI_SUPPORT_DDR50	0x00000004
201d6d50a15SArindam Nath #define  SDHCI_DRIVER_TYPE_A	0x00000010
202d6d50a15SArindam Nath #define  SDHCI_DRIVER_TYPE_C	0x00000020
203d6d50a15SArindam Nath #define  SDHCI_DRIVER_TYPE_D	0x00000040
204cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_TIMER_COUNT_MASK	0x00000F00
205cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT	8
206b513ea25SArindam Nath #define  SDHCI_USE_SDR50_TUNING			0x00002000
207cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_MODE_MASK		0x0000C000
208cf2b5eeaSArindam Nath #define  SDHCI_RETUNING_MODE_SHIFT		14
209c3ed3877SArindam Nath #define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
210c3ed3877SArindam Nath #define  SDHCI_CLOCK_MUL_SHIFT	16
211e9fb05d5SAdrian Hunter #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
212f2119df6SArindam Nath 
213e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1	0x44
2141c6a0718SPierre Ossman 
2151c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT		0x48
216bad37e1aSPhilip Rakity #define  SDHCI_MAX_CURRENT_LIMIT	0xFF
217f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_330_MASK	0x0000FF
218f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_330_SHIFT	0
219f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_300_MASK	0x00FF00
220f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_300_SHIFT	8
221f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_180_MASK	0xFF0000
222f2119df6SArindam Nath #define  SDHCI_MAX_CURRENT_180_SHIFT	16
223f2119df6SArindam Nath #define   SDHCI_MAX_CURRENT_MULTIPLIER	4
2241c6a0718SPierre Ossman 
2251c6a0718SPierre Ossman /* 4C-4F reserved for more max current */
2261c6a0718SPierre Ossman 
2272134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR	0x50
2282134a922SPierre Ossman #define SDHCI_SET_INT_ERROR	0x52
2292134a922SPierre Ossman 
2302134a922SPierre Ossman #define SDHCI_ADMA_ERROR	0x54
2312134a922SPierre Ossman 
2322134a922SPierre Ossman /* 55-57 reserved */
2332134a922SPierre Ossman 
2342134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS	0x58
235e57a5f61SAdrian Hunter #define SDHCI_ADMA_ADDRESS_HI	0x5C
2362134a922SPierre Ossman 
2372134a922SPierre Ossman /* 60-FB reserved */
2381c6a0718SPierre Ossman 
23952983382SKevin Liu #define SDHCI_PRESET_FOR_SDR12 0x66
24052983382SKevin Liu #define SDHCI_PRESET_FOR_SDR25 0x68
24152983382SKevin Liu #define SDHCI_PRESET_FOR_SDR50 0x6A
24252983382SKevin Liu #define SDHCI_PRESET_FOR_SDR104        0x6C
24352983382SKevin Liu #define SDHCI_PRESET_FOR_DDR50 0x6E
244e9fb05d5SAdrian Hunter #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
24552983382SKevin Liu #define SDHCI_PRESET_DRV_MASK  0xC000
24652983382SKevin Liu #define SDHCI_PRESET_DRV_SHIFT  14
24752983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
24852983382SKevin Liu #define SDHCI_PRESET_CLKGEN_SEL_SHIFT	10
24952983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
25052983382SKevin Liu #define SDHCI_PRESET_SDCLK_FREQ_SHIFT	0
25152983382SKevin Liu 
2521c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS	0xFC
2531c6a0718SPierre Ossman 
2541c6a0718SPierre Ossman #define SDHCI_HOST_VERSION	0xFE
2551c6a0718SPierre Ossman #define  SDHCI_VENDOR_VER_MASK	0xFF00
2561c6a0718SPierre Ossman #define  SDHCI_VENDOR_VER_SHIFT	8
2571c6a0718SPierre Ossman #define  SDHCI_SPEC_VER_MASK	0x00FF
2581c6a0718SPierre Ossman #define  SDHCI_SPEC_VER_SHIFT	0
2592134a922SPierre Ossman #define   SDHCI_SPEC_100	0
2602134a922SPierre Ossman #define   SDHCI_SPEC_200	1
26185105c53SZhangfei Gao #define   SDHCI_SPEC_300	2
2621c6a0718SPierre Ossman 
2630397526dSZhangfei Gao /*
2640397526dSZhangfei Gao  * End of controller registers.
2650397526dSZhangfei Gao  */
2660397526dSZhangfei Gao 
2670397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200	256
2680397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300	2046
2690397526dSZhangfei Gao 
270f6a03cbfSMikko Vinni /*
271f6a03cbfSMikko Vinni  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
272f6a03cbfSMikko Vinni  */
273f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
274f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
275f6a03cbfSMikko Vinni 
276739d46dcSAdrian Hunter /* ADMA2 32-bit DMA descriptor size */
277739d46dcSAdrian Hunter #define SDHCI_ADMA2_32_DESC_SZ	8
278739d46dcSAdrian Hunter 
2790545230fSAdrian Hunter /* ADMA2 32-bit descriptor */
2800545230fSAdrian Hunter struct sdhci_adma2_32_desc {
2810545230fSAdrian Hunter 	__le16	cmd;
2820545230fSAdrian Hunter 	__le16	len;
2830545230fSAdrian Hunter 	__le32	addr;
28404a5ae6fSAdrian Hunter }  __packed __aligned(4);
28504a5ae6fSAdrian Hunter 
28604a5ae6fSAdrian Hunter /* ADMA2 data alignment */
28704a5ae6fSAdrian Hunter #define SDHCI_ADMA2_ALIGN	4
28804a5ae6fSAdrian Hunter #define SDHCI_ADMA2_MASK	(SDHCI_ADMA2_ALIGN - 1)
28904a5ae6fSAdrian Hunter 
29004a5ae6fSAdrian Hunter /*
29104a5ae6fSAdrian Hunter  * ADMA2 descriptor alignment.  Some controllers (e.g. Intel) require 8 byte
29204a5ae6fSAdrian Hunter  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
29304a5ae6fSAdrian Hunter  * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
29404a5ae6fSAdrian Hunter  */
29504a5ae6fSAdrian Hunter #define SDHCI_ADMA2_DESC_ALIGN	8
2960545230fSAdrian Hunter 
297e57a5f61SAdrian Hunter /* ADMA2 64-bit DMA descriptor size */
298e57a5f61SAdrian Hunter #define SDHCI_ADMA2_64_DESC_SZ	12
299e57a5f61SAdrian Hunter 
300e57a5f61SAdrian Hunter /*
301e57a5f61SAdrian Hunter  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
302e57a5f61SAdrian Hunter  * aligned.
303e57a5f61SAdrian Hunter  */
304e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc {
305e57a5f61SAdrian Hunter 	__le16	cmd;
306e57a5f61SAdrian Hunter 	__le16	len;
307e57a5f61SAdrian Hunter 	__le32	addr_lo;
308e57a5f61SAdrian Hunter 	__le32	addr_hi;
309e57a5f61SAdrian Hunter }  __packed __aligned(4);
310e57a5f61SAdrian Hunter 
311739d46dcSAdrian Hunter #define ADMA2_TRAN_VALID	0x21
312739d46dcSAdrian Hunter #define ADMA2_NOP_END_VALID	0x3
313739d46dcSAdrian Hunter #define ADMA2_END		0x2
314739d46dcSAdrian Hunter 
3154fb213f8SAdrian Hunter /*
3164fb213f8SAdrian Hunter  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
3174fb213f8SAdrian Hunter  * 4KiB page size.
3184fb213f8SAdrian Hunter  */
3194fb213f8SAdrian Hunter #define SDHCI_MAX_SEGS		128
3204fb213f8SAdrian Hunter 
3214e9f8fe5SAdrian Hunter /* Allow for a a command request and a data request at the same time */
3224e9f8fe5SAdrian Hunter #define SDHCI_MAX_MRQS		2
3234e9f8fe5SAdrian Hunter 
324d31911b9SHaibo Chen enum sdhci_cookie {
325d31911b9SHaibo Chen 	COOKIE_UNMAPPED,
32694538e51SRussell King 	COOKIE_PRE_MAPPED,	/* mapped by sdhci_pre_req() */
32794538e51SRussell King 	COOKIE_MAPPED,		/* mapped by sdhci_prepare_data() */
32883f13cc9SUlf Hansson };
32983f13cc9SUlf Hansson 
33083f13cc9SUlf Hansson struct sdhci_host {
33183f13cc9SUlf Hansson 	/* Data set by hardware interface driver */
33283f13cc9SUlf Hansson 	const char *hw_name;	/* Hardware bus name */
33383f13cc9SUlf Hansson 
33483f13cc9SUlf Hansson 	unsigned int quirks;	/* Deviations from spec. */
33583f13cc9SUlf Hansson 
33683f13cc9SUlf Hansson /* Controller doesn't honor resets unless we touch the clock register */
33783f13cc9SUlf Hansson #define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
33883f13cc9SUlf Hansson /* Controller has bad caps bits, but really supports DMA */
33983f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_DMA				(1<<1)
34083f13cc9SUlf Hansson /* Controller doesn't like to be reset when there is no card inserted. */
34183f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
34283f13cc9SUlf Hansson /* Controller doesn't like clearing the power reg before a change */
34383f13cc9SUlf Hansson #define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
34483f13cc9SUlf Hansson /* Controller has flaky internal state so reset it on each ios change */
34583f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
34683f13cc9SUlf Hansson /* Controller has an unusable DMA engine */
34783f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
34883f13cc9SUlf Hansson /* Controller has an unusable ADMA engine */
34983f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA				(1<<6)
35083f13cc9SUlf Hansson /* Controller can only DMA from 32-bit aligned addresses */
35183f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<7)
35283f13cc9SUlf Hansson /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
35383f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<8)
35483f13cc9SUlf Hansson /* Controller can only ADMA chunks that are a multiple of 32 bits */
35583f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_ADMA_SIZE			(1<<9)
35683f13cc9SUlf Hansson /* Controller needs to be reset after each request to stay stable */
35783f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<10)
35883f13cc9SUlf Hansson /* Controller needs voltage and power writes to happen separately */
35983f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<11)
36083f13cc9SUlf Hansson /* Controller provides an incorrect timeout value for transfers */
36183f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1<<12)
36283f13cc9SUlf Hansson /* Controller has an issue with buffer bits for small transfers */
36383f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_SMALL_PIO			(1<<13)
36483f13cc9SUlf Hansson /* Controller does not provide transfer-complete interrupt when not busy */
36583f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_BUSY_IRQ				(1<<14)
36683f13cc9SUlf Hansson /* Controller has unreliable card detection */
36783f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_CARD_DETECTION		(1<<15)
36883f13cc9SUlf Hansson /* Controller reports inverted write-protect state */
36983f13cc9SUlf Hansson #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT		(1<<16)
37083f13cc9SUlf Hansson /* Controller does not like fast PIO transfers */
37183f13cc9SUlf Hansson #define SDHCI_QUIRK_PIO_NEEDS_DELAY			(1<<18)
37283f13cc9SUlf Hansson /* Controller has to be forced to use block size of 2048 bytes */
37383f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_BLK_SZ_2048			(1<<20)
37483f13cc9SUlf Hansson /* Controller cannot do multi-block transfers */
37583f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_MULTIBLOCK			(1<<21)
37683f13cc9SUlf Hansson /* Controller can only handle 1-bit data transfers */
37783f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_1_BIT_DATA			(1<<22)
37883f13cc9SUlf Hansson /* Controller needs 10ms delay between applying power and clock */
37983f13cc9SUlf Hansson #define SDHCI_QUIRK_DELAY_AFTER_POWER			(1<<23)
38083f13cc9SUlf Hansson /* Controller uses SDCLK instead of TMCLK for data timeouts */
38183f13cc9SUlf Hansson #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK		(1<<24)
38283f13cc9SUlf Hansson /* Controller reports wrong base clock capability */
38383f13cc9SUlf Hansson #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
38483f13cc9SUlf Hansson /* Controller cannot support End Attribute in NOP ADMA descriptor */
38583f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
38683f13cc9SUlf Hansson /* Controller is missing device caps. Use caps provided by host */
38783f13cc9SUlf Hansson #define SDHCI_QUIRK_MISSING_CAPS			(1<<27)
38883f13cc9SUlf Hansson /* Controller uses Auto CMD12 command to stop the transfer */
38983f13cc9SUlf Hansson #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12		(1<<28)
39083f13cc9SUlf Hansson /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
39183f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_HISPD_BIT			(1<<29)
39283f13cc9SUlf Hansson /* Controller treats ADMA descriptors with length 0000h incorrectly */
39383f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC		(1<<30)
39483f13cc9SUlf Hansson /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
39583f13cc9SUlf Hansson #define SDHCI_QUIRK_UNSTABLE_RO_DETECT			(1<<31)
39683f13cc9SUlf Hansson 
39783f13cc9SUlf Hansson 	unsigned int quirks2;	/* More deviations from spec. */
39883f13cc9SUlf Hansson 
39983f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_OFF_CARD_ON			(1<<0)
40083f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_NO_CMD23			(1<<1)
40183f13cc9SUlf Hansson /* The system physically doesn't support 1.8v, even if the host does */
40283f13cc9SUlf Hansson #define SDHCI_QUIRK2_NO_1_8_V				(1<<2)
40383f13cc9SUlf Hansson #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN		(1<<3)
40483f13cc9SUlf Hansson #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON		(1<<4)
40583f13cc9SUlf Hansson /* Controller has a non-standard host control register */
40683f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL		(1<<5)
40783f13cc9SUlf Hansson /* Controller does not support HS200 */
40883f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HS200			(1<<6)
40983f13cc9SUlf Hansson /* Controller does not support DDR50 */
41083f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
41183f13cc9SUlf Hansson /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
41283f13cc9SUlf Hansson #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
41383f13cc9SUlf Hansson /* Controller does not support 64-bit DMA */
41483f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA			(1<<9)
41583f13cc9SUlf Hansson /* need clear transfer mode register before send cmd */
41683f13cc9SUlf Hansson #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
41783f13cc9SUlf Hansson /* Capability register bit-63 indicates HS400 support */
41883f13cc9SUlf Hansson #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<11)
41983f13cc9SUlf Hansson /* forced tuned clock */
42083f13cc9SUlf Hansson #define SDHCI_QUIRK2_TUNING_WORK_AROUND			(1<<12)
42183f13cc9SUlf Hansson /* disable the block count for single block transactions */
42283f13cc9SUlf Hansson #define SDHCI_QUIRK2_SUPPORT_SINGLE			(1<<13)
42383f13cc9SUlf Hansson /* Controller broken with using ACMD23 */
42483f13cc9SUlf Hansson #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
425d1955c3aSSuneel Garapati /* Broken Clock divider zero in controller */
426d1955c3aSSuneel Garapati #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
42783f13cc9SUlf Hansson 
42883f13cc9SUlf Hansson 	int irq;		/* Device IRQ */
42983f13cc9SUlf Hansson 	void __iomem *ioaddr;	/* Mapped address */
43083f13cc9SUlf Hansson 
43183f13cc9SUlf Hansson 	const struct sdhci_ops *ops;	/* Low level hw interface */
43283f13cc9SUlf Hansson 
43383f13cc9SUlf Hansson 	/* Internal data */
43483f13cc9SUlf Hansson 	struct mmc_host *mmc;	/* MMC structure */
435bf60e592SAdrian Hunter 	struct mmc_host_ops mmc_host_ops;	/* MMC host ops */
43683f13cc9SUlf Hansson 	u64 dma_mask;		/* custom DMA mask */
43783f13cc9SUlf Hansson 
43874479c5dSMasahiro Yamada #if IS_ENABLED(CONFIG_LEDS_CLASS)
43983f13cc9SUlf Hansson 	struct led_classdev led;	/* LED control */
44083f13cc9SUlf Hansson 	char led_name[32];
44183f13cc9SUlf Hansson #endif
44283f13cc9SUlf Hansson 
44383f13cc9SUlf Hansson 	spinlock_t lock;	/* Mutex */
44483f13cc9SUlf Hansson 
44583f13cc9SUlf Hansson 	int flags;		/* Host attributes */
44683f13cc9SUlf Hansson #define SDHCI_USE_SDMA		(1<<0)	/* Host is SDMA capable */
44783f13cc9SUlf Hansson #define SDHCI_USE_ADMA		(1<<1)	/* Host is ADMA capable */
44883f13cc9SUlf Hansson #define SDHCI_REQ_USE_DMA	(1<<2)	/* Use DMA for this req. */
44983f13cc9SUlf Hansson #define SDHCI_DEVICE_DEAD	(1<<3)	/* Device unresponsive */
45083f13cc9SUlf Hansson #define SDHCI_SDR50_NEEDS_TUNING (1<<4)	/* SDR50 needs tuning */
45183f13cc9SUlf Hansson #define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
45283f13cc9SUlf Hansson #define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
45383f13cc9SUlf Hansson #define SDHCI_PV_ENABLED	(1<<8)	/* Preset value enabled */
45483f13cc9SUlf Hansson #define SDHCI_SDIO_IRQ_ENABLED	(1<<9)	/* SDIO irq enabled */
45583f13cc9SUlf Hansson #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
45683f13cc9SUlf Hansson #define SDHCI_HS400_TUNING	(1<<13)	/* Tuning for HS400 */
4578cb851a4SAdrian Hunter #define SDHCI_SIGNALING_330	(1<<14)	/* Host is capable of 3.3V signaling */
4588cb851a4SAdrian Hunter #define SDHCI_SIGNALING_180	(1<<15)	/* Host is capable of 1.8V signaling */
4598cb851a4SAdrian Hunter #define SDHCI_SIGNALING_120	(1<<16)	/* Host is capable of 1.2V signaling */
46083f13cc9SUlf Hansson 
46183f13cc9SUlf Hansson 	unsigned int version;	/* SDHCI spec. version */
46283f13cc9SUlf Hansson 
46383f13cc9SUlf Hansson 	unsigned int max_clk;	/* Max possible freq (MHz) */
46483f13cc9SUlf Hansson 	unsigned int timeout_clk;	/* Timeout freq (KHz) */
46583f13cc9SUlf Hansson 	unsigned int clk_mul;	/* Clock Muliplier value */
46683f13cc9SUlf Hansson 
46783f13cc9SUlf Hansson 	unsigned int clock;	/* Current clock (MHz) */
46883f13cc9SUlf Hansson 	u8 pwr;			/* Current voltage */
46983f13cc9SUlf Hansson 
47083f13cc9SUlf Hansson 	bool runtime_suspended;	/* Host is runtime suspended */
47183f13cc9SUlf Hansson 	bool bus_on;		/* Bus power prevents runtime suspend */
47283f13cc9SUlf Hansson 	bool preset_enabled;	/* Preset is enabled */
473ed1563deSAdrian Hunter 	bool pending_reset;	/* Cmd/data reset is pending */
47483f13cc9SUlf Hansson 
4754e9f8fe5SAdrian Hunter 	struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];	/* Requests done */
47683f13cc9SUlf Hansson 	struct mmc_command *cmd;	/* Current command */
4777c89a3d9SAdrian Hunter 	struct mmc_command *data_cmd;	/* Current data command */
47883f13cc9SUlf Hansson 	struct mmc_data *data;	/* Current data request */
47983f13cc9SUlf Hansson 	unsigned int data_early:1;	/* Data finished before cmd */
48083f13cc9SUlf Hansson 
48183f13cc9SUlf Hansson 	struct sg_mapping_iter sg_miter;	/* SG state for PIO */
48283f13cc9SUlf Hansson 	unsigned int blocks;	/* remaining PIO blocks */
48383f13cc9SUlf Hansson 
48483f13cc9SUlf Hansson 	int sg_count;		/* Mapped sg entries */
48583f13cc9SUlf Hansson 
48683f13cc9SUlf Hansson 	void *adma_table;	/* ADMA descriptor table */
48783f13cc9SUlf Hansson 	void *align_buffer;	/* Bounce buffer */
48883f13cc9SUlf Hansson 
48983f13cc9SUlf Hansson 	size_t adma_table_sz;	/* ADMA descriptor table size */
49083f13cc9SUlf Hansson 	size_t align_buffer_sz;	/* Bounce buffer size */
49183f13cc9SUlf Hansson 
49283f13cc9SUlf Hansson 	dma_addr_t adma_addr;	/* Mapped ADMA descr. table */
49383f13cc9SUlf Hansson 	dma_addr_t align_addr;	/* Mapped bounce buffer */
49483f13cc9SUlf Hansson 
49583f13cc9SUlf Hansson 	unsigned int desc_sz;	/* ADMA descriptor size */
49683f13cc9SUlf Hansson 
49783f13cc9SUlf Hansson 	struct tasklet_struct finish_tasklet;	/* Tasklet structures */
49883f13cc9SUlf Hansson 
49983f13cc9SUlf Hansson 	struct timer_list timer;	/* Timer for timeouts */
500d7422fb4SAdrian Hunter 	struct timer_list data_timer;	/* Timer for data timeouts */
50183f13cc9SUlf Hansson 
50228da3589SAdrian Hunter 	u32 caps;		/* CAPABILITY_0 */
50328da3589SAdrian Hunter 	u32 caps1;		/* CAPABILITY_1 */
5046132a3bfSAdrian Hunter 	bool read_caps;		/* Capability flags have been read */
50583f13cc9SUlf Hansson 
50683f13cc9SUlf Hansson 	unsigned int            ocr_avail_sdio;	/* OCR bit masks */
50783f13cc9SUlf Hansson 	unsigned int            ocr_avail_sd;
50883f13cc9SUlf Hansson 	unsigned int            ocr_avail_mmc;
50983f13cc9SUlf Hansson 	u32 ocr_mask;		/* available voltages */
51083f13cc9SUlf Hansson 
51183f13cc9SUlf Hansson 	unsigned		timing;		/* Current timing */
51283f13cc9SUlf Hansson 
51383f13cc9SUlf Hansson 	u32			thread_isr;
51483f13cc9SUlf Hansson 
51583f13cc9SUlf Hansson 	/* cached registers */
51683f13cc9SUlf Hansson 	u32			ier;
51783f13cc9SUlf Hansson 
51883f13cc9SUlf Hansson 	wait_queue_head_t	buf_ready_int;	/* Waitqueue for Buffer Read Ready interrupt */
51983f13cc9SUlf Hansson 	unsigned int		tuning_done;	/* Condition flag set when CMD19 succeeds */
52083f13cc9SUlf Hansson 
52183f13cc9SUlf Hansson 	unsigned int		tuning_count;	/* Timer count for re-tuning */
52283f13cc9SUlf Hansson 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
52383f13cc9SUlf Hansson #define SDHCI_TUNING_MODE_1	0
524f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_2	1
525f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_3	2
52683f13cc9SUlf Hansson 
52783f13cc9SUlf Hansson 	unsigned long private[0] ____cacheline_aligned;
52883f13cc9SUlf Hansson };
52983f13cc9SUlf Hansson 
530b8c86fc5SPierre Ossman struct sdhci_ops {
5314e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
532dc297c92SMatt Fleming 	u32		(*read_l)(struct sdhci_host *host, int reg);
533dc297c92SMatt Fleming 	u16		(*read_w)(struct sdhci_host *host, int reg);
534dc297c92SMatt Fleming 	u8		(*read_b)(struct sdhci_host *host, int reg);
535dc297c92SMatt Fleming 	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
536dc297c92SMatt Fleming 	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
537dc297c92SMatt Fleming 	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
5384e4141a5SAnton Vorontsov #endif
5394e4141a5SAnton Vorontsov 
5408114634cSAnton Vorontsov 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);
5411dceb041SAdrian Hunter 	void	(*set_power)(struct sdhci_host *host, unsigned char mode,
5421dceb041SAdrian Hunter 			     unsigned short vdd);
5438114634cSAnton Vorontsov 
544b8c86fc5SPierre Ossman 	int		(*enable_dma)(struct sdhci_host *host);
5454240ff0aSBen Dooks 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
546a9e58f25SAnton Vorontsov 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
5474240ff0aSBen Dooks 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
548a6ff5aebSAisheng Dong 	unsigned int	(*get_max_timeout_count)(struct sdhci_host *host);
549b45e668aSAisheng Dong 	void		(*set_timeout)(struct sdhci_host *host,
550b45e668aSAisheng Dong 				       struct mmc_command *cmd);
5512317f56cSRussell King 	void		(*set_bus_width)(struct sdhci_host *host, int width);
552643a81ffSPhilip Rakity 	void (*platform_send_init_74_clocks)(struct sdhci_host *host,
553643a81ffSPhilip Rakity 					     u8 power_mode);
5542dfb579cSWolfram Sang 	unsigned int    (*get_ro)(struct sdhci_host *host);
55503231f9bSRussell King 	void		(*reset)(struct sdhci_host *host, u8 mask);
55645251812SDong Aisheng 	int	(*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
55713e64501SRussell King 	void	(*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
55820758b66SAdrian Hunter 	void	(*hw_reset)(struct sdhci_host *host);
559a4071fbbSHaijun Zhang 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
560722e1280SChristian Daudt 	void    (*card_event)(struct sdhci_host *host);
5619d967a61SVincent Yang 	void	(*voltage_switch)(struct sdhci_host *host);
562cb849648SAdrian Hunter 	int	(*select_drive_strength)(struct sdhci_host *host,
563cb849648SAdrian Hunter 					 struct mmc_card *card,
564cb849648SAdrian Hunter 					 unsigned int max_dtr, int host_drv,
565cb849648SAdrian Hunter 					 int card_drv, int *drv_type);
5661c6a0718SPierre Ossman };
567b8c86fc5SPierre Ossman 
5684e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
5694e4141a5SAnton Vorontsov 
5704e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
5714e4141a5SAnton Vorontsov {
572dc297c92SMatt Fleming 	if (unlikely(host->ops->write_l))
573dc297c92SMatt Fleming 		host->ops->write_l(host, val, reg);
5744e4141a5SAnton Vorontsov 	else
5754e4141a5SAnton Vorontsov 		writel(val, host->ioaddr + reg);
5764e4141a5SAnton Vorontsov }
5774e4141a5SAnton Vorontsov 
5784e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
5794e4141a5SAnton Vorontsov {
580dc297c92SMatt Fleming 	if (unlikely(host->ops->write_w))
581dc297c92SMatt Fleming 		host->ops->write_w(host, val, reg);
5824e4141a5SAnton Vorontsov 	else
5834e4141a5SAnton Vorontsov 		writew(val, host->ioaddr + reg);
5844e4141a5SAnton Vorontsov }
5854e4141a5SAnton Vorontsov 
5864e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
5874e4141a5SAnton Vorontsov {
588dc297c92SMatt Fleming 	if (unlikely(host->ops->write_b))
589dc297c92SMatt Fleming 		host->ops->write_b(host, val, reg);
5904e4141a5SAnton Vorontsov 	else
5914e4141a5SAnton Vorontsov 		writeb(val, host->ioaddr + reg);
5924e4141a5SAnton Vorontsov }
5934e4141a5SAnton Vorontsov 
5944e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
5954e4141a5SAnton Vorontsov {
596dc297c92SMatt Fleming 	if (unlikely(host->ops->read_l))
597dc297c92SMatt Fleming 		return host->ops->read_l(host, reg);
5984e4141a5SAnton Vorontsov 	else
5994e4141a5SAnton Vorontsov 		return readl(host->ioaddr + reg);
6004e4141a5SAnton Vorontsov }
6014e4141a5SAnton Vorontsov 
6024e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
6034e4141a5SAnton Vorontsov {
604dc297c92SMatt Fleming 	if (unlikely(host->ops->read_w))
605dc297c92SMatt Fleming 		return host->ops->read_w(host, reg);
6064e4141a5SAnton Vorontsov 	else
6074e4141a5SAnton Vorontsov 		return readw(host->ioaddr + reg);
6084e4141a5SAnton Vorontsov }
6094e4141a5SAnton Vorontsov 
6104e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
6114e4141a5SAnton Vorontsov {
612dc297c92SMatt Fleming 	if (unlikely(host->ops->read_b))
613dc297c92SMatt Fleming 		return host->ops->read_b(host, reg);
6144e4141a5SAnton Vorontsov 	else
6154e4141a5SAnton Vorontsov 		return readb(host->ioaddr + reg);
6164e4141a5SAnton Vorontsov }
6174e4141a5SAnton Vorontsov 
6184e4141a5SAnton Vorontsov #else
6194e4141a5SAnton Vorontsov 
6204e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
6214e4141a5SAnton Vorontsov {
6224e4141a5SAnton Vorontsov 	writel(val, host->ioaddr + reg);
6234e4141a5SAnton Vorontsov }
6244e4141a5SAnton Vorontsov 
6254e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
6264e4141a5SAnton Vorontsov {
6274e4141a5SAnton Vorontsov 	writew(val, host->ioaddr + reg);
6284e4141a5SAnton Vorontsov }
6294e4141a5SAnton Vorontsov 
6304e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
6314e4141a5SAnton Vorontsov {
6324e4141a5SAnton Vorontsov 	writeb(val, host->ioaddr + reg);
6334e4141a5SAnton Vorontsov }
6344e4141a5SAnton Vorontsov 
6354e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
6364e4141a5SAnton Vorontsov {
6374e4141a5SAnton Vorontsov 	return readl(host->ioaddr + reg);
6384e4141a5SAnton Vorontsov }
6394e4141a5SAnton Vorontsov 
6404e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
6414e4141a5SAnton Vorontsov {
6424e4141a5SAnton Vorontsov 	return readw(host->ioaddr + reg);
6434e4141a5SAnton Vorontsov }
6444e4141a5SAnton Vorontsov 
6454e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
6464e4141a5SAnton Vorontsov {
6474e4141a5SAnton Vorontsov 	return readb(host->ioaddr + reg);
6484e4141a5SAnton Vorontsov }
6494e4141a5SAnton Vorontsov 
6504e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
651b8c86fc5SPierre Ossman 
652b8c86fc5SPierre Ossman extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
653b8c86fc5SPierre Ossman 	size_t priv_size);
654b8c86fc5SPierre Ossman extern void sdhci_free_host(struct sdhci_host *host);
655b8c86fc5SPierre Ossman 
656b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host)
657b8c86fc5SPierre Ossman {
658b8c86fc5SPierre Ossman 	return (void *)host->private;
659b8c86fc5SPierre Ossman }
660b8c86fc5SPierre Ossman 
66117866e14SMarek Szyprowski extern void sdhci_card_detect(struct sdhci_host *host);
6626132a3bfSAdrian Hunter extern void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
6636132a3bfSAdrian Hunter 			      u32 *caps1);
66452f5336dSAdrian Hunter extern int sdhci_setup_host(struct sdhci_host *host);
66552f5336dSAdrian Hunter extern int __sdhci_add_host(struct sdhci_host *host);
666b8c86fc5SPierre Ossman extern int sdhci_add_host(struct sdhci_host *host);
6671e72859eSPierre Ossman extern void sdhci_remove_host(struct sdhci_host *host, int dead);
668c0e55129SDong Aisheng extern void sdhci_send_command(struct sdhci_host *host,
669c0e55129SDong Aisheng 				struct mmc_command *cmd);
670b8c86fc5SPierre Ossman 
6716132a3bfSAdrian Hunter static inline void sdhci_read_caps(struct sdhci_host *host)
6726132a3bfSAdrian Hunter {
6736132a3bfSAdrian Hunter 	__sdhci_read_caps(host, NULL, NULL, NULL);
6746132a3bfSAdrian Hunter }
6756132a3bfSAdrian Hunter 
676be138554SRussell King static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
677be138554SRussell King {
678be138554SRussell King 	return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
679be138554SRussell King }
680be138554SRussell King 
681fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
682fb9ee047SLudovic Desroches 		   unsigned int *actual_clock);
6831771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
6841dceb041SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
6851dceb041SAdrian Hunter 		     unsigned short vdd);
6862317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width);
68703231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask);
68896d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
6892317f56cSRussell King 
690b8c86fc5SPierre Ossman #ifdef CONFIG_PM
69129495aa0SManuel Lauss extern int sdhci_suspend_host(struct sdhci_host *host);
692b8c86fc5SPierre Ossman extern int sdhci_resume_host(struct sdhci_host *host);
6935f619704SDaniel Drake extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
69466fd8ad5SAdrian Hunter extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
69566fd8ad5SAdrian Hunter extern int sdhci_runtime_resume_host(struct sdhci_host *host);
69666fd8ad5SAdrian Hunter #endif
69766fd8ad5SAdrian Hunter 
6981978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */
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