12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 41c6a0718SPierre Ossman * 51978fda8SGiuseppe Cavallaro * Header file for Host Controller registers and I/O accessors. 61978fda8SGiuseppe Cavallaro * 7b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 81c6a0718SPierre Ossman */ 91978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H 101978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H 111c6a0718SPierre Ossman 12fa091010SMasahiro Yamada #include <linux/bits.h> 130c7ad106SAndrew Morton #include <linux/scatterlist.h> 144e4141a5SAnton Vorontsov #include <linux/compiler.h> 154e4141a5SAnton Vorontsov #include <linux/types.h> 164e4141a5SAnton Vorontsov #include <linux/io.h> 17210583f4SUlf Hansson #include <linux/leds.h> 18b8789ec4SUlf Hansson #include <linux/interrupt.h> 190c7ad106SAndrew Morton 2083f13cc9SUlf Hansson #include <linux/mmc/host.h> 211978fda8SGiuseppe Cavallaro 221c6a0718SPierre Ossman /* 231c6a0718SPierre Ossman * Controller registers 241c6a0718SPierre Ossman */ 251c6a0718SPierre Ossman 261c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 278edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 28e65953d4SChunyan Zhang #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 291c6a0718SPierre Ossman 301c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 311c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 381c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 391c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 40e89d456fSAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD12 0x04 418edf6371SAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD23 0x08 42427b6514SChunyan Zhang #define SDHCI_TRNS_AUTO_SEL 0x0C 431c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 441c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 451c6a0718SPierre Ossman 461c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 471c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 481c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 491c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 501c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 51574e3f56SRichard Zhu #define SDHCI_CMD_ABORTCMD 0xC0 521c6a0718SPierre Ossman 531c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 541c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 551c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 561c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 571c6a0718SPierre Ossman 581c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 5922113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 601c6a0718SPierre Ossman 611c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 621c6a0718SPierre Ossman 631c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 641c6a0718SPierre Ossman 651c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 661c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 671c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 681c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 691c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 701c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 711c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 721c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 7369d91ed1SErnest Zhang(WH) #define SDHCI_CARD_PRES_SHIFT 16 7469d91ed1SErnest Zhang(WH) #define SDHCI_CD_STABLE 0x00020000 7569d91ed1SErnest Zhang(WH) #define SDHCI_CD_LVL 0x00040000 7669d91ed1SErnest Zhang(WH) #define SDHCI_CD_LVL_SHIFT 18 771c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 78f2119df6SArindam Nath #define SDHCI_DATA_LVL_MASK 0x00F00000 79f2119df6SArindam Nath #define SDHCI_DATA_LVL_SHIFT 20 807756a96dSYi Sun #define SDHCI_DATA_0_LVL_MASK 0x00100000 81b0921d5cSMichael Walle #define SDHCI_CMD_LVL 0x01000000 821c6a0718SPierre Ossman 831c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 841c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 851c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 861c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 872134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 882134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 892134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 902134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 912134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 924c4faff6SSowjanya Komatineni #define SDHCI_CTRL_ADMA3 0x18 93ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 943794c542SZach Brown #define SDHCI_CTRL_CDTEST_INS 0x40 953794c542SZach Brown #define SDHCI_CTRL_CDTEST_EN 0x80 961c6a0718SPierre Ossman 971c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 981c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 991c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 1001c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 1011c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 1021c6a0718SPierre Ossman 1031c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 1041c6a0718SPierre Ossman 1052df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 1065f619704SDaniel Drake #define SDHCI_WAKE_ON_INT 0x01 1075f619704SDaniel Drake #define SDHCI_WAKE_ON_INSERT 0x02 1085f619704SDaniel Drake #define SDHCI_WAKE_ON_REMOVE 0x04 1091c6a0718SPierre Ossman 1101c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 1111c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 11285105c53SZhangfei Gao #define SDHCI_DIVIDER_HI_SHIFT 6 11385105c53SZhangfei Gao #define SDHCI_DIV_MASK 0xFF 11485105c53SZhangfei Gao #define SDHCI_DIV_MASK_LEN 8 11585105c53SZhangfei Gao #define SDHCI_DIV_HI_MASK 0x300 116c3ed3877SArindam Nath #define SDHCI_PROG_CLOCK_MODE 0x0020 1171c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 1181beabbdbSBen Chuang #define SDHCI_CLOCK_PLL_EN 0x0008 1191c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 1201c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 1211c6a0718SPierre Ossman 1221c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 1231c6a0718SPierre Ossman 1241c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 1251c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 1261c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 1271c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 1281c6a0718SPierre Ossman 1291c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1301c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1311c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1321c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1331c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 134a4071fbbSHaijun Zhang #define SDHCI_INT_BLK_GAP 0x00000004 1351c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1361c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1371c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1381c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1391c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1401c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 141f37b20ebSDong Aisheng #define SDHCI_INT_RETUNE 0x00001000 142f12e39dbSAdrian Hunter #define SDHCI_INT_CQE 0x00004000 143964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1441c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1451c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1461c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1471c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1481c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1491c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1501c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1511c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 152869f8a69SAdrian Hunter #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 1532134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1541c6a0718SPierre Ossman 1551c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1561c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1571c6a0718SPierre Ossman 1581c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 159af849c86SAdrian Hunter SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 160af849c86SAdrian Hunter SDHCI_INT_AUTO_CMD_ERR) 1611c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1621c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1631c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 164a4071fbbSHaijun Zhang SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 165a4071fbbSHaijun Zhang SDHCI_INT_BLK_GAP) 1667260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1671c6a0718SPierre Ossman 168f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_ERR_MASK ( \ 169f12e39dbSAdrian Hunter SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 170f12e39dbSAdrian Hunter SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 171f12e39dbSAdrian Hunter SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 172f12e39dbSAdrian Hunter 173f12e39dbSAdrian Hunter #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 174f12e39dbSAdrian Hunter 175869f8a69SAdrian Hunter #define SDHCI_AUTO_CMD_STATUS 0x3C 176af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 177af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_CRC 0x00000004 178af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_END_BIT 0x00000008 179af849c86SAdrian Hunter #define SDHCI_AUTO_CMD_INDEX 0x00000010 1801c6a0718SPierre Ossman 181f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2 0x3E 18249c468fcSArindam Nath #define SDHCI_CTRL_UHS_MASK 0x0007 18349c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR12 0x0000 18449c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR25 0x0001 18549c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR50 0x0002 18649c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR104 0x0003 18749c468fcSArindam Nath #define SDHCI_CTRL_UHS_DDR50 0x0004 188e9fb05d5SAdrian Hunter #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 189f2119df6SArindam Nath #define SDHCI_CTRL_VDD_180 0x0008 190d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 191d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_B 0x0000 192d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_A 0x0010 193d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_C 0x0020 194d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_D 0x0030 195b513ea25SArindam Nath #define SDHCI_CTRL_EXEC_TUNING 0x0040 196b513ea25SArindam Nath #define SDHCI_CTRL_TUNED_CLK 0x0080 197427b6514SChunyan Zhang #define SDHCI_CMD23_ENABLE 0x0800 198b3f80b43SChunyan Zhang #define SDHCI_CTRL_V4_MODE 0x1000 199685e444bSChunyan Zhang #define SDHCI_CTRL_64BIT_ADDR 0x2000 200d6d50a15SArindam Nath #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 2011c6a0718SPierre Ossman 2021c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 203a8e809ecSMasahiro Yamada #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) 20498b5ce4cSAl Cooper #define SDHCI_TIMEOUT_CLK_SHIFT 0 2051c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 206a8e809ecSMasahiro Yamada #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) 20798b5ce4cSAl Cooper #define SDHCI_CLOCK_BASE_SHIFT 8 208a8e809ecSMasahiro Yamada #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) 2091c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 2101c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 21115ec4461SPhilip Rakity #define SDHCI_CAN_DO_8BIT 0x00040000 2122134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 2132134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 2141c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 215a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 216e71d4b81SStefan Wahren #define SDHCI_CAN_DO_SUSPEND 0x00800000 2171c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 2181c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 2191c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 220685e444bSChunyan Zhang #define SDHCI_CAN_64BIT_V4 0x08000000 2212134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 2221c6a0718SPierre Ossman 2232941e4caSMasahiro Yamada #define SDHCI_CAPABILITIES_1 0x44 224f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR50 0x00000001 225f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR104 0x00000002 226f2119df6SArindam Nath #define SDHCI_SUPPORT_DDR50 0x00000004 227d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_A 0x00000010 228d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_C 0x00000020 229d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_D 0x00000040 230a8e809ecSMasahiro Yamada #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) 231b513ea25SArindam Nath #define SDHCI_USE_SDR50_TUNING 0x00002000 232a8e809ecSMasahiro Yamada #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) 233a8e809ecSMasahiro Yamada #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) 2344c4faff6SSowjanya Komatineni #define SDHCI_CAN_DO_ADMA3 0x08000000 235e9fb05d5SAdrian Hunter #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 236f2119df6SArindam Nath 2371c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 238804a65b3SMasahiro Yamada #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) 239804a65b3SMasahiro Yamada #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) 240804a65b3SMasahiro Yamada #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) 241804a65b3SMasahiro Yamada #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) 242f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_MULTIPLIER 4 2431c6a0718SPierre Ossman 2441c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 2451c6a0718SPierre Ossman 2462134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 2472134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 2482134a922SPierre Ossman 2492134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 2502134a922SPierre Ossman 2512134a922SPierre Ossman /* 55-57 reserved */ 2522134a922SPierre Ossman 2532134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 254e57a5f61SAdrian Hunter #define SDHCI_ADMA_ADDRESS_HI 0x5C 2552134a922SPierre Ossman 2562134a922SPierre Ossman /* 60-FB reserved */ 2571c6a0718SPierre Ossman 258d0244847SAl Cooper #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 25952983382SKevin Liu #define SDHCI_PRESET_FOR_SDR12 0x66 26052983382SKevin Liu #define SDHCI_PRESET_FOR_SDR25 0x68 26152983382SKevin Liu #define SDHCI_PRESET_FOR_SDR50 0x6A 26252983382SKevin Liu #define SDHCI_PRESET_FOR_SDR104 0x6C 26352983382SKevin Liu #define SDHCI_PRESET_FOR_DDR50 0x6E 264e9fb05d5SAdrian Hunter #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 265fa091010SMasahiro Yamada #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) 266fa091010SMasahiro Yamada #define SDHCI_PRESET_CLKGEN_SEL BIT(10) 267fa091010SMasahiro Yamada #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) 26852983382SKevin Liu 2691c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 2701c6a0718SPierre Ossman 2711c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 2721c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 2731c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 2741c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 2751c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 2762134a922SPierre Ossman #define SDHCI_SPEC_100 0 2772134a922SPierre Ossman #define SDHCI_SPEC_200 1 27885105c53SZhangfei Gao #define SDHCI_SPEC_300 2 27918da1990SChunyan Zhang #define SDHCI_SPEC_400 3 28018da1990SChunyan Zhang #define SDHCI_SPEC_410 4 28118da1990SChunyan Zhang #define SDHCI_SPEC_420 5 2821c6a0718SPierre Ossman 2830397526dSZhangfei Gao /* 2840397526dSZhangfei Gao * End of controller registers. 2850397526dSZhangfei Gao */ 2860397526dSZhangfei Gao 2870397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200 256 2880397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300 2046 2890397526dSZhangfei Gao 290f6a03cbfSMikko Vinni /* 291f6a03cbfSMikko Vinni * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 292f6a03cbfSMikko Vinni */ 293f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 294f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 295f6a03cbfSMikko Vinni 296739d46dcSAdrian Hunter /* ADMA2 32-bit DMA descriptor size */ 297739d46dcSAdrian Hunter #define SDHCI_ADMA2_32_DESC_SZ 8 298739d46dcSAdrian Hunter 2990545230fSAdrian Hunter /* ADMA2 32-bit descriptor */ 3000545230fSAdrian Hunter struct sdhci_adma2_32_desc { 3010545230fSAdrian Hunter __le16 cmd; 3020545230fSAdrian Hunter __le16 len; 3030545230fSAdrian Hunter __le32 addr; 30404a5ae6fSAdrian Hunter } __packed __aligned(4); 30504a5ae6fSAdrian Hunter 30604a5ae6fSAdrian Hunter /* ADMA2 data alignment */ 30704a5ae6fSAdrian Hunter #define SDHCI_ADMA2_ALIGN 4 30804a5ae6fSAdrian Hunter #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 30904a5ae6fSAdrian Hunter 31004a5ae6fSAdrian Hunter /* 31104a5ae6fSAdrian Hunter * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 31204a5ae6fSAdrian Hunter * alignment for the descriptor table even in 32-bit DMA mode. Memory 31304a5ae6fSAdrian Hunter * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 31404a5ae6fSAdrian Hunter */ 31504a5ae6fSAdrian Hunter #define SDHCI_ADMA2_DESC_ALIGN 8 3160545230fSAdrian Hunter 317685e444bSChunyan Zhang /* 318685e444bSChunyan Zhang * ADMA2 64-bit DMA descriptor size 319685e444bSChunyan Zhang * According to SD Host Controller spec v4.10, there are two kinds of 320685e444bSChunyan Zhang * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 321685e444bSChunyan Zhang * Descriptor, if Host Version 4 Enable is set in the Host Control 2 322685e444bSChunyan Zhang * register, 128-bit Descriptor will be selected. 323685e444bSChunyan Zhang */ 324685e444bSChunyan Zhang #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 325e57a5f61SAdrian Hunter 326e57a5f61SAdrian Hunter /* 327e57a5f61SAdrian Hunter * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 328e57a5f61SAdrian Hunter * aligned. 329e57a5f61SAdrian Hunter */ 330e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc { 331e57a5f61SAdrian Hunter __le16 cmd; 332e57a5f61SAdrian Hunter __le16 len; 333e57a5f61SAdrian Hunter __le32 addr_lo; 334e57a5f61SAdrian Hunter __le32 addr_hi; 335e57a5f61SAdrian Hunter } __packed __aligned(4); 336e57a5f61SAdrian Hunter 337739d46dcSAdrian Hunter #define ADMA2_TRAN_VALID 0x21 338739d46dcSAdrian Hunter #define ADMA2_NOP_END_VALID 0x3 339739d46dcSAdrian Hunter #define ADMA2_END 0x2 340739d46dcSAdrian Hunter 3414fb213f8SAdrian Hunter /* 3424fb213f8SAdrian Hunter * Maximum segments assuming a 512KiB maximum requisition size and a minimum 3434fb213f8SAdrian Hunter * 4KiB page size. 3444fb213f8SAdrian Hunter */ 3454fb213f8SAdrian Hunter #define SDHCI_MAX_SEGS 128 3464fb213f8SAdrian Hunter 3474e9f8fe5SAdrian Hunter /* Allow for a a command request and a data request at the same time */ 3484e9f8fe5SAdrian Hunter #define SDHCI_MAX_MRQS 2 3494e9f8fe5SAdrian Hunter 350fc1fa1b7SKishon Vijay Abraham I /* 351fc1fa1b7SKishon Vijay Abraham I * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 352fc1fa1b7SKishon Vijay Abraham I * However since the start time of the command, the time between 353fc1fa1b7SKishon Vijay Abraham I * command and response, and the time between response and start of data is 354fc1fa1b7SKishon Vijay Abraham I * not known, set the command transfer time to 10ms. 355fc1fa1b7SKishon Vijay Abraham I */ 356fc1fa1b7SKishon Vijay Abraham I #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 357fc1fa1b7SKishon Vijay Abraham I 358d31911b9SHaibo Chen enum sdhci_cookie { 359d31911b9SHaibo Chen COOKIE_UNMAPPED, 36094538e51SRussell King COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 36194538e51SRussell King COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 36283f13cc9SUlf Hansson }; 36383f13cc9SUlf Hansson 36483f13cc9SUlf Hansson struct sdhci_host { 36583f13cc9SUlf Hansson /* Data set by hardware interface driver */ 36683f13cc9SUlf Hansson const char *hw_name; /* Hardware bus name */ 36783f13cc9SUlf Hansson 36883f13cc9SUlf Hansson unsigned int quirks; /* Deviations from spec. */ 36983f13cc9SUlf Hansson 37083f13cc9SUlf Hansson /* Controller doesn't honor resets unless we touch the clock register */ 37183f13cc9SUlf Hansson #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 37283f13cc9SUlf Hansson /* Controller has bad caps bits, but really supports DMA */ 37383f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_DMA (1<<1) 37483f13cc9SUlf Hansson /* Controller doesn't like to be reset when there is no card inserted. */ 37583f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 37683f13cc9SUlf Hansson /* Controller doesn't like clearing the power reg before a change */ 37783f13cc9SUlf Hansson #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 37883f13cc9SUlf Hansson /* Controller has flaky internal state so reset it on each ios change */ 37983f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 38083f13cc9SUlf Hansson /* Controller has an unusable DMA engine */ 38183f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 38283f13cc9SUlf Hansson /* Controller has an unusable ADMA engine */ 38383f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 38483f13cc9SUlf Hansson /* Controller can only DMA from 32-bit aligned addresses */ 38583f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 38683f13cc9SUlf Hansson /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 38783f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 38883f13cc9SUlf Hansson /* Controller can only ADMA chunks that are a multiple of 32 bits */ 38983f13cc9SUlf Hansson #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 39083f13cc9SUlf Hansson /* Controller needs to be reset after each request to stay stable */ 39183f13cc9SUlf Hansson #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 39283f13cc9SUlf Hansson /* Controller needs voltage and power writes to happen separately */ 39383f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 39483f13cc9SUlf Hansson /* Controller provides an incorrect timeout value for transfers */ 39583f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 39683f13cc9SUlf Hansson /* Controller has an issue with buffer bits for small transfers */ 39783f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 39883f13cc9SUlf Hansson /* Controller does not provide transfer-complete interrupt when not busy */ 39983f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 40083f13cc9SUlf Hansson /* Controller has unreliable card detection */ 40183f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 40283f13cc9SUlf Hansson /* Controller reports inverted write-protect state */ 40383f13cc9SUlf Hansson #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 40475d27ea1SAdrian Hunter /* Controller has unusable command queue engine */ 40575d27ea1SAdrian Hunter #define SDHCI_QUIRK_BROKEN_CQE (1<<17) 40683f13cc9SUlf Hansson /* Controller does not like fast PIO transfers */ 40783f13cc9SUlf Hansson #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 408bd29f58bSAdrian Hunter /* Controller does not have a LED */ 409bd29f58bSAdrian Hunter #define SDHCI_QUIRK_NO_LED (1<<19) 41083f13cc9SUlf Hansson /* Controller has to be forced to use block size of 2048 bytes */ 41183f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 41283f13cc9SUlf Hansson /* Controller cannot do multi-block transfers */ 41383f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 41483f13cc9SUlf Hansson /* Controller can only handle 1-bit data transfers */ 41583f13cc9SUlf Hansson #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 41683f13cc9SUlf Hansson /* Controller needs 10ms delay between applying power and clock */ 41783f13cc9SUlf Hansson #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 41883f13cc9SUlf Hansson /* Controller uses SDCLK instead of TMCLK for data timeouts */ 41983f13cc9SUlf Hansson #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 42083f13cc9SUlf Hansson /* Controller reports wrong base clock capability */ 42183f13cc9SUlf Hansson #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 42283f13cc9SUlf Hansson /* Controller cannot support End Attribute in NOP ADMA descriptor */ 42383f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 42483f13cc9SUlf Hansson /* Controller is missing device caps. Use caps provided by host */ 42583f13cc9SUlf Hansson #define SDHCI_QUIRK_MISSING_CAPS (1<<27) 42683f13cc9SUlf Hansson /* Controller uses Auto CMD12 command to stop the transfer */ 42783f13cc9SUlf Hansson #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 42883f13cc9SUlf Hansson /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 42983f13cc9SUlf Hansson #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 43083f13cc9SUlf Hansson /* Controller treats ADMA descriptors with length 0000h incorrectly */ 43183f13cc9SUlf Hansson #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 43283f13cc9SUlf Hansson /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 43383f13cc9SUlf Hansson #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 43483f13cc9SUlf Hansson 43583f13cc9SUlf Hansson unsigned int quirks2; /* More deviations from spec. */ 43683f13cc9SUlf Hansson 43783f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 43883f13cc9SUlf Hansson #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 43983f13cc9SUlf Hansson /* The system physically doesn't support 1.8v, even if the host does */ 44083f13cc9SUlf Hansson #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 44183f13cc9SUlf Hansson #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 44283f13cc9SUlf Hansson #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 44383f13cc9SUlf Hansson /* Controller has a non-standard host control register */ 44483f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 44583f13cc9SUlf Hansson /* Controller does not support HS200 */ 44683f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 44783f13cc9SUlf Hansson /* Controller does not support DDR50 */ 44883f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 44983f13cc9SUlf Hansson /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 45083f13cc9SUlf Hansson #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 45183f13cc9SUlf Hansson /* Controller does not support 64-bit DMA */ 45283f13cc9SUlf Hansson #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 45383f13cc9SUlf Hansson /* need clear transfer mode register before send cmd */ 45483f13cc9SUlf Hansson #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 45583f13cc9SUlf Hansson /* Capability register bit-63 indicates HS400 support */ 45683f13cc9SUlf Hansson #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 45783f13cc9SUlf Hansson /* forced tuned clock */ 45883f13cc9SUlf Hansson #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 45983f13cc9SUlf Hansson /* disable the block count for single block transactions */ 46083f13cc9SUlf Hansson #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 46183f13cc9SUlf Hansson /* Controller broken with using ACMD23 */ 46283f13cc9SUlf Hansson #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 463d1955c3aSSuneel Garapati /* Broken Clock divider zero in controller */ 464d1955c3aSSuneel Garapati #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 4651284c248SKishon Vijay Abraham I /* Controller has CRC in 136 bit Command Response */ 4661284c248SKishon Vijay Abraham I #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 467a999fd93SAdrian Hunter /* 468a999fd93SAdrian Hunter * Disable HW timeout if the requested timeout is more than the maximum 469a999fd93SAdrian Hunter * obtainable timeout. 470a999fd93SAdrian Hunter */ 471a999fd93SAdrian Hunter #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 472e65953d4SChunyan Zhang /* 473e65953d4SChunyan Zhang * 32-bit block count may not support eMMC where upper bits of CMD23 are used 474e65953d4SChunyan Zhang * for other purposes. Consequently we support 16-bit block count by default. 475e65953d4SChunyan Zhang * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 476e65953d4SChunyan Zhang * block count. 477e65953d4SChunyan Zhang */ 478e65953d4SChunyan Zhang #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 47983f13cc9SUlf Hansson 48083f13cc9SUlf Hansson int irq; /* Device IRQ */ 48183f13cc9SUlf Hansson void __iomem *ioaddr; /* Mapped address */ 48218e762e3SChunyan Zhang phys_addr_t mapbase; /* physical address base */ 483bd9b9027SLinus Walleij char *bounce_buffer; /* For packing SDMA reads/writes */ 484bd9b9027SLinus Walleij dma_addr_t bounce_addr; 485bd9b9027SLinus Walleij unsigned int bounce_buffer_size; 48683f13cc9SUlf Hansson 48783f13cc9SUlf Hansson const struct sdhci_ops *ops; /* Low level hw interface */ 48883f13cc9SUlf Hansson 48983f13cc9SUlf Hansson /* Internal data */ 49083f13cc9SUlf Hansson struct mmc_host *mmc; /* MMC structure */ 491bf60e592SAdrian Hunter struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 49283f13cc9SUlf Hansson u64 dma_mask; /* custom DMA mask */ 49383f13cc9SUlf Hansson 49474479c5dSMasahiro Yamada #if IS_ENABLED(CONFIG_LEDS_CLASS) 49583f13cc9SUlf Hansson struct led_classdev led; /* LED control */ 49683f13cc9SUlf Hansson char led_name[32]; 49783f13cc9SUlf Hansson #endif 49883f13cc9SUlf Hansson 49983f13cc9SUlf Hansson spinlock_t lock; /* Mutex */ 50083f13cc9SUlf Hansson 50183f13cc9SUlf Hansson int flags; /* Host attributes */ 50283f13cc9SUlf Hansson #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 50383f13cc9SUlf Hansson #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 50483f13cc9SUlf Hansson #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 50583f13cc9SUlf Hansson #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 50683f13cc9SUlf Hansson #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 50783f13cc9SUlf Hansson #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 50883f13cc9SUlf Hansson #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 50983f13cc9SUlf Hansson #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 51083f13cc9SUlf Hansson #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 51183f13cc9SUlf Hansson #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 5128cb851a4SAdrian Hunter #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 5138cb851a4SAdrian Hunter #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 5148cb851a4SAdrian Hunter #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 51583f13cc9SUlf Hansson 51683f13cc9SUlf Hansson unsigned int version; /* SDHCI spec. version */ 51783f13cc9SUlf Hansson 51883f13cc9SUlf Hansson unsigned int max_clk; /* Max possible freq (MHz) */ 51983f13cc9SUlf Hansson unsigned int timeout_clk; /* Timeout freq (KHz) */ 520e30314f2SSarthak Garg u8 max_timeout_count; /* Vendor specific max timeout count */ 52183f13cc9SUlf Hansson unsigned int clk_mul; /* Clock Muliplier value */ 52283f13cc9SUlf Hansson 52383f13cc9SUlf Hansson unsigned int clock; /* Current clock (MHz) */ 52483f13cc9SUlf Hansson u8 pwr; /* Current voltage */ 52583f13cc9SUlf Hansson 52683f13cc9SUlf Hansson bool runtime_suspended; /* Host is runtime suspended */ 52783f13cc9SUlf Hansson bool bus_on; /* Bus power prevents runtime suspend */ 52883f13cc9SUlf Hansson bool preset_enabled; /* Preset is enabled */ 529ed1563deSAdrian Hunter bool pending_reset; /* Cmd/data reset is pending */ 53058e79b60SAdrian Hunter bool irq_wake_enabled; /* IRQ wakeup is enabled */ 531b3f80b43SChunyan Zhang bool v4_mode; /* Host Version 4 Enable */ 53218e762e3SChunyan Zhang bool use_external_dma; /* Host selects to use external DMA */ 5334730831cSBaolin Wang bool always_defer_done; /* Always defer to complete requests */ 53483f13cc9SUlf Hansson 5354e9f8fe5SAdrian Hunter struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 53683f13cc9SUlf Hansson struct mmc_command *cmd; /* Current command */ 5377c89a3d9SAdrian Hunter struct mmc_command *data_cmd; /* Current data command */ 538845c939eSAdrian Hunter struct mmc_command *deferred_cmd; /* Deferred command */ 53983f13cc9SUlf Hansson struct mmc_data *data; /* Current data request */ 54083f13cc9SUlf Hansson unsigned int data_early:1; /* Data finished before cmd */ 54183f13cc9SUlf Hansson 54283f13cc9SUlf Hansson struct sg_mapping_iter sg_miter; /* SG state for PIO */ 54383f13cc9SUlf Hansson unsigned int blocks; /* remaining PIO blocks */ 54483f13cc9SUlf Hansson 54583f13cc9SUlf Hansson int sg_count; /* Mapped sg entries */ 54683f13cc9SUlf Hansson 54783f13cc9SUlf Hansson void *adma_table; /* ADMA descriptor table */ 54883f13cc9SUlf Hansson void *align_buffer; /* Bounce buffer */ 54983f13cc9SUlf Hansson 55083f13cc9SUlf Hansson size_t adma_table_sz; /* ADMA descriptor table size */ 55183f13cc9SUlf Hansson size_t align_buffer_sz; /* Bounce buffer size */ 55283f13cc9SUlf Hansson 55383f13cc9SUlf Hansson dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 55483f13cc9SUlf Hansson dma_addr_t align_addr; /* Mapped bounce buffer */ 55583f13cc9SUlf Hansson 556a663f64bSVeerabhadrarao Badiganti unsigned int desc_sz; /* ADMA current descriptor size */ 557a663f64bSVeerabhadrarao Badiganti unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ 55883f13cc9SUlf Hansson 559c07a48c2SAdrian Hunter struct workqueue_struct *complete_wq; /* Request completion wq */ 560c07a48c2SAdrian Hunter struct work_struct complete_work; /* Request completion work */ 56183f13cc9SUlf Hansson 56283f13cc9SUlf Hansson struct timer_list timer; /* Timer for timeouts */ 563d7422fb4SAdrian Hunter struct timer_list data_timer; /* Timer for data timeouts */ 56483f13cc9SUlf Hansson 56518e762e3SChunyan Zhang #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) 56618e762e3SChunyan Zhang struct dma_chan *rx_chan; 56718e762e3SChunyan Zhang struct dma_chan *tx_chan; 56818e762e3SChunyan Zhang #endif 56918e762e3SChunyan Zhang 57028da3589SAdrian Hunter u32 caps; /* CAPABILITY_0 */ 57128da3589SAdrian Hunter u32 caps1; /* CAPABILITY_1 */ 5726132a3bfSAdrian Hunter bool read_caps; /* Capability flags have been read */ 57383f13cc9SUlf Hansson 5740fcb031eSVijay Viswanath bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ 57583f13cc9SUlf Hansson unsigned int ocr_avail_sdio; /* OCR bit masks */ 57683f13cc9SUlf Hansson unsigned int ocr_avail_sd; 57783f13cc9SUlf Hansson unsigned int ocr_avail_mmc; 57883f13cc9SUlf Hansson u32 ocr_mask; /* available voltages */ 57983f13cc9SUlf Hansson 58083f13cc9SUlf Hansson unsigned timing; /* Current timing */ 58183f13cc9SUlf Hansson 58283f13cc9SUlf Hansson u32 thread_isr; 58383f13cc9SUlf Hansson 58483f13cc9SUlf Hansson /* cached registers */ 58583f13cc9SUlf Hansson u32 ier; 58683f13cc9SUlf Hansson 587f12e39dbSAdrian Hunter bool cqe_on; /* CQE is operating */ 588f12e39dbSAdrian Hunter u32 cqe_ier; /* CQE interrupt mask */ 589f12e39dbSAdrian Hunter u32 cqe_err_ier; /* CQE error interrupt mask */ 590f12e39dbSAdrian Hunter 59183f13cc9SUlf Hansson wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 59283f13cc9SUlf Hansson unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 59383f13cc9SUlf Hansson 59483f13cc9SUlf Hansson unsigned int tuning_count; /* Timer count for re-tuning */ 59583f13cc9SUlf Hansson unsigned int tuning_mode; /* Re-tuning mode supported by host */ 5967d8bb1f4SYinbo Zhu unsigned int tuning_err; /* Error code for re-tuning */ 59783f13cc9SUlf Hansson #define SDHCI_TUNING_MODE_1 0 598f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_2 1 599f37b20ebSDong Aisheng #define SDHCI_TUNING_MODE_3 2 60083b600b8SAdrian Hunter /* Delay (ms) between tuning commands */ 60183b600b8SAdrian Hunter int tuning_delay; 6021d8cd065SSowjanya Komatineni int tuning_loop_count; 60383f13cc9SUlf Hansson 604c846a00fSSrinivas Kandagatla /* Host SDMA buffer boundary. */ 605c846a00fSSrinivas Kandagatla u32 sdma_boundary; 606c846a00fSSrinivas Kandagatla 607e93be38aSJisheng Zhang /* Host ADMA table count */ 608e93be38aSJisheng Zhang u32 adma_table_cnt; 609e93be38aSJisheng Zhang 610fc1fa1b7SKishon Vijay Abraham I u64 data_timeout; 611fc1fa1b7SKishon Vijay Abraham I 6121a91a36aSGustavo A. R. Silva unsigned long private[] ____cacheline_aligned; 61383f13cc9SUlf Hansson }; 61483f13cc9SUlf Hansson 615b8c86fc5SPierre Ossman struct sdhci_ops { 6164e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 617dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 618dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 619dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 620dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 621dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 622dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 6234e4141a5SAnton Vorontsov #endif 6244e4141a5SAnton Vorontsov 6258114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 6261dceb041SAdrian Hunter void (*set_power)(struct sdhci_host *host, unsigned char mode, 6271dceb041SAdrian Hunter unsigned short vdd); 6288114634cSAnton Vorontsov 629f12e39dbSAdrian Hunter u32 (*irq)(struct sdhci_host *host, u32 intmask); 630f12e39dbSAdrian Hunter 6314ee7dde4SAdrian Hunter int (*set_dma_mask)(struct sdhci_host *host); 632b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 6334240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 634a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 6358cc35289SShawn Lin /* get_timeout_clock should return clk rate in unit of Hz */ 6364240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 637a6ff5aebSAisheng Dong unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 638b45e668aSAisheng Dong void (*set_timeout)(struct sdhci_host *host, 639b45e668aSAisheng Dong struct mmc_command *cmd); 6402317f56cSRussell King void (*set_bus_width)(struct sdhci_host *host, int width); 641643a81ffSPhilip Rakity void (*platform_send_init_74_clocks)(struct sdhci_host *host, 642643a81ffSPhilip Rakity u8 power_mode); 6432dfb579cSWolfram Sang unsigned int (*get_ro)(struct sdhci_host *host); 64403231f9bSRussell King void (*reset)(struct sdhci_host *host, u8 mask); 64545251812SDong Aisheng int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 64613e64501SRussell King void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 64720758b66SAdrian Hunter void (*hw_reset)(struct sdhci_host *host); 648a4071fbbSHaijun Zhang void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 649722e1280SChristian Daudt void (*card_event)(struct sdhci_host *host); 6509d967a61SVincent Yang void (*voltage_switch)(struct sdhci_host *host); 65154552e49SJisheng Zhang void (*adma_write_desc)(struct sdhci_host *host, void **desc, 65254552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd); 653e93577ecSAngelo Dureghello void (*copy_to_bounce_buffer)(struct sdhci_host *host, 654e93577ecSAngelo Dureghello struct mmc_data *data, 655e93577ecSAngelo Dureghello unsigned int length); 6561774b002SBaolin Wang void (*request_done)(struct sdhci_host *host, 6571774b002SBaolin Wang struct mmc_request *mrq); 658d1fe0762SSarthak Garg void (*dump_vendor_regs)(struct sdhci_host *host); 6591c6a0718SPierre Ossman }; 660b8c86fc5SPierre Ossman 6614e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 6624e4141a5SAnton Vorontsov 6634e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 6644e4141a5SAnton Vorontsov { 665dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 666dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 6674e4141a5SAnton Vorontsov else 6684e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 6694e4141a5SAnton Vorontsov } 6704e4141a5SAnton Vorontsov 6714e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 6724e4141a5SAnton Vorontsov { 673dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 674dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 6754e4141a5SAnton Vorontsov else 6764e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 6774e4141a5SAnton Vorontsov } 6784e4141a5SAnton Vorontsov 6794e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 6804e4141a5SAnton Vorontsov { 681dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 682dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 6834e4141a5SAnton Vorontsov else 6844e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 6854e4141a5SAnton Vorontsov } 6864e4141a5SAnton Vorontsov 6874e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 6884e4141a5SAnton Vorontsov { 689dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 690dc297c92SMatt Fleming return host->ops->read_l(host, reg); 6914e4141a5SAnton Vorontsov else 6924e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 6934e4141a5SAnton Vorontsov } 6944e4141a5SAnton Vorontsov 6954e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 6964e4141a5SAnton Vorontsov { 697dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 698dc297c92SMatt Fleming return host->ops->read_w(host, reg); 6994e4141a5SAnton Vorontsov else 7004e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 7014e4141a5SAnton Vorontsov } 7024e4141a5SAnton Vorontsov 7034e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 7044e4141a5SAnton Vorontsov { 705dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 706dc297c92SMatt Fleming return host->ops->read_b(host, reg); 7074e4141a5SAnton Vorontsov else 7084e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 7094e4141a5SAnton Vorontsov } 7104e4141a5SAnton Vorontsov 7114e4141a5SAnton Vorontsov #else 7124e4141a5SAnton Vorontsov 7134e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 7144e4141a5SAnton Vorontsov { 7154e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 7164e4141a5SAnton Vorontsov } 7174e4141a5SAnton Vorontsov 7184e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 7194e4141a5SAnton Vorontsov { 7204e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 7214e4141a5SAnton Vorontsov } 7224e4141a5SAnton Vorontsov 7234e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 7244e4141a5SAnton Vorontsov { 7254e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 7264e4141a5SAnton Vorontsov } 7274e4141a5SAnton Vorontsov 7284e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 7294e4141a5SAnton Vorontsov { 7304e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 7314e4141a5SAnton Vorontsov } 7324e4141a5SAnton Vorontsov 7334e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 7344e4141a5SAnton Vorontsov { 7354e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 7364e4141a5SAnton Vorontsov } 7374e4141a5SAnton Vorontsov 7384e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 7394e4141a5SAnton Vorontsov { 7404e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 7414e4141a5SAnton Vorontsov } 7424e4141a5SAnton Vorontsov 7434e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 744b8c86fc5SPierre Ossman 74515becf68SAdrian Hunter struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 74615becf68SAdrian Hunter void sdhci_free_host(struct sdhci_host *host); 747b8c86fc5SPierre Ossman 748b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 749b8c86fc5SPierre Ossman { 750178b0fa0SMasahiro Yamada return host->private; 751b8c86fc5SPierre Ossman } 752b8c86fc5SPierre Ossman 75315becf68SAdrian Hunter void sdhci_card_detect(struct sdhci_host *host); 7548784edc8SMasahiro Yamada void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 7558784edc8SMasahiro Yamada const u32 *caps, const u32 *caps1); 75615becf68SAdrian Hunter int sdhci_setup_host(struct sdhci_host *host); 7574180ffa8SAdrian Hunter void sdhci_cleanup_host(struct sdhci_host *host); 75815becf68SAdrian Hunter int __sdhci_add_host(struct sdhci_host *host); 75915becf68SAdrian Hunter int sdhci_add_host(struct sdhci_host *host); 76015becf68SAdrian Hunter void sdhci_remove_host(struct sdhci_host *host, int dead); 761b8c86fc5SPierre Ossman 7626132a3bfSAdrian Hunter static inline void sdhci_read_caps(struct sdhci_host *host) 7636132a3bfSAdrian Hunter { 7646132a3bfSAdrian Hunter __sdhci_read_caps(host, NULL, NULL, NULL); 7656132a3bfSAdrian Hunter } 7666132a3bfSAdrian Hunter 767fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 768fb9ee047SLudovic Desroches unsigned int *actual_clock); 7691771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 770fec79673SRitesh Harjani void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 7711dceb041SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 7721dceb041SAdrian Hunter unsigned short vdd); 7736c92ae1eSNicolas Saenz Julienne void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, 7746c92ae1eSNicolas Saenz Julienne unsigned char mode, 7756c92ae1eSNicolas Saenz Julienne unsigned short vdd); 776606d3131SAdrian Hunter void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 777606d3131SAdrian Hunter unsigned short vdd); 778*2caa11bcSAndy Shevchenko int sdhci_get_cd_nogpio(struct mmc_host *mmc); 779d462c1b4SAapo Vienamo void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 78048ef8a2aSBaolin Wang int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); 7812317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width); 78203231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask); 78396d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 78485a882c2SMasahiro Yamada int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 7856a6d4cebSHu Ziji void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 786c376ea9eSHu Ziji int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 787c376ea9eSHu Ziji struct mmc_ios *ios); 7882f05b6abSHu Ziji void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 78954552e49SJisheng Zhang void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 79054552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd); 7912317f56cSRussell King 792b8c86fc5SPierre Ossman #ifdef CONFIG_PM 79315becf68SAdrian Hunter int sdhci_suspend_host(struct sdhci_host *host); 79415becf68SAdrian Hunter int sdhci_resume_host(struct sdhci_host *host); 79515becf68SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host); 796c6303c5dSBaolin Wang int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 79766fd8ad5SAdrian Hunter #endif 79866fd8ad5SAdrian Hunter 799f12e39dbSAdrian Hunter void sdhci_cqe_enable(struct mmc_host *mmc); 800f12e39dbSAdrian Hunter void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 801f12e39dbSAdrian Hunter bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 802f12e39dbSAdrian Hunter int *data_error); 803f12e39dbSAdrian Hunter 804d2898172SAdrian Hunter void sdhci_dumpregs(struct sdhci_host *host); 805b3f80b43SChunyan Zhang void sdhci_enable_v4_mode(struct sdhci_host *host); 806d2898172SAdrian Hunter 8076663c419Sernest.zhang void sdhci_start_tuning(struct sdhci_host *host); 8086663c419Sernest.zhang void sdhci_end_tuning(struct sdhci_host *host); 8096663c419Sernest.zhang void sdhci_reset_tuning(struct sdhci_host *host); 8106663c419Sernest.zhang void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 8117353788cSBen Chuang void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); 81218e762e3SChunyan Zhang void sdhci_switch_external_dma(struct sdhci_host *host, bool en); 8137907ebe7SFaiz Abbas void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); 8147d76ed77SFaiz Abbas void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); 8156663c419Sernest.zhang 8161978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */ 817