11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 41978fda8SGiuseppe Cavallaro * Header file for Host Controller registers and I/O accessors. 51978fda8SGiuseppe Cavallaro * 6b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 71c6a0718SPierre Ossman * 81c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 91c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 101c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 111c6a0718SPierre Ossman * your option) any later version. 121c6a0718SPierre Ossman */ 131978fda8SGiuseppe Cavallaro #ifndef __SDHCI_HW_H 141978fda8SGiuseppe Cavallaro #define __SDHCI_HW_H 151c6a0718SPierre Ossman 160c7ad106SAndrew Morton #include <linux/scatterlist.h> 174e4141a5SAnton Vorontsov #include <linux/compiler.h> 184e4141a5SAnton Vorontsov #include <linux/types.h> 194e4141a5SAnton Vorontsov #include <linux/io.h> 200c7ad106SAndrew Morton 211978fda8SGiuseppe Cavallaro #include <linux/mmc/sdhci.h> 221978fda8SGiuseppe Cavallaro 231c6a0718SPierre Ossman /* 241c6a0718SPierre Ossman * Controller registers 251c6a0718SPierre Ossman */ 261c6a0718SPierre Ossman 271c6a0718SPierre Ossman #define SDHCI_DMA_ADDRESS 0x00 288edf6371SAndrei Warkentin #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 291c6a0718SPierre Ossman 301c6a0718SPierre Ossman #define SDHCI_BLOCK_SIZE 0x04 311c6a0718SPierre Ossman #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #define SDHCI_BLOCK_COUNT 0x06 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define SDHCI_ARGUMENT 0x08 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define SDHCI_TRANSFER_MODE 0x0C 381c6a0718SPierre Ossman #define SDHCI_TRNS_DMA 0x01 391c6a0718SPierre Ossman #define SDHCI_TRNS_BLK_CNT_EN 0x02 40e89d456fSAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD12 0x04 418edf6371SAndrei Warkentin #define SDHCI_TRNS_AUTO_CMD23 0x08 421c6a0718SPierre Ossman #define SDHCI_TRNS_READ 0x10 431c6a0718SPierre Ossman #define SDHCI_TRNS_MULTI 0x20 441c6a0718SPierre Ossman 451c6a0718SPierre Ossman #define SDHCI_COMMAND 0x0E 461c6a0718SPierre Ossman #define SDHCI_CMD_RESP_MASK 0x03 471c6a0718SPierre Ossman #define SDHCI_CMD_CRC 0x08 481c6a0718SPierre Ossman #define SDHCI_CMD_INDEX 0x10 491c6a0718SPierre Ossman #define SDHCI_CMD_DATA 0x20 50574e3f56SRichard Zhu #define SDHCI_CMD_ABORTCMD 0xC0 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman #define SDHCI_CMD_RESP_NONE 0x00 531c6a0718SPierre Ossman #define SDHCI_CMD_RESP_LONG 0x01 541c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT 0x02 551c6a0718SPierre Ossman #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 561c6a0718SPierre Ossman 571c6a0718SPierre Ossman #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 5822113efdSAries Lee #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 591c6a0718SPierre Ossman 601c6a0718SPierre Ossman #define SDHCI_RESPONSE 0x10 611c6a0718SPierre Ossman 621c6a0718SPierre Ossman #define SDHCI_BUFFER 0x20 631c6a0718SPierre Ossman 641c6a0718SPierre Ossman #define SDHCI_PRESENT_STATE 0x24 651c6a0718SPierre Ossman #define SDHCI_CMD_INHIBIT 0x00000001 661c6a0718SPierre Ossman #define SDHCI_DATA_INHIBIT 0x00000002 671c6a0718SPierre Ossman #define SDHCI_DOING_WRITE 0x00000100 681c6a0718SPierre Ossman #define SDHCI_DOING_READ 0x00000200 691c6a0718SPierre Ossman #define SDHCI_SPACE_AVAILABLE 0x00000400 701c6a0718SPierre Ossman #define SDHCI_DATA_AVAILABLE 0x00000800 711c6a0718SPierre Ossman #define SDHCI_CARD_PRESENT 0x00010000 721c6a0718SPierre Ossman #define SDHCI_WRITE_PROTECT 0x00080000 73f2119df6SArindam Nath #define SDHCI_DATA_LVL_MASK 0x00F00000 74f2119df6SArindam Nath #define SDHCI_DATA_LVL_SHIFT 20 751c6a0718SPierre Ossman 761c6a0718SPierre Ossman #define SDHCI_HOST_CONTROL 0x28 771c6a0718SPierre Ossman #define SDHCI_CTRL_LED 0x01 781c6a0718SPierre Ossman #define SDHCI_CTRL_4BITBUS 0x02 791c6a0718SPierre Ossman #define SDHCI_CTRL_HISPD 0x04 802134a922SPierre Ossman #define SDHCI_CTRL_DMA_MASK 0x18 812134a922SPierre Ossman #define SDHCI_CTRL_SDMA 0x00 822134a922SPierre Ossman #define SDHCI_CTRL_ADMA1 0x08 832134a922SPierre Ossman #define SDHCI_CTRL_ADMA32 0x10 842134a922SPierre Ossman #define SDHCI_CTRL_ADMA64 0x18 85ae6d6c92SKyungmin Park #define SDHCI_CTRL_8BITBUS 0x20 861c6a0718SPierre Ossman 871c6a0718SPierre Ossman #define SDHCI_POWER_CONTROL 0x29 881c6a0718SPierre Ossman #define SDHCI_POWER_ON 0x01 891c6a0718SPierre Ossman #define SDHCI_POWER_180 0x0A 901c6a0718SPierre Ossman #define SDHCI_POWER_300 0x0C 911c6a0718SPierre Ossman #define SDHCI_POWER_330 0x0E 921c6a0718SPierre Ossman 931c6a0718SPierre Ossman #define SDHCI_BLOCK_GAP_CONTROL 0x2A 941c6a0718SPierre Ossman 952df3b71bSNicolas Pitre #define SDHCI_WAKE_UP_CONTROL 0x2B 965f619704SDaniel Drake #define SDHCI_WAKE_ON_INT 0x01 975f619704SDaniel Drake #define SDHCI_WAKE_ON_INSERT 0x02 985f619704SDaniel Drake #define SDHCI_WAKE_ON_REMOVE 0x04 991c6a0718SPierre Ossman 1001c6a0718SPierre Ossman #define SDHCI_CLOCK_CONTROL 0x2C 1011c6a0718SPierre Ossman #define SDHCI_DIVIDER_SHIFT 8 10285105c53SZhangfei Gao #define SDHCI_DIVIDER_HI_SHIFT 6 10385105c53SZhangfei Gao #define SDHCI_DIV_MASK 0xFF 10485105c53SZhangfei Gao #define SDHCI_DIV_MASK_LEN 8 10585105c53SZhangfei Gao #define SDHCI_DIV_HI_MASK 0x300 106c3ed3877SArindam Nath #define SDHCI_PROG_CLOCK_MODE 0x0020 1071c6a0718SPierre Ossman #define SDHCI_CLOCK_CARD_EN 0x0004 1081c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_STABLE 0x0002 1091c6a0718SPierre Ossman #define SDHCI_CLOCK_INT_EN 0x0001 1101c6a0718SPierre Ossman 1111c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CONTROL 0x2E 1121c6a0718SPierre Ossman 1131c6a0718SPierre Ossman #define SDHCI_SOFTWARE_RESET 0x2F 1141c6a0718SPierre Ossman #define SDHCI_RESET_ALL 0x01 1151c6a0718SPierre Ossman #define SDHCI_RESET_CMD 0x02 1161c6a0718SPierre Ossman #define SDHCI_RESET_DATA 0x04 1171c6a0718SPierre Ossman 1181c6a0718SPierre Ossman #define SDHCI_INT_STATUS 0x30 1191c6a0718SPierre Ossman #define SDHCI_INT_ENABLE 0x34 1201c6a0718SPierre Ossman #define SDHCI_SIGNAL_ENABLE 0x38 1211c6a0718SPierre Ossman #define SDHCI_INT_RESPONSE 0x00000001 1221c6a0718SPierre Ossman #define SDHCI_INT_DATA_END 0x00000002 1231c6a0718SPierre Ossman #define SDHCI_INT_DMA_END 0x00000008 1241c6a0718SPierre Ossman #define SDHCI_INT_SPACE_AVAIL 0x00000010 1251c6a0718SPierre Ossman #define SDHCI_INT_DATA_AVAIL 0x00000020 1261c6a0718SPierre Ossman #define SDHCI_INT_CARD_INSERT 0x00000040 1271c6a0718SPierre Ossman #define SDHCI_INT_CARD_REMOVE 0x00000080 1281c6a0718SPierre Ossman #define SDHCI_INT_CARD_INT 0x00000100 129964f9ce2SPierre Ossman #define SDHCI_INT_ERROR 0x00008000 1301c6a0718SPierre Ossman #define SDHCI_INT_TIMEOUT 0x00010000 1311c6a0718SPierre Ossman #define SDHCI_INT_CRC 0x00020000 1321c6a0718SPierre Ossman #define SDHCI_INT_END_BIT 0x00040000 1331c6a0718SPierre Ossman #define SDHCI_INT_INDEX 0x00080000 1341c6a0718SPierre Ossman #define SDHCI_INT_DATA_TIMEOUT 0x00100000 1351c6a0718SPierre Ossman #define SDHCI_INT_DATA_CRC 0x00200000 1361c6a0718SPierre Ossman #define SDHCI_INT_DATA_END_BIT 0x00400000 1371c6a0718SPierre Ossman #define SDHCI_INT_BUS_POWER 0x00800000 1381c6a0718SPierre Ossman #define SDHCI_INT_ACMD12ERR 0x01000000 1392134a922SPierre Ossman #define SDHCI_INT_ADMA_ERROR 0x02000000 1401c6a0718SPierre Ossman 1411c6a0718SPierre Ossman #define SDHCI_INT_NORMAL_MASK 0x00007FFF 1421c6a0718SPierre Ossman #define SDHCI_INT_ERROR_MASK 0xFFFF8000 1431c6a0718SPierre Ossman 1441c6a0718SPierre Ossman #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 1451c6a0718SPierre Ossman SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 1461c6a0718SPierre Ossman #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 1471c6a0718SPierre Ossman SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 1481c6a0718SPierre Ossman SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 149a751a7d6SZhangfei Gao SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 1507260cf5eSAnton Vorontsov #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 1511c6a0718SPierre Ossman 1521c6a0718SPierre Ossman #define SDHCI_ACMD12_ERR 0x3C 1531c6a0718SPierre Ossman 154f2119df6SArindam Nath #define SDHCI_HOST_CONTROL2 0x3E 15549c468fcSArindam Nath #define SDHCI_CTRL_UHS_MASK 0x0007 15649c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR12 0x0000 15749c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR25 0x0001 15849c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR50 0x0002 15949c468fcSArindam Nath #define SDHCI_CTRL_UHS_SDR104 0x0003 16049c468fcSArindam Nath #define SDHCI_CTRL_UHS_DDR50 0x0004 161069c9f14SGirish K S #define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */ 162f2119df6SArindam Nath #define SDHCI_CTRL_VDD_180 0x0008 163d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 164d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_B 0x0000 165d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_A 0x0010 166d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_C 0x0020 167d6d50a15SArindam Nath #define SDHCI_CTRL_DRV_TYPE_D 0x0030 168b513ea25SArindam Nath #define SDHCI_CTRL_EXEC_TUNING 0x0040 169b513ea25SArindam Nath #define SDHCI_CTRL_TUNED_CLK 0x0080 170d6d50a15SArindam Nath #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 1711c6a0718SPierre Ossman 1721c6a0718SPierre Ossman #define SDHCI_CAPABILITIES 0x40 1731c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 1741c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_SHIFT 0 1751c6a0718SPierre Ossman #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 1761c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_MASK 0x00003F00 177c4687d5fSZhangfei Gao #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 1781c6a0718SPierre Ossman #define SDHCI_CLOCK_BASE_SHIFT 8 1791c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_MASK 0x00030000 1801c6a0718SPierre Ossman #define SDHCI_MAX_BLOCK_SHIFT 16 18115ec4461SPhilip Rakity #define SDHCI_CAN_DO_8BIT 0x00040000 1822134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA2 0x00080000 1832134a922SPierre Ossman #define SDHCI_CAN_DO_ADMA1 0x00100000 1841c6a0718SPierre Ossman #define SDHCI_CAN_DO_HISPD 0x00200000 185a13abc7bSRichard Röjfors #define SDHCI_CAN_DO_SDMA 0x00400000 1861c6a0718SPierre Ossman #define SDHCI_CAN_VDD_330 0x01000000 1871c6a0718SPierre Ossman #define SDHCI_CAN_VDD_300 0x02000000 1881c6a0718SPierre Ossman #define SDHCI_CAN_VDD_180 0x04000000 1892134a922SPierre Ossman #define SDHCI_CAN_64BIT 0x10000000 1901c6a0718SPierre Ossman 191f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR50 0x00000001 192f2119df6SArindam Nath #define SDHCI_SUPPORT_SDR104 0x00000002 193f2119df6SArindam Nath #define SDHCI_SUPPORT_DDR50 0x00000004 194d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_A 0x00000010 195d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_C 0x00000020 196d6d50a15SArindam Nath #define SDHCI_DRIVER_TYPE_D 0x00000040 197cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 198cf2b5eeaSArindam Nath #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 199b513ea25SArindam Nath #define SDHCI_USE_SDR50_TUNING 0x00002000 200cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_MASK 0x0000C000 201cf2b5eeaSArindam Nath #define SDHCI_RETUNING_MODE_SHIFT 14 202c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 203c3ed3877SArindam Nath #define SDHCI_CLOCK_MUL_SHIFT 16 204f2119df6SArindam Nath 205e8120ad1SPhilip Rakity #define SDHCI_CAPABILITIES_1 0x44 2061c6a0718SPierre Ossman 2071c6a0718SPierre Ossman #define SDHCI_MAX_CURRENT 0x48 208f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 209f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_330_SHIFT 0 210f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 211f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_300_SHIFT 8 212f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 213f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_180_SHIFT 16 214f2119df6SArindam Nath #define SDHCI_MAX_CURRENT_MULTIPLIER 4 2151c6a0718SPierre Ossman 2161c6a0718SPierre Ossman /* 4C-4F reserved for more max current */ 2171c6a0718SPierre Ossman 2182134a922SPierre Ossman #define SDHCI_SET_ACMD12_ERROR 0x50 2192134a922SPierre Ossman #define SDHCI_SET_INT_ERROR 0x52 2202134a922SPierre Ossman 2212134a922SPierre Ossman #define SDHCI_ADMA_ERROR 0x54 2222134a922SPierre Ossman 2232134a922SPierre Ossman /* 55-57 reserved */ 2242134a922SPierre Ossman 2252134a922SPierre Ossman #define SDHCI_ADMA_ADDRESS 0x58 2262134a922SPierre Ossman 2272134a922SPierre Ossman /* 60-FB reserved */ 2281c6a0718SPierre Ossman 2291c6a0718SPierre Ossman #define SDHCI_SLOT_INT_STATUS 0xFC 2301c6a0718SPierre Ossman 2311c6a0718SPierre Ossman #define SDHCI_HOST_VERSION 0xFE 2321c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_MASK 0xFF00 2331c6a0718SPierre Ossman #define SDHCI_VENDOR_VER_SHIFT 8 2341c6a0718SPierre Ossman #define SDHCI_SPEC_VER_MASK 0x00FF 2351c6a0718SPierre Ossman #define SDHCI_SPEC_VER_SHIFT 0 2362134a922SPierre Ossman #define SDHCI_SPEC_100 0 2372134a922SPierre Ossman #define SDHCI_SPEC_200 1 23885105c53SZhangfei Gao #define SDHCI_SPEC_300 2 2391c6a0718SPierre Ossman 2400397526dSZhangfei Gao /* 2410397526dSZhangfei Gao * End of controller registers. 2420397526dSZhangfei Gao */ 2430397526dSZhangfei Gao 2440397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_200 256 2450397526dSZhangfei Gao #define SDHCI_MAX_DIV_SPEC_300 2046 2460397526dSZhangfei Gao 247f6a03cbfSMikko Vinni /* 248f6a03cbfSMikko Vinni * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 249f6a03cbfSMikko Vinni */ 250f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 251f6a03cbfSMikko Vinni #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 252f6a03cbfSMikko Vinni 253b8c86fc5SPierre Ossman struct sdhci_ops { 2544e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 255dc297c92SMatt Fleming u32 (*read_l)(struct sdhci_host *host, int reg); 256dc297c92SMatt Fleming u16 (*read_w)(struct sdhci_host *host, int reg); 257dc297c92SMatt Fleming u8 (*read_b)(struct sdhci_host *host, int reg); 258dc297c92SMatt Fleming void (*write_l)(struct sdhci_host *host, u32 val, int reg); 259dc297c92SMatt Fleming void (*write_w)(struct sdhci_host *host, u16 val, int reg); 260dc297c92SMatt Fleming void (*write_b)(struct sdhci_host *host, u8 val, int reg); 2614e4141a5SAnton Vorontsov #endif 2624e4141a5SAnton Vorontsov 2638114634cSAnton Vorontsov void (*set_clock)(struct sdhci_host *host, unsigned int clock); 2648114634cSAnton Vorontsov 265b8c86fc5SPierre Ossman int (*enable_dma)(struct sdhci_host *host); 2664240ff0aSBen Dooks unsigned int (*get_max_clock)(struct sdhci_host *host); 267a9e58f25SAnton Vorontsov unsigned int (*get_min_clock)(struct sdhci_host *host); 2684240ff0aSBen Dooks unsigned int (*get_timeout_clock)(struct sdhci_host *host); 26915ec4461SPhilip Rakity int (*platform_8bit_width)(struct sdhci_host *host, 27015ec4461SPhilip Rakity int width); 271643a81ffSPhilip Rakity void (*platform_send_init_74_clocks)(struct sdhci_host *host, 272643a81ffSPhilip Rakity u8 power_mode); 2732dfb579cSWolfram Sang unsigned int (*get_ro)(struct sdhci_host *host); 274393c1a34SPhilip Rakity void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); 275393c1a34SPhilip Rakity void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); 2766322cdd0SPhilip Rakity int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 27720758b66SAdrian Hunter void (*hw_reset)(struct sdhci_host *host); 2781c6a0718SPierre Ossman }; 279b8c86fc5SPierre Ossman 2804e4141a5SAnton Vorontsov #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 2814e4141a5SAnton Vorontsov 2824e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 2834e4141a5SAnton Vorontsov { 284dc297c92SMatt Fleming if (unlikely(host->ops->write_l)) 285dc297c92SMatt Fleming host->ops->write_l(host, val, reg); 2864e4141a5SAnton Vorontsov else 2874e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 2884e4141a5SAnton Vorontsov } 2894e4141a5SAnton Vorontsov 2904e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 2914e4141a5SAnton Vorontsov { 292dc297c92SMatt Fleming if (unlikely(host->ops->write_w)) 293dc297c92SMatt Fleming host->ops->write_w(host, val, reg); 2944e4141a5SAnton Vorontsov else 2954e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 2964e4141a5SAnton Vorontsov } 2974e4141a5SAnton Vorontsov 2984e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 2994e4141a5SAnton Vorontsov { 300dc297c92SMatt Fleming if (unlikely(host->ops->write_b)) 301dc297c92SMatt Fleming host->ops->write_b(host, val, reg); 3024e4141a5SAnton Vorontsov else 3034e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3044e4141a5SAnton Vorontsov } 3054e4141a5SAnton Vorontsov 3064e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3074e4141a5SAnton Vorontsov { 308dc297c92SMatt Fleming if (unlikely(host->ops->read_l)) 309dc297c92SMatt Fleming return host->ops->read_l(host, reg); 3104e4141a5SAnton Vorontsov else 3114e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3124e4141a5SAnton Vorontsov } 3134e4141a5SAnton Vorontsov 3144e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3154e4141a5SAnton Vorontsov { 316dc297c92SMatt Fleming if (unlikely(host->ops->read_w)) 317dc297c92SMatt Fleming return host->ops->read_w(host, reg); 3184e4141a5SAnton Vorontsov else 3194e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3204e4141a5SAnton Vorontsov } 3214e4141a5SAnton Vorontsov 3224e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3234e4141a5SAnton Vorontsov { 324dc297c92SMatt Fleming if (unlikely(host->ops->read_b)) 325dc297c92SMatt Fleming return host->ops->read_b(host, reg); 3264e4141a5SAnton Vorontsov else 3274e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3284e4141a5SAnton Vorontsov } 3294e4141a5SAnton Vorontsov 3304e4141a5SAnton Vorontsov #else 3314e4141a5SAnton Vorontsov 3324e4141a5SAnton Vorontsov static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 3334e4141a5SAnton Vorontsov { 3344e4141a5SAnton Vorontsov writel(val, host->ioaddr + reg); 3354e4141a5SAnton Vorontsov } 3364e4141a5SAnton Vorontsov 3374e4141a5SAnton Vorontsov static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 3384e4141a5SAnton Vorontsov { 3394e4141a5SAnton Vorontsov writew(val, host->ioaddr + reg); 3404e4141a5SAnton Vorontsov } 3414e4141a5SAnton Vorontsov 3424e4141a5SAnton Vorontsov static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 3434e4141a5SAnton Vorontsov { 3444e4141a5SAnton Vorontsov writeb(val, host->ioaddr + reg); 3454e4141a5SAnton Vorontsov } 3464e4141a5SAnton Vorontsov 3474e4141a5SAnton Vorontsov static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 3484e4141a5SAnton Vorontsov { 3494e4141a5SAnton Vorontsov return readl(host->ioaddr + reg); 3504e4141a5SAnton Vorontsov } 3514e4141a5SAnton Vorontsov 3524e4141a5SAnton Vorontsov static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 3534e4141a5SAnton Vorontsov { 3544e4141a5SAnton Vorontsov return readw(host->ioaddr + reg); 3554e4141a5SAnton Vorontsov } 3564e4141a5SAnton Vorontsov 3574e4141a5SAnton Vorontsov static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 3584e4141a5SAnton Vorontsov { 3594e4141a5SAnton Vorontsov return readb(host->ioaddr + reg); 3604e4141a5SAnton Vorontsov } 3614e4141a5SAnton Vorontsov 3624e4141a5SAnton Vorontsov #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 363b8c86fc5SPierre Ossman 364b8c86fc5SPierre Ossman extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 365b8c86fc5SPierre Ossman size_t priv_size); 366b8c86fc5SPierre Ossman extern void sdhci_free_host(struct sdhci_host *host); 367b8c86fc5SPierre Ossman 368b8c86fc5SPierre Ossman static inline void *sdhci_priv(struct sdhci_host *host) 369b8c86fc5SPierre Ossman { 370b8c86fc5SPierre Ossman return (void *)host->private; 371b8c86fc5SPierre Ossman } 372b8c86fc5SPierre Ossman 37317866e14SMarek Szyprowski extern void sdhci_card_detect(struct sdhci_host *host); 374b8c86fc5SPierre Ossman extern int sdhci_add_host(struct sdhci_host *host); 3751e72859eSPierre Ossman extern void sdhci_remove_host(struct sdhci_host *host, int dead); 376b8c86fc5SPierre Ossman 377b8c86fc5SPierre Ossman #ifdef CONFIG_PM 37829495aa0SManuel Lauss extern int sdhci_suspend_host(struct sdhci_host *host); 379b8c86fc5SPierre Ossman extern int sdhci_resume_host(struct sdhci_host *host); 3805f619704SDaniel Drake extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 381b8c86fc5SPierre Ossman #endif 382c0bba0d2SAlbert Herranz 38366fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 38466fd8ad5SAdrian Hunter extern int sdhci_runtime_suspend_host(struct sdhci_host *host); 38566fd8ad5SAdrian Hunter extern int sdhci_runtime_resume_host(struct sdhci_host *host); 38666fd8ad5SAdrian Hunter #endif 38766fd8ad5SAdrian Hunter 3881978fda8SGiuseppe Cavallaro #endif /* __SDHCI_HW_H */ 389