1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #include "sdhci.h" 35 36 #define DRIVER_NAME "sdhci" 37 38 #define DBG(f, x...) \ 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 40 41 #define MAX_TUNING_LOOP 40 42 43 static unsigned int debug_quirks = 0; 44 static unsigned int debug_quirks2; 45 46 static void sdhci_finish_data(struct sdhci_host *); 47 48 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 49 50 static void sdhci_dumpregs(struct sdhci_host *host) 51 { 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 53 mmc_hostname(host->mmc)); 54 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 56 sdhci_readl(host, SDHCI_DMA_ADDRESS), 57 sdhci_readw(host, SDHCI_HOST_VERSION)); 58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 59 sdhci_readw(host, SDHCI_BLOCK_SIZE), 60 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 62 sdhci_readl(host, SDHCI_ARGUMENT), 63 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 65 sdhci_readl(host, SDHCI_PRESENT_STATE), 66 sdhci_readb(host, SDHCI_HOST_CONTROL)); 67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 68 sdhci_readb(host, SDHCI_POWER_CONTROL), 69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 72 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 75 sdhci_readl(host, SDHCI_INT_STATUS)); 76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 77 sdhci_readl(host, SDHCI_INT_ENABLE), 78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 80 sdhci_readw(host, SDHCI_ACMD12_ERR), 81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 83 sdhci_readl(host, SDHCI_CAPABILITIES), 84 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 86 sdhci_readw(host, SDHCI_COMMAND), 87 sdhci_readl(host, SDHCI_MAX_CURRENT)); 88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n", 89 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 90 91 if (host->flags & SDHCI_USE_ADMA) { 92 if (host->flags & SDHCI_USE_64_BIT_DMA) 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 94 readl(host->ioaddr + SDHCI_ADMA_ERROR), 95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 97 else 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 99 readl(host->ioaddr + SDHCI_ADMA_ERROR), 100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 101 } 102 103 pr_err(DRIVER_NAME ": ===========================================\n"); 104 } 105 106 /*****************************************************************************\ 107 * * 108 * Low level functions * 109 * * 110 \*****************************************************************************/ 111 112 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 113 { 114 return cmd->data || cmd->flags & MMC_RSP_BUSY; 115 } 116 117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 118 { 119 u32 present; 120 121 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 122 !mmc_card_is_removable(host->mmc)) 123 return; 124 125 if (enable) { 126 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 127 SDHCI_CARD_PRESENT; 128 129 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 130 SDHCI_INT_CARD_INSERT; 131 } else { 132 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 133 } 134 135 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 136 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 137 } 138 139 static void sdhci_enable_card_detection(struct sdhci_host *host) 140 { 141 sdhci_set_card_detection(host, true); 142 } 143 144 static void sdhci_disable_card_detection(struct sdhci_host *host) 145 { 146 sdhci_set_card_detection(host, false); 147 } 148 149 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 150 { 151 if (host->bus_on) 152 return; 153 host->bus_on = true; 154 pm_runtime_get_noresume(host->mmc->parent); 155 } 156 157 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 158 { 159 if (!host->bus_on) 160 return; 161 host->bus_on = false; 162 pm_runtime_put_noidle(host->mmc->parent); 163 } 164 165 void sdhci_reset(struct sdhci_host *host, u8 mask) 166 { 167 unsigned long timeout; 168 169 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 170 171 if (mask & SDHCI_RESET_ALL) { 172 host->clock = 0; 173 /* Reset-all turns off SD Bus Power */ 174 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 175 sdhci_runtime_pm_bus_off(host); 176 } 177 178 /* Wait max 100 ms */ 179 timeout = 100; 180 181 /* hw clears the bit when it's done */ 182 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 183 if (timeout == 0) { 184 pr_err("%s: Reset 0x%x never completed.\n", 185 mmc_hostname(host->mmc), (int)mask); 186 sdhci_dumpregs(host); 187 return; 188 } 189 timeout--; 190 mdelay(1); 191 } 192 } 193 EXPORT_SYMBOL_GPL(sdhci_reset); 194 195 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 196 { 197 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 198 struct mmc_host *mmc = host->mmc; 199 200 if (!mmc->ops->get_cd(mmc)) 201 return; 202 } 203 204 host->ops->reset(host, mask); 205 206 if (mask & SDHCI_RESET_ALL) { 207 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 208 if (host->ops->enable_dma) 209 host->ops->enable_dma(host); 210 } 211 212 /* Resetting the controller clears many */ 213 host->preset_enabled = false; 214 } 215 } 216 217 static void sdhci_init(struct sdhci_host *host, int soft) 218 { 219 struct mmc_host *mmc = host->mmc; 220 221 if (soft) 222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 223 else 224 sdhci_do_reset(host, SDHCI_RESET_ALL); 225 226 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 228 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 230 SDHCI_INT_RESPONSE; 231 232 if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 233 host->tuning_mode == SDHCI_TUNING_MODE_3) 234 host->ier |= SDHCI_INT_RETUNE; 235 236 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 237 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 238 239 if (soft) { 240 /* force clock reconfiguration */ 241 host->clock = 0; 242 mmc->ops->set_ios(mmc, &mmc->ios); 243 } 244 } 245 246 static void sdhci_reinit(struct sdhci_host *host) 247 { 248 sdhci_init(host, 0); 249 sdhci_enable_card_detection(host); 250 } 251 252 static void __sdhci_led_activate(struct sdhci_host *host) 253 { 254 u8 ctrl; 255 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 257 ctrl |= SDHCI_CTRL_LED; 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 259 } 260 261 static void __sdhci_led_deactivate(struct sdhci_host *host) 262 { 263 u8 ctrl; 264 265 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 266 ctrl &= ~SDHCI_CTRL_LED; 267 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 268 } 269 270 #if IS_REACHABLE(CONFIG_LEDS_CLASS) 271 static void sdhci_led_control(struct led_classdev *led, 272 enum led_brightness brightness) 273 { 274 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 275 unsigned long flags; 276 277 spin_lock_irqsave(&host->lock, flags); 278 279 if (host->runtime_suspended) 280 goto out; 281 282 if (brightness == LED_OFF) 283 __sdhci_led_deactivate(host); 284 else 285 __sdhci_led_activate(host); 286 out: 287 spin_unlock_irqrestore(&host->lock, flags); 288 } 289 290 static int sdhci_led_register(struct sdhci_host *host) 291 { 292 struct mmc_host *mmc = host->mmc; 293 294 snprintf(host->led_name, sizeof(host->led_name), 295 "%s::", mmc_hostname(mmc)); 296 297 host->led.name = host->led_name; 298 host->led.brightness = LED_OFF; 299 host->led.default_trigger = mmc_hostname(mmc); 300 host->led.brightness_set = sdhci_led_control; 301 302 return led_classdev_register(mmc_dev(mmc), &host->led); 303 } 304 305 static void sdhci_led_unregister(struct sdhci_host *host) 306 { 307 led_classdev_unregister(&host->led); 308 } 309 310 static inline void sdhci_led_activate(struct sdhci_host *host) 311 { 312 } 313 314 static inline void sdhci_led_deactivate(struct sdhci_host *host) 315 { 316 } 317 318 #else 319 320 static inline int sdhci_led_register(struct sdhci_host *host) 321 { 322 return 0; 323 } 324 325 static inline void sdhci_led_unregister(struct sdhci_host *host) 326 { 327 } 328 329 static inline void sdhci_led_activate(struct sdhci_host *host) 330 { 331 __sdhci_led_activate(host); 332 } 333 334 static inline void sdhci_led_deactivate(struct sdhci_host *host) 335 { 336 __sdhci_led_deactivate(host); 337 } 338 339 #endif 340 341 /*****************************************************************************\ 342 * * 343 * Core functions * 344 * * 345 \*****************************************************************************/ 346 347 static void sdhci_read_block_pio(struct sdhci_host *host) 348 { 349 unsigned long flags; 350 size_t blksize, len, chunk; 351 u32 uninitialized_var(scratch); 352 u8 *buf; 353 354 DBG("PIO reading\n"); 355 356 blksize = host->data->blksz; 357 chunk = 0; 358 359 local_irq_save(flags); 360 361 while (blksize) { 362 BUG_ON(!sg_miter_next(&host->sg_miter)); 363 364 len = min(host->sg_miter.length, blksize); 365 366 blksize -= len; 367 host->sg_miter.consumed = len; 368 369 buf = host->sg_miter.addr; 370 371 while (len) { 372 if (chunk == 0) { 373 scratch = sdhci_readl(host, SDHCI_BUFFER); 374 chunk = 4; 375 } 376 377 *buf = scratch & 0xFF; 378 379 buf++; 380 scratch >>= 8; 381 chunk--; 382 len--; 383 } 384 } 385 386 sg_miter_stop(&host->sg_miter); 387 388 local_irq_restore(flags); 389 } 390 391 static void sdhci_write_block_pio(struct sdhci_host *host) 392 { 393 unsigned long flags; 394 size_t blksize, len, chunk; 395 u32 scratch; 396 u8 *buf; 397 398 DBG("PIO writing\n"); 399 400 blksize = host->data->blksz; 401 chunk = 0; 402 scratch = 0; 403 404 local_irq_save(flags); 405 406 while (blksize) { 407 BUG_ON(!sg_miter_next(&host->sg_miter)); 408 409 len = min(host->sg_miter.length, blksize); 410 411 blksize -= len; 412 host->sg_miter.consumed = len; 413 414 buf = host->sg_miter.addr; 415 416 while (len) { 417 scratch |= (u32)*buf << (chunk * 8); 418 419 buf++; 420 chunk++; 421 len--; 422 423 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 424 sdhci_writel(host, scratch, SDHCI_BUFFER); 425 chunk = 0; 426 scratch = 0; 427 } 428 } 429 } 430 431 sg_miter_stop(&host->sg_miter); 432 433 local_irq_restore(flags); 434 } 435 436 static void sdhci_transfer_pio(struct sdhci_host *host) 437 { 438 u32 mask; 439 440 if (host->blocks == 0) 441 return; 442 443 if (host->data->flags & MMC_DATA_READ) 444 mask = SDHCI_DATA_AVAILABLE; 445 else 446 mask = SDHCI_SPACE_AVAILABLE; 447 448 /* 449 * Some controllers (JMicron JMB38x) mess up the buffer bits 450 * for transfers < 4 bytes. As long as it is just one block, 451 * we can ignore the bits. 452 */ 453 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 454 (host->data->blocks == 1)) 455 mask = ~0; 456 457 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 458 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 459 udelay(100); 460 461 if (host->data->flags & MMC_DATA_READ) 462 sdhci_read_block_pio(host); 463 else 464 sdhci_write_block_pio(host); 465 466 host->blocks--; 467 if (host->blocks == 0) 468 break; 469 } 470 471 DBG("PIO transfer complete.\n"); 472 } 473 474 static int sdhci_pre_dma_transfer(struct sdhci_host *host, 475 struct mmc_data *data, int cookie) 476 { 477 int sg_count; 478 479 /* 480 * If the data buffers are already mapped, return the previous 481 * dma_map_sg() result. 482 */ 483 if (data->host_cookie == COOKIE_PRE_MAPPED) 484 return data->sg_count; 485 486 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 487 data->flags & MMC_DATA_WRITE ? 488 DMA_TO_DEVICE : DMA_FROM_DEVICE); 489 490 if (sg_count == 0) 491 return -ENOSPC; 492 493 data->sg_count = sg_count; 494 data->host_cookie = cookie; 495 496 return sg_count; 497 } 498 499 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 500 { 501 local_irq_save(*flags); 502 return kmap_atomic(sg_page(sg)) + sg->offset; 503 } 504 505 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 506 { 507 kunmap_atomic(buffer); 508 local_irq_restore(*flags); 509 } 510 511 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 512 dma_addr_t addr, int len, unsigned cmd) 513 { 514 struct sdhci_adma2_64_desc *dma_desc = desc; 515 516 /* 32-bit and 64-bit descriptors have these members in same position */ 517 dma_desc->cmd = cpu_to_le16(cmd); 518 dma_desc->len = cpu_to_le16(len); 519 dma_desc->addr_lo = cpu_to_le32((u32)addr); 520 521 if (host->flags & SDHCI_USE_64_BIT_DMA) 522 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 523 } 524 525 static void sdhci_adma_mark_end(void *desc) 526 { 527 struct sdhci_adma2_64_desc *dma_desc = desc; 528 529 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 530 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 531 } 532 533 static void sdhci_adma_table_pre(struct sdhci_host *host, 534 struct mmc_data *data, int sg_count) 535 { 536 struct scatterlist *sg; 537 unsigned long flags; 538 dma_addr_t addr, align_addr; 539 void *desc, *align; 540 char *buffer; 541 int len, offset, i; 542 543 /* 544 * The spec does not specify endianness of descriptor table. 545 * We currently guess that it is LE. 546 */ 547 548 host->sg_count = sg_count; 549 550 desc = host->adma_table; 551 align = host->align_buffer; 552 553 align_addr = host->align_addr; 554 555 for_each_sg(data->sg, sg, host->sg_count, i) { 556 addr = sg_dma_address(sg); 557 len = sg_dma_len(sg); 558 559 /* 560 * The SDHCI specification states that ADMA addresses must 561 * be 32-bit aligned. If they aren't, then we use a bounce 562 * buffer for the (up to three) bytes that screw up the 563 * alignment. 564 */ 565 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 566 SDHCI_ADMA2_MASK; 567 if (offset) { 568 if (data->flags & MMC_DATA_WRITE) { 569 buffer = sdhci_kmap_atomic(sg, &flags); 570 memcpy(align, buffer, offset); 571 sdhci_kunmap_atomic(buffer, &flags); 572 } 573 574 /* tran, valid */ 575 sdhci_adma_write_desc(host, desc, align_addr, offset, 576 ADMA2_TRAN_VALID); 577 578 BUG_ON(offset > 65536); 579 580 align += SDHCI_ADMA2_ALIGN; 581 align_addr += SDHCI_ADMA2_ALIGN; 582 583 desc += host->desc_sz; 584 585 addr += offset; 586 len -= offset; 587 } 588 589 BUG_ON(len > 65536); 590 591 if (len) { 592 /* tran, valid */ 593 sdhci_adma_write_desc(host, desc, addr, len, 594 ADMA2_TRAN_VALID); 595 desc += host->desc_sz; 596 } 597 598 /* 599 * If this triggers then we have a calculation bug 600 * somewhere. :/ 601 */ 602 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 603 } 604 605 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 606 /* Mark the last descriptor as the terminating descriptor */ 607 if (desc != host->adma_table) { 608 desc -= host->desc_sz; 609 sdhci_adma_mark_end(desc); 610 } 611 } else { 612 /* Add a terminating entry - nop, end, valid */ 613 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 614 } 615 } 616 617 static void sdhci_adma_table_post(struct sdhci_host *host, 618 struct mmc_data *data) 619 { 620 struct scatterlist *sg; 621 int i, size; 622 void *align; 623 char *buffer; 624 unsigned long flags; 625 626 if (data->flags & MMC_DATA_READ) { 627 bool has_unaligned = false; 628 629 /* Do a quick scan of the SG list for any unaligned mappings */ 630 for_each_sg(data->sg, sg, host->sg_count, i) 631 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 632 has_unaligned = true; 633 break; 634 } 635 636 if (has_unaligned) { 637 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 638 data->sg_len, DMA_FROM_DEVICE); 639 640 align = host->align_buffer; 641 642 for_each_sg(data->sg, sg, host->sg_count, i) { 643 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 644 size = SDHCI_ADMA2_ALIGN - 645 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 646 647 buffer = sdhci_kmap_atomic(sg, &flags); 648 memcpy(buffer, align, size); 649 sdhci_kunmap_atomic(buffer, &flags); 650 651 align += SDHCI_ADMA2_ALIGN; 652 } 653 } 654 } 655 } 656 } 657 658 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 659 { 660 u8 count; 661 struct mmc_data *data = cmd->data; 662 unsigned target_timeout, current_timeout; 663 664 /* 665 * If the host controller provides us with an incorrect timeout 666 * value, just skip the check and use 0xE. The hardware may take 667 * longer to time out, but that's much better than having a too-short 668 * timeout value. 669 */ 670 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 671 return 0xE; 672 673 /* Unspecified timeout, assume max */ 674 if (!data && !cmd->busy_timeout) 675 return 0xE; 676 677 /* timeout in us */ 678 if (!data) 679 target_timeout = cmd->busy_timeout * 1000; 680 else { 681 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 682 if (host->clock && data->timeout_clks) { 683 unsigned long long val; 684 685 /* 686 * data->timeout_clks is in units of clock cycles. 687 * host->clock is in Hz. target_timeout is in us. 688 * Hence, us = 1000000 * cycles / Hz. Round up. 689 */ 690 val = 1000000 * data->timeout_clks; 691 if (do_div(val, host->clock)) 692 target_timeout++; 693 target_timeout += val; 694 } 695 } 696 697 /* 698 * Figure out needed cycles. 699 * We do this in steps in order to fit inside a 32 bit int. 700 * The first step is the minimum timeout, which will have a 701 * minimum resolution of 6 bits: 702 * (1) 2^13*1000 > 2^22, 703 * (2) host->timeout_clk < 2^16 704 * => 705 * (1) / (2) > 2^6 706 */ 707 count = 0; 708 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 709 while (current_timeout < target_timeout) { 710 count++; 711 current_timeout <<= 1; 712 if (count >= 0xF) 713 break; 714 } 715 716 if (count >= 0xF) { 717 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 718 mmc_hostname(host->mmc), count, cmd->opcode); 719 count = 0xE; 720 } 721 722 return count; 723 } 724 725 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 726 { 727 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 728 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 729 730 if (host->flags & SDHCI_REQ_USE_DMA) 731 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 732 else 733 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 734 735 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 736 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 737 } 738 739 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 740 { 741 u8 count; 742 743 if (host->ops->set_timeout) { 744 host->ops->set_timeout(host, cmd); 745 } else { 746 count = sdhci_calc_timeout(host, cmd); 747 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 748 } 749 } 750 751 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 752 { 753 u8 ctrl; 754 struct mmc_data *data = cmd->data; 755 756 if (sdhci_data_line_cmd(cmd)) 757 sdhci_set_timeout(host, cmd); 758 759 if (!data) 760 return; 761 762 WARN_ON(host->data); 763 764 /* Sanity checks */ 765 BUG_ON(data->blksz * data->blocks > 524288); 766 BUG_ON(data->blksz > host->mmc->max_blk_size); 767 BUG_ON(data->blocks > 65535); 768 769 host->data = data; 770 host->data_early = 0; 771 host->data->bytes_xfered = 0; 772 773 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 774 struct scatterlist *sg; 775 unsigned int length_mask, offset_mask; 776 int i; 777 778 host->flags |= SDHCI_REQ_USE_DMA; 779 780 /* 781 * FIXME: This doesn't account for merging when mapping the 782 * scatterlist. 783 * 784 * The assumption here being that alignment and lengths are 785 * the same after DMA mapping to device address space. 786 */ 787 length_mask = 0; 788 offset_mask = 0; 789 if (host->flags & SDHCI_USE_ADMA) { 790 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 791 length_mask = 3; 792 /* 793 * As we use up to 3 byte chunks to work 794 * around alignment problems, we need to 795 * check the offset as well. 796 */ 797 offset_mask = 3; 798 } 799 } else { 800 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 801 length_mask = 3; 802 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 803 offset_mask = 3; 804 } 805 806 if (unlikely(length_mask | offset_mask)) { 807 for_each_sg(data->sg, sg, data->sg_len, i) { 808 if (sg->length & length_mask) { 809 DBG("Reverting to PIO because of transfer size (%d)\n", 810 sg->length); 811 host->flags &= ~SDHCI_REQ_USE_DMA; 812 break; 813 } 814 if (sg->offset & offset_mask) { 815 DBG("Reverting to PIO because of bad alignment\n"); 816 host->flags &= ~SDHCI_REQ_USE_DMA; 817 break; 818 } 819 } 820 } 821 } 822 823 if (host->flags & SDHCI_REQ_USE_DMA) { 824 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 825 826 if (sg_cnt <= 0) { 827 /* 828 * This only happens when someone fed 829 * us an invalid request. 830 */ 831 WARN_ON(1); 832 host->flags &= ~SDHCI_REQ_USE_DMA; 833 } else if (host->flags & SDHCI_USE_ADMA) { 834 sdhci_adma_table_pre(host, data, sg_cnt); 835 836 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 837 if (host->flags & SDHCI_USE_64_BIT_DMA) 838 sdhci_writel(host, 839 (u64)host->adma_addr >> 32, 840 SDHCI_ADMA_ADDRESS_HI); 841 } else { 842 WARN_ON(sg_cnt != 1); 843 sdhci_writel(host, sg_dma_address(data->sg), 844 SDHCI_DMA_ADDRESS); 845 } 846 } 847 848 /* 849 * Always adjust the DMA selection as some controllers 850 * (e.g. JMicron) can't do PIO properly when the selection 851 * is ADMA. 852 */ 853 if (host->version >= SDHCI_SPEC_200) { 854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 855 ctrl &= ~SDHCI_CTRL_DMA_MASK; 856 if ((host->flags & SDHCI_REQ_USE_DMA) && 857 (host->flags & SDHCI_USE_ADMA)) { 858 if (host->flags & SDHCI_USE_64_BIT_DMA) 859 ctrl |= SDHCI_CTRL_ADMA64; 860 else 861 ctrl |= SDHCI_CTRL_ADMA32; 862 } else { 863 ctrl |= SDHCI_CTRL_SDMA; 864 } 865 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 866 } 867 868 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 869 int flags; 870 871 flags = SG_MITER_ATOMIC; 872 if (host->data->flags & MMC_DATA_READ) 873 flags |= SG_MITER_TO_SG; 874 else 875 flags |= SG_MITER_FROM_SG; 876 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 877 host->blocks = data->blocks; 878 } 879 880 sdhci_set_transfer_irqs(host); 881 882 /* Set the DMA boundary value and block size */ 883 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 884 data->blksz), SDHCI_BLOCK_SIZE); 885 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 886 } 887 888 static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 889 struct mmc_request *mrq) 890 { 891 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 892 !mrq->cap_cmd_during_tfr; 893 } 894 895 static void sdhci_set_transfer_mode(struct sdhci_host *host, 896 struct mmc_command *cmd) 897 { 898 u16 mode = 0; 899 struct mmc_data *data = cmd->data; 900 901 if (data == NULL) { 902 if (host->quirks2 & 903 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 904 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 905 } else { 906 /* clear Auto CMD settings for no data CMDs */ 907 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 908 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 909 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 910 } 911 return; 912 } 913 914 WARN_ON(!host->data); 915 916 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 917 mode = SDHCI_TRNS_BLK_CNT_EN; 918 919 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 920 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 921 /* 922 * If we are sending CMD23, CMD12 never gets sent 923 * on successful completion (so no Auto-CMD12). 924 */ 925 if (sdhci_auto_cmd12(host, cmd->mrq) && 926 (cmd->opcode != SD_IO_RW_EXTENDED)) 927 mode |= SDHCI_TRNS_AUTO_CMD12; 928 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 929 mode |= SDHCI_TRNS_AUTO_CMD23; 930 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 931 } 932 } 933 934 if (data->flags & MMC_DATA_READ) 935 mode |= SDHCI_TRNS_READ; 936 if (host->flags & SDHCI_REQ_USE_DMA) 937 mode |= SDHCI_TRNS_DMA; 938 939 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 940 } 941 942 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 943 { 944 return (!(host->flags & SDHCI_DEVICE_DEAD) && 945 ((mrq->cmd && mrq->cmd->error) || 946 (mrq->sbc && mrq->sbc->error) || 947 (mrq->data && ((mrq->data->error && !mrq->data->stop) || 948 (mrq->data->stop && mrq->data->stop->error))) || 949 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 950 } 951 952 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 953 { 954 int i; 955 956 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 957 if (host->mrqs_done[i] == mrq) { 958 WARN_ON(1); 959 return; 960 } 961 } 962 963 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 964 if (!host->mrqs_done[i]) { 965 host->mrqs_done[i] = mrq; 966 break; 967 } 968 } 969 970 WARN_ON(i >= SDHCI_MAX_MRQS); 971 972 tasklet_schedule(&host->finish_tasklet); 973 } 974 975 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 976 { 977 if (host->cmd && host->cmd->mrq == mrq) 978 host->cmd = NULL; 979 980 if (host->data_cmd && host->data_cmd->mrq == mrq) 981 host->data_cmd = NULL; 982 983 if (host->data && host->data->mrq == mrq) 984 host->data = NULL; 985 986 if (sdhci_needs_reset(host, mrq)) 987 host->pending_reset = true; 988 989 __sdhci_finish_mrq(host, mrq); 990 } 991 992 static void sdhci_finish_data(struct sdhci_host *host) 993 { 994 struct mmc_command *data_cmd = host->data_cmd; 995 struct mmc_data *data = host->data; 996 997 host->data = NULL; 998 host->data_cmd = NULL; 999 1000 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1001 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 1002 sdhci_adma_table_post(host, data); 1003 1004 /* 1005 * The specification states that the block count register must 1006 * be updated, but it does not specify at what point in the 1007 * data flow. That makes the register entirely useless to read 1008 * back so we have to assume that nothing made it to the card 1009 * in the event of an error. 1010 */ 1011 if (data->error) 1012 data->bytes_xfered = 0; 1013 else 1014 data->bytes_xfered = data->blksz * data->blocks; 1015 1016 /* 1017 * Need to send CMD12 if - 1018 * a) open-ended multiblock transfer (no CMD23) 1019 * b) error in multiblock transfer 1020 */ 1021 if (data->stop && 1022 (data->error || 1023 !data->mrq->sbc)) { 1024 1025 /* 1026 * The controller needs a reset of internal state machines 1027 * upon error conditions. 1028 */ 1029 if (data->error) { 1030 if (!host->cmd || host->cmd == data_cmd) 1031 sdhci_do_reset(host, SDHCI_RESET_CMD); 1032 sdhci_do_reset(host, SDHCI_RESET_DATA); 1033 } 1034 1035 /* 1036 * 'cap_cmd_during_tfr' request must not use the command line 1037 * after mmc_command_done() has been called. It is upper layer's 1038 * responsibility to send the stop command if required. 1039 */ 1040 if (data->mrq->cap_cmd_during_tfr) { 1041 sdhci_finish_mrq(host, data->mrq); 1042 } else { 1043 /* Avoid triggering warning in sdhci_send_command() */ 1044 host->cmd = NULL; 1045 sdhci_send_command(host, data->stop); 1046 } 1047 } else { 1048 sdhci_finish_mrq(host, data->mrq); 1049 } 1050 } 1051 1052 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 1053 unsigned long timeout) 1054 { 1055 if (sdhci_data_line_cmd(mrq->cmd)) 1056 mod_timer(&host->data_timer, timeout); 1057 else 1058 mod_timer(&host->timer, timeout); 1059 } 1060 1061 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 1062 { 1063 if (sdhci_data_line_cmd(mrq->cmd)) 1064 del_timer(&host->data_timer); 1065 else 1066 del_timer(&host->timer); 1067 } 1068 1069 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1070 { 1071 int flags; 1072 u32 mask; 1073 unsigned long timeout; 1074 1075 WARN_ON(host->cmd); 1076 1077 /* Initially, a command has no error */ 1078 cmd->error = 0; 1079 1080 /* Wait max 10 ms */ 1081 timeout = 10; 1082 1083 mask = SDHCI_CMD_INHIBIT; 1084 if (sdhci_data_line_cmd(cmd)) 1085 mask |= SDHCI_DATA_INHIBIT; 1086 1087 /* We shouldn't wait for data inihibit for stop commands, even 1088 though they might use busy signaling */ 1089 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 1090 mask &= ~SDHCI_DATA_INHIBIT; 1091 1092 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1093 if (timeout == 0) { 1094 pr_err("%s: Controller never released inhibit bit(s).\n", 1095 mmc_hostname(host->mmc)); 1096 sdhci_dumpregs(host); 1097 cmd->error = -EIO; 1098 sdhci_finish_mrq(host, cmd->mrq); 1099 return; 1100 } 1101 timeout--; 1102 mdelay(1); 1103 } 1104 1105 timeout = jiffies; 1106 if (!cmd->data && cmd->busy_timeout > 9000) 1107 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1108 else 1109 timeout += 10 * HZ; 1110 sdhci_mod_timer(host, cmd->mrq, timeout); 1111 1112 host->cmd = cmd; 1113 if (sdhci_data_line_cmd(cmd)) { 1114 WARN_ON(host->data_cmd); 1115 host->data_cmd = cmd; 1116 } 1117 1118 sdhci_prepare_data(host, cmd); 1119 1120 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1121 1122 sdhci_set_transfer_mode(host, cmd); 1123 1124 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1125 pr_err("%s: Unsupported response type!\n", 1126 mmc_hostname(host->mmc)); 1127 cmd->error = -EINVAL; 1128 sdhci_finish_mrq(host, cmd->mrq); 1129 return; 1130 } 1131 1132 if (!(cmd->flags & MMC_RSP_PRESENT)) 1133 flags = SDHCI_CMD_RESP_NONE; 1134 else if (cmd->flags & MMC_RSP_136) 1135 flags = SDHCI_CMD_RESP_LONG; 1136 else if (cmd->flags & MMC_RSP_BUSY) 1137 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1138 else 1139 flags = SDHCI_CMD_RESP_SHORT; 1140 1141 if (cmd->flags & MMC_RSP_CRC) 1142 flags |= SDHCI_CMD_CRC; 1143 if (cmd->flags & MMC_RSP_OPCODE) 1144 flags |= SDHCI_CMD_INDEX; 1145 1146 /* CMD19 is special in that the Data Present Select should be set */ 1147 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1148 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1149 flags |= SDHCI_CMD_DATA; 1150 1151 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1152 } 1153 EXPORT_SYMBOL_GPL(sdhci_send_command); 1154 1155 static void sdhci_finish_command(struct sdhci_host *host) 1156 { 1157 struct mmc_command *cmd = host->cmd; 1158 int i; 1159 1160 host->cmd = NULL; 1161 1162 if (cmd->flags & MMC_RSP_PRESENT) { 1163 if (cmd->flags & MMC_RSP_136) { 1164 /* CRC is stripped so we need to do some shifting. */ 1165 for (i = 0;i < 4;i++) { 1166 cmd->resp[i] = sdhci_readl(host, 1167 SDHCI_RESPONSE + (3-i)*4) << 8; 1168 if (i != 3) 1169 cmd->resp[i] |= 1170 sdhci_readb(host, 1171 SDHCI_RESPONSE + (3-i)*4-1); 1172 } 1173 } else { 1174 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1175 } 1176 } 1177 1178 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 1179 mmc_command_done(host->mmc, cmd->mrq); 1180 1181 /* 1182 * The host can send and interrupt when the busy state has 1183 * ended, allowing us to wait without wasting CPU cycles. 1184 * The busy signal uses DAT0 so this is similar to waiting 1185 * for data to complete. 1186 * 1187 * Note: The 1.0 specification is a bit ambiguous about this 1188 * feature so there might be some problems with older 1189 * controllers. 1190 */ 1191 if (cmd->flags & MMC_RSP_BUSY) { 1192 if (cmd->data) { 1193 DBG("Cannot wait for busy signal when also doing a data transfer"); 1194 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1195 cmd == host->data_cmd) { 1196 /* Command complete before busy is ended */ 1197 return; 1198 } 1199 } 1200 1201 /* Finished CMD23, now send actual command. */ 1202 if (cmd == cmd->mrq->sbc) { 1203 sdhci_send_command(host, cmd->mrq->cmd); 1204 } else { 1205 1206 /* Processed actual command. */ 1207 if (host->data && host->data_early) 1208 sdhci_finish_data(host); 1209 1210 if (!cmd->data) 1211 sdhci_finish_mrq(host, cmd->mrq); 1212 } 1213 } 1214 1215 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1216 { 1217 u16 preset = 0; 1218 1219 switch (host->timing) { 1220 case MMC_TIMING_UHS_SDR12: 1221 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1222 break; 1223 case MMC_TIMING_UHS_SDR25: 1224 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1225 break; 1226 case MMC_TIMING_UHS_SDR50: 1227 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1228 break; 1229 case MMC_TIMING_UHS_SDR104: 1230 case MMC_TIMING_MMC_HS200: 1231 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1232 break; 1233 case MMC_TIMING_UHS_DDR50: 1234 case MMC_TIMING_MMC_DDR52: 1235 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1236 break; 1237 case MMC_TIMING_MMC_HS400: 1238 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1239 break; 1240 default: 1241 pr_warn("%s: Invalid UHS-I mode selected\n", 1242 mmc_hostname(host->mmc)); 1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1244 break; 1245 } 1246 return preset; 1247 } 1248 1249 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1250 unsigned int *actual_clock) 1251 { 1252 int div = 0; /* Initialized for compiler warning */ 1253 int real_div = div, clk_mul = 1; 1254 u16 clk = 0; 1255 bool switch_base_clk = false; 1256 1257 if (host->version >= SDHCI_SPEC_300) { 1258 if (host->preset_enabled) { 1259 u16 pre_val; 1260 1261 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1262 pre_val = sdhci_get_preset_value(host); 1263 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1264 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1265 if (host->clk_mul && 1266 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1267 clk = SDHCI_PROG_CLOCK_MODE; 1268 real_div = div + 1; 1269 clk_mul = host->clk_mul; 1270 } else { 1271 real_div = max_t(int, 1, div << 1); 1272 } 1273 goto clock_set; 1274 } 1275 1276 /* 1277 * Check if the Host Controller supports Programmable Clock 1278 * Mode. 1279 */ 1280 if (host->clk_mul) { 1281 for (div = 1; div <= 1024; div++) { 1282 if ((host->max_clk * host->clk_mul / div) 1283 <= clock) 1284 break; 1285 } 1286 if ((host->max_clk * host->clk_mul / div) <= clock) { 1287 /* 1288 * Set Programmable Clock Mode in the Clock 1289 * Control register. 1290 */ 1291 clk = SDHCI_PROG_CLOCK_MODE; 1292 real_div = div; 1293 clk_mul = host->clk_mul; 1294 div--; 1295 } else { 1296 /* 1297 * Divisor can be too small to reach clock 1298 * speed requirement. Then use the base clock. 1299 */ 1300 switch_base_clk = true; 1301 } 1302 } 1303 1304 if (!host->clk_mul || switch_base_clk) { 1305 /* Version 3.00 divisors must be a multiple of 2. */ 1306 if (host->max_clk <= clock) 1307 div = 1; 1308 else { 1309 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1310 div += 2) { 1311 if ((host->max_clk / div) <= clock) 1312 break; 1313 } 1314 } 1315 real_div = div; 1316 div >>= 1; 1317 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1318 && !div && host->max_clk <= 25000000) 1319 div = 1; 1320 } 1321 } else { 1322 /* Version 2.00 divisors must be a power of 2. */ 1323 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1324 if ((host->max_clk / div) <= clock) 1325 break; 1326 } 1327 real_div = div; 1328 div >>= 1; 1329 } 1330 1331 clock_set: 1332 if (real_div) 1333 *actual_clock = (host->max_clk * clk_mul) / real_div; 1334 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1335 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1336 << SDHCI_DIVIDER_HI_SHIFT; 1337 1338 return clk; 1339 } 1340 EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1341 1342 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1343 { 1344 u16 clk; 1345 unsigned long timeout; 1346 1347 host->mmc->actual_clock = 0; 1348 1349 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1350 1351 if (clock == 0) 1352 return; 1353 1354 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1355 1356 clk |= SDHCI_CLOCK_INT_EN; 1357 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1358 1359 /* Wait max 20 ms */ 1360 timeout = 20; 1361 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1362 & SDHCI_CLOCK_INT_STABLE)) { 1363 if (timeout == 0) { 1364 pr_err("%s: Internal clock never stabilised.\n", 1365 mmc_hostname(host->mmc)); 1366 sdhci_dumpregs(host); 1367 return; 1368 } 1369 timeout--; 1370 mdelay(1); 1371 } 1372 1373 clk |= SDHCI_CLOCK_CARD_EN; 1374 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1375 } 1376 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1377 1378 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 1379 unsigned short vdd) 1380 { 1381 struct mmc_host *mmc = host->mmc; 1382 1383 spin_unlock_irq(&host->lock); 1384 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1385 spin_lock_irq(&host->lock); 1386 1387 if (mode != MMC_POWER_OFF) 1388 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1389 else 1390 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1391 } 1392 1393 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1394 unsigned short vdd) 1395 { 1396 u8 pwr = 0; 1397 1398 if (mode != MMC_POWER_OFF) { 1399 switch (1 << vdd) { 1400 case MMC_VDD_165_195: 1401 pwr = SDHCI_POWER_180; 1402 break; 1403 case MMC_VDD_29_30: 1404 case MMC_VDD_30_31: 1405 pwr = SDHCI_POWER_300; 1406 break; 1407 case MMC_VDD_32_33: 1408 case MMC_VDD_33_34: 1409 pwr = SDHCI_POWER_330; 1410 break; 1411 default: 1412 WARN(1, "%s: Invalid vdd %#x\n", 1413 mmc_hostname(host->mmc), vdd); 1414 break; 1415 } 1416 } 1417 1418 if (host->pwr == pwr) 1419 return; 1420 1421 host->pwr = pwr; 1422 1423 if (pwr == 0) { 1424 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1425 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1426 sdhci_runtime_pm_bus_off(host); 1427 } else { 1428 /* 1429 * Spec says that we should clear the power reg before setting 1430 * a new value. Some controllers don't seem to like this though. 1431 */ 1432 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1433 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1434 1435 /* 1436 * At least the Marvell CaFe chip gets confused if we set the 1437 * voltage and set turn on power at the same time, so set the 1438 * voltage first. 1439 */ 1440 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1441 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1442 1443 pwr |= SDHCI_POWER_ON; 1444 1445 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1446 1447 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1448 sdhci_runtime_pm_bus_on(host); 1449 1450 /* 1451 * Some controllers need an extra 10ms delay of 10ms before 1452 * they can apply clock after applying power 1453 */ 1454 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1455 mdelay(10); 1456 } 1457 } 1458 EXPORT_SYMBOL_GPL(sdhci_set_power); 1459 1460 static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1461 unsigned short vdd) 1462 { 1463 struct mmc_host *mmc = host->mmc; 1464 1465 if (host->ops->set_power) 1466 host->ops->set_power(host, mode, vdd); 1467 else if (!IS_ERR(mmc->supply.vmmc)) 1468 sdhci_set_power_reg(host, mode, vdd); 1469 else 1470 sdhci_set_power(host, mode, vdd); 1471 } 1472 1473 /*****************************************************************************\ 1474 * * 1475 * MMC callbacks * 1476 * * 1477 \*****************************************************************************/ 1478 1479 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1480 { 1481 struct sdhci_host *host; 1482 int present; 1483 unsigned long flags; 1484 1485 host = mmc_priv(mmc); 1486 1487 /* Firstly check card presence */ 1488 present = mmc->ops->get_cd(mmc); 1489 1490 spin_lock_irqsave(&host->lock, flags); 1491 1492 sdhci_led_activate(host); 1493 1494 /* 1495 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1496 * requests if Auto-CMD12 is enabled. 1497 */ 1498 if (sdhci_auto_cmd12(host, mrq)) { 1499 if (mrq->stop) { 1500 mrq->data->stop = NULL; 1501 mrq->stop = NULL; 1502 } 1503 } 1504 1505 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1506 mrq->cmd->error = -ENOMEDIUM; 1507 sdhci_finish_mrq(host, mrq); 1508 } else { 1509 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1510 sdhci_send_command(host, mrq->sbc); 1511 else 1512 sdhci_send_command(host, mrq->cmd); 1513 } 1514 1515 mmiowb(); 1516 spin_unlock_irqrestore(&host->lock, flags); 1517 } 1518 1519 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1520 { 1521 u8 ctrl; 1522 1523 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1524 if (width == MMC_BUS_WIDTH_8) { 1525 ctrl &= ~SDHCI_CTRL_4BITBUS; 1526 if (host->version >= SDHCI_SPEC_300) 1527 ctrl |= SDHCI_CTRL_8BITBUS; 1528 } else { 1529 if (host->version >= SDHCI_SPEC_300) 1530 ctrl &= ~SDHCI_CTRL_8BITBUS; 1531 if (width == MMC_BUS_WIDTH_4) 1532 ctrl |= SDHCI_CTRL_4BITBUS; 1533 else 1534 ctrl &= ~SDHCI_CTRL_4BITBUS; 1535 } 1536 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1537 } 1538 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1539 1540 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1541 { 1542 u16 ctrl_2; 1543 1544 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1545 /* Select Bus Speed Mode for host */ 1546 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1547 if ((timing == MMC_TIMING_MMC_HS200) || 1548 (timing == MMC_TIMING_UHS_SDR104)) 1549 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1550 else if (timing == MMC_TIMING_UHS_SDR12) 1551 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1552 else if (timing == MMC_TIMING_UHS_SDR25) 1553 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1554 else if (timing == MMC_TIMING_UHS_SDR50) 1555 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1556 else if ((timing == MMC_TIMING_UHS_DDR50) || 1557 (timing == MMC_TIMING_MMC_DDR52)) 1558 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1559 else if (timing == MMC_TIMING_MMC_HS400) 1560 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1561 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1562 } 1563 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1564 1565 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1566 { 1567 struct sdhci_host *host = mmc_priv(mmc); 1568 unsigned long flags; 1569 u8 ctrl; 1570 1571 spin_lock_irqsave(&host->lock, flags); 1572 1573 if (host->flags & SDHCI_DEVICE_DEAD) { 1574 spin_unlock_irqrestore(&host->lock, flags); 1575 if (!IS_ERR(mmc->supply.vmmc) && 1576 ios->power_mode == MMC_POWER_OFF) 1577 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1578 return; 1579 } 1580 1581 /* 1582 * Reset the chip on each power off. 1583 * Should clear out any weird states. 1584 */ 1585 if (ios->power_mode == MMC_POWER_OFF) { 1586 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1587 sdhci_reinit(host); 1588 } 1589 1590 if (host->version >= SDHCI_SPEC_300 && 1591 (ios->power_mode == MMC_POWER_UP) && 1592 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1593 sdhci_enable_preset_value(host, false); 1594 1595 if (!ios->clock || ios->clock != host->clock) { 1596 host->ops->set_clock(host, ios->clock); 1597 host->clock = ios->clock; 1598 1599 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1600 host->clock) { 1601 host->timeout_clk = host->mmc->actual_clock ? 1602 host->mmc->actual_clock / 1000 : 1603 host->clock / 1000; 1604 host->mmc->max_busy_timeout = 1605 host->ops->get_max_timeout_count ? 1606 host->ops->get_max_timeout_count(host) : 1607 1 << 27; 1608 host->mmc->max_busy_timeout /= host->timeout_clk; 1609 } 1610 } 1611 1612 __sdhci_set_power(host, ios->power_mode, ios->vdd); 1613 1614 if (host->ops->platform_send_init_74_clocks) 1615 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1616 1617 host->ops->set_bus_width(host, ios->bus_width); 1618 1619 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1620 1621 if ((ios->timing == MMC_TIMING_SD_HS || 1622 ios->timing == MMC_TIMING_MMC_HS) 1623 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1624 ctrl |= SDHCI_CTRL_HISPD; 1625 else 1626 ctrl &= ~SDHCI_CTRL_HISPD; 1627 1628 if (host->version >= SDHCI_SPEC_300) { 1629 u16 clk, ctrl_2; 1630 1631 /* In case of UHS-I modes, set High Speed Enable */ 1632 if ((ios->timing == MMC_TIMING_MMC_HS400) || 1633 (ios->timing == MMC_TIMING_MMC_HS200) || 1634 (ios->timing == MMC_TIMING_MMC_DDR52) || 1635 (ios->timing == MMC_TIMING_UHS_SDR50) || 1636 (ios->timing == MMC_TIMING_UHS_SDR104) || 1637 (ios->timing == MMC_TIMING_UHS_DDR50) || 1638 (ios->timing == MMC_TIMING_UHS_SDR25)) 1639 ctrl |= SDHCI_CTRL_HISPD; 1640 1641 if (!host->preset_enabled) { 1642 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1643 /* 1644 * We only need to set Driver Strength if the 1645 * preset value enable is not set. 1646 */ 1647 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1648 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1649 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1650 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1651 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 1652 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1653 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1654 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1655 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 1656 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 1657 else { 1658 pr_warn("%s: invalid driver type, default to driver type B\n", 1659 mmc_hostname(mmc)); 1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1661 } 1662 1663 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1664 } else { 1665 /* 1666 * According to SDHC Spec v3.00, if the Preset Value 1667 * Enable in the Host Control 2 register is set, we 1668 * need to reset SD Clock Enable before changing High 1669 * Speed Enable to avoid generating clock gliches. 1670 */ 1671 1672 /* Reset SD Clock Enable */ 1673 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1674 clk &= ~SDHCI_CLOCK_CARD_EN; 1675 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1676 1677 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1678 1679 /* Re-enable SD Clock */ 1680 host->ops->set_clock(host, host->clock); 1681 } 1682 1683 /* Reset SD Clock Enable */ 1684 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1685 clk &= ~SDHCI_CLOCK_CARD_EN; 1686 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1687 1688 host->ops->set_uhs_signaling(host, ios->timing); 1689 host->timing = ios->timing; 1690 1691 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1692 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1693 (ios->timing == MMC_TIMING_UHS_SDR25) || 1694 (ios->timing == MMC_TIMING_UHS_SDR50) || 1695 (ios->timing == MMC_TIMING_UHS_SDR104) || 1696 (ios->timing == MMC_TIMING_UHS_DDR50) || 1697 (ios->timing == MMC_TIMING_MMC_DDR52))) { 1698 u16 preset; 1699 1700 sdhci_enable_preset_value(host, true); 1701 preset = sdhci_get_preset_value(host); 1702 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1703 >> SDHCI_PRESET_DRV_SHIFT; 1704 } 1705 1706 /* Re-enable SD Clock */ 1707 host->ops->set_clock(host, host->clock); 1708 } else 1709 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1710 1711 /* 1712 * Some (ENE) controllers go apeshit on some ios operation, 1713 * signalling timeout and CRC errors even on CMD0. Resetting 1714 * it on each ios seems to solve the problem. 1715 */ 1716 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1717 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1718 1719 mmiowb(); 1720 spin_unlock_irqrestore(&host->lock, flags); 1721 } 1722 1723 static int sdhci_get_cd(struct mmc_host *mmc) 1724 { 1725 struct sdhci_host *host = mmc_priv(mmc); 1726 int gpio_cd = mmc_gpio_get_cd(mmc); 1727 1728 if (host->flags & SDHCI_DEVICE_DEAD) 1729 return 0; 1730 1731 /* If nonremovable, assume that the card is always present. */ 1732 if (!mmc_card_is_removable(host->mmc)) 1733 return 1; 1734 1735 /* 1736 * Try slot gpio detect, if defined it take precedence 1737 * over build in controller functionality 1738 */ 1739 if (gpio_cd >= 0) 1740 return !!gpio_cd; 1741 1742 /* If polling, assume that the card is always present. */ 1743 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1744 return 1; 1745 1746 /* Host native card detect */ 1747 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1748 } 1749 1750 static int sdhci_check_ro(struct sdhci_host *host) 1751 { 1752 unsigned long flags; 1753 int is_readonly; 1754 1755 spin_lock_irqsave(&host->lock, flags); 1756 1757 if (host->flags & SDHCI_DEVICE_DEAD) 1758 is_readonly = 0; 1759 else if (host->ops->get_ro) 1760 is_readonly = host->ops->get_ro(host); 1761 else 1762 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1763 & SDHCI_WRITE_PROTECT); 1764 1765 spin_unlock_irqrestore(&host->lock, flags); 1766 1767 /* This quirk needs to be replaced by a callback-function later */ 1768 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1769 !is_readonly : is_readonly; 1770 } 1771 1772 #define SAMPLE_COUNT 5 1773 1774 static int sdhci_get_ro(struct mmc_host *mmc) 1775 { 1776 struct sdhci_host *host = mmc_priv(mmc); 1777 int i, ro_count; 1778 1779 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1780 return sdhci_check_ro(host); 1781 1782 ro_count = 0; 1783 for (i = 0; i < SAMPLE_COUNT; i++) { 1784 if (sdhci_check_ro(host)) { 1785 if (++ro_count > SAMPLE_COUNT / 2) 1786 return 1; 1787 } 1788 msleep(30); 1789 } 1790 return 0; 1791 } 1792 1793 static void sdhci_hw_reset(struct mmc_host *mmc) 1794 { 1795 struct sdhci_host *host = mmc_priv(mmc); 1796 1797 if (host->ops && host->ops->hw_reset) 1798 host->ops->hw_reset(host); 1799 } 1800 1801 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1802 { 1803 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1804 if (enable) 1805 host->ier |= SDHCI_INT_CARD_INT; 1806 else 1807 host->ier &= ~SDHCI_INT_CARD_INT; 1808 1809 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1810 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1811 mmiowb(); 1812 } 1813 } 1814 1815 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1816 { 1817 struct sdhci_host *host = mmc_priv(mmc); 1818 unsigned long flags; 1819 1820 spin_lock_irqsave(&host->lock, flags); 1821 if (enable) 1822 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1823 else 1824 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1825 1826 sdhci_enable_sdio_irq_nolock(host, enable); 1827 spin_unlock_irqrestore(&host->lock, flags); 1828 } 1829 1830 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1831 struct mmc_ios *ios) 1832 { 1833 struct sdhci_host *host = mmc_priv(mmc); 1834 u16 ctrl; 1835 int ret; 1836 1837 /* 1838 * Signal Voltage Switching is only applicable for Host Controllers 1839 * v3.00 and above. 1840 */ 1841 if (host->version < SDHCI_SPEC_300) 1842 return 0; 1843 1844 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1845 1846 switch (ios->signal_voltage) { 1847 case MMC_SIGNAL_VOLTAGE_330: 1848 if (!(host->flags & SDHCI_SIGNALING_330)) 1849 return -EINVAL; 1850 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1851 ctrl &= ~SDHCI_CTRL_VDD_180; 1852 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1853 1854 if (!IS_ERR(mmc->supply.vqmmc)) { 1855 ret = mmc_regulator_set_vqmmc(mmc, ios); 1856 if (ret) { 1857 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1858 mmc_hostname(mmc)); 1859 return -EIO; 1860 } 1861 } 1862 /* Wait for 5ms */ 1863 usleep_range(5000, 5500); 1864 1865 /* 3.3V regulator output should be stable within 5 ms */ 1866 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1867 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1868 return 0; 1869 1870 pr_warn("%s: 3.3V regulator output did not became stable\n", 1871 mmc_hostname(mmc)); 1872 1873 return -EAGAIN; 1874 case MMC_SIGNAL_VOLTAGE_180: 1875 if (!(host->flags & SDHCI_SIGNALING_180)) 1876 return -EINVAL; 1877 if (!IS_ERR(mmc->supply.vqmmc)) { 1878 ret = mmc_regulator_set_vqmmc(mmc, ios); 1879 if (ret) { 1880 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1881 mmc_hostname(mmc)); 1882 return -EIO; 1883 } 1884 } 1885 1886 /* 1887 * Enable 1.8V Signal Enable in the Host Control2 1888 * register 1889 */ 1890 ctrl |= SDHCI_CTRL_VDD_180; 1891 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1892 1893 /* Some controller need to do more when switching */ 1894 if (host->ops->voltage_switch) 1895 host->ops->voltage_switch(host); 1896 1897 /* 1.8V regulator output should be stable within 5 ms */ 1898 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1899 if (ctrl & SDHCI_CTRL_VDD_180) 1900 return 0; 1901 1902 pr_warn("%s: 1.8V regulator output did not became stable\n", 1903 mmc_hostname(mmc)); 1904 1905 return -EAGAIN; 1906 case MMC_SIGNAL_VOLTAGE_120: 1907 if (!(host->flags & SDHCI_SIGNALING_120)) 1908 return -EINVAL; 1909 if (!IS_ERR(mmc->supply.vqmmc)) { 1910 ret = mmc_regulator_set_vqmmc(mmc, ios); 1911 if (ret) { 1912 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1913 mmc_hostname(mmc)); 1914 return -EIO; 1915 } 1916 } 1917 return 0; 1918 default: 1919 /* No signal voltage switch required */ 1920 return 0; 1921 } 1922 } 1923 1924 static int sdhci_card_busy(struct mmc_host *mmc) 1925 { 1926 struct sdhci_host *host = mmc_priv(mmc); 1927 u32 present_state; 1928 1929 /* Check whether DAT[0] is 0 */ 1930 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1931 1932 return !(present_state & SDHCI_DATA_0_LVL_MASK); 1933 } 1934 1935 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1936 { 1937 struct sdhci_host *host = mmc_priv(mmc); 1938 unsigned long flags; 1939 1940 spin_lock_irqsave(&host->lock, flags); 1941 host->flags |= SDHCI_HS400_TUNING; 1942 spin_unlock_irqrestore(&host->lock, flags); 1943 1944 return 0; 1945 } 1946 1947 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1948 { 1949 struct sdhci_host *host = mmc_priv(mmc); 1950 u16 ctrl; 1951 int tuning_loop_counter = MAX_TUNING_LOOP; 1952 int err = 0; 1953 unsigned long flags; 1954 unsigned int tuning_count = 0; 1955 bool hs400_tuning; 1956 1957 spin_lock_irqsave(&host->lock, flags); 1958 1959 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1960 host->flags &= ~SDHCI_HS400_TUNING; 1961 1962 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1963 tuning_count = host->tuning_count; 1964 1965 /* 1966 * The Host Controller needs tuning in case of SDR104 and DDR50 1967 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 1968 * the Capabilities register. 1969 * If the Host Controller supports the HS200 mode then the 1970 * tuning function has to be executed. 1971 */ 1972 switch (host->timing) { 1973 /* HS400 tuning is done in HS200 mode */ 1974 case MMC_TIMING_MMC_HS400: 1975 err = -EINVAL; 1976 goto out_unlock; 1977 1978 case MMC_TIMING_MMC_HS200: 1979 /* 1980 * Periodic re-tuning for HS400 is not expected to be needed, so 1981 * disable it here. 1982 */ 1983 if (hs400_tuning) 1984 tuning_count = 0; 1985 break; 1986 1987 case MMC_TIMING_UHS_SDR104: 1988 case MMC_TIMING_UHS_DDR50: 1989 break; 1990 1991 case MMC_TIMING_UHS_SDR50: 1992 if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 1993 break; 1994 /* FALLTHROUGH */ 1995 1996 default: 1997 goto out_unlock; 1998 } 1999 2000 if (host->ops->platform_execute_tuning) { 2001 spin_unlock_irqrestore(&host->lock, flags); 2002 err = host->ops->platform_execute_tuning(host, opcode); 2003 return err; 2004 } 2005 2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2007 ctrl |= SDHCI_CTRL_EXEC_TUNING; 2008 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 2009 ctrl |= SDHCI_CTRL_TUNED_CLK; 2010 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2011 2012 /* 2013 * As per the Host Controller spec v3.00, tuning command 2014 * generates Buffer Read Ready interrupt, so enable that. 2015 * 2016 * Note: The spec clearly says that when tuning sequence 2017 * is being performed, the controller does not generate 2018 * interrupts other than Buffer Read Ready interrupt. But 2019 * to make sure we don't hit a controller bug, we _only_ 2020 * enable Buffer Read Ready interrupt here. 2021 */ 2022 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 2023 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 2024 2025 /* 2026 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 2027 * of loops reaches 40 times. 2028 */ 2029 do { 2030 struct mmc_command cmd = {0}; 2031 struct mmc_request mrq = {NULL}; 2032 2033 cmd.opcode = opcode; 2034 cmd.arg = 0; 2035 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2036 cmd.retries = 0; 2037 cmd.data = NULL; 2038 cmd.mrq = &mrq; 2039 cmd.error = 0; 2040 2041 if (tuning_loop_counter-- == 0) 2042 break; 2043 2044 mrq.cmd = &cmd; 2045 2046 /* 2047 * In response to CMD19, the card sends 64 bytes of tuning 2048 * block to the Host Controller. So we set the block size 2049 * to 64 here. 2050 */ 2051 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 2052 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2053 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 2054 SDHCI_BLOCK_SIZE); 2055 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 2056 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 2057 SDHCI_BLOCK_SIZE); 2058 } else { 2059 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 2060 SDHCI_BLOCK_SIZE); 2061 } 2062 2063 /* 2064 * The tuning block is sent by the card to the host controller. 2065 * So we set the TRNS_READ bit in the Transfer Mode register. 2066 * This also takes care of setting DMA Enable and Multi Block 2067 * Select in the same register to 0. 2068 */ 2069 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2070 2071 sdhci_send_command(host, &cmd); 2072 2073 host->cmd = NULL; 2074 sdhci_del_timer(host, &mrq); 2075 2076 spin_unlock_irqrestore(&host->lock, flags); 2077 /* Wait for Buffer Read Ready interrupt */ 2078 wait_event_timeout(host->buf_ready_int, 2079 (host->tuning_done == 1), 2080 msecs_to_jiffies(50)); 2081 spin_lock_irqsave(&host->lock, flags); 2082 2083 if (!host->tuning_done) { 2084 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); 2085 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2086 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2087 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2088 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2089 2090 err = -EIO; 2091 goto out; 2092 } 2093 2094 host->tuning_done = 0; 2095 2096 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2097 2098 /* eMMC spec does not require a delay between tuning cycles */ 2099 if (opcode == MMC_SEND_TUNING_BLOCK) 2100 mdelay(1); 2101 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 2102 2103 /* 2104 * The Host Driver has exhausted the maximum number of loops allowed, 2105 * so use fixed sampling frequency. 2106 */ 2107 if (tuning_loop_counter < 0) { 2108 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2109 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2110 } 2111 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 2112 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); 2113 err = -EIO; 2114 } 2115 2116 out: 2117 if (tuning_count) { 2118 /* 2119 * In case tuning fails, host controllers which support 2120 * re-tuning can try tuning again at a later time, when the 2121 * re-tuning timer expires. So for these controllers, we 2122 * return 0. Since there might be other controllers who do not 2123 * have this capability, we return error for them. 2124 */ 2125 err = 0; 2126 } 2127 2128 host->mmc->retune_period = err ? 0 : tuning_count; 2129 2130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2132 out_unlock: 2133 spin_unlock_irqrestore(&host->lock, flags); 2134 return err; 2135 } 2136 2137 static int sdhci_select_drive_strength(struct mmc_card *card, 2138 unsigned int max_dtr, int host_drv, 2139 int card_drv, int *drv_type) 2140 { 2141 struct sdhci_host *host = mmc_priv(card->host); 2142 2143 if (!host->ops->select_drive_strength) 2144 return 0; 2145 2146 return host->ops->select_drive_strength(host, card, max_dtr, host_drv, 2147 card_drv, drv_type); 2148 } 2149 2150 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2151 { 2152 /* Host Controller v3.00 defines preset value registers */ 2153 if (host->version < SDHCI_SPEC_300) 2154 return; 2155 2156 /* 2157 * We only enable or disable Preset Value if they are not already 2158 * enabled or disabled respectively. Otherwise, we bail out. 2159 */ 2160 if (host->preset_enabled != enable) { 2161 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2162 2163 if (enable) 2164 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2165 else 2166 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2167 2168 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2169 2170 if (enable) 2171 host->flags |= SDHCI_PV_ENABLED; 2172 else 2173 host->flags &= ~SDHCI_PV_ENABLED; 2174 2175 host->preset_enabled = enable; 2176 } 2177 } 2178 2179 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2180 int err) 2181 { 2182 struct sdhci_host *host = mmc_priv(mmc); 2183 struct mmc_data *data = mrq->data; 2184 2185 if (data->host_cookie != COOKIE_UNMAPPED) 2186 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2187 data->flags & MMC_DATA_WRITE ? 2188 DMA_TO_DEVICE : DMA_FROM_DEVICE); 2189 2190 data->host_cookie = COOKIE_UNMAPPED; 2191 } 2192 2193 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 2194 bool is_first_req) 2195 { 2196 struct sdhci_host *host = mmc_priv(mmc); 2197 2198 mrq->data->host_cookie = COOKIE_UNMAPPED; 2199 2200 if (host->flags & SDHCI_REQ_USE_DMA) 2201 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2202 } 2203 2204 static inline bool sdhci_has_requests(struct sdhci_host *host) 2205 { 2206 return host->cmd || host->data_cmd; 2207 } 2208 2209 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 2210 { 2211 if (host->data_cmd) { 2212 host->data_cmd->error = err; 2213 sdhci_finish_mrq(host, host->data_cmd->mrq); 2214 } 2215 2216 if (host->cmd) { 2217 host->cmd->error = err; 2218 sdhci_finish_mrq(host, host->cmd->mrq); 2219 } 2220 } 2221 2222 static void sdhci_card_event(struct mmc_host *mmc) 2223 { 2224 struct sdhci_host *host = mmc_priv(mmc); 2225 unsigned long flags; 2226 int present; 2227 2228 /* First check if client has provided their own card event */ 2229 if (host->ops->card_event) 2230 host->ops->card_event(host); 2231 2232 present = mmc->ops->get_cd(mmc); 2233 2234 spin_lock_irqsave(&host->lock, flags); 2235 2236 /* Check sdhci_has_requests() first in case we are runtime suspended */ 2237 if (sdhci_has_requests(host) && !present) { 2238 pr_err("%s: Card removed during transfer!\n", 2239 mmc_hostname(host->mmc)); 2240 pr_err("%s: Resetting controller.\n", 2241 mmc_hostname(host->mmc)); 2242 2243 sdhci_do_reset(host, SDHCI_RESET_CMD); 2244 sdhci_do_reset(host, SDHCI_RESET_DATA); 2245 2246 sdhci_error_out_mrqs(host, -ENOMEDIUM); 2247 } 2248 2249 spin_unlock_irqrestore(&host->lock, flags); 2250 } 2251 2252 static const struct mmc_host_ops sdhci_ops = { 2253 .request = sdhci_request, 2254 .post_req = sdhci_post_req, 2255 .pre_req = sdhci_pre_req, 2256 .set_ios = sdhci_set_ios, 2257 .get_cd = sdhci_get_cd, 2258 .get_ro = sdhci_get_ro, 2259 .hw_reset = sdhci_hw_reset, 2260 .enable_sdio_irq = sdhci_enable_sdio_irq, 2261 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2262 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2263 .execute_tuning = sdhci_execute_tuning, 2264 .select_drive_strength = sdhci_select_drive_strength, 2265 .card_event = sdhci_card_event, 2266 .card_busy = sdhci_card_busy, 2267 }; 2268 2269 /*****************************************************************************\ 2270 * * 2271 * Tasklets * 2272 * * 2273 \*****************************************************************************/ 2274 2275 static bool sdhci_request_done(struct sdhci_host *host) 2276 { 2277 unsigned long flags; 2278 struct mmc_request *mrq; 2279 int i; 2280 2281 spin_lock_irqsave(&host->lock, flags); 2282 2283 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 2284 mrq = host->mrqs_done[i]; 2285 if (mrq) { 2286 host->mrqs_done[i] = NULL; 2287 break; 2288 } 2289 } 2290 2291 if (!mrq) { 2292 spin_unlock_irqrestore(&host->lock, flags); 2293 return true; 2294 } 2295 2296 sdhci_del_timer(host, mrq); 2297 2298 /* 2299 * Always unmap the data buffers if they were mapped by 2300 * sdhci_prepare_data() whenever we finish with a request. 2301 * This avoids leaking DMA mappings on error. 2302 */ 2303 if (host->flags & SDHCI_REQ_USE_DMA) { 2304 struct mmc_data *data = mrq->data; 2305 2306 if (data && data->host_cookie == COOKIE_MAPPED) { 2307 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2308 (data->flags & MMC_DATA_READ) ? 2309 DMA_FROM_DEVICE : DMA_TO_DEVICE); 2310 data->host_cookie = COOKIE_UNMAPPED; 2311 } 2312 } 2313 2314 /* 2315 * The controller needs a reset of internal state machines 2316 * upon error conditions. 2317 */ 2318 if (sdhci_needs_reset(host, mrq)) { 2319 /* Some controllers need this kick or reset won't work here */ 2320 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2321 /* This is to force an update */ 2322 host->ops->set_clock(host, host->clock); 2323 2324 /* Spec says we should do both at the same time, but Ricoh 2325 controllers do not like that. */ 2326 if (!host->cmd) 2327 sdhci_do_reset(host, SDHCI_RESET_CMD); 2328 if (!host->data_cmd) 2329 sdhci_do_reset(host, SDHCI_RESET_DATA); 2330 2331 host->pending_reset = false; 2332 } 2333 2334 if (!sdhci_has_requests(host)) 2335 sdhci_led_deactivate(host); 2336 2337 mmiowb(); 2338 spin_unlock_irqrestore(&host->lock, flags); 2339 2340 mmc_request_done(host->mmc, mrq); 2341 2342 return false; 2343 } 2344 2345 static void sdhci_tasklet_finish(unsigned long param) 2346 { 2347 struct sdhci_host *host = (struct sdhci_host *)param; 2348 2349 while (!sdhci_request_done(host)) 2350 ; 2351 } 2352 2353 static void sdhci_timeout_timer(unsigned long data) 2354 { 2355 struct sdhci_host *host; 2356 unsigned long flags; 2357 2358 host = (struct sdhci_host*)data; 2359 2360 spin_lock_irqsave(&host->lock, flags); 2361 2362 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2363 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2364 mmc_hostname(host->mmc)); 2365 sdhci_dumpregs(host); 2366 2367 host->cmd->error = -ETIMEDOUT; 2368 sdhci_finish_mrq(host, host->cmd->mrq); 2369 } 2370 2371 mmiowb(); 2372 spin_unlock_irqrestore(&host->lock, flags); 2373 } 2374 2375 static void sdhci_timeout_data_timer(unsigned long data) 2376 { 2377 struct sdhci_host *host; 2378 unsigned long flags; 2379 2380 host = (struct sdhci_host *)data; 2381 2382 spin_lock_irqsave(&host->lock, flags); 2383 2384 if (host->data || host->data_cmd || 2385 (host->cmd && sdhci_data_line_cmd(host->cmd))) { 2386 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2387 mmc_hostname(host->mmc)); 2388 sdhci_dumpregs(host); 2389 2390 if (host->data) { 2391 host->data->error = -ETIMEDOUT; 2392 sdhci_finish_data(host); 2393 } else if (host->data_cmd) { 2394 host->data_cmd->error = -ETIMEDOUT; 2395 sdhci_finish_mrq(host, host->data_cmd->mrq); 2396 } else { 2397 host->cmd->error = -ETIMEDOUT; 2398 sdhci_finish_mrq(host, host->cmd->mrq); 2399 } 2400 } 2401 2402 mmiowb(); 2403 spin_unlock_irqrestore(&host->lock, flags); 2404 } 2405 2406 /*****************************************************************************\ 2407 * * 2408 * Interrupt handling * 2409 * * 2410 \*****************************************************************************/ 2411 2412 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 2413 { 2414 if (!host->cmd) { 2415 /* 2416 * SDHCI recovers from errors by resetting the cmd and data 2417 * circuits. Until that is done, there very well might be more 2418 * interrupts, so ignore them in that case. 2419 */ 2420 if (host->pending_reset) 2421 return; 2422 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2423 mmc_hostname(host->mmc), (unsigned)intmask); 2424 sdhci_dumpregs(host); 2425 return; 2426 } 2427 2428 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2429 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 2430 if (intmask & SDHCI_INT_TIMEOUT) 2431 host->cmd->error = -ETIMEDOUT; 2432 else 2433 host->cmd->error = -EILSEQ; 2434 2435 /* 2436 * If this command initiates a data phase and a response 2437 * CRC error is signalled, the card can start transferring 2438 * data - the card may have received the command without 2439 * error. We must not terminate the mmc_request early. 2440 * 2441 * If the card did not receive the command or returned an 2442 * error which prevented it sending data, the data phase 2443 * will time out. 2444 */ 2445 if (host->cmd->data && 2446 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 2447 SDHCI_INT_CRC) { 2448 host->cmd = NULL; 2449 return; 2450 } 2451 2452 sdhci_finish_mrq(host, host->cmd->mrq); 2453 return; 2454 } 2455 2456 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 2457 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data && 2458 host->cmd->opcode == MMC_STOP_TRANSMISSION) 2459 *mask &= ~SDHCI_INT_DATA_END; 2460 2461 if (intmask & SDHCI_INT_RESPONSE) 2462 sdhci_finish_command(host); 2463 } 2464 2465 #ifdef CONFIG_MMC_DEBUG 2466 static void sdhci_adma_show_error(struct sdhci_host *host) 2467 { 2468 const char *name = mmc_hostname(host->mmc); 2469 void *desc = host->adma_table; 2470 2471 sdhci_dumpregs(host); 2472 2473 while (true) { 2474 struct sdhci_adma2_64_desc *dma_desc = desc; 2475 2476 if (host->flags & SDHCI_USE_64_BIT_DMA) 2477 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2478 name, desc, le32_to_cpu(dma_desc->addr_hi), 2479 le32_to_cpu(dma_desc->addr_lo), 2480 le16_to_cpu(dma_desc->len), 2481 le16_to_cpu(dma_desc->cmd)); 2482 else 2483 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2484 name, desc, le32_to_cpu(dma_desc->addr_lo), 2485 le16_to_cpu(dma_desc->len), 2486 le16_to_cpu(dma_desc->cmd)); 2487 2488 desc += host->desc_sz; 2489 2490 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2491 break; 2492 } 2493 } 2494 #else 2495 static void sdhci_adma_show_error(struct sdhci_host *host) { } 2496 #endif 2497 2498 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2499 { 2500 u32 command; 2501 2502 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2503 if (intmask & SDHCI_INT_DATA_AVAIL) { 2504 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2505 if (command == MMC_SEND_TUNING_BLOCK || 2506 command == MMC_SEND_TUNING_BLOCK_HS200) { 2507 host->tuning_done = 1; 2508 wake_up(&host->buf_ready_int); 2509 return; 2510 } 2511 } 2512 2513 if (!host->data) { 2514 struct mmc_command *data_cmd = host->data_cmd; 2515 2516 if (data_cmd) 2517 host->data_cmd = NULL; 2518 2519 /* 2520 * The "data complete" interrupt is also used to 2521 * indicate that a busy state has ended. See comment 2522 * above in sdhci_cmd_irq(). 2523 */ 2524 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 2525 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2526 data_cmd->error = -ETIMEDOUT; 2527 sdhci_finish_mrq(host, data_cmd->mrq); 2528 return; 2529 } 2530 if (intmask & SDHCI_INT_DATA_END) { 2531 /* 2532 * Some cards handle busy-end interrupt 2533 * before the command completed, so make 2534 * sure we do things in the proper order. 2535 */ 2536 if (host->cmd == data_cmd) 2537 return; 2538 2539 sdhci_finish_mrq(host, data_cmd->mrq); 2540 return; 2541 } 2542 } 2543 2544 /* 2545 * SDHCI recovers from errors by resetting the cmd and data 2546 * circuits. Until that is done, there very well might be more 2547 * interrupts, so ignore them in that case. 2548 */ 2549 if (host->pending_reset) 2550 return; 2551 2552 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2553 mmc_hostname(host->mmc), (unsigned)intmask); 2554 sdhci_dumpregs(host); 2555 2556 return; 2557 } 2558 2559 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2560 host->data->error = -ETIMEDOUT; 2561 else if (intmask & SDHCI_INT_DATA_END_BIT) 2562 host->data->error = -EILSEQ; 2563 else if ((intmask & SDHCI_INT_DATA_CRC) && 2564 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2565 != MMC_BUS_TEST_R) 2566 host->data->error = -EILSEQ; 2567 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2568 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2569 sdhci_adma_show_error(host); 2570 host->data->error = -EIO; 2571 if (host->ops->adma_workaround) 2572 host->ops->adma_workaround(host, intmask); 2573 } 2574 2575 if (host->data->error) 2576 sdhci_finish_data(host); 2577 else { 2578 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2579 sdhci_transfer_pio(host); 2580 2581 /* 2582 * We currently don't do anything fancy with DMA 2583 * boundaries, but as we can't disable the feature 2584 * we need to at least restart the transfer. 2585 * 2586 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2587 * should return a valid address to continue from, but as 2588 * some controllers are faulty, don't trust them. 2589 */ 2590 if (intmask & SDHCI_INT_DMA_END) { 2591 u32 dmastart, dmanow; 2592 dmastart = sg_dma_address(host->data->sg); 2593 dmanow = dmastart + host->data->bytes_xfered; 2594 /* 2595 * Force update to the next DMA block boundary. 2596 */ 2597 dmanow = (dmanow & 2598 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2599 SDHCI_DEFAULT_BOUNDARY_SIZE; 2600 host->data->bytes_xfered = dmanow - dmastart; 2601 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2602 " next 0x%08x\n", 2603 mmc_hostname(host->mmc), dmastart, 2604 host->data->bytes_xfered, dmanow); 2605 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2606 } 2607 2608 if (intmask & SDHCI_INT_DATA_END) { 2609 if (host->cmd == host->data_cmd) { 2610 /* 2611 * Data managed to finish before the 2612 * command completed. Make sure we do 2613 * things in the proper order. 2614 */ 2615 host->data_early = 1; 2616 } else { 2617 sdhci_finish_data(host); 2618 } 2619 } 2620 } 2621 } 2622 2623 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2624 { 2625 irqreturn_t result = IRQ_NONE; 2626 struct sdhci_host *host = dev_id; 2627 u32 intmask, mask, unexpected = 0; 2628 int max_loops = 16; 2629 2630 spin_lock(&host->lock); 2631 2632 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2633 spin_unlock(&host->lock); 2634 return IRQ_NONE; 2635 } 2636 2637 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2638 if (!intmask || intmask == 0xffffffff) { 2639 result = IRQ_NONE; 2640 goto out; 2641 } 2642 2643 do { 2644 /* Clear selected interrupts. */ 2645 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2646 SDHCI_INT_BUS_POWER); 2647 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2648 2649 DBG("*** %s got interrupt: 0x%08x\n", 2650 mmc_hostname(host->mmc), intmask); 2651 2652 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2653 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2654 SDHCI_CARD_PRESENT; 2655 2656 /* 2657 * There is a observation on i.mx esdhc. INSERT 2658 * bit will be immediately set again when it gets 2659 * cleared, if a card is inserted. We have to mask 2660 * the irq to prevent interrupt storm which will 2661 * freeze the system. And the REMOVE gets the 2662 * same situation. 2663 * 2664 * More testing are needed here to ensure it works 2665 * for other platforms though. 2666 */ 2667 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2668 SDHCI_INT_CARD_REMOVE); 2669 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2670 SDHCI_INT_CARD_INSERT; 2671 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2672 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2673 2674 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2675 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2676 2677 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2678 SDHCI_INT_CARD_REMOVE); 2679 result = IRQ_WAKE_THREAD; 2680 } 2681 2682 if (intmask & SDHCI_INT_CMD_MASK) 2683 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, 2684 &intmask); 2685 2686 if (intmask & SDHCI_INT_DATA_MASK) 2687 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2688 2689 if (intmask & SDHCI_INT_BUS_POWER) 2690 pr_err("%s: Card is consuming too much power!\n", 2691 mmc_hostname(host->mmc)); 2692 2693 if (intmask & SDHCI_INT_RETUNE) 2694 mmc_retune_needed(host->mmc); 2695 2696 if (intmask & SDHCI_INT_CARD_INT) { 2697 sdhci_enable_sdio_irq_nolock(host, false); 2698 host->thread_isr |= SDHCI_INT_CARD_INT; 2699 result = IRQ_WAKE_THREAD; 2700 } 2701 2702 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2703 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2704 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2705 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 2706 2707 if (intmask) { 2708 unexpected |= intmask; 2709 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2710 } 2711 2712 if (result == IRQ_NONE) 2713 result = IRQ_HANDLED; 2714 2715 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2716 } while (intmask && --max_loops); 2717 out: 2718 spin_unlock(&host->lock); 2719 2720 if (unexpected) { 2721 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2722 mmc_hostname(host->mmc), unexpected); 2723 sdhci_dumpregs(host); 2724 } 2725 2726 return result; 2727 } 2728 2729 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2730 { 2731 struct sdhci_host *host = dev_id; 2732 unsigned long flags; 2733 u32 isr; 2734 2735 spin_lock_irqsave(&host->lock, flags); 2736 isr = host->thread_isr; 2737 host->thread_isr = 0; 2738 spin_unlock_irqrestore(&host->lock, flags); 2739 2740 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2741 struct mmc_host *mmc = host->mmc; 2742 2743 mmc->ops->card_event(mmc); 2744 mmc_detect_change(mmc, msecs_to_jiffies(200)); 2745 } 2746 2747 if (isr & SDHCI_INT_CARD_INT) { 2748 sdio_run_irqs(host->mmc); 2749 2750 spin_lock_irqsave(&host->lock, flags); 2751 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2752 sdhci_enable_sdio_irq_nolock(host, true); 2753 spin_unlock_irqrestore(&host->lock, flags); 2754 } 2755 2756 return isr ? IRQ_HANDLED : IRQ_NONE; 2757 } 2758 2759 /*****************************************************************************\ 2760 * * 2761 * Suspend/resume * 2762 * * 2763 \*****************************************************************************/ 2764 2765 #ifdef CONFIG_PM 2766 /* 2767 * To enable wakeup events, the corresponding events have to be enabled in 2768 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 2769 * Table' in the SD Host Controller Standard Specification. 2770 * It is useless to restore SDHCI_INT_ENABLE state in 2771 * sdhci_disable_irq_wakeups() since it will be set by 2772 * sdhci_enable_card_detection() or sdhci_init(). 2773 */ 2774 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2775 { 2776 u8 val; 2777 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2778 | SDHCI_WAKE_ON_INT; 2779 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2780 SDHCI_INT_CARD_INT; 2781 2782 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2783 val |= mask ; 2784 /* Avoid fake wake up */ 2785 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) { 2786 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2787 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2788 } 2789 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2790 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 2791 } 2792 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2793 2794 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2795 { 2796 u8 val; 2797 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2798 | SDHCI_WAKE_ON_INT; 2799 2800 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2801 val &= ~mask; 2802 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2803 } 2804 2805 int sdhci_suspend_host(struct sdhci_host *host) 2806 { 2807 sdhci_disable_card_detection(host); 2808 2809 mmc_retune_timer_stop(host->mmc); 2810 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2811 mmc_retune_needed(host->mmc); 2812 2813 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2814 host->ier = 0; 2815 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2816 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2817 free_irq(host->irq, host); 2818 } else { 2819 sdhci_enable_irq_wakeups(host); 2820 enable_irq_wake(host->irq); 2821 } 2822 return 0; 2823 } 2824 2825 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2826 2827 int sdhci_resume_host(struct sdhci_host *host) 2828 { 2829 struct mmc_host *mmc = host->mmc; 2830 int ret = 0; 2831 2832 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2833 if (host->ops->enable_dma) 2834 host->ops->enable_dma(host); 2835 } 2836 2837 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2838 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2839 /* Card keeps power but host controller does not */ 2840 sdhci_init(host, 0); 2841 host->pwr = 0; 2842 host->clock = 0; 2843 mmc->ops->set_ios(mmc, &mmc->ios); 2844 } else { 2845 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2846 mmiowb(); 2847 } 2848 2849 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2850 ret = request_threaded_irq(host->irq, sdhci_irq, 2851 sdhci_thread_irq, IRQF_SHARED, 2852 mmc_hostname(host->mmc), host); 2853 if (ret) 2854 return ret; 2855 } else { 2856 sdhci_disable_irq_wakeups(host); 2857 disable_irq_wake(host->irq); 2858 } 2859 2860 sdhci_enable_card_detection(host); 2861 2862 return ret; 2863 } 2864 2865 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2866 2867 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2868 { 2869 unsigned long flags; 2870 2871 mmc_retune_timer_stop(host->mmc); 2872 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2873 mmc_retune_needed(host->mmc); 2874 2875 spin_lock_irqsave(&host->lock, flags); 2876 host->ier &= SDHCI_INT_CARD_INT; 2877 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2878 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2879 spin_unlock_irqrestore(&host->lock, flags); 2880 2881 synchronize_hardirq(host->irq); 2882 2883 spin_lock_irqsave(&host->lock, flags); 2884 host->runtime_suspended = true; 2885 spin_unlock_irqrestore(&host->lock, flags); 2886 2887 return 0; 2888 } 2889 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2890 2891 int sdhci_runtime_resume_host(struct sdhci_host *host) 2892 { 2893 struct mmc_host *mmc = host->mmc; 2894 unsigned long flags; 2895 int host_flags = host->flags; 2896 2897 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2898 if (host->ops->enable_dma) 2899 host->ops->enable_dma(host); 2900 } 2901 2902 sdhci_init(host, 0); 2903 2904 /* Force clock and power re-program */ 2905 host->pwr = 0; 2906 host->clock = 0; 2907 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 2908 mmc->ops->set_ios(mmc, &mmc->ios); 2909 2910 if ((host_flags & SDHCI_PV_ENABLED) && 2911 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2912 spin_lock_irqsave(&host->lock, flags); 2913 sdhci_enable_preset_value(host, true); 2914 spin_unlock_irqrestore(&host->lock, flags); 2915 } 2916 2917 spin_lock_irqsave(&host->lock, flags); 2918 2919 host->runtime_suspended = false; 2920 2921 /* Enable SDIO IRQ */ 2922 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2923 sdhci_enable_sdio_irq_nolock(host, true); 2924 2925 /* Enable Card Detection */ 2926 sdhci_enable_card_detection(host); 2927 2928 spin_unlock_irqrestore(&host->lock, flags); 2929 2930 return 0; 2931 } 2932 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2933 2934 #endif /* CONFIG_PM */ 2935 2936 /*****************************************************************************\ 2937 * * 2938 * Device allocation/registration * 2939 * * 2940 \*****************************************************************************/ 2941 2942 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2943 size_t priv_size) 2944 { 2945 struct mmc_host *mmc; 2946 struct sdhci_host *host; 2947 2948 WARN_ON(dev == NULL); 2949 2950 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2951 if (!mmc) 2952 return ERR_PTR(-ENOMEM); 2953 2954 host = mmc_priv(mmc); 2955 host->mmc = mmc; 2956 host->mmc_host_ops = sdhci_ops; 2957 mmc->ops = &host->mmc_host_ops; 2958 2959 host->flags = SDHCI_SIGNALING_330; 2960 2961 return host; 2962 } 2963 2964 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2965 2966 static int sdhci_set_dma_mask(struct sdhci_host *host) 2967 { 2968 struct mmc_host *mmc = host->mmc; 2969 struct device *dev = mmc_dev(mmc); 2970 int ret = -EINVAL; 2971 2972 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 2973 host->flags &= ~SDHCI_USE_64_BIT_DMA; 2974 2975 /* Try 64-bit mask if hardware is capable of it */ 2976 if (host->flags & SDHCI_USE_64_BIT_DMA) { 2977 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 2978 if (ret) { 2979 pr_warn("%s: Failed to set 64-bit DMA mask.\n", 2980 mmc_hostname(mmc)); 2981 host->flags &= ~SDHCI_USE_64_BIT_DMA; 2982 } 2983 } 2984 2985 /* 32-bit mask as default & fallback */ 2986 if (ret) { 2987 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 2988 if (ret) 2989 pr_warn("%s: Failed to set 32-bit DMA mask.\n", 2990 mmc_hostname(mmc)); 2991 } 2992 2993 return ret; 2994 } 2995 2996 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 2997 { 2998 u16 v; 2999 3000 if (host->read_caps) 3001 return; 3002 3003 host->read_caps = true; 3004 3005 if (debug_quirks) 3006 host->quirks = debug_quirks; 3007 3008 if (debug_quirks2) 3009 host->quirks2 = debug_quirks2; 3010 3011 sdhci_do_reset(host, SDHCI_RESET_ALL); 3012 3013 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 3014 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 3015 3016 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 3017 return; 3018 3019 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES); 3020 3021 if (host->version < SDHCI_SPEC_300) 3022 return; 3023 3024 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1); 3025 } 3026 EXPORT_SYMBOL_GPL(__sdhci_read_caps); 3027 3028 int sdhci_setup_host(struct sdhci_host *host) 3029 { 3030 struct mmc_host *mmc; 3031 u32 max_current_caps; 3032 unsigned int ocr_avail; 3033 unsigned int override_timeout_clk; 3034 u32 max_clk; 3035 int ret; 3036 3037 WARN_ON(host == NULL); 3038 if (host == NULL) 3039 return -EINVAL; 3040 3041 mmc = host->mmc; 3042 3043 /* 3044 * If there are external regulators, get them. Note this must be done 3045 * early before resetting the host and reading the capabilities so that 3046 * the host can take the appropriate action if regulators are not 3047 * available. 3048 */ 3049 ret = mmc_regulator_get_supply(mmc); 3050 if (ret == -EPROBE_DEFER) 3051 return ret; 3052 3053 sdhci_read_caps(host); 3054 3055 override_timeout_clk = host->timeout_clk; 3056 3057 if (host->version > SDHCI_SPEC_300) { 3058 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 3059 mmc_hostname(mmc), host->version); 3060 } 3061 3062 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3063 host->flags |= SDHCI_USE_SDMA; 3064 else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3065 DBG("Controller doesn't have SDMA capability\n"); 3066 else 3067 host->flags |= SDHCI_USE_SDMA; 3068 3069 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3070 (host->flags & SDHCI_USE_SDMA)) { 3071 DBG("Disabling DMA as it is marked broken\n"); 3072 host->flags &= ~SDHCI_USE_SDMA; 3073 } 3074 3075 if ((host->version >= SDHCI_SPEC_200) && 3076 (host->caps & SDHCI_CAN_DO_ADMA2)) 3077 host->flags |= SDHCI_USE_ADMA; 3078 3079 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 3080 (host->flags & SDHCI_USE_ADMA)) { 3081 DBG("Disabling ADMA as it is marked broken\n"); 3082 host->flags &= ~SDHCI_USE_ADMA; 3083 } 3084 3085 /* 3086 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 3087 * and *must* do 64-bit DMA. A driver has the opportunity to change 3088 * that during the first call to ->enable_dma(). Similarly 3089 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3090 * implement. 3091 */ 3092 if (host->caps & SDHCI_CAN_64BIT) 3093 host->flags |= SDHCI_USE_64_BIT_DMA; 3094 3095 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3096 ret = sdhci_set_dma_mask(host); 3097 3098 if (!ret && host->ops->enable_dma) 3099 ret = host->ops->enable_dma(host); 3100 3101 if (ret) { 3102 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 3103 mmc_hostname(mmc)); 3104 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 3105 3106 ret = 0; 3107 } 3108 } 3109 3110 /* SDMA does not support 64-bit DMA */ 3111 if (host->flags & SDHCI_USE_64_BIT_DMA) 3112 host->flags &= ~SDHCI_USE_SDMA; 3113 3114 if (host->flags & SDHCI_USE_ADMA) { 3115 dma_addr_t dma; 3116 void *buf; 3117 3118 /* 3119 * The DMA descriptor table size is calculated as the maximum 3120 * number of segments times 2, to allow for an alignment 3121 * descriptor for each segment, plus 1 for a nop end descriptor, 3122 * all multipled by the descriptor size. 3123 */ 3124 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3125 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3126 SDHCI_ADMA2_64_DESC_SZ; 3127 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 3128 } else { 3129 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3130 SDHCI_ADMA2_32_DESC_SZ; 3131 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 3132 } 3133 3134 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 3135 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + 3136 host->adma_table_sz, &dma, GFP_KERNEL); 3137 if (!buf) { 3138 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 3139 mmc_hostname(mmc)); 3140 host->flags &= ~SDHCI_USE_ADMA; 3141 } else if ((dma + host->align_buffer_sz) & 3142 (SDHCI_ADMA2_DESC_ALIGN - 1)) { 3143 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 3144 mmc_hostname(mmc)); 3145 host->flags &= ~SDHCI_USE_ADMA; 3146 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3147 host->adma_table_sz, buf, dma); 3148 } else { 3149 host->align_buffer = buf; 3150 host->align_addr = dma; 3151 3152 host->adma_table = buf + host->align_buffer_sz; 3153 host->adma_addr = dma + host->align_buffer_sz; 3154 } 3155 } 3156 3157 /* 3158 * If we use DMA, then it's up to the caller to set the DMA 3159 * mask, but PIO does not need the hw shim so we set a new 3160 * mask here in that case. 3161 */ 3162 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 3163 host->dma_mask = DMA_BIT_MASK(64); 3164 mmc_dev(mmc)->dma_mask = &host->dma_mask; 3165 } 3166 3167 if (host->version >= SDHCI_SPEC_300) 3168 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 3169 >> SDHCI_CLOCK_BASE_SHIFT; 3170 else 3171 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 3172 >> SDHCI_CLOCK_BASE_SHIFT; 3173 3174 host->max_clk *= 1000000; 3175 if (host->max_clk == 0 || host->quirks & 3176 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 3177 if (!host->ops->get_max_clock) { 3178 pr_err("%s: Hardware doesn't specify base clock frequency.\n", 3179 mmc_hostname(mmc)); 3180 ret = -ENODEV; 3181 goto undma; 3182 } 3183 host->max_clk = host->ops->get_max_clock(host); 3184 } 3185 3186 /* 3187 * In case of Host Controller v3.00, find out whether clock 3188 * multiplier is supported. 3189 */ 3190 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 3191 SDHCI_CLOCK_MUL_SHIFT; 3192 3193 /* 3194 * In case the value in Clock Multiplier is 0, then programmable 3195 * clock mode is not supported, otherwise the actual clock 3196 * multiplier is one more than the value of Clock Multiplier 3197 * in the Capabilities Register. 3198 */ 3199 if (host->clk_mul) 3200 host->clk_mul += 1; 3201 3202 /* 3203 * Set host parameters. 3204 */ 3205 max_clk = host->max_clk; 3206 3207 if (host->ops->get_min_clock) 3208 mmc->f_min = host->ops->get_min_clock(host); 3209 else if (host->version >= SDHCI_SPEC_300) { 3210 if (host->clk_mul) { 3211 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3212 max_clk = host->max_clk * host->clk_mul; 3213 } else 3214 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3215 } else 3216 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3217 3218 if (!mmc->f_max || mmc->f_max > max_clk) 3219 mmc->f_max = max_clk; 3220 3221 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3222 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 3223 SDHCI_TIMEOUT_CLK_SHIFT; 3224 if (host->timeout_clk == 0) { 3225 if (host->ops->get_timeout_clock) { 3226 host->timeout_clk = 3227 host->ops->get_timeout_clock(host); 3228 } else { 3229 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3230 mmc_hostname(mmc)); 3231 ret = -ENODEV; 3232 goto undma; 3233 } 3234 } 3235 3236 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 3237 host->timeout_clk *= 1000; 3238 3239 if (override_timeout_clk) 3240 host->timeout_clk = override_timeout_clk; 3241 3242 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3243 host->ops->get_max_timeout_count(host) : 1 << 27; 3244 mmc->max_busy_timeout /= host->timeout_clk; 3245 } 3246 3247 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3248 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3249 3250 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3251 host->flags |= SDHCI_AUTO_CMD12; 3252 3253 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 3254 if ((host->version >= SDHCI_SPEC_300) && 3255 ((host->flags & SDHCI_USE_ADMA) || 3256 !(host->flags & SDHCI_USE_SDMA)) && 3257 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 3258 host->flags |= SDHCI_AUTO_CMD23; 3259 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 3260 } else { 3261 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 3262 } 3263 3264 /* 3265 * A controller may support 8-bit width, but the board itself 3266 * might not have the pins brought out. Boards that support 3267 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3268 * their platform code before calling sdhci_add_host(), and we 3269 * won't assume 8-bit width for hosts without that CAP. 3270 */ 3271 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3272 mmc->caps |= MMC_CAP_4_BIT_DATA; 3273 3274 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3275 mmc->caps &= ~MMC_CAP_CMD23; 3276 3277 if (host->caps & SDHCI_CAN_DO_HISPD) 3278 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3279 3280 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3281 mmc_card_is_removable(mmc) && 3282 mmc_gpio_get_cd(host->mmc) < 0) 3283 mmc->caps |= MMC_CAP_NEEDS_POLL; 3284 3285 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3286 if (!IS_ERR(mmc->supply.vqmmc)) { 3287 ret = regulator_enable(mmc->supply.vqmmc); 3288 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3289 1950000)) 3290 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 3291 SDHCI_SUPPORT_SDR50 | 3292 SDHCI_SUPPORT_DDR50); 3293 if (ret) { 3294 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3295 mmc_hostname(mmc), ret); 3296 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3297 } 3298 } 3299 3300 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 3301 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3302 SDHCI_SUPPORT_DDR50); 3303 } 3304 3305 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3306 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3307 SDHCI_SUPPORT_DDR50)) 3308 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3309 3310 /* SDR104 supports also implies SDR50 support */ 3311 if (host->caps1 & SDHCI_SUPPORT_SDR104) { 3312 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3313 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3314 * field can be promoted to support HS200. 3315 */ 3316 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3317 mmc->caps2 |= MMC_CAP2_HS200; 3318 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 3319 mmc->caps |= MMC_CAP_UHS_SDR50; 3320 } 3321 3322 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3323 (host->caps1 & SDHCI_SUPPORT_HS400)) 3324 mmc->caps2 |= MMC_CAP2_HS400; 3325 3326 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3327 (IS_ERR(mmc->supply.vqmmc) || 3328 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3329 1300000))) 3330 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3331 3332 if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 3333 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3334 mmc->caps |= MMC_CAP_UHS_DDR50; 3335 3336 /* Does the host need tuning for SDR50? */ 3337 if (host->caps1 & SDHCI_USE_SDR50_TUNING) 3338 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3339 3340 /* Driver Type(s) (A, C, D) supported by the host */ 3341 if (host->caps1 & SDHCI_DRIVER_TYPE_A) 3342 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3343 if (host->caps1 & SDHCI_DRIVER_TYPE_C) 3344 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3345 if (host->caps1 & SDHCI_DRIVER_TYPE_D) 3346 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3347 3348 /* Initial value for re-tuning timer count */ 3349 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3350 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3351 3352 /* 3353 * In case Re-tuning Timer is not disabled, the actual value of 3354 * re-tuning timer will be 2 ^ (n - 1). 3355 */ 3356 if (host->tuning_count) 3357 host->tuning_count = 1 << (host->tuning_count - 1); 3358 3359 /* Re-tuning mode supported by the Host Controller */ 3360 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 3361 SDHCI_RETUNING_MODE_SHIFT; 3362 3363 ocr_avail = 0; 3364 3365 /* 3366 * According to SD Host Controller spec v3.00, if the Host System 3367 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3368 * the value is meaningful only if Voltage Support in the Capabilities 3369 * register is set. The actual current value is 4 times the register 3370 * value. 3371 */ 3372 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3373 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3374 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3375 if (curr > 0) { 3376 3377 /* convert to SDHCI_MAX_CURRENT format */ 3378 curr = curr/1000; /* convert to mA */ 3379 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3380 3381 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3382 max_current_caps = 3383 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3384 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3385 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3386 } 3387 } 3388 3389 if (host->caps & SDHCI_CAN_VDD_330) { 3390 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3391 3392 mmc->max_current_330 = ((max_current_caps & 3393 SDHCI_MAX_CURRENT_330_MASK) >> 3394 SDHCI_MAX_CURRENT_330_SHIFT) * 3395 SDHCI_MAX_CURRENT_MULTIPLIER; 3396 } 3397 if (host->caps & SDHCI_CAN_VDD_300) { 3398 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3399 3400 mmc->max_current_300 = ((max_current_caps & 3401 SDHCI_MAX_CURRENT_300_MASK) >> 3402 SDHCI_MAX_CURRENT_300_SHIFT) * 3403 SDHCI_MAX_CURRENT_MULTIPLIER; 3404 } 3405 if (host->caps & SDHCI_CAN_VDD_180) { 3406 ocr_avail |= MMC_VDD_165_195; 3407 3408 mmc->max_current_180 = ((max_current_caps & 3409 SDHCI_MAX_CURRENT_180_MASK) >> 3410 SDHCI_MAX_CURRENT_180_SHIFT) * 3411 SDHCI_MAX_CURRENT_MULTIPLIER; 3412 } 3413 3414 /* If OCR set by host, use it instead. */ 3415 if (host->ocr_mask) 3416 ocr_avail = host->ocr_mask; 3417 3418 /* If OCR set by external regulators, give it highest prio. */ 3419 if (mmc->ocr_avail) 3420 ocr_avail = mmc->ocr_avail; 3421 3422 mmc->ocr_avail = ocr_avail; 3423 mmc->ocr_avail_sdio = ocr_avail; 3424 if (host->ocr_avail_sdio) 3425 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3426 mmc->ocr_avail_sd = ocr_avail; 3427 if (host->ocr_avail_sd) 3428 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3429 else /* normal SD controllers don't support 1.8V */ 3430 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3431 mmc->ocr_avail_mmc = ocr_avail; 3432 if (host->ocr_avail_mmc) 3433 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3434 3435 if (mmc->ocr_avail == 0) { 3436 pr_err("%s: Hardware doesn't report any support voltages.\n", 3437 mmc_hostname(mmc)); 3438 ret = -ENODEV; 3439 goto unreg; 3440 } 3441 3442 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 3443 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 3444 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 3445 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 3446 host->flags |= SDHCI_SIGNALING_180; 3447 3448 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 3449 host->flags |= SDHCI_SIGNALING_120; 3450 3451 spin_lock_init(&host->lock); 3452 3453 /* 3454 * Maximum number of segments. Depends on if the hardware 3455 * can do scatter/gather or not. 3456 */ 3457 if (host->flags & SDHCI_USE_ADMA) 3458 mmc->max_segs = SDHCI_MAX_SEGS; 3459 else if (host->flags & SDHCI_USE_SDMA) 3460 mmc->max_segs = 1; 3461 else /* PIO */ 3462 mmc->max_segs = SDHCI_MAX_SEGS; 3463 3464 /* 3465 * Maximum number of sectors in one transfer. Limited by SDMA boundary 3466 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3467 * is less anyway. 3468 */ 3469 mmc->max_req_size = 524288; 3470 3471 /* 3472 * Maximum segment size. Could be one segment with the maximum number 3473 * of bytes. When doing hardware scatter/gather, each entry cannot 3474 * be larger than 64 KiB though. 3475 */ 3476 if (host->flags & SDHCI_USE_ADMA) { 3477 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3478 mmc->max_seg_size = 65535; 3479 else 3480 mmc->max_seg_size = 65536; 3481 } else { 3482 mmc->max_seg_size = mmc->max_req_size; 3483 } 3484 3485 /* 3486 * Maximum block size. This varies from controller to controller and 3487 * is specified in the capabilities register. 3488 */ 3489 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3490 mmc->max_blk_size = 2; 3491 } else { 3492 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 3493 SDHCI_MAX_BLOCK_SHIFT; 3494 if (mmc->max_blk_size >= 3) { 3495 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3496 mmc_hostname(mmc)); 3497 mmc->max_blk_size = 0; 3498 } 3499 } 3500 3501 mmc->max_blk_size = 512 << mmc->max_blk_size; 3502 3503 /* 3504 * Maximum block count. 3505 */ 3506 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3507 3508 return 0; 3509 3510 unreg: 3511 if (!IS_ERR(mmc->supply.vqmmc)) 3512 regulator_disable(mmc->supply.vqmmc); 3513 undma: 3514 if (host->align_buffer) 3515 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3516 host->adma_table_sz, host->align_buffer, 3517 host->align_addr); 3518 host->adma_table = NULL; 3519 host->align_buffer = NULL; 3520 3521 return ret; 3522 } 3523 EXPORT_SYMBOL_GPL(sdhci_setup_host); 3524 3525 int __sdhci_add_host(struct sdhci_host *host) 3526 { 3527 struct mmc_host *mmc = host->mmc; 3528 int ret; 3529 3530 /* 3531 * Init tasklets. 3532 */ 3533 tasklet_init(&host->finish_tasklet, 3534 sdhci_tasklet_finish, (unsigned long)host); 3535 3536 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3537 setup_timer(&host->data_timer, sdhci_timeout_data_timer, 3538 (unsigned long)host); 3539 3540 init_waitqueue_head(&host->buf_ready_int); 3541 3542 sdhci_init(host, 0); 3543 3544 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3545 IRQF_SHARED, mmc_hostname(mmc), host); 3546 if (ret) { 3547 pr_err("%s: Failed to request IRQ %d: %d\n", 3548 mmc_hostname(mmc), host->irq, ret); 3549 goto untasklet; 3550 } 3551 3552 #ifdef CONFIG_MMC_DEBUG 3553 sdhci_dumpregs(host); 3554 #endif 3555 3556 ret = sdhci_led_register(host); 3557 if (ret) { 3558 pr_err("%s: Failed to register LED device: %d\n", 3559 mmc_hostname(mmc), ret); 3560 goto unirq; 3561 } 3562 3563 mmiowb(); 3564 3565 ret = mmc_add_host(mmc); 3566 if (ret) 3567 goto unled; 3568 3569 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3570 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3571 (host->flags & SDHCI_USE_ADMA) ? 3572 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3573 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3574 3575 sdhci_enable_card_detection(host); 3576 3577 return 0; 3578 3579 unled: 3580 sdhci_led_unregister(host); 3581 unirq: 3582 sdhci_do_reset(host, SDHCI_RESET_ALL); 3583 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3584 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3585 free_irq(host->irq, host); 3586 untasklet: 3587 tasklet_kill(&host->finish_tasklet); 3588 3589 if (!IS_ERR(mmc->supply.vqmmc)) 3590 regulator_disable(mmc->supply.vqmmc); 3591 3592 if (host->align_buffer) 3593 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3594 host->adma_table_sz, host->align_buffer, 3595 host->align_addr); 3596 host->adma_table = NULL; 3597 host->align_buffer = NULL; 3598 3599 return ret; 3600 } 3601 EXPORT_SYMBOL_GPL(__sdhci_add_host); 3602 3603 int sdhci_add_host(struct sdhci_host *host) 3604 { 3605 int ret; 3606 3607 ret = sdhci_setup_host(host); 3608 if (ret) 3609 return ret; 3610 3611 return __sdhci_add_host(host); 3612 } 3613 EXPORT_SYMBOL_GPL(sdhci_add_host); 3614 3615 void sdhci_remove_host(struct sdhci_host *host, int dead) 3616 { 3617 struct mmc_host *mmc = host->mmc; 3618 unsigned long flags; 3619 3620 if (dead) { 3621 spin_lock_irqsave(&host->lock, flags); 3622 3623 host->flags |= SDHCI_DEVICE_DEAD; 3624 3625 if (sdhci_has_requests(host)) { 3626 pr_err("%s: Controller removed during " 3627 " transfer!\n", mmc_hostname(mmc)); 3628 sdhci_error_out_mrqs(host, -ENOMEDIUM); 3629 } 3630 3631 spin_unlock_irqrestore(&host->lock, flags); 3632 } 3633 3634 sdhci_disable_card_detection(host); 3635 3636 mmc_remove_host(mmc); 3637 3638 sdhci_led_unregister(host); 3639 3640 if (!dead) 3641 sdhci_do_reset(host, SDHCI_RESET_ALL); 3642 3643 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3644 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3645 free_irq(host->irq, host); 3646 3647 del_timer_sync(&host->timer); 3648 del_timer_sync(&host->data_timer); 3649 3650 tasklet_kill(&host->finish_tasklet); 3651 3652 if (!IS_ERR(mmc->supply.vqmmc)) 3653 regulator_disable(mmc->supply.vqmmc); 3654 3655 if (host->align_buffer) 3656 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3657 host->adma_table_sz, host->align_buffer, 3658 host->align_addr); 3659 3660 host->adma_table = NULL; 3661 host->align_buffer = NULL; 3662 } 3663 3664 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3665 3666 void sdhci_free_host(struct sdhci_host *host) 3667 { 3668 mmc_free_host(host->mmc); 3669 } 3670 3671 EXPORT_SYMBOL_GPL(sdhci_free_host); 3672 3673 /*****************************************************************************\ 3674 * * 3675 * Driver init/exit * 3676 * * 3677 \*****************************************************************************/ 3678 3679 static int __init sdhci_drv_init(void) 3680 { 3681 pr_info(DRIVER_NAME 3682 ": Secure Digital Host Controller Interface driver\n"); 3683 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3684 3685 return 0; 3686 } 3687 3688 static void __exit sdhci_drv_exit(void) 3689 { 3690 } 3691 3692 module_init(sdhci_drv_init); 3693 module_exit(sdhci_drv_exit); 3694 3695 module_param(debug_quirks, uint, 0444); 3696 module_param(debug_quirks2, uint, 0444); 3697 3698 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3699 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3700 MODULE_LICENSE("GPL"); 3701 3702 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3703 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3704