1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/slot-gpio.h> 32 33 #include "sdhci.h" 34 35 #define DRIVER_NAME "sdhci" 36 37 #define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42 #define SDHCI_USE_LEDS_CLASS 43 #endif 44 45 #define MAX_TUNING_LOOP 40 46 47 #define ADMA_SIZE ((128 * 2 + 1) * 4) 48 49 static unsigned int debug_quirks = 0; 50 static unsigned int debug_quirks2; 51 52 static void sdhci_finish_data(struct sdhci_host *); 53 54 static void sdhci_finish_command(struct sdhci_host *); 55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 56 static void sdhci_tuning_timer(unsigned long data); 57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 58 59 #ifdef CONFIG_PM_RUNTIME 60 static int sdhci_runtime_pm_get(struct sdhci_host *host); 61 static int sdhci_runtime_pm_put(struct sdhci_host *host); 62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 64 #else 65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 66 { 67 return 0; 68 } 69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 70 { 71 return 0; 72 } 73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 74 { 75 } 76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 77 { 78 } 79 #endif 80 81 static void sdhci_dumpregs(struct sdhci_host *host) 82 { 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 84 mmc_hostname(host->mmc)); 85 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 87 sdhci_readl(host, SDHCI_DMA_ADDRESS), 88 sdhci_readw(host, SDHCI_HOST_VERSION)); 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 90 sdhci_readw(host, SDHCI_BLOCK_SIZE), 91 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 93 sdhci_readl(host, SDHCI_ARGUMENT), 94 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 96 sdhci_readl(host, SDHCI_PRESENT_STATE), 97 sdhci_readb(host, SDHCI_HOST_CONTROL)); 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 99 sdhci_readb(host, SDHCI_POWER_CONTROL), 100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 103 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 106 sdhci_readl(host, SDHCI_INT_STATUS)); 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 108 sdhci_readl(host, SDHCI_INT_ENABLE), 109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 111 sdhci_readw(host, SDHCI_ACMD12_ERR), 112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 114 sdhci_readl(host, SDHCI_CAPABILITIES), 115 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 117 sdhci_readw(host, SDHCI_COMMAND), 118 sdhci_readl(host, SDHCI_MAX_CURRENT)); 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 120 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 121 122 if (host->flags & SDHCI_USE_ADMA) 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 124 readl(host->ioaddr + SDHCI_ADMA_ERROR), 125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 126 127 pr_debug(DRIVER_NAME ": ===========================================\n"); 128 } 129 130 /*****************************************************************************\ 131 * * 132 * Low level functions * 133 * * 134 \*****************************************************************************/ 135 136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 137 { 138 u32 present; 139 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 142 return; 143 144 if (enable) { 145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 146 SDHCI_CARD_PRESENT; 147 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 149 SDHCI_INT_CARD_INSERT; 150 } else { 151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 152 } 153 154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 156 } 157 158 static void sdhci_enable_card_detection(struct sdhci_host *host) 159 { 160 sdhci_set_card_detection(host, true); 161 } 162 163 static void sdhci_disable_card_detection(struct sdhci_host *host) 164 { 165 sdhci_set_card_detection(host, false); 166 } 167 168 void sdhci_reset(struct sdhci_host *host, u8 mask) 169 { 170 unsigned long timeout; 171 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 173 174 if (mask & SDHCI_RESET_ALL) { 175 host->clock = 0; 176 /* Reset-all turns off SD Bus Power */ 177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 178 sdhci_runtime_pm_bus_off(host); 179 } 180 181 /* Wait max 100 ms */ 182 timeout = 100; 183 184 /* hw clears the bit when it's done */ 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 186 if (timeout == 0) { 187 pr_err("%s: Reset 0x%x never completed.\n", 188 mmc_hostname(host->mmc), (int)mask); 189 sdhci_dumpregs(host); 190 return; 191 } 192 timeout--; 193 mdelay(1); 194 } 195 } 196 EXPORT_SYMBOL_GPL(sdhci_reset); 197 198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 199 { 200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 202 SDHCI_CARD_PRESENT)) 203 return; 204 } 205 206 host->ops->reset(host, mask); 207 208 if (mask & SDHCI_RESET_ALL) { 209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 210 if (host->ops->enable_dma) 211 host->ops->enable_dma(host); 212 } 213 214 /* Resetting the controller clears many */ 215 host->preset_enabled = false; 216 } 217 } 218 219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 220 221 static void sdhci_init(struct sdhci_host *host, int soft) 222 { 223 if (soft) 224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 225 else 226 sdhci_do_reset(host, SDHCI_RESET_ALL); 227 228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 232 SDHCI_INT_RESPONSE; 233 234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 236 237 if (soft) { 238 /* force clock reconfiguration */ 239 host->clock = 0; 240 sdhci_set_ios(host->mmc, &host->mmc->ios); 241 } 242 } 243 244 static void sdhci_reinit(struct sdhci_host *host) 245 { 246 sdhci_init(host, 0); 247 /* 248 * Retuning stuffs are affected by different cards inserted and only 249 * applicable to UHS-I cards. So reset these fields to their initial 250 * value when card is removed. 251 */ 252 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 253 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 254 255 del_timer_sync(&host->tuning_timer); 256 host->flags &= ~SDHCI_NEEDS_RETUNING; 257 host->mmc->max_blk_count = 258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 259 } 260 sdhci_enable_card_detection(host); 261 } 262 263 static void sdhci_activate_led(struct sdhci_host *host) 264 { 265 u8 ctrl; 266 267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 268 ctrl |= SDHCI_CTRL_LED; 269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 270 } 271 272 static void sdhci_deactivate_led(struct sdhci_host *host) 273 { 274 u8 ctrl; 275 276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 277 ctrl &= ~SDHCI_CTRL_LED; 278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 279 } 280 281 #ifdef SDHCI_USE_LEDS_CLASS 282 static void sdhci_led_control(struct led_classdev *led, 283 enum led_brightness brightness) 284 { 285 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 286 unsigned long flags; 287 288 spin_lock_irqsave(&host->lock, flags); 289 290 if (host->runtime_suspended) 291 goto out; 292 293 if (brightness == LED_OFF) 294 sdhci_deactivate_led(host); 295 else 296 sdhci_activate_led(host); 297 out: 298 spin_unlock_irqrestore(&host->lock, flags); 299 } 300 #endif 301 302 /*****************************************************************************\ 303 * * 304 * Core functions * 305 * * 306 \*****************************************************************************/ 307 308 static void sdhci_read_block_pio(struct sdhci_host *host) 309 { 310 unsigned long flags; 311 size_t blksize, len, chunk; 312 u32 uninitialized_var(scratch); 313 u8 *buf; 314 315 DBG("PIO reading\n"); 316 317 blksize = host->data->blksz; 318 chunk = 0; 319 320 local_irq_save(flags); 321 322 while (blksize) { 323 if (!sg_miter_next(&host->sg_miter)) 324 BUG(); 325 326 len = min(host->sg_miter.length, blksize); 327 328 blksize -= len; 329 host->sg_miter.consumed = len; 330 331 buf = host->sg_miter.addr; 332 333 while (len) { 334 if (chunk == 0) { 335 scratch = sdhci_readl(host, SDHCI_BUFFER); 336 chunk = 4; 337 } 338 339 *buf = scratch & 0xFF; 340 341 buf++; 342 scratch >>= 8; 343 chunk--; 344 len--; 345 } 346 } 347 348 sg_miter_stop(&host->sg_miter); 349 350 local_irq_restore(flags); 351 } 352 353 static void sdhci_write_block_pio(struct sdhci_host *host) 354 { 355 unsigned long flags; 356 size_t blksize, len, chunk; 357 u32 scratch; 358 u8 *buf; 359 360 DBG("PIO writing\n"); 361 362 blksize = host->data->blksz; 363 chunk = 0; 364 scratch = 0; 365 366 local_irq_save(flags); 367 368 while (blksize) { 369 if (!sg_miter_next(&host->sg_miter)) 370 BUG(); 371 372 len = min(host->sg_miter.length, blksize); 373 374 blksize -= len; 375 host->sg_miter.consumed = len; 376 377 buf = host->sg_miter.addr; 378 379 while (len) { 380 scratch |= (u32)*buf << (chunk * 8); 381 382 buf++; 383 chunk++; 384 len--; 385 386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 387 sdhci_writel(host, scratch, SDHCI_BUFFER); 388 chunk = 0; 389 scratch = 0; 390 } 391 } 392 } 393 394 sg_miter_stop(&host->sg_miter); 395 396 local_irq_restore(flags); 397 } 398 399 static void sdhci_transfer_pio(struct sdhci_host *host) 400 { 401 u32 mask; 402 403 BUG_ON(!host->data); 404 405 if (host->blocks == 0) 406 return; 407 408 if (host->data->flags & MMC_DATA_READ) 409 mask = SDHCI_DATA_AVAILABLE; 410 else 411 mask = SDHCI_SPACE_AVAILABLE; 412 413 /* 414 * Some controllers (JMicron JMB38x) mess up the buffer bits 415 * for transfers < 4 bytes. As long as it is just one block, 416 * we can ignore the bits. 417 */ 418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 419 (host->data->blocks == 1)) 420 mask = ~0; 421 422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 424 udelay(100); 425 426 if (host->data->flags & MMC_DATA_READ) 427 sdhci_read_block_pio(host); 428 else 429 sdhci_write_block_pio(host); 430 431 host->blocks--; 432 if (host->blocks == 0) 433 break; 434 } 435 436 DBG("PIO transfer complete.\n"); 437 } 438 439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 440 { 441 local_irq_save(*flags); 442 return kmap_atomic(sg_page(sg)) + sg->offset; 443 } 444 445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 446 { 447 kunmap_atomic(buffer); 448 local_irq_restore(*flags); 449 } 450 451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 452 { 453 __le32 *dataddr = (__le32 __force *)(desc + 4); 454 __le16 *cmdlen = (__le16 __force *)desc; 455 456 /* SDHCI specification says ADMA descriptors should be 4 byte 457 * aligned, so using 16 or 32bit operations should be safe. */ 458 459 cmdlen[0] = cpu_to_le16(cmd); 460 cmdlen[1] = cpu_to_le16(len); 461 462 dataddr[0] = cpu_to_le32(addr); 463 } 464 465 static int sdhci_adma_table_pre(struct sdhci_host *host, 466 struct mmc_data *data) 467 { 468 int direction; 469 470 u8 *desc; 471 u8 *align; 472 dma_addr_t addr; 473 dma_addr_t align_addr; 474 int len, offset; 475 476 struct scatterlist *sg; 477 int i; 478 char *buffer; 479 unsigned long flags; 480 481 /* 482 * The spec does not specify endianness of descriptor table. 483 * We currently guess that it is LE. 484 */ 485 486 if (data->flags & MMC_DATA_READ) 487 direction = DMA_FROM_DEVICE; 488 else 489 direction = DMA_TO_DEVICE; 490 491 host->align_addr = dma_map_single(mmc_dev(host->mmc), 492 host->align_buffer, 128 * 4, direction); 493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 494 goto fail; 495 BUG_ON(host->align_addr & 0x3); 496 497 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 498 data->sg, data->sg_len, direction); 499 if (host->sg_count == 0) 500 goto unmap_align; 501 502 desc = host->adma_desc; 503 align = host->align_buffer; 504 505 align_addr = host->align_addr; 506 507 for_each_sg(data->sg, sg, host->sg_count, i) { 508 addr = sg_dma_address(sg); 509 len = sg_dma_len(sg); 510 511 /* 512 * The SDHCI specification states that ADMA 513 * addresses must be 32-bit aligned. If they 514 * aren't, then we use a bounce buffer for 515 * the (up to three) bytes that screw up the 516 * alignment. 517 */ 518 offset = (4 - (addr & 0x3)) & 0x3; 519 if (offset) { 520 if (data->flags & MMC_DATA_WRITE) { 521 buffer = sdhci_kmap_atomic(sg, &flags); 522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 523 memcpy(align, buffer, offset); 524 sdhci_kunmap_atomic(buffer, &flags); 525 } 526 527 /* tran, valid */ 528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 529 530 BUG_ON(offset > 65536); 531 532 align += 4; 533 align_addr += 4; 534 535 desc += 8; 536 537 addr += offset; 538 len -= offset; 539 } 540 541 BUG_ON(len > 65536); 542 543 /* tran, valid */ 544 sdhci_set_adma_desc(desc, addr, len, 0x21); 545 desc += 8; 546 547 /* 548 * If this triggers then we have a calculation bug 549 * somewhere. :/ 550 */ 551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE); 552 } 553 554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 555 /* 556 * Mark the last descriptor as the terminating descriptor 557 */ 558 if (desc != host->adma_desc) { 559 desc -= 8; 560 desc[0] |= 0x2; /* end */ 561 } 562 } else { 563 /* 564 * Add a terminating entry. 565 */ 566 567 /* nop, end, valid */ 568 sdhci_set_adma_desc(desc, 0, 0, 0x3); 569 } 570 571 /* 572 * Resync align buffer as we might have changed it. 573 */ 574 if (data->flags & MMC_DATA_WRITE) { 575 dma_sync_single_for_device(mmc_dev(host->mmc), 576 host->align_addr, 128 * 4, direction); 577 } 578 579 return 0; 580 581 unmap_align: 582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 583 128 * 4, direction); 584 fail: 585 return -EINVAL; 586 } 587 588 static void sdhci_adma_table_post(struct sdhci_host *host, 589 struct mmc_data *data) 590 { 591 int direction; 592 593 struct scatterlist *sg; 594 int i, size; 595 u8 *align; 596 char *buffer; 597 unsigned long flags; 598 bool has_unaligned; 599 600 if (data->flags & MMC_DATA_READ) 601 direction = DMA_FROM_DEVICE; 602 else 603 direction = DMA_TO_DEVICE; 604 605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 606 128 * 4, direction); 607 608 /* Do a quick scan of the SG list for any unaligned mappings */ 609 has_unaligned = false; 610 for_each_sg(data->sg, sg, host->sg_count, i) 611 if (sg_dma_address(sg) & 3) { 612 has_unaligned = true; 613 break; 614 } 615 616 if (has_unaligned && data->flags & MMC_DATA_READ) { 617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 618 data->sg_len, direction); 619 620 align = host->align_buffer; 621 622 for_each_sg(data->sg, sg, host->sg_count, i) { 623 if (sg_dma_address(sg) & 0x3) { 624 size = 4 - (sg_dma_address(sg) & 0x3); 625 626 buffer = sdhci_kmap_atomic(sg, &flags); 627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 628 memcpy(buffer, align, size); 629 sdhci_kunmap_atomic(buffer, &flags); 630 631 align += 4; 632 } 633 } 634 } 635 636 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 637 data->sg_len, direction); 638 } 639 640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 641 { 642 u8 count; 643 struct mmc_data *data = cmd->data; 644 unsigned target_timeout, current_timeout; 645 646 /* 647 * If the host controller provides us with an incorrect timeout 648 * value, just skip the check and use 0xE. The hardware may take 649 * longer to time out, but that's much better than having a too-short 650 * timeout value. 651 */ 652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 653 return 0xE; 654 655 /* Unspecified timeout, assume max */ 656 if (!data && !cmd->busy_timeout) 657 return 0xE; 658 659 /* timeout in us */ 660 if (!data) 661 target_timeout = cmd->busy_timeout * 1000; 662 else { 663 target_timeout = data->timeout_ns / 1000; 664 if (host->clock) 665 target_timeout += data->timeout_clks / host->clock; 666 } 667 668 /* 669 * Figure out needed cycles. 670 * We do this in steps in order to fit inside a 32 bit int. 671 * The first step is the minimum timeout, which will have a 672 * minimum resolution of 6 bits: 673 * (1) 2^13*1000 > 2^22, 674 * (2) host->timeout_clk < 2^16 675 * => 676 * (1) / (2) > 2^6 677 */ 678 count = 0; 679 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 680 while (current_timeout < target_timeout) { 681 count++; 682 current_timeout <<= 1; 683 if (count >= 0xF) 684 break; 685 } 686 687 if (count >= 0xF) { 688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 689 mmc_hostname(host->mmc), count, cmd->opcode); 690 count = 0xE; 691 } 692 693 return count; 694 } 695 696 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 697 { 698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 700 701 if (host->flags & SDHCI_REQ_USE_DMA) 702 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 703 else 704 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 705 706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 708 } 709 710 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 711 { 712 u8 count; 713 u8 ctrl; 714 struct mmc_data *data = cmd->data; 715 int ret; 716 717 WARN_ON(host->data); 718 719 if (data || (cmd->flags & MMC_RSP_BUSY)) { 720 count = sdhci_calc_timeout(host, cmd); 721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 722 } 723 724 if (!data) 725 return; 726 727 /* Sanity checks */ 728 BUG_ON(data->blksz * data->blocks > 524288); 729 BUG_ON(data->blksz > host->mmc->max_blk_size); 730 BUG_ON(data->blocks > 65535); 731 732 host->data = data; 733 host->data_early = 0; 734 host->data->bytes_xfered = 0; 735 736 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 737 host->flags |= SDHCI_REQ_USE_DMA; 738 739 /* 740 * FIXME: This doesn't account for merging when mapping the 741 * scatterlist. 742 */ 743 if (host->flags & SDHCI_REQ_USE_DMA) { 744 int broken, i; 745 struct scatterlist *sg; 746 747 broken = 0; 748 if (host->flags & SDHCI_USE_ADMA) { 749 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 750 broken = 1; 751 } else { 752 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 753 broken = 1; 754 } 755 756 if (unlikely(broken)) { 757 for_each_sg(data->sg, sg, data->sg_len, i) { 758 if (sg->length & 0x3) { 759 DBG("Reverting to PIO because of " 760 "transfer size (%d)\n", 761 sg->length); 762 host->flags &= ~SDHCI_REQ_USE_DMA; 763 break; 764 } 765 } 766 } 767 } 768 769 /* 770 * The assumption here being that alignment is the same after 771 * translation to device address space. 772 */ 773 if (host->flags & SDHCI_REQ_USE_DMA) { 774 int broken, i; 775 struct scatterlist *sg; 776 777 broken = 0; 778 if (host->flags & SDHCI_USE_ADMA) { 779 /* 780 * As we use 3 byte chunks to work around 781 * alignment problems, we need to check this 782 * quirk. 783 */ 784 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 785 broken = 1; 786 } else { 787 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 788 broken = 1; 789 } 790 791 if (unlikely(broken)) { 792 for_each_sg(data->sg, sg, data->sg_len, i) { 793 if (sg->offset & 0x3) { 794 DBG("Reverting to PIO because of " 795 "bad alignment\n"); 796 host->flags &= ~SDHCI_REQ_USE_DMA; 797 break; 798 } 799 } 800 } 801 } 802 803 if (host->flags & SDHCI_REQ_USE_DMA) { 804 if (host->flags & SDHCI_USE_ADMA) { 805 ret = sdhci_adma_table_pre(host, data); 806 if (ret) { 807 /* 808 * This only happens when someone fed 809 * us an invalid request. 810 */ 811 WARN_ON(1); 812 host->flags &= ~SDHCI_REQ_USE_DMA; 813 } else { 814 sdhci_writel(host, host->adma_addr, 815 SDHCI_ADMA_ADDRESS); 816 } 817 } else { 818 int sg_cnt; 819 820 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 821 data->sg, data->sg_len, 822 (data->flags & MMC_DATA_READ) ? 823 DMA_FROM_DEVICE : 824 DMA_TO_DEVICE); 825 if (sg_cnt == 0) { 826 /* 827 * This only happens when someone fed 828 * us an invalid request. 829 */ 830 WARN_ON(1); 831 host->flags &= ~SDHCI_REQ_USE_DMA; 832 } else { 833 WARN_ON(sg_cnt != 1); 834 sdhci_writel(host, sg_dma_address(data->sg), 835 SDHCI_DMA_ADDRESS); 836 } 837 } 838 } 839 840 /* 841 * Always adjust the DMA selection as some controllers 842 * (e.g. JMicron) can't do PIO properly when the selection 843 * is ADMA. 844 */ 845 if (host->version >= SDHCI_SPEC_200) { 846 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 847 ctrl &= ~SDHCI_CTRL_DMA_MASK; 848 if ((host->flags & SDHCI_REQ_USE_DMA) && 849 (host->flags & SDHCI_USE_ADMA)) 850 ctrl |= SDHCI_CTRL_ADMA32; 851 else 852 ctrl |= SDHCI_CTRL_SDMA; 853 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 854 } 855 856 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 857 int flags; 858 859 flags = SG_MITER_ATOMIC; 860 if (host->data->flags & MMC_DATA_READ) 861 flags |= SG_MITER_TO_SG; 862 else 863 flags |= SG_MITER_FROM_SG; 864 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 865 host->blocks = data->blocks; 866 } 867 868 sdhci_set_transfer_irqs(host); 869 870 /* Set the DMA boundary value and block size */ 871 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 872 data->blksz), SDHCI_BLOCK_SIZE); 873 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 874 } 875 876 static void sdhci_set_transfer_mode(struct sdhci_host *host, 877 struct mmc_command *cmd) 878 { 879 u16 mode; 880 struct mmc_data *data = cmd->data; 881 882 if (data == NULL) { 883 /* clear Auto CMD settings for no data CMDs */ 884 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 885 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 886 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 887 return; 888 } 889 890 WARN_ON(!host->data); 891 892 mode = SDHCI_TRNS_BLK_CNT_EN; 893 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 894 mode |= SDHCI_TRNS_MULTI; 895 /* 896 * If we are sending CMD23, CMD12 never gets sent 897 * on successful completion (so no Auto-CMD12). 898 */ 899 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 900 mode |= SDHCI_TRNS_AUTO_CMD12; 901 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 902 mode |= SDHCI_TRNS_AUTO_CMD23; 903 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 904 } 905 } 906 907 if (data->flags & MMC_DATA_READ) 908 mode |= SDHCI_TRNS_READ; 909 if (host->flags & SDHCI_REQ_USE_DMA) 910 mode |= SDHCI_TRNS_DMA; 911 912 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 913 } 914 915 static void sdhci_finish_data(struct sdhci_host *host) 916 { 917 struct mmc_data *data; 918 919 BUG_ON(!host->data); 920 921 data = host->data; 922 host->data = NULL; 923 924 if (host->flags & SDHCI_REQ_USE_DMA) { 925 if (host->flags & SDHCI_USE_ADMA) 926 sdhci_adma_table_post(host, data); 927 else { 928 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 929 data->sg_len, (data->flags & MMC_DATA_READ) ? 930 DMA_FROM_DEVICE : DMA_TO_DEVICE); 931 } 932 } 933 934 /* 935 * The specification states that the block count register must 936 * be updated, but it does not specify at what point in the 937 * data flow. That makes the register entirely useless to read 938 * back so we have to assume that nothing made it to the card 939 * in the event of an error. 940 */ 941 if (data->error) 942 data->bytes_xfered = 0; 943 else 944 data->bytes_xfered = data->blksz * data->blocks; 945 946 /* 947 * Need to send CMD12 if - 948 * a) open-ended multiblock transfer (no CMD23) 949 * b) error in multiblock transfer 950 */ 951 if (data->stop && 952 (data->error || 953 !host->mrq->sbc)) { 954 955 /* 956 * The controller needs a reset of internal state machines 957 * upon error conditions. 958 */ 959 if (data->error) { 960 sdhci_do_reset(host, SDHCI_RESET_CMD); 961 sdhci_do_reset(host, SDHCI_RESET_DATA); 962 } 963 964 sdhci_send_command(host, data->stop); 965 } else 966 tasklet_schedule(&host->finish_tasklet); 967 } 968 969 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 970 { 971 int flags; 972 u32 mask; 973 unsigned long timeout; 974 975 WARN_ON(host->cmd); 976 977 /* Wait max 10 ms */ 978 timeout = 10; 979 980 mask = SDHCI_CMD_INHIBIT; 981 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 982 mask |= SDHCI_DATA_INHIBIT; 983 984 /* We shouldn't wait for data inihibit for stop commands, even 985 though they might use busy signaling */ 986 if (host->mrq->data && (cmd == host->mrq->data->stop)) 987 mask &= ~SDHCI_DATA_INHIBIT; 988 989 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 990 if (timeout == 0) { 991 pr_err("%s: Controller never released " 992 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 993 sdhci_dumpregs(host); 994 cmd->error = -EIO; 995 tasklet_schedule(&host->finish_tasklet); 996 return; 997 } 998 timeout--; 999 mdelay(1); 1000 } 1001 1002 timeout = jiffies; 1003 if (!cmd->data && cmd->busy_timeout > 9000) 1004 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1005 else 1006 timeout += 10 * HZ; 1007 mod_timer(&host->timer, timeout); 1008 1009 host->cmd = cmd; 1010 1011 sdhci_prepare_data(host, cmd); 1012 1013 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1014 1015 sdhci_set_transfer_mode(host, cmd); 1016 1017 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1018 pr_err("%s: Unsupported response type!\n", 1019 mmc_hostname(host->mmc)); 1020 cmd->error = -EINVAL; 1021 tasklet_schedule(&host->finish_tasklet); 1022 return; 1023 } 1024 1025 if (!(cmd->flags & MMC_RSP_PRESENT)) 1026 flags = SDHCI_CMD_RESP_NONE; 1027 else if (cmd->flags & MMC_RSP_136) 1028 flags = SDHCI_CMD_RESP_LONG; 1029 else if (cmd->flags & MMC_RSP_BUSY) 1030 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1031 else 1032 flags = SDHCI_CMD_RESP_SHORT; 1033 1034 if (cmd->flags & MMC_RSP_CRC) 1035 flags |= SDHCI_CMD_CRC; 1036 if (cmd->flags & MMC_RSP_OPCODE) 1037 flags |= SDHCI_CMD_INDEX; 1038 1039 /* CMD19 is special in that the Data Present Select should be set */ 1040 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1041 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1042 flags |= SDHCI_CMD_DATA; 1043 1044 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1045 } 1046 EXPORT_SYMBOL_GPL(sdhci_send_command); 1047 1048 static void sdhci_finish_command(struct sdhci_host *host) 1049 { 1050 int i; 1051 1052 BUG_ON(host->cmd == NULL); 1053 1054 if (host->cmd->flags & MMC_RSP_PRESENT) { 1055 if (host->cmd->flags & MMC_RSP_136) { 1056 /* CRC is stripped so we need to do some shifting. */ 1057 for (i = 0;i < 4;i++) { 1058 host->cmd->resp[i] = sdhci_readl(host, 1059 SDHCI_RESPONSE + (3-i)*4) << 8; 1060 if (i != 3) 1061 host->cmd->resp[i] |= 1062 sdhci_readb(host, 1063 SDHCI_RESPONSE + (3-i)*4-1); 1064 } 1065 } else { 1066 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1067 } 1068 } 1069 1070 host->cmd->error = 0; 1071 1072 /* Finished CMD23, now send actual command. */ 1073 if (host->cmd == host->mrq->sbc) { 1074 host->cmd = NULL; 1075 sdhci_send_command(host, host->mrq->cmd); 1076 } else { 1077 1078 /* Processed actual command. */ 1079 if (host->data && host->data_early) 1080 sdhci_finish_data(host); 1081 1082 if (!host->cmd->data) 1083 tasklet_schedule(&host->finish_tasklet); 1084 1085 host->cmd = NULL; 1086 } 1087 } 1088 1089 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1090 { 1091 u16 preset = 0; 1092 1093 switch (host->timing) { 1094 case MMC_TIMING_UHS_SDR12: 1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1096 break; 1097 case MMC_TIMING_UHS_SDR25: 1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1099 break; 1100 case MMC_TIMING_UHS_SDR50: 1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1102 break; 1103 case MMC_TIMING_UHS_SDR104: 1104 case MMC_TIMING_MMC_HS200: 1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1106 break; 1107 case MMC_TIMING_UHS_DDR50: 1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1109 break; 1110 default: 1111 pr_warn("%s: Invalid UHS-I mode selected\n", 1112 mmc_hostname(host->mmc)); 1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1114 break; 1115 } 1116 return preset; 1117 } 1118 1119 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1120 { 1121 int div = 0; /* Initialized for compiler warning */ 1122 int real_div = div, clk_mul = 1; 1123 u16 clk = 0; 1124 unsigned long timeout; 1125 1126 host->mmc->actual_clock = 0; 1127 1128 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1129 1130 if (clock == 0) 1131 return; 1132 1133 if (host->version >= SDHCI_SPEC_300) { 1134 if (host->preset_enabled) { 1135 u16 pre_val; 1136 1137 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1138 pre_val = sdhci_get_preset_value(host); 1139 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1140 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1141 if (host->clk_mul && 1142 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1143 clk = SDHCI_PROG_CLOCK_MODE; 1144 real_div = div + 1; 1145 clk_mul = host->clk_mul; 1146 } else { 1147 real_div = max_t(int, 1, div << 1); 1148 } 1149 goto clock_set; 1150 } 1151 1152 /* 1153 * Check if the Host Controller supports Programmable Clock 1154 * Mode. 1155 */ 1156 if (host->clk_mul) { 1157 for (div = 1; div <= 1024; div++) { 1158 if ((host->max_clk * host->clk_mul / div) 1159 <= clock) 1160 break; 1161 } 1162 /* 1163 * Set Programmable Clock Mode in the Clock 1164 * Control register. 1165 */ 1166 clk = SDHCI_PROG_CLOCK_MODE; 1167 real_div = div; 1168 clk_mul = host->clk_mul; 1169 div--; 1170 } else { 1171 /* Version 3.00 divisors must be a multiple of 2. */ 1172 if (host->max_clk <= clock) 1173 div = 1; 1174 else { 1175 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1176 div += 2) { 1177 if ((host->max_clk / div) <= clock) 1178 break; 1179 } 1180 } 1181 real_div = div; 1182 div >>= 1; 1183 } 1184 } else { 1185 /* Version 2.00 divisors must be a power of 2. */ 1186 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1187 if ((host->max_clk / div) <= clock) 1188 break; 1189 } 1190 real_div = div; 1191 div >>= 1; 1192 } 1193 1194 clock_set: 1195 if (real_div) 1196 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1197 1198 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1199 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1200 << SDHCI_DIVIDER_HI_SHIFT; 1201 clk |= SDHCI_CLOCK_INT_EN; 1202 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1203 1204 /* Wait max 20 ms */ 1205 timeout = 20; 1206 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1207 & SDHCI_CLOCK_INT_STABLE)) { 1208 if (timeout == 0) { 1209 pr_err("%s: Internal clock never " 1210 "stabilised.\n", mmc_hostname(host->mmc)); 1211 sdhci_dumpregs(host); 1212 return; 1213 } 1214 timeout--; 1215 mdelay(1); 1216 } 1217 1218 clk |= SDHCI_CLOCK_CARD_EN; 1219 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1220 } 1221 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1222 1223 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1224 unsigned short vdd) 1225 { 1226 u8 pwr = 0; 1227 1228 if (mode != MMC_POWER_OFF) { 1229 switch (1 << vdd) { 1230 case MMC_VDD_165_195: 1231 pwr = SDHCI_POWER_180; 1232 break; 1233 case MMC_VDD_29_30: 1234 case MMC_VDD_30_31: 1235 pwr = SDHCI_POWER_300; 1236 break; 1237 case MMC_VDD_32_33: 1238 case MMC_VDD_33_34: 1239 pwr = SDHCI_POWER_330; 1240 break; 1241 default: 1242 BUG(); 1243 } 1244 } 1245 1246 if (host->pwr == pwr) 1247 return; 1248 1249 host->pwr = pwr; 1250 1251 if (pwr == 0) { 1252 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1253 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1254 sdhci_runtime_pm_bus_off(host); 1255 vdd = 0; 1256 } else { 1257 /* 1258 * Spec says that we should clear the power reg before setting 1259 * a new value. Some controllers don't seem to like this though. 1260 */ 1261 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1262 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1263 1264 /* 1265 * At least the Marvell CaFe chip gets confused if we set the 1266 * voltage and set turn on power at the same time, so set the 1267 * voltage first. 1268 */ 1269 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1270 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1271 1272 pwr |= SDHCI_POWER_ON; 1273 1274 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1275 1276 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1277 sdhci_runtime_pm_bus_on(host); 1278 1279 /* 1280 * Some controllers need an extra 10ms delay of 10ms before 1281 * they can apply clock after applying power 1282 */ 1283 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1284 mdelay(10); 1285 } 1286 1287 if (host->vmmc) { 1288 spin_unlock_irq(&host->lock); 1289 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd); 1290 spin_lock_irq(&host->lock); 1291 } 1292 } 1293 1294 /*****************************************************************************\ 1295 * * 1296 * MMC callbacks * 1297 * * 1298 \*****************************************************************************/ 1299 1300 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1301 { 1302 struct sdhci_host *host; 1303 int present; 1304 unsigned long flags; 1305 u32 tuning_opcode; 1306 1307 host = mmc_priv(mmc); 1308 1309 sdhci_runtime_pm_get(host); 1310 1311 spin_lock_irqsave(&host->lock, flags); 1312 1313 WARN_ON(host->mrq != NULL); 1314 1315 #ifndef SDHCI_USE_LEDS_CLASS 1316 sdhci_activate_led(host); 1317 #endif 1318 1319 /* 1320 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1321 * requests if Auto-CMD12 is enabled. 1322 */ 1323 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1324 if (mrq->stop) { 1325 mrq->data->stop = NULL; 1326 mrq->stop = NULL; 1327 } 1328 } 1329 1330 host->mrq = mrq; 1331 1332 /* 1333 * Firstly check card presence from cd-gpio. The return could 1334 * be one of the following possibilities: 1335 * negative: cd-gpio is not available 1336 * zero: cd-gpio is used, and card is removed 1337 * one: cd-gpio is used, and card is present 1338 */ 1339 present = mmc_gpio_get_cd(host->mmc); 1340 if (present < 0) { 1341 /* If polling, assume that the card is always present. */ 1342 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1343 present = 1; 1344 else 1345 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1346 SDHCI_CARD_PRESENT; 1347 } 1348 1349 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1350 host->mrq->cmd->error = -ENOMEDIUM; 1351 tasklet_schedule(&host->finish_tasklet); 1352 } else { 1353 u32 present_state; 1354 1355 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1356 /* 1357 * Check if the re-tuning timer has already expired and there 1358 * is no on-going data transfer. If so, we need to execute 1359 * tuning procedure before sending command. 1360 */ 1361 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1362 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1363 if (mmc->card) { 1364 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1365 tuning_opcode = 1366 mmc->card->type == MMC_TYPE_MMC ? 1367 MMC_SEND_TUNING_BLOCK_HS200 : 1368 MMC_SEND_TUNING_BLOCK; 1369 1370 /* Here we need to set the host->mrq to NULL, 1371 * in case the pending finish_tasklet 1372 * finishes it incorrectly. 1373 */ 1374 host->mrq = NULL; 1375 1376 spin_unlock_irqrestore(&host->lock, flags); 1377 sdhci_execute_tuning(mmc, tuning_opcode); 1378 spin_lock_irqsave(&host->lock, flags); 1379 1380 /* Restore original mmc_request structure */ 1381 host->mrq = mrq; 1382 } 1383 } 1384 1385 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1386 sdhci_send_command(host, mrq->sbc); 1387 else 1388 sdhci_send_command(host, mrq->cmd); 1389 } 1390 1391 mmiowb(); 1392 spin_unlock_irqrestore(&host->lock, flags); 1393 } 1394 1395 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1396 { 1397 u8 ctrl; 1398 1399 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1400 if (width == MMC_BUS_WIDTH_8) { 1401 ctrl &= ~SDHCI_CTRL_4BITBUS; 1402 if (host->version >= SDHCI_SPEC_300) 1403 ctrl |= SDHCI_CTRL_8BITBUS; 1404 } else { 1405 if (host->version >= SDHCI_SPEC_300) 1406 ctrl &= ~SDHCI_CTRL_8BITBUS; 1407 if (width == MMC_BUS_WIDTH_4) 1408 ctrl |= SDHCI_CTRL_4BITBUS; 1409 else 1410 ctrl &= ~SDHCI_CTRL_4BITBUS; 1411 } 1412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1413 } 1414 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1415 1416 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1417 { 1418 u16 ctrl_2; 1419 1420 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1421 /* Select Bus Speed Mode for host */ 1422 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1423 if ((timing == MMC_TIMING_MMC_HS200) || 1424 (timing == MMC_TIMING_UHS_SDR104)) 1425 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1426 else if (timing == MMC_TIMING_UHS_SDR12) 1427 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1428 else if (timing == MMC_TIMING_UHS_SDR25) 1429 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1430 else if (timing == MMC_TIMING_UHS_SDR50) 1431 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1432 else if ((timing == MMC_TIMING_UHS_DDR50) || 1433 (timing == MMC_TIMING_MMC_DDR52)) 1434 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1435 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1436 } 1437 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1438 1439 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1440 { 1441 unsigned long flags; 1442 u8 ctrl; 1443 1444 spin_lock_irqsave(&host->lock, flags); 1445 1446 if (host->flags & SDHCI_DEVICE_DEAD) { 1447 spin_unlock_irqrestore(&host->lock, flags); 1448 if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1449 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1450 return; 1451 } 1452 1453 /* 1454 * Reset the chip on each power off. 1455 * Should clear out any weird states. 1456 */ 1457 if (ios->power_mode == MMC_POWER_OFF) { 1458 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1459 sdhci_reinit(host); 1460 } 1461 1462 if (host->version >= SDHCI_SPEC_300 && 1463 (ios->power_mode == MMC_POWER_UP) && 1464 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1465 sdhci_enable_preset_value(host, false); 1466 1467 if (!ios->clock || ios->clock != host->clock) { 1468 host->ops->set_clock(host, ios->clock); 1469 host->clock = ios->clock; 1470 } 1471 1472 sdhci_set_power(host, ios->power_mode, ios->vdd); 1473 1474 if (host->ops->platform_send_init_74_clocks) 1475 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1476 1477 host->ops->set_bus_width(host, ios->bus_width); 1478 1479 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1480 1481 if ((ios->timing == MMC_TIMING_SD_HS || 1482 ios->timing == MMC_TIMING_MMC_HS) 1483 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1484 ctrl |= SDHCI_CTRL_HISPD; 1485 else 1486 ctrl &= ~SDHCI_CTRL_HISPD; 1487 1488 if (host->version >= SDHCI_SPEC_300) { 1489 u16 clk, ctrl_2; 1490 1491 /* In case of UHS-I modes, set High Speed Enable */ 1492 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1493 (ios->timing == MMC_TIMING_MMC_DDR52) || 1494 (ios->timing == MMC_TIMING_UHS_SDR50) || 1495 (ios->timing == MMC_TIMING_UHS_SDR104) || 1496 (ios->timing == MMC_TIMING_UHS_DDR50) || 1497 (ios->timing == MMC_TIMING_UHS_SDR25)) 1498 ctrl |= SDHCI_CTRL_HISPD; 1499 1500 if (!host->preset_enabled) { 1501 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1502 /* 1503 * We only need to set Driver Strength if the 1504 * preset value enable is not set. 1505 */ 1506 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1507 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1508 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1509 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1510 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1512 1513 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1514 } else { 1515 /* 1516 * According to SDHC Spec v3.00, if the Preset Value 1517 * Enable in the Host Control 2 register is set, we 1518 * need to reset SD Clock Enable before changing High 1519 * Speed Enable to avoid generating clock gliches. 1520 */ 1521 1522 /* Reset SD Clock Enable */ 1523 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1524 clk &= ~SDHCI_CLOCK_CARD_EN; 1525 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1526 1527 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1528 1529 /* Re-enable SD Clock */ 1530 host->ops->set_clock(host, host->clock); 1531 } 1532 1533 1534 /* Reset SD Clock Enable */ 1535 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1536 clk &= ~SDHCI_CLOCK_CARD_EN; 1537 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1538 1539 host->ops->set_uhs_signaling(host, ios->timing); 1540 host->timing = ios->timing; 1541 1542 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1543 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1544 (ios->timing == MMC_TIMING_UHS_SDR25) || 1545 (ios->timing == MMC_TIMING_UHS_SDR50) || 1546 (ios->timing == MMC_TIMING_UHS_SDR104) || 1547 (ios->timing == MMC_TIMING_UHS_DDR50))) { 1548 u16 preset; 1549 1550 sdhci_enable_preset_value(host, true); 1551 preset = sdhci_get_preset_value(host); 1552 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1553 >> SDHCI_PRESET_DRV_SHIFT; 1554 } 1555 1556 /* Re-enable SD Clock */ 1557 host->ops->set_clock(host, host->clock); 1558 } else 1559 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1560 1561 /* 1562 * Some (ENE) controllers go apeshit on some ios operation, 1563 * signalling timeout and CRC errors even on CMD0. Resetting 1564 * it on each ios seems to solve the problem. 1565 */ 1566 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1567 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1568 1569 mmiowb(); 1570 spin_unlock_irqrestore(&host->lock, flags); 1571 } 1572 1573 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1574 { 1575 struct sdhci_host *host = mmc_priv(mmc); 1576 1577 sdhci_runtime_pm_get(host); 1578 sdhci_do_set_ios(host, ios); 1579 sdhci_runtime_pm_put(host); 1580 } 1581 1582 static int sdhci_do_get_cd(struct sdhci_host *host) 1583 { 1584 int gpio_cd = mmc_gpio_get_cd(host->mmc); 1585 1586 if (host->flags & SDHCI_DEVICE_DEAD) 1587 return 0; 1588 1589 /* If polling/nonremovable, assume that the card is always present. */ 1590 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 1591 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 1592 return 1; 1593 1594 /* Try slot gpio detect */ 1595 if (!IS_ERR_VALUE(gpio_cd)) 1596 return !!gpio_cd; 1597 1598 /* Host native card detect */ 1599 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1600 } 1601 1602 static int sdhci_get_cd(struct mmc_host *mmc) 1603 { 1604 struct sdhci_host *host = mmc_priv(mmc); 1605 int ret; 1606 1607 sdhci_runtime_pm_get(host); 1608 ret = sdhci_do_get_cd(host); 1609 sdhci_runtime_pm_put(host); 1610 return ret; 1611 } 1612 1613 static int sdhci_check_ro(struct sdhci_host *host) 1614 { 1615 unsigned long flags; 1616 int is_readonly; 1617 1618 spin_lock_irqsave(&host->lock, flags); 1619 1620 if (host->flags & SDHCI_DEVICE_DEAD) 1621 is_readonly = 0; 1622 else if (host->ops->get_ro) 1623 is_readonly = host->ops->get_ro(host); 1624 else 1625 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1626 & SDHCI_WRITE_PROTECT); 1627 1628 spin_unlock_irqrestore(&host->lock, flags); 1629 1630 /* This quirk needs to be replaced by a callback-function later */ 1631 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1632 !is_readonly : is_readonly; 1633 } 1634 1635 #define SAMPLE_COUNT 5 1636 1637 static int sdhci_do_get_ro(struct sdhci_host *host) 1638 { 1639 int i, ro_count; 1640 1641 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1642 return sdhci_check_ro(host); 1643 1644 ro_count = 0; 1645 for (i = 0; i < SAMPLE_COUNT; i++) { 1646 if (sdhci_check_ro(host)) { 1647 if (++ro_count > SAMPLE_COUNT / 2) 1648 return 1; 1649 } 1650 msleep(30); 1651 } 1652 return 0; 1653 } 1654 1655 static void sdhci_hw_reset(struct mmc_host *mmc) 1656 { 1657 struct sdhci_host *host = mmc_priv(mmc); 1658 1659 if (host->ops && host->ops->hw_reset) 1660 host->ops->hw_reset(host); 1661 } 1662 1663 static int sdhci_get_ro(struct mmc_host *mmc) 1664 { 1665 struct sdhci_host *host = mmc_priv(mmc); 1666 int ret; 1667 1668 sdhci_runtime_pm_get(host); 1669 ret = sdhci_do_get_ro(host); 1670 sdhci_runtime_pm_put(host); 1671 return ret; 1672 } 1673 1674 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1675 { 1676 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1677 if (enable) 1678 host->ier |= SDHCI_INT_CARD_INT; 1679 else 1680 host->ier &= ~SDHCI_INT_CARD_INT; 1681 1682 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1683 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1684 mmiowb(); 1685 } 1686 } 1687 1688 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1689 { 1690 struct sdhci_host *host = mmc_priv(mmc); 1691 unsigned long flags; 1692 1693 sdhci_runtime_pm_get(host); 1694 1695 spin_lock_irqsave(&host->lock, flags); 1696 if (enable) 1697 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1698 else 1699 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1700 1701 sdhci_enable_sdio_irq_nolock(host, enable); 1702 spin_unlock_irqrestore(&host->lock, flags); 1703 1704 sdhci_runtime_pm_put(host); 1705 } 1706 1707 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1708 struct mmc_ios *ios) 1709 { 1710 u16 ctrl; 1711 int ret; 1712 1713 /* 1714 * Signal Voltage Switching is only applicable for Host Controllers 1715 * v3.00 and above. 1716 */ 1717 if (host->version < SDHCI_SPEC_300) 1718 return 0; 1719 1720 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1721 1722 switch (ios->signal_voltage) { 1723 case MMC_SIGNAL_VOLTAGE_330: 1724 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1725 ctrl &= ~SDHCI_CTRL_VDD_180; 1726 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1727 1728 if (host->vqmmc) { 1729 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 1730 if (ret) { 1731 pr_warning("%s: Switching to 3.3V signalling voltage " 1732 " failed\n", mmc_hostname(host->mmc)); 1733 return -EIO; 1734 } 1735 } 1736 /* Wait for 5ms */ 1737 usleep_range(5000, 5500); 1738 1739 /* 3.3V regulator output should be stable within 5 ms */ 1740 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1741 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1742 return 0; 1743 1744 pr_warning("%s: 3.3V regulator output did not became stable\n", 1745 mmc_hostname(host->mmc)); 1746 1747 return -EAGAIN; 1748 case MMC_SIGNAL_VOLTAGE_180: 1749 if (host->vqmmc) { 1750 ret = regulator_set_voltage(host->vqmmc, 1751 1700000, 1950000); 1752 if (ret) { 1753 pr_warning("%s: Switching to 1.8V signalling voltage " 1754 " failed\n", mmc_hostname(host->mmc)); 1755 return -EIO; 1756 } 1757 } 1758 1759 /* 1760 * Enable 1.8V Signal Enable in the Host Control2 1761 * register 1762 */ 1763 ctrl |= SDHCI_CTRL_VDD_180; 1764 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1765 1766 /* Wait for 5ms */ 1767 usleep_range(5000, 5500); 1768 1769 /* 1.8V regulator output should be stable within 5 ms */ 1770 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1771 if (ctrl & SDHCI_CTRL_VDD_180) 1772 return 0; 1773 1774 pr_warning("%s: 1.8V regulator output did not became stable\n", 1775 mmc_hostname(host->mmc)); 1776 1777 return -EAGAIN; 1778 case MMC_SIGNAL_VOLTAGE_120: 1779 if (host->vqmmc) { 1780 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); 1781 if (ret) { 1782 pr_warning("%s: Switching to 1.2V signalling voltage " 1783 " failed\n", mmc_hostname(host->mmc)); 1784 return -EIO; 1785 } 1786 } 1787 return 0; 1788 default: 1789 /* No signal voltage switch required */ 1790 return 0; 1791 } 1792 } 1793 1794 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1795 struct mmc_ios *ios) 1796 { 1797 struct sdhci_host *host = mmc_priv(mmc); 1798 int err; 1799 1800 if (host->version < SDHCI_SPEC_300) 1801 return 0; 1802 sdhci_runtime_pm_get(host); 1803 err = sdhci_do_start_signal_voltage_switch(host, ios); 1804 sdhci_runtime_pm_put(host); 1805 return err; 1806 } 1807 1808 static int sdhci_card_busy(struct mmc_host *mmc) 1809 { 1810 struct sdhci_host *host = mmc_priv(mmc); 1811 u32 present_state; 1812 1813 sdhci_runtime_pm_get(host); 1814 /* Check whether DAT[3:0] is 0000 */ 1815 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1816 sdhci_runtime_pm_put(host); 1817 1818 return !(present_state & SDHCI_DATA_LVL_MASK); 1819 } 1820 1821 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1822 { 1823 struct sdhci_host *host = mmc_priv(mmc); 1824 u16 ctrl; 1825 int tuning_loop_counter = MAX_TUNING_LOOP; 1826 int err = 0; 1827 unsigned long flags; 1828 1829 sdhci_runtime_pm_get(host); 1830 spin_lock_irqsave(&host->lock, flags); 1831 1832 /* 1833 * The Host Controller needs tuning only in case of SDR104 mode 1834 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1835 * Capabilities register. 1836 * If the Host Controller supports the HS200 mode then the 1837 * tuning function has to be executed. 1838 */ 1839 switch (host->timing) { 1840 case MMC_TIMING_MMC_HS200: 1841 case MMC_TIMING_UHS_SDR104: 1842 break; 1843 1844 case MMC_TIMING_UHS_SDR50: 1845 if (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1846 host->flags & SDHCI_SDR104_NEEDS_TUNING) 1847 break; 1848 /* FALLTHROUGH */ 1849 1850 default: 1851 spin_unlock_irqrestore(&host->lock, flags); 1852 sdhci_runtime_pm_put(host); 1853 return 0; 1854 } 1855 1856 if (host->ops->platform_execute_tuning) { 1857 spin_unlock_irqrestore(&host->lock, flags); 1858 err = host->ops->platform_execute_tuning(host, opcode); 1859 sdhci_runtime_pm_put(host); 1860 return err; 1861 } 1862 1863 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1864 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1865 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1866 1867 /* 1868 * As per the Host Controller spec v3.00, tuning command 1869 * generates Buffer Read Ready interrupt, so enable that. 1870 * 1871 * Note: The spec clearly says that when tuning sequence 1872 * is being performed, the controller does not generate 1873 * interrupts other than Buffer Read Ready interrupt. But 1874 * to make sure we don't hit a controller bug, we _only_ 1875 * enable Buffer Read Ready interrupt here. 1876 */ 1877 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1878 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1879 1880 /* 1881 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1882 * of loops reaches 40 times or a timeout of 150ms occurs. 1883 */ 1884 do { 1885 struct mmc_command cmd = {0}; 1886 struct mmc_request mrq = {NULL}; 1887 1888 cmd.opcode = opcode; 1889 cmd.arg = 0; 1890 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1891 cmd.retries = 0; 1892 cmd.data = NULL; 1893 cmd.error = 0; 1894 1895 if (tuning_loop_counter-- == 0) 1896 break; 1897 1898 mrq.cmd = &cmd; 1899 host->mrq = &mrq; 1900 1901 /* 1902 * In response to CMD19, the card sends 64 bytes of tuning 1903 * block to the Host Controller. So we set the block size 1904 * to 64 here. 1905 */ 1906 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1907 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1908 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1909 SDHCI_BLOCK_SIZE); 1910 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1911 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1912 SDHCI_BLOCK_SIZE); 1913 } else { 1914 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1915 SDHCI_BLOCK_SIZE); 1916 } 1917 1918 /* 1919 * The tuning block is sent by the card to the host controller. 1920 * So we set the TRNS_READ bit in the Transfer Mode register. 1921 * This also takes care of setting DMA Enable and Multi Block 1922 * Select in the same register to 0. 1923 */ 1924 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1925 1926 sdhci_send_command(host, &cmd); 1927 1928 host->cmd = NULL; 1929 host->mrq = NULL; 1930 1931 spin_unlock_irqrestore(&host->lock, flags); 1932 /* Wait for Buffer Read Ready interrupt */ 1933 wait_event_interruptible_timeout(host->buf_ready_int, 1934 (host->tuning_done == 1), 1935 msecs_to_jiffies(50)); 1936 spin_lock_irqsave(&host->lock, flags); 1937 1938 if (!host->tuning_done) { 1939 pr_info(DRIVER_NAME ": Timeout waiting for " 1940 "Buffer Read Ready interrupt during tuning " 1941 "procedure, falling back to fixed sampling " 1942 "clock\n"); 1943 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1944 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1945 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1946 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1947 1948 err = -EIO; 1949 goto out; 1950 } 1951 1952 host->tuning_done = 0; 1953 1954 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1955 1956 /* eMMC spec does not require a delay between tuning cycles */ 1957 if (opcode == MMC_SEND_TUNING_BLOCK) 1958 mdelay(1); 1959 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1960 1961 /* 1962 * The Host Driver has exhausted the maximum number of loops allowed, 1963 * so use fixed sampling frequency. 1964 */ 1965 if (tuning_loop_counter < 0) { 1966 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1967 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1968 } 1969 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1970 pr_info(DRIVER_NAME ": Tuning procedure" 1971 " failed, falling back to fixed sampling" 1972 " clock\n"); 1973 err = -EIO; 1974 } 1975 1976 out: 1977 /* 1978 * If this is the very first time we are here, we start the retuning 1979 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1980 * flag won't be set, we check this condition before actually starting 1981 * the timer. 1982 */ 1983 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1984 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1985 host->flags |= SDHCI_USING_RETUNING_TIMER; 1986 mod_timer(&host->tuning_timer, jiffies + 1987 host->tuning_count * HZ); 1988 /* Tuning mode 1 limits the maximum data length to 4MB */ 1989 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1990 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { 1991 host->flags &= ~SDHCI_NEEDS_RETUNING; 1992 /* Reload the new initial value for timer */ 1993 mod_timer(&host->tuning_timer, jiffies + 1994 host->tuning_count * HZ); 1995 } 1996 1997 /* 1998 * In case tuning fails, host controllers which support re-tuning can 1999 * try tuning again at a later time, when the re-tuning timer expires. 2000 * So for these controllers, we return 0. Since there might be other 2001 * controllers who do not have this capability, we return error for 2002 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2003 * a retuning timer to do the retuning for the card. 2004 */ 2005 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2006 err = 0; 2007 2008 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2009 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2010 spin_unlock_irqrestore(&host->lock, flags); 2011 sdhci_runtime_pm_put(host); 2012 2013 return err; 2014 } 2015 2016 2017 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2018 { 2019 /* Host Controller v3.00 defines preset value registers */ 2020 if (host->version < SDHCI_SPEC_300) 2021 return; 2022 2023 /* 2024 * We only enable or disable Preset Value if they are not already 2025 * enabled or disabled respectively. Otherwise, we bail out. 2026 */ 2027 if (host->preset_enabled != enable) { 2028 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2029 2030 if (enable) 2031 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2032 else 2033 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2034 2035 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2036 2037 if (enable) 2038 host->flags |= SDHCI_PV_ENABLED; 2039 else 2040 host->flags &= ~SDHCI_PV_ENABLED; 2041 2042 host->preset_enabled = enable; 2043 } 2044 } 2045 2046 static void sdhci_card_event(struct mmc_host *mmc) 2047 { 2048 struct sdhci_host *host = mmc_priv(mmc); 2049 unsigned long flags; 2050 2051 /* First check if client has provided their own card event */ 2052 if (host->ops->card_event) 2053 host->ops->card_event(host); 2054 2055 spin_lock_irqsave(&host->lock, flags); 2056 2057 /* Check host->mrq first in case we are runtime suspended */ 2058 if (host->mrq && !sdhci_do_get_cd(host)) { 2059 pr_err("%s: Card removed during transfer!\n", 2060 mmc_hostname(host->mmc)); 2061 pr_err("%s: Resetting controller.\n", 2062 mmc_hostname(host->mmc)); 2063 2064 sdhci_do_reset(host, SDHCI_RESET_CMD); 2065 sdhci_do_reset(host, SDHCI_RESET_DATA); 2066 2067 host->mrq->cmd->error = -ENOMEDIUM; 2068 tasklet_schedule(&host->finish_tasklet); 2069 } 2070 2071 spin_unlock_irqrestore(&host->lock, flags); 2072 } 2073 2074 static const struct mmc_host_ops sdhci_ops = { 2075 .request = sdhci_request, 2076 .set_ios = sdhci_set_ios, 2077 .get_cd = sdhci_get_cd, 2078 .get_ro = sdhci_get_ro, 2079 .hw_reset = sdhci_hw_reset, 2080 .enable_sdio_irq = sdhci_enable_sdio_irq, 2081 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2082 .execute_tuning = sdhci_execute_tuning, 2083 .card_event = sdhci_card_event, 2084 .card_busy = sdhci_card_busy, 2085 }; 2086 2087 /*****************************************************************************\ 2088 * * 2089 * Tasklets * 2090 * * 2091 \*****************************************************************************/ 2092 2093 static void sdhci_tasklet_finish(unsigned long param) 2094 { 2095 struct sdhci_host *host; 2096 unsigned long flags; 2097 struct mmc_request *mrq; 2098 2099 host = (struct sdhci_host*)param; 2100 2101 spin_lock_irqsave(&host->lock, flags); 2102 2103 /* 2104 * If this tasklet gets rescheduled while running, it will 2105 * be run again afterwards but without any active request. 2106 */ 2107 if (!host->mrq) { 2108 spin_unlock_irqrestore(&host->lock, flags); 2109 return; 2110 } 2111 2112 del_timer(&host->timer); 2113 2114 mrq = host->mrq; 2115 2116 /* 2117 * The controller needs a reset of internal state machines 2118 * upon error conditions. 2119 */ 2120 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2121 ((mrq->cmd && mrq->cmd->error) || 2122 (mrq->data && (mrq->data->error || 2123 (mrq->data->stop && mrq->data->stop->error))) || 2124 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2125 2126 /* Some controllers need this kick or reset won't work here */ 2127 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2128 /* This is to force an update */ 2129 host->ops->set_clock(host, host->clock); 2130 2131 /* Spec says we should do both at the same time, but Ricoh 2132 controllers do not like that. */ 2133 sdhci_do_reset(host, SDHCI_RESET_CMD); 2134 sdhci_do_reset(host, SDHCI_RESET_DATA); 2135 } 2136 2137 host->mrq = NULL; 2138 host->cmd = NULL; 2139 host->data = NULL; 2140 2141 #ifndef SDHCI_USE_LEDS_CLASS 2142 sdhci_deactivate_led(host); 2143 #endif 2144 2145 mmiowb(); 2146 spin_unlock_irqrestore(&host->lock, flags); 2147 2148 mmc_request_done(host->mmc, mrq); 2149 sdhci_runtime_pm_put(host); 2150 } 2151 2152 static void sdhci_timeout_timer(unsigned long data) 2153 { 2154 struct sdhci_host *host; 2155 unsigned long flags; 2156 2157 host = (struct sdhci_host*)data; 2158 2159 spin_lock_irqsave(&host->lock, flags); 2160 2161 if (host->mrq) { 2162 pr_err("%s: Timeout waiting for hardware " 2163 "interrupt.\n", mmc_hostname(host->mmc)); 2164 sdhci_dumpregs(host); 2165 2166 if (host->data) { 2167 host->data->error = -ETIMEDOUT; 2168 sdhci_finish_data(host); 2169 } else { 2170 if (host->cmd) 2171 host->cmd->error = -ETIMEDOUT; 2172 else 2173 host->mrq->cmd->error = -ETIMEDOUT; 2174 2175 tasklet_schedule(&host->finish_tasklet); 2176 } 2177 } 2178 2179 mmiowb(); 2180 spin_unlock_irqrestore(&host->lock, flags); 2181 } 2182 2183 static void sdhci_tuning_timer(unsigned long data) 2184 { 2185 struct sdhci_host *host; 2186 unsigned long flags; 2187 2188 host = (struct sdhci_host *)data; 2189 2190 spin_lock_irqsave(&host->lock, flags); 2191 2192 host->flags |= SDHCI_NEEDS_RETUNING; 2193 2194 spin_unlock_irqrestore(&host->lock, flags); 2195 } 2196 2197 /*****************************************************************************\ 2198 * * 2199 * Interrupt handling * 2200 * * 2201 \*****************************************************************************/ 2202 2203 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2204 { 2205 BUG_ON(intmask == 0); 2206 2207 if (!host->cmd) { 2208 pr_err("%s: Got command interrupt 0x%08x even " 2209 "though no command operation was in progress.\n", 2210 mmc_hostname(host->mmc), (unsigned)intmask); 2211 sdhci_dumpregs(host); 2212 return; 2213 } 2214 2215 if (intmask & SDHCI_INT_TIMEOUT) 2216 host->cmd->error = -ETIMEDOUT; 2217 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2218 SDHCI_INT_INDEX)) 2219 host->cmd->error = -EILSEQ; 2220 2221 if (host->cmd->error) { 2222 tasklet_schedule(&host->finish_tasklet); 2223 return; 2224 } 2225 2226 /* 2227 * The host can send and interrupt when the busy state has 2228 * ended, allowing us to wait without wasting CPU cycles. 2229 * Unfortunately this is overloaded on the "data complete" 2230 * interrupt, so we need to take some care when handling 2231 * it. 2232 * 2233 * Note: The 1.0 specification is a bit ambiguous about this 2234 * feature so there might be some problems with older 2235 * controllers. 2236 */ 2237 if (host->cmd->flags & MMC_RSP_BUSY) { 2238 if (host->cmd->data) 2239 DBG("Cannot wait for busy signal when also " 2240 "doing a data transfer"); 2241 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2242 return; 2243 2244 /* The controller does not support the end-of-busy IRQ, 2245 * fall through and take the SDHCI_INT_RESPONSE */ 2246 } 2247 2248 if (intmask & SDHCI_INT_RESPONSE) 2249 sdhci_finish_command(host); 2250 } 2251 2252 #ifdef CONFIG_MMC_DEBUG 2253 static void sdhci_show_adma_error(struct sdhci_host *host) 2254 { 2255 const char *name = mmc_hostname(host->mmc); 2256 u8 *desc = host->adma_desc; 2257 __le32 *dma; 2258 __le16 *len; 2259 u8 attr; 2260 2261 sdhci_dumpregs(host); 2262 2263 while (true) { 2264 dma = (__le32 *)(desc + 4); 2265 len = (__le16 *)(desc + 2); 2266 attr = *desc; 2267 2268 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2269 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2270 2271 desc += 8; 2272 2273 if (attr & 2) 2274 break; 2275 } 2276 } 2277 #else 2278 static void sdhci_show_adma_error(struct sdhci_host *host) { } 2279 #endif 2280 2281 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2282 { 2283 u32 command; 2284 BUG_ON(intmask == 0); 2285 2286 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2287 if (intmask & SDHCI_INT_DATA_AVAIL) { 2288 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2289 if (command == MMC_SEND_TUNING_BLOCK || 2290 command == MMC_SEND_TUNING_BLOCK_HS200) { 2291 host->tuning_done = 1; 2292 wake_up(&host->buf_ready_int); 2293 return; 2294 } 2295 } 2296 2297 if (!host->data) { 2298 /* 2299 * The "data complete" interrupt is also used to 2300 * indicate that a busy state has ended. See comment 2301 * above in sdhci_cmd_irq(). 2302 */ 2303 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2304 if (intmask & SDHCI_INT_DATA_END) { 2305 sdhci_finish_command(host); 2306 return; 2307 } 2308 } 2309 2310 pr_err("%s: Got data interrupt 0x%08x even " 2311 "though no data operation was in progress.\n", 2312 mmc_hostname(host->mmc), (unsigned)intmask); 2313 sdhci_dumpregs(host); 2314 2315 return; 2316 } 2317 2318 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2319 host->data->error = -ETIMEDOUT; 2320 else if (intmask & SDHCI_INT_DATA_END_BIT) 2321 host->data->error = -EILSEQ; 2322 else if ((intmask & SDHCI_INT_DATA_CRC) && 2323 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2324 != MMC_BUS_TEST_R) 2325 host->data->error = -EILSEQ; 2326 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2327 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2328 sdhci_show_adma_error(host); 2329 host->data->error = -EIO; 2330 if (host->ops->adma_workaround) 2331 host->ops->adma_workaround(host, intmask); 2332 } 2333 2334 if (host->data->error) 2335 sdhci_finish_data(host); 2336 else { 2337 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2338 sdhci_transfer_pio(host); 2339 2340 /* 2341 * We currently don't do anything fancy with DMA 2342 * boundaries, but as we can't disable the feature 2343 * we need to at least restart the transfer. 2344 * 2345 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2346 * should return a valid address to continue from, but as 2347 * some controllers are faulty, don't trust them. 2348 */ 2349 if (intmask & SDHCI_INT_DMA_END) { 2350 u32 dmastart, dmanow; 2351 dmastart = sg_dma_address(host->data->sg); 2352 dmanow = dmastart + host->data->bytes_xfered; 2353 /* 2354 * Force update to the next DMA block boundary. 2355 */ 2356 dmanow = (dmanow & 2357 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2358 SDHCI_DEFAULT_BOUNDARY_SIZE; 2359 host->data->bytes_xfered = dmanow - dmastart; 2360 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2361 " next 0x%08x\n", 2362 mmc_hostname(host->mmc), dmastart, 2363 host->data->bytes_xfered, dmanow); 2364 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2365 } 2366 2367 if (intmask & SDHCI_INT_DATA_END) { 2368 if (host->cmd) { 2369 /* 2370 * Data managed to finish before the 2371 * command completed. Make sure we do 2372 * things in the proper order. 2373 */ 2374 host->data_early = 1; 2375 } else { 2376 sdhci_finish_data(host); 2377 } 2378 } 2379 } 2380 } 2381 2382 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2383 { 2384 irqreturn_t result = IRQ_NONE; 2385 struct sdhci_host *host = dev_id; 2386 u32 intmask, mask, unexpected = 0; 2387 int max_loops = 16; 2388 2389 spin_lock(&host->lock); 2390 2391 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2392 spin_unlock(&host->lock); 2393 return IRQ_NONE; 2394 } 2395 2396 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2397 if (!intmask || intmask == 0xffffffff) { 2398 result = IRQ_NONE; 2399 goto out; 2400 } 2401 2402 do { 2403 /* Clear selected interrupts. */ 2404 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2405 SDHCI_INT_BUS_POWER); 2406 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2407 2408 DBG("*** %s got interrupt: 0x%08x\n", 2409 mmc_hostname(host->mmc), intmask); 2410 2411 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2412 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2413 SDHCI_CARD_PRESENT; 2414 2415 /* 2416 * There is a observation on i.mx esdhc. INSERT 2417 * bit will be immediately set again when it gets 2418 * cleared, if a card is inserted. We have to mask 2419 * the irq to prevent interrupt storm which will 2420 * freeze the system. And the REMOVE gets the 2421 * same situation. 2422 * 2423 * More testing are needed here to ensure it works 2424 * for other platforms though. 2425 */ 2426 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2427 SDHCI_INT_CARD_REMOVE); 2428 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2429 SDHCI_INT_CARD_INSERT; 2430 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2431 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2432 2433 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2434 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2435 2436 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2437 SDHCI_INT_CARD_REMOVE); 2438 result = IRQ_WAKE_THREAD; 2439 } 2440 2441 if (intmask & SDHCI_INT_CMD_MASK) 2442 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2443 2444 if (intmask & SDHCI_INT_DATA_MASK) 2445 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2446 2447 if (intmask & SDHCI_INT_BUS_POWER) 2448 pr_err("%s: Card is consuming too much power!\n", 2449 mmc_hostname(host->mmc)); 2450 2451 if (intmask & SDHCI_INT_CARD_INT) { 2452 sdhci_enable_sdio_irq_nolock(host, false); 2453 host->thread_isr |= SDHCI_INT_CARD_INT; 2454 result = IRQ_WAKE_THREAD; 2455 } 2456 2457 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2458 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2459 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2460 SDHCI_INT_CARD_INT); 2461 2462 if (intmask) { 2463 unexpected |= intmask; 2464 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2465 } 2466 2467 if (result == IRQ_NONE) 2468 result = IRQ_HANDLED; 2469 2470 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2471 } while (intmask && --max_loops); 2472 out: 2473 spin_unlock(&host->lock); 2474 2475 if (unexpected) { 2476 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2477 mmc_hostname(host->mmc), unexpected); 2478 sdhci_dumpregs(host); 2479 } 2480 2481 return result; 2482 } 2483 2484 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2485 { 2486 struct sdhci_host *host = dev_id; 2487 unsigned long flags; 2488 u32 isr; 2489 2490 spin_lock_irqsave(&host->lock, flags); 2491 isr = host->thread_isr; 2492 host->thread_isr = 0; 2493 spin_unlock_irqrestore(&host->lock, flags); 2494 2495 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2496 sdhci_card_event(host->mmc); 2497 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2498 } 2499 2500 if (isr & SDHCI_INT_CARD_INT) { 2501 sdio_run_irqs(host->mmc); 2502 2503 spin_lock_irqsave(&host->lock, flags); 2504 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2505 sdhci_enable_sdio_irq_nolock(host, true); 2506 spin_unlock_irqrestore(&host->lock, flags); 2507 } 2508 2509 return isr ? IRQ_HANDLED : IRQ_NONE; 2510 } 2511 2512 /*****************************************************************************\ 2513 * * 2514 * Suspend/resume * 2515 * * 2516 \*****************************************************************************/ 2517 2518 #ifdef CONFIG_PM 2519 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2520 { 2521 u8 val; 2522 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2523 | SDHCI_WAKE_ON_INT; 2524 2525 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2526 val |= mask ; 2527 /* Avoid fake wake up */ 2528 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2529 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2530 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2531 } 2532 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2533 2534 void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2535 { 2536 u8 val; 2537 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2538 | SDHCI_WAKE_ON_INT; 2539 2540 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2541 val &= ~mask; 2542 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2543 } 2544 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); 2545 2546 int sdhci_suspend_host(struct sdhci_host *host) 2547 { 2548 sdhci_disable_card_detection(host); 2549 2550 /* Disable tuning since we are suspending */ 2551 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2552 del_timer_sync(&host->tuning_timer); 2553 host->flags &= ~SDHCI_NEEDS_RETUNING; 2554 } 2555 2556 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2557 host->ier = 0; 2558 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2559 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2560 free_irq(host->irq, host); 2561 } else { 2562 sdhci_enable_irq_wakeups(host); 2563 enable_irq_wake(host->irq); 2564 } 2565 return 0; 2566 } 2567 2568 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2569 2570 int sdhci_resume_host(struct sdhci_host *host) 2571 { 2572 int ret = 0; 2573 2574 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2575 if (host->ops->enable_dma) 2576 host->ops->enable_dma(host); 2577 } 2578 2579 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2580 ret = request_threaded_irq(host->irq, sdhci_irq, 2581 sdhci_thread_irq, IRQF_SHARED, 2582 mmc_hostname(host->mmc), host); 2583 if (ret) 2584 return ret; 2585 } else { 2586 sdhci_disable_irq_wakeups(host); 2587 disable_irq_wake(host->irq); 2588 } 2589 2590 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2591 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2592 /* Card keeps power but host controller does not */ 2593 sdhci_init(host, 0); 2594 host->pwr = 0; 2595 host->clock = 0; 2596 sdhci_do_set_ios(host, &host->mmc->ios); 2597 } else { 2598 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2599 mmiowb(); 2600 } 2601 2602 sdhci_enable_card_detection(host); 2603 2604 /* Set the re-tuning expiration flag */ 2605 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2606 host->flags |= SDHCI_NEEDS_RETUNING; 2607 2608 return ret; 2609 } 2610 2611 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2612 #endif /* CONFIG_PM */ 2613 2614 #ifdef CONFIG_PM_RUNTIME 2615 2616 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2617 { 2618 return pm_runtime_get_sync(host->mmc->parent); 2619 } 2620 2621 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2622 { 2623 pm_runtime_mark_last_busy(host->mmc->parent); 2624 return pm_runtime_put_autosuspend(host->mmc->parent); 2625 } 2626 2627 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2628 { 2629 if (host->runtime_suspended || host->bus_on) 2630 return; 2631 host->bus_on = true; 2632 pm_runtime_get_noresume(host->mmc->parent); 2633 } 2634 2635 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2636 { 2637 if (host->runtime_suspended || !host->bus_on) 2638 return; 2639 host->bus_on = false; 2640 pm_runtime_put_noidle(host->mmc->parent); 2641 } 2642 2643 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2644 { 2645 unsigned long flags; 2646 int ret = 0; 2647 2648 /* Disable tuning since we are suspending */ 2649 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2650 del_timer_sync(&host->tuning_timer); 2651 host->flags &= ~SDHCI_NEEDS_RETUNING; 2652 } 2653 2654 spin_lock_irqsave(&host->lock, flags); 2655 host->ier &= SDHCI_INT_CARD_INT; 2656 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2657 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2658 spin_unlock_irqrestore(&host->lock, flags); 2659 2660 synchronize_hardirq(host->irq); 2661 2662 spin_lock_irqsave(&host->lock, flags); 2663 host->runtime_suspended = true; 2664 spin_unlock_irqrestore(&host->lock, flags); 2665 2666 return ret; 2667 } 2668 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2669 2670 int sdhci_runtime_resume_host(struct sdhci_host *host) 2671 { 2672 unsigned long flags; 2673 int ret = 0, host_flags = host->flags; 2674 2675 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2676 if (host->ops->enable_dma) 2677 host->ops->enable_dma(host); 2678 } 2679 2680 sdhci_init(host, 0); 2681 2682 /* Force clock and power re-program */ 2683 host->pwr = 0; 2684 host->clock = 0; 2685 sdhci_do_set_ios(host, &host->mmc->ios); 2686 2687 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2688 if ((host_flags & SDHCI_PV_ENABLED) && 2689 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2690 spin_lock_irqsave(&host->lock, flags); 2691 sdhci_enable_preset_value(host, true); 2692 spin_unlock_irqrestore(&host->lock, flags); 2693 } 2694 2695 /* Set the re-tuning expiration flag */ 2696 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2697 host->flags |= SDHCI_NEEDS_RETUNING; 2698 2699 spin_lock_irqsave(&host->lock, flags); 2700 2701 host->runtime_suspended = false; 2702 2703 /* Enable SDIO IRQ */ 2704 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2705 sdhci_enable_sdio_irq_nolock(host, true); 2706 2707 /* Enable Card Detection */ 2708 sdhci_enable_card_detection(host); 2709 2710 spin_unlock_irqrestore(&host->lock, flags); 2711 2712 return ret; 2713 } 2714 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2715 2716 #endif 2717 2718 /*****************************************************************************\ 2719 * * 2720 * Device allocation/registration * 2721 * * 2722 \*****************************************************************************/ 2723 2724 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2725 size_t priv_size) 2726 { 2727 struct mmc_host *mmc; 2728 struct sdhci_host *host; 2729 2730 WARN_ON(dev == NULL); 2731 2732 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2733 if (!mmc) 2734 return ERR_PTR(-ENOMEM); 2735 2736 host = mmc_priv(mmc); 2737 host->mmc = mmc; 2738 2739 return host; 2740 } 2741 2742 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2743 2744 int sdhci_add_host(struct sdhci_host *host) 2745 { 2746 struct mmc_host *mmc; 2747 u32 caps[2] = {0, 0}; 2748 u32 max_current_caps; 2749 unsigned int ocr_avail; 2750 int ret; 2751 2752 WARN_ON(host == NULL); 2753 if (host == NULL) 2754 return -EINVAL; 2755 2756 mmc = host->mmc; 2757 2758 if (debug_quirks) 2759 host->quirks = debug_quirks; 2760 if (debug_quirks2) 2761 host->quirks2 = debug_quirks2; 2762 2763 sdhci_do_reset(host, SDHCI_RESET_ALL); 2764 2765 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2766 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2767 >> SDHCI_SPEC_VER_SHIFT; 2768 if (host->version > SDHCI_SPEC_300) { 2769 pr_err("%s: Unknown controller version (%d). " 2770 "You may experience problems.\n", mmc_hostname(mmc), 2771 host->version); 2772 } 2773 2774 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2775 sdhci_readl(host, SDHCI_CAPABILITIES); 2776 2777 if (host->version >= SDHCI_SPEC_300) 2778 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2779 host->caps1 : 2780 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2781 2782 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2783 host->flags |= SDHCI_USE_SDMA; 2784 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2785 DBG("Controller doesn't have SDMA capability\n"); 2786 else 2787 host->flags |= SDHCI_USE_SDMA; 2788 2789 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2790 (host->flags & SDHCI_USE_SDMA)) { 2791 DBG("Disabling DMA as it is marked broken\n"); 2792 host->flags &= ~SDHCI_USE_SDMA; 2793 } 2794 2795 if ((host->version >= SDHCI_SPEC_200) && 2796 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2797 host->flags |= SDHCI_USE_ADMA; 2798 2799 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2800 (host->flags & SDHCI_USE_ADMA)) { 2801 DBG("Disabling ADMA as it is marked broken\n"); 2802 host->flags &= ~SDHCI_USE_ADMA; 2803 } 2804 2805 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2806 if (host->ops->enable_dma) { 2807 if (host->ops->enable_dma(host)) { 2808 pr_warning("%s: No suitable DMA " 2809 "available. Falling back to PIO.\n", 2810 mmc_hostname(mmc)); 2811 host->flags &= 2812 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2813 } 2814 } 2815 } 2816 2817 if (host->flags & SDHCI_USE_ADMA) { 2818 /* 2819 * We need to allocate descriptors for all sg entries 2820 * (128) and potentially one alignment transfer for 2821 * each of those entries. 2822 */ 2823 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc), 2824 ADMA_SIZE, &host->adma_addr, 2825 GFP_KERNEL); 2826 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2827 if (!host->adma_desc || !host->align_buffer) { 2828 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, 2829 host->adma_desc, host->adma_addr); 2830 kfree(host->align_buffer); 2831 pr_warning("%s: Unable to allocate ADMA " 2832 "buffers. Falling back to standard DMA.\n", 2833 mmc_hostname(mmc)); 2834 host->flags &= ~SDHCI_USE_ADMA; 2835 host->adma_desc = NULL; 2836 host->align_buffer = NULL; 2837 } else if (host->adma_addr & 3) { 2838 pr_warning("%s: unable to allocate aligned ADMA descriptor\n", 2839 mmc_hostname(mmc)); 2840 host->flags &= ~SDHCI_USE_ADMA; 2841 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, 2842 host->adma_desc, host->adma_addr); 2843 kfree(host->align_buffer); 2844 host->adma_desc = NULL; 2845 host->align_buffer = NULL; 2846 } 2847 } 2848 2849 /* 2850 * If we use DMA, then it's up to the caller to set the DMA 2851 * mask, but PIO does not need the hw shim so we set a new 2852 * mask here in that case. 2853 */ 2854 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2855 host->dma_mask = DMA_BIT_MASK(64); 2856 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2857 } 2858 2859 if (host->version >= SDHCI_SPEC_300) 2860 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2861 >> SDHCI_CLOCK_BASE_SHIFT; 2862 else 2863 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2864 >> SDHCI_CLOCK_BASE_SHIFT; 2865 2866 host->max_clk *= 1000000; 2867 if (host->max_clk == 0 || host->quirks & 2868 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2869 if (!host->ops->get_max_clock) { 2870 pr_err("%s: Hardware doesn't specify base clock " 2871 "frequency.\n", mmc_hostname(mmc)); 2872 return -ENODEV; 2873 } 2874 host->max_clk = host->ops->get_max_clock(host); 2875 } 2876 2877 /* 2878 * In case of Host Controller v3.00, find out whether clock 2879 * multiplier is supported. 2880 */ 2881 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2882 SDHCI_CLOCK_MUL_SHIFT; 2883 2884 /* 2885 * In case the value in Clock Multiplier is 0, then programmable 2886 * clock mode is not supported, otherwise the actual clock 2887 * multiplier is one more than the value of Clock Multiplier 2888 * in the Capabilities Register. 2889 */ 2890 if (host->clk_mul) 2891 host->clk_mul += 1; 2892 2893 /* 2894 * Set host parameters. 2895 */ 2896 mmc->ops = &sdhci_ops; 2897 mmc->f_max = host->max_clk; 2898 if (host->ops->get_min_clock) 2899 mmc->f_min = host->ops->get_min_clock(host); 2900 else if (host->version >= SDHCI_SPEC_300) { 2901 if (host->clk_mul) { 2902 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2903 mmc->f_max = host->max_clk * host->clk_mul; 2904 } else 2905 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2906 } else 2907 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2908 2909 host->timeout_clk = 2910 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2911 if (host->timeout_clk == 0) { 2912 if (host->ops->get_timeout_clock) { 2913 host->timeout_clk = host->ops->get_timeout_clock(host); 2914 } else if (!(host->quirks & 2915 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2916 pr_err("%s: Hardware doesn't specify timeout clock " 2917 "frequency.\n", mmc_hostname(mmc)); 2918 return -ENODEV; 2919 } 2920 } 2921 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2922 host->timeout_clk *= 1000; 2923 2924 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 2925 host->timeout_clk = mmc->f_max / 1000; 2926 2927 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; 2928 2929 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2930 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2931 2932 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2933 host->flags |= SDHCI_AUTO_CMD12; 2934 2935 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2936 if ((host->version >= SDHCI_SPEC_300) && 2937 ((host->flags & SDHCI_USE_ADMA) || 2938 !(host->flags & SDHCI_USE_SDMA))) { 2939 host->flags |= SDHCI_AUTO_CMD23; 2940 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2941 } else { 2942 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2943 } 2944 2945 /* 2946 * A controller may support 8-bit width, but the board itself 2947 * might not have the pins brought out. Boards that support 2948 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2949 * their platform code before calling sdhci_add_host(), and we 2950 * won't assume 8-bit width for hosts without that CAP. 2951 */ 2952 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2953 mmc->caps |= MMC_CAP_4_BIT_DATA; 2954 2955 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 2956 mmc->caps &= ~MMC_CAP_CMD23; 2957 2958 if (caps[0] & SDHCI_CAN_DO_HISPD) 2959 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2960 2961 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2962 !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 2963 mmc->caps |= MMC_CAP_NEEDS_POLL; 2964 2965 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 2966 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc"); 2967 if (IS_ERR_OR_NULL(host->vqmmc)) { 2968 if (PTR_ERR(host->vqmmc) < 0) { 2969 pr_info("%s: no vqmmc regulator found\n", 2970 mmc_hostname(mmc)); 2971 host->vqmmc = NULL; 2972 } 2973 } else { 2974 ret = regulator_enable(host->vqmmc); 2975 if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2976 1950000)) 2977 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 2978 SDHCI_SUPPORT_SDR50 | 2979 SDHCI_SUPPORT_DDR50); 2980 if (ret) { 2981 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 2982 mmc_hostname(mmc), ret); 2983 host->vqmmc = NULL; 2984 } 2985 } 2986 2987 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 2988 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2989 SDHCI_SUPPORT_DDR50); 2990 2991 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 2992 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2993 SDHCI_SUPPORT_DDR50)) 2994 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 2995 2996 /* SDR104 supports also implies SDR50 support */ 2997 if (caps[1] & SDHCI_SUPPORT_SDR104) { 2998 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 2999 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3000 * field can be promoted to support HS200. 3001 */ 3002 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3003 mmc->caps2 |= MMC_CAP2_HS200; 3004 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3005 mmc->caps |= MMC_CAP_UHS_SDR50; 3006 3007 if ((caps[1] & SDHCI_SUPPORT_DDR50) && 3008 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3009 mmc->caps |= MMC_CAP_UHS_DDR50; 3010 3011 /* Does the host need tuning for SDR50? */ 3012 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3013 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3014 3015 /* Does the host need tuning for SDR104 / HS200? */ 3016 if (mmc->caps2 & MMC_CAP2_HS200) 3017 host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3018 3019 /* Driver Type(s) (A, C, D) supported by the host */ 3020 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3021 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3022 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3023 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3024 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3025 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3026 3027 /* Initial value for re-tuning timer count */ 3028 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3029 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3030 3031 /* 3032 * In case Re-tuning Timer is not disabled, the actual value of 3033 * re-tuning timer will be 2 ^ (n - 1). 3034 */ 3035 if (host->tuning_count) 3036 host->tuning_count = 1 << (host->tuning_count - 1); 3037 3038 /* Re-tuning mode supported by the Host Controller */ 3039 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3040 SDHCI_RETUNING_MODE_SHIFT; 3041 3042 ocr_avail = 0; 3043 3044 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc"); 3045 if (IS_ERR_OR_NULL(host->vmmc)) { 3046 if (PTR_ERR(host->vmmc) < 0) { 3047 pr_info("%s: no vmmc regulator found\n", 3048 mmc_hostname(mmc)); 3049 host->vmmc = NULL; 3050 } 3051 } 3052 3053 #ifdef CONFIG_REGULATOR 3054 /* 3055 * Voltage range check makes sense only if regulator reports 3056 * any voltage value. 3057 */ 3058 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { 3059 ret = regulator_is_supported_voltage(host->vmmc, 2700000, 3060 3600000); 3061 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 3062 caps[0] &= ~SDHCI_CAN_VDD_330; 3063 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 3064 caps[0] &= ~SDHCI_CAN_VDD_300; 3065 ret = regulator_is_supported_voltage(host->vmmc, 1700000, 3066 1950000); 3067 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 3068 caps[0] &= ~SDHCI_CAN_VDD_180; 3069 } 3070 #endif /* CONFIG_REGULATOR */ 3071 3072 /* 3073 * According to SD Host Controller spec v3.00, if the Host System 3074 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3075 * the value is meaningful only if Voltage Support in the Capabilities 3076 * register is set. The actual current value is 4 times the register 3077 * value. 3078 */ 3079 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3080 if (!max_current_caps && host->vmmc) { 3081 u32 curr = regulator_get_current_limit(host->vmmc); 3082 if (curr > 0) { 3083 3084 /* convert to SDHCI_MAX_CURRENT format */ 3085 curr = curr/1000; /* convert to mA */ 3086 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3087 3088 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3089 max_current_caps = 3090 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3091 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3092 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3093 } 3094 } 3095 3096 if (caps[0] & SDHCI_CAN_VDD_330) { 3097 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3098 3099 mmc->max_current_330 = ((max_current_caps & 3100 SDHCI_MAX_CURRENT_330_MASK) >> 3101 SDHCI_MAX_CURRENT_330_SHIFT) * 3102 SDHCI_MAX_CURRENT_MULTIPLIER; 3103 } 3104 if (caps[0] & SDHCI_CAN_VDD_300) { 3105 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3106 3107 mmc->max_current_300 = ((max_current_caps & 3108 SDHCI_MAX_CURRENT_300_MASK) >> 3109 SDHCI_MAX_CURRENT_300_SHIFT) * 3110 SDHCI_MAX_CURRENT_MULTIPLIER; 3111 } 3112 if (caps[0] & SDHCI_CAN_VDD_180) { 3113 ocr_avail |= MMC_VDD_165_195; 3114 3115 mmc->max_current_180 = ((max_current_caps & 3116 SDHCI_MAX_CURRENT_180_MASK) >> 3117 SDHCI_MAX_CURRENT_180_SHIFT) * 3118 SDHCI_MAX_CURRENT_MULTIPLIER; 3119 } 3120 3121 if (host->ocr_mask) 3122 ocr_avail = host->ocr_mask; 3123 3124 mmc->ocr_avail = ocr_avail; 3125 mmc->ocr_avail_sdio = ocr_avail; 3126 if (host->ocr_avail_sdio) 3127 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3128 mmc->ocr_avail_sd = ocr_avail; 3129 if (host->ocr_avail_sd) 3130 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3131 else /* normal SD controllers don't support 1.8V */ 3132 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3133 mmc->ocr_avail_mmc = ocr_avail; 3134 if (host->ocr_avail_mmc) 3135 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3136 3137 if (mmc->ocr_avail == 0) { 3138 pr_err("%s: Hardware doesn't report any " 3139 "support voltages.\n", mmc_hostname(mmc)); 3140 return -ENODEV; 3141 } 3142 3143 spin_lock_init(&host->lock); 3144 3145 /* 3146 * Maximum number of segments. Depends on if the hardware 3147 * can do scatter/gather or not. 3148 */ 3149 if (host->flags & SDHCI_USE_ADMA) 3150 mmc->max_segs = 128; 3151 else if (host->flags & SDHCI_USE_SDMA) 3152 mmc->max_segs = 1; 3153 else /* PIO */ 3154 mmc->max_segs = 128; 3155 3156 /* 3157 * Maximum number of sectors in one transfer. Limited by DMA boundary 3158 * size (512KiB). 3159 */ 3160 mmc->max_req_size = 524288; 3161 3162 /* 3163 * Maximum segment size. Could be one segment with the maximum number 3164 * of bytes. When doing hardware scatter/gather, each entry cannot 3165 * be larger than 64 KiB though. 3166 */ 3167 if (host->flags & SDHCI_USE_ADMA) { 3168 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3169 mmc->max_seg_size = 65535; 3170 else 3171 mmc->max_seg_size = 65536; 3172 } else { 3173 mmc->max_seg_size = mmc->max_req_size; 3174 } 3175 3176 /* 3177 * Maximum block size. This varies from controller to controller and 3178 * is specified in the capabilities register. 3179 */ 3180 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3181 mmc->max_blk_size = 2; 3182 } else { 3183 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3184 SDHCI_MAX_BLOCK_SHIFT; 3185 if (mmc->max_blk_size >= 3) { 3186 pr_warning("%s: Invalid maximum block size, " 3187 "assuming 512 bytes\n", mmc_hostname(mmc)); 3188 mmc->max_blk_size = 0; 3189 } 3190 } 3191 3192 mmc->max_blk_size = 512 << mmc->max_blk_size; 3193 3194 /* 3195 * Maximum block count. 3196 */ 3197 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3198 3199 /* 3200 * Init tasklets. 3201 */ 3202 tasklet_init(&host->finish_tasklet, 3203 sdhci_tasklet_finish, (unsigned long)host); 3204 3205 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3206 3207 if (host->version >= SDHCI_SPEC_300) { 3208 init_waitqueue_head(&host->buf_ready_int); 3209 3210 /* Initialize re-tuning timer */ 3211 init_timer(&host->tuning_timer); 3212 host->tuning_timer.data = (unsigned long)host; 3213 host->tuning_timer.function = sdhci_tuning_timer; 3214 } 3215 3216 sdhci_init(host, 0); 3217 3218 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3219 IRQF_SHARED, mmc_hostname(mmc), host); 3220 if (ret) { 3221 pr_err("%s: Failed to request IRQ %d: %d\n", 3222 mmc_hostname(mmc), host->irq, ret); 3223 goto untasklet; 3224 } 3225 3226 #ifdef CONFIG_MMC_DEBUG 3227 sdhci_dumpregs(host); 3228 #endif 3229 3230 #ifdef SDHCI_USE_LEDS_CLASS 3231 snprintf(host->led_name, sizeof(host->led_name), 3232 "%s::", mmc_hostname(mmc)); 3233 host->led.name = host->led_name; 3234 host->led.brightness = LED_OFF; 3235 host->led.default_trigger = mmc_hostname(mmc); 3236 host->led.brightness_set = sdhci_led_control; 3237 3238 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3239 if (ret) { 3240 pr_err("%s: Failed to register LED device: %d\n", 3241 mmc_hostname(mmc), ret); 3242 goto reset; 3243 } 3244 #endif 3245 3246 mmiowb(); 3247 3248 mmc_add_host(mmc); 3249 3250 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3251 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3252 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3253 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3254 3255 sdhci_enable_card_detection(host); 3256 3257 return 0; 3258 3259 #ifdef SDHCI_USE_LEDS_CLASS 3260 reset: 3261 sdhci_do_reset(host, SDHCI_RESET_ALL); 3262 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3263 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3264 free_irq(host->irq, host); 3265 #endif 3266 untasklet: 3267 tasklet_kill(&host->finish_tasklet); 3268 3269 return ret; 3270 } 3271 3272 EXPORT_SYMBOL_GPL(sdhci_add_host); 3273 3274 void sdhci_remove_host(struct sdhci_host *host, int dead) 3275 { 3276 unsigned long flags; 3277 3278 if (dead) { 3279 spin_lock_irqsave(&host->lock, flags); 3280 3281 host->flags |= SDHCI_DEVICE_DEAD; 3282 3283 if (host->mrq) { 3284 pr_err("%s: Controller removed during " 3285 " transfer!\n", mmc_hostname(host->mmc)); 3286 3287 host->mrq->cmd->error = -ENOMEDIUM; 3288 tasklet_schedule(&host->finish_tasklet); 3289 } 3290 3291 spin_unlock_irqrestore(&host->lock, flags); 3292 } 3293 3294 sdhci_disable_card_detection(host); 3295 3296 mmc_remove_host(host->mmc); 3297 3298 #ifdef SDHCI_USE_LEDS_CLASS 3299 led_classdev_unregister(&host->led); 3300 #endif 3301 3302 if (!dead) 3303 sdhci_do_reset(host, SDHCI_RESET_ALL); 3304 3305 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3307 free_irq(host->irq, host); 3308 3309 del_timer_sync(&host->timer); 3310 3311 tasklet_kill(&host->finish_tasklet); 3312 3313 if (host->vmmc) { 3314 regulator_disable(host->vmmc); 3315 regulator_put(host->vmmc); 3316 } 3317 3318 if (host->vqmmc) { 3319 regulator_disable(host->vqmmc); 3320 regulator_put(host->vqmmc); 3321 } 3322 3323 if (host->adma_desc) 3324 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, 3325 host->adma_desc, host->adma_addr); 3326 kfree(host->align_buffer); 3327 3328 host->adma_desc = NULL; 3329 host->align_buffer = NULL; 3330 } 3331 3332 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3333 3334 void sdhci_free_host(struct sdhci_host *host) 3335 { 3336 mmc_free_host(host->mmc); 3337 } 3338 3339 EXPORT_SYMBOL_GPL(sdhci_free_host); 3340 3341 /*****************************************************************************\ 3342 * * 3343 * Driver init/exit * 3344 * * 3345 \*****************************************************************************/ 3346 3347 static int __init sdhci_drv_init(void) 3348 { 3349 pr_info(DRIVER_NAME 3350 ": Secure Digital Host Controller Interface driver\n"); 3351 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3352 3353 return 0; 3354 } 3355 3356 static void __exit sdhci_drv_exit(void) 3357 { 3358 } 3359 3360 module_init(sdhci_drv_init); 3361 module_exit(sdhci_drv_exit); 3362 3363 module_param(debug_quirks, uint, 0444); 3364 module_param(debug_quirks2, uint, 0444); 3365 3366 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3367 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3368 MODULE_LICENSE("GPL"); 3369 3370 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3371 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3372