1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 27 #include <linux/leds.h> 28 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/card.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "sdhci.h" 36 37 #define DRIVER_NAME "sdhci" 38 39 #define DBG(f, x...) \ 40 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 41 42 #define MAX_TUNING_LOOP 40 43 44 static unsigned int debug_quirks = 0; 45 static unsigned int debug_quirks2; 46 47 static void sdhci_finish_data(struct sdhci_host *); 48 49 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 50 51 static void sdhci_dumpregs(struct sdhci_host *host) 52 { 53 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 54 mmc_hostname(host->mmc)); 55 56 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 57 sdhci_readl(host, SDHCI_DMA_ADDRESS), 58 sdhci_readw(host, SDHCI_HOST_VERSION)); 59 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 60 sdhci_readw(host, SDHCI_BLOCK_SIZE), 61 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 62 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 63 sdhci_readl(host, SDHCI_ARGUMENT), 64 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 65 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 66 sdhci_readl(host, SDHCI_PRESENT_STATE), 67 sdhci_readb(host, SDHCI_HOST_CONTROL)); 68 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 69 sdhci_readb(host, SDHCI_POWER_CONTROL), 70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 71 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 73 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 74 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 76 sdhci_readl(host, SDHCI_INT_STATUS)); 77 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 78 sdhci_readl(host, SDHCI_INT_ENABLE), 79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 80 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 81 sdhci_readw(host, SDHCI_ACMD12_ERR), 82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 83 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 84 sdhci_readl(host, SDHCI_CAPABILITIES), 85 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 86 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 87 sdhci_readw(host, SDHCI_COMMAND), 88 sdhci_readl(host, SDHCI_MAX_CURRENT)); 89 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n", 90 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 91 92 if (host->flags & SDHCI_USE_ADMA) { 93 if (host->flags & SDHCI_USE_64_BIT_DMA) 94 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 95 readl(host->ioaddr + SDHCI_ADMA_ERROR), 96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 97 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 98 else 99 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 100 readl(host->ioaddr + SDHCI_ADMA_ERROR), 101 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 102 } 103 104 pr_err(DRIVER_NAME ": ===========================================\n"); 105 } 106 107 /*****************************************************************************\ 108 * * 109 * Low level functions * 110 * * 111 \*****************************************************************************/ 112 113 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 114 { 115 return cmd->data || cmd->flags & MMC_RSP_BUSY; 116 } 117 118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 119 { 120 u32 present; 121 122 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 123 !mmc_card_is_removable(host->mmc)) 124 return; 125 126 if (enable) { 127 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 128 SDHCI_CARD_PRESENT; 129 130 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 131 SDHCI_INT_CARD_INSERT; 132 } else { 133 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 134 } 135 136 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 137 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 138 } 139 140 static void sdhci_enable_card_detection(struct sdhci_host *host) 141 { 142 sdhci_set_card_detection(host, true); 143 } 144 145 static void sdhci_disable_card_detection(struct sdhci_host *host) 146 { 147 sdhci_set_card_detection(host, false); 148 } 149 150 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 151 { 152 if (host->bus_on) 153 return; 154 host->bus_on = true; 155 pm_runtime_get_noresume(host->mmc->parent); 156 } 157 158 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 159 { 160 if (!host->bus_on) 161 return; 162 host->bus_on = false; 163 pm_runtime_put_noidle(host->mmc->parent); 164 } 165 166 void sdhci_reset(struct sdhci_host *host, u8 mask) 167 { 168 unsigned long timeout; 169 170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 171 172 if (mask & SDHCI_RESET_ALL) { 173 host->clock = 0; 174 /* Reset-all turns off SD Bus Power */ 175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 176 sdhci_runtime_pm_bus_off(host); 177 } 178 179 /* Wait max 100 ms */ 180 timeout = 100; 181 182 /* hw clears the bit when it's done */ 183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 184 if (timeout == 0) { 185 pr_err("%s: Reset 0x%x never completed.\n", 186 mmc_hostname(host->mmc), (int)mask); 187 sdhci_dumpregs(host); 188 return; 189 } 190 timeout--; 191 mdelay(1); 192 } 193 } 194 EXPORT_SYMBOL_GPL(sdhci_reset); 195 196 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 197 { 198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 199 struct mmc_host *mmc = host->mmc; 200 201 if (!mmc->ops->get_cd(mmc)) 202 return; 203 } 204 205 host->ops->reset(host, mask); 206 207 if (mask & SDHCI_RESET_ALL) { 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 209 if (host->ops->enable_dma) 210 host->ops->enable_dma(host); 211 } 212 213 /* Resetting the controller clears many */ 214 host->preset_enabled = false; 215 } 216 } 217 218 static void sdhci_init(struct sdhci_host *host, int soft) 219 { 220 struct mmc_host *mmc = host->mmc; 221 222 if (soft) 223 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 224 else 225 sdhci_do_reset(host, SDHCI_RESET_ALL); 226 227 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 229 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 230 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 231 SDHCI_INT_RESPONSE; 232 233 if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 234 host->tuning_mode == SDHCI_TUNING_MODE_3) 235 host->ier |= SDHCI_INT_RETUNE; 236 237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 239 240 if (soft) { 241 /* force clock reconfiguration */ 242 host->clock = 0; 243 mmc->ops->set_ios(mmc, &mmc->ios); 244 } 245 } 246 247 static void sdhci_reinit(struct sdhci_host *host) 248 { 249 sdhci_init(host, 0); 250 sdhci_enable_card_detection(host); 251 } 252 253 static void __sdhci_led_activate(struct sdhci_host *host) 254 { 255 u8 ctrl; 256 257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 258 ctrl |= SDHCI_CTRL_LED; 259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 260 } 261 262 static void __sdhci_led_deactivate(struct sdhci_host *host) 263 { 264 u8 ctrl; 265 266 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 267 ctrl &= ~SDHCI_CTRL_LED; 268 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 269 } 270 271 #if IS_REACHABLE(CONFIG_LEDS_CLASS) 272 static void sdhci_led_control(struct led_classdev *led, 273 enum led_brightness brightness) 274 { 275 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 276 unsigned long flags; 277 278 spin_lock_irqsave(&host->lock, flags); 279 280 if (host->runtime_suspended) 281 goto out; 282 283 if (brightness == LED_OFF) 284 __sdhci_led_deactivate(host); 285 else 286 __sdhci_led_activate(host); 287 out: 288 spin_unlock_irqrestore(&host->lock, flags); 289 } 290 291 static int sdhci_led_register(struct sdhci_host *host) 292 { 293 struct mmc_host *mmc = host->mmc; 294 295 snprintf(host->led_name, sizeof(host->led_name), 296 "%s::", mmc_hostname(mmc)); 297 298 host->led.name = host->led_name; 299 host->led.brightness = LED_OFF; 300 host->led.default_trigger = mmc_hostname(mmc); 301 host->led.brightness_set = sdhci_led_control; 302 303 return led_classdev_register(mmc_dev(mmc), &host->led); 304 } 305 306 static void sdhci_led_unregister(struct sdhci_host *host) 307 { 308 led_classdev_unregister(&host->led); 309 } 310 311 static inline void sdhci_led_activate(struct sdhci_host *host) 312 { 313 } 314 315 static inline void sdhci_led_deactivate(struct sdhci_host *host) 316 { 317 } 318 319 #else 320 321 static inline int sdhci_led_register(struct sdhci_host *host) 322 { 323 return 0; 324 } 325 326 static inline void sdhci_led_unregister(struct sdhci_host *host) 327 { 328 } 329 330 static inline void sdhci_led_activate(struct sdhci_host *host) 331 { 332 __sdhci_led_activate(host); 333 } 334 335 static inline void sdhci_led_deactivate(struct sdhci_host *host) 336 { 337 __sdhci_led_deactivate(host); 338 } 339 340 #endif 341 342 /*****************************************************************************\ 343 * * 344 * Core functions * 345 * * 346 \*****************************************************************************/ 347 348 static void sdhci_read_block_pio(struct sdhci_host *host) 349 { 350 unsigned long flags; 351 size_t blksize, len, chunk; 352 u32 uninitialized_var(scratch); 353 u8 *buf; 354 355 DBG("PIO reading\n"); 356 357 blksize = host->data->blksz; 358 chunk = 0; 359 360 local_irq_save(flags); 361 362 while (blksize) { 363 BUG_ON(!sg_miter_next(&host->sg_miter)); 364 365 len = min(host->sg_miter.length, blksize); 366 367 blksize -= len; 368 host->sg_miter.consumed = len; 369 370 buf = host->sg_miter.addr; 371 372 while (len) { 373 if (chunk == 0) { 374 scratch = sdhci_readl(host, SDHCI_BUFFER); 375 chunk = 4; 376 } 377 378 *buf = scratch & 0xFF; 379 380 buf++; 381 scratch >>= 8; 382 chunk--; 383 len--; 384 } 385 } 386 387 sg_miter_stop(&host->sg_miter); 388 389 local_irq_restore(flags); 390 } 391 392 static void sdhci_write_block_pio(struct sdhci_host *host) 393 { 394 unsigned long flags; 395 size_t blksize, len, chunk; 396 u32 scratch; 397 u8 *buf; 398 399 DBG("PIO writing\n"); 400 401 blksize = host->data->blksz; 402 chunk = 0; 403 scratch = 0; 404 405 local_irq_save(flags); 406 407 while (blksize) { 408 BUG_ON(!sg_miter_next(&host->sg_miter)); 409 410 len = min(host->sg_miter.length, blksize); 411 412 blksize -= len; 413 host->sg_miter.consumed = len; 414 415 buf = host->sg_miter.addr; 416 417 while (len) { 418 scratch |= (u32)*buf << (chunk * 8); 419 420 buf++; 421 chunk++; 422 len--; 423 424 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 425 sdhci_writel(host, scratch, SDHCI_BUFFER); 426 chunk = 0; 427 scratch = 0; 428 } 429 } 430 } 431 432 sg_miter_stop(&host->sg_miter); 433 434 local_irq_restore(flags); 435 } 436 437 static void sdhci_transfer_pio(struct sdhci_host *host) 438 { 439 u32 mask; 440 441 if (host->blocks == 0) 442 return; 443 444 if (host->data->flags & MMC_DATA_READ) 445 mask = SDHCI_DATA_AVAILABLE; 446 else 447 mask = SDHCI_SPACE_AVAILABLE; 448 449 /* 450 * Some controllers (JMicron JMB38x) mess up the buffer bits 451 * for transfers < 4 bytes. As long as it is just one block, 452 * we can ignore the bits. 453 */ 454 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 455 (host->data->blocks == 1)) 456 mask = ~0; 457 458 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 459 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 460 udelay(100); 461 462 if (host->data->flags & MMC_DATA_READ) 463 sdhci_read_block_pio(host); 464 else 465 sdhci_write_block_pio(host); 466 467 host->blocks--; 468 if (host->blocks == 0) 469 break; 470 } 471 472 DBG("PIO transfer complete.\n"); 473 } 474 475 static int sdhci_pre_dma_transfer(struct sdhci_host *host, 476 struct mmc_data *data, int cookie) 477 { 478 int sg_count; 479 480 /* 481 * If the data buffers are already mapped, return the previous 482 * dma_map_sg() result. 483 */ 484 if (data->host_cookie == COOKIE_PRE_MAPPED) 485 return data->sg_count; 486 487 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 488 data->flags & MMC_DATA_WRITE ? 489 DMA_TO_DEVICE : DMA_FROM_DEVICE); 490 491 if (sg_count == 0) 492 return -ENOSPC; 493 494 data->sg_count = sg_count; 495 data->host_cookie = cookie; 496 497 return sg_count; 498 } 499 500 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 501 { 502 local_irq_save(*flags); 503 return kmap_atomic(sg_page(sg)) + sg->offset; 504 } 505 506 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 507 { 508 kunmap_atomic(buffer); 509 local_irq_restore(*flags); 510 } 511 512 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 513 dma_addr_t addr, int len, unsigned cmd) 514 { 515 struct sdhci_adma2_64_desc *dma_desc = desc; 516 517 /* 32-bit and 64-bit descriptors have these members in same position */ 518 dma_desc->cmd = cpu_to_le16(cmd); 519 dma_desc->len = cpu_to_le16(len); 520 dma_desc->addr_lo = cpu_to_le32((u32)addr); 521 522 if (host->flags & SDHCI_USE_64_BIT_DMA) 523 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 524 } 525 526 static void sdhci_adma_mark_end(void *desc) 527 { 528 struct sdhci_adma2_64_desc *dma_desc = desc; 529 530 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 531 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 532 } 533 534 static void sdhci_adma_table_pre(struct sdhci_host *host, 535 struct mmc_data *data, int sg_count) 536 { 537 struct scatterlist *sg; 538 unsigned long flags; 539 dma_addr_t addr, align_addr; 540 void *desc, *align; 541 char *buffer; 542 int len, offset, i; 543 544 /* 545 * The spec does not specify endianness of descriptor table. 546 * We currently guess that it is LE. 547 */ 548 549 host->sg_count = sg_count; 550 551 desc = host->adma_table; 552 align = host->align_buffer; 553 554 align_addr = host->align_addr; 555 556 for_each_sg(data->sg, sg, host->sg_count, i) { 557 addr = sg_dma_address(sg); 558 len = sg_dma_len(sg); 559 560 /* 561 * The SDHCI specification states that ADMA addresses must 562 * be 32-bit aligned. If they aren't, then we use a bounce 563 * buffer for the (up to three) bytes that screw up the 564 * alignment. 565 */ 566 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 567 SDHCI_ADMA2_MASK; 568 if (offset) { 569 if (data->flags & MMC_DATA_WRITE) { 570 buffer = sdhci_kmap_atomic(sg, &flags); 571 memcpy(align, buffer, offset); 572 sdhci_kunmap_atomic(buffer, &flags); 573 } 574 575 /* tran, valid */ 576 sdhci_adma_write_desc(host, desc, align_addr, offset, 577 ADMA2_TRAN_VALID); 578 579 BUG_ON(offset > 65536); 580 581 align += SDHCI_ADMA2_ALIGN; 582 align_addr += SDHCI_ADMA2_ALIGN; 583 584 desc += host->desc_sz; 585 586 addr += offset; 587 len -= offset; 588 } 589 590 BUG_ON(len > 65536); 591 592 if (len) { 593 /* tran, valid */ 594 sdhci_adma_write_desc(host, desc, addr, len, 595 ADMA2_TRAN_VALID); 596 desc += host->desc_sz; 597 } 598 599 /* 600 * If this triggers then we have a calculation bug 601 * somewhere. :/ 602 */ 603 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 604 } 605 606 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 607 /* Mark the last descriptor as the terminating descriptor */ 608 if (desc != host->adma_table) { 609 desc -= host->desc_sz; 610 sdhci_adma_mark_end(desc); 611 } 612 } else { 613 /* Add a terminating entry - nop, end, valid */ 614 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 615 } 616 } 617 618 static void sdhci_adma_table_post(struct sdhci_host *host, 619 struct mmc_data *data) 620 { 621 struct scatterlist *sg; 622 int i, size; 623 void *align; 624 char *buffer; 625 unsigned long flags; 626 627 if (data->flags & MMC_DATA_READ) { 628 bool has_unaligned = false; 629 630 /* Do a quick scan of the SG list for any unaligned mappings */ 631 for_each_sg(data->sg, sg, host->sg_count, i) 632 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 633 has_unaligned = true; 634 break; 635 } 636 637 if (has_unaligned) { 638 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 639 data->sg_len, DMA_FROM_DEVICE); 640 641 align = host->align_buffer; 642 643 for_each_sg(data->sg, sg, host->sg_count, i) { 644 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 645 size = SDHCI_ADMA2_ALIGN - 646 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 647 648 buffer = sdhci_kmap_atomic(sg, &flags); 649 memcpy(buffer, align, size); 650 sdhci_kunmap_atomic(buffer, &flags); 651 652 align += SDHCI_ADMA2_ALIGN; 653 } 654 } 655 } 656 } 657 } 658 659 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 660 { 661 u8 count; 662 struct mmc_data *data = cmd->data; 663 unsigned target_timeout, current_timeout; 664 665 /* 666 * If the host controller provides us with an incorrect timeout 667 * value, just skip the check and use 0xE. The hardware may take 668 * longer to time out, but that's much better than having a too-short 669 * timeout value. 670 */ 671 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 672 return 0xE; 673 674 /* Unspecified timeout, assume max */ 675 if (!data && !cmd->busy_timeout) 676 return 0xE; 677 678 /* timeout in us */ 679 if (!data) 680 target_timeout = cmd->busy_timeout * 1000; 681 else { 682 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 683 if (host->clock && data->timeout_clks) { 684 unsigned long long val; 685 686 /* 687 * data->timeout_clks is in units of clock cycles. 688 * host->clock is in Hz. target_timeout is in us. 689 * Hence, us = 1000000 * cycles / Hz. Round up. 690 */ 691 val = 1000000ULL * data->timeout_clks; 692 if (do_div(val, host->clock)) 693 target_timeout++; 694 target_timeout += val; 695 } 696 } 697 698 /* 699 * Figure out needed cycles. 700 * We do this in steps in order to fit inside a 32 bit int. 701 * The first step is the minimum timeout, which will have a 702 * minimum resolution of 6 bits: 703 * (1) 2^13*1000 > 2^22, 704 * (2) host->timeout_clk < 2^16 705 * => 706 * (1) / (2) > 2^6 707 */ 708 count = 0; 709 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 710 while (current_timeout < target_timeout) { 711 count++; 712 current_timeout <<= 1; 713 if (count >= 0xF) 714 break; 715 } 716 717 if (count >= 0xF) { 718 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 719 mmc_hostname(host->mmc), count, cmd->opcode); 720 count = 0xE; 721 } 722 723 return count; 724 } 725 726 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 727 { 728 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 729 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 730 731 if (host->flags & SDHCI_REQ_USE_DMA) 732 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 733 else 734 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 735 736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 738 } 739 740 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 741 { 742 u8 count; 743 744 if (host->ops->set_timeout) { 745 host->ops->set_timeout(host, cmd); 746 } else { 747 count = sdhci_calc_timeout(host, cmd); 748 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 749 } 750 } 751 752 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 753 { 754 u8 ctrl; 755 struct mmc_data *data = cmd->data; 756 757 if (sdhci_data_line_cmd(cmd)) 758 sdhci_set_timeout(host, cmd); 759 760 if (!data) 761 return; 762 763 WARN_ON(host->data); 764 765 /* Sanity checks */ 766 BUG_ON(data->blksz * data->blocks > 524288); 767 BUG_ON(data->blksz > host->mmc->max_blk_size); 768 BUG_ON(data->blocks > 65535); 769 770 host->data = data; 771 host->data_early = 0; 772 host->data->bytes_xfered = 0; 773 774 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 775 struct scatterlist *sg; 776 unsigned int length_mask, offset_mask; 777 int i; 778 779 host->flags |= SDHCI_REQ_USE_DMA; 780 781 /* 782 * FIXME: This doesn't account for merging when mapping the 783 * scatterlist. 784 * 785 * The assumption here being that alignment and lengths are 786 * the same after DMA mapping to device address space. 787 */ 788 length_mask = 0; 789 offset_mask = 0; 790 if (host->flags & SDHCI_USE_ADMA) { 791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 792 length_mask = 3; 793 /* 794 * As we use up to 3 byte chunks to work 795 * around alignment problems, we need to 796 * check the offset as well. 797 */ 798 offset_mask = 3; 799 } 800 } else { 801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 802 length_mask = 3; 803 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 804 offset_mask = 3; 805 } 806 807 if (unlikely(length_mask | offset_mask)) { 808 for_each_sg(data->sg, sg, data->sg_len, i) { 809 if (sg->length & length_mask) { 810 DBG("Reverting to PIO because of transfer size (%d)\n", 811 sg->length); 812 host->flags &= ~SDHCI_REQ_USE_DMA; 813 break; 814 } 815 if (sg->offset & offset_mask) { 816 DBG("Reverting to PIO because of bad alignment\n"); 817 host->flags &= ~SDHCI_REQ_USE_DMA; 818 break; 819 } 820 } 821 } 822 } 823 824 if (host->flags & SDHCI_REQ_USE_DMA) { 825 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 826 827 if (sg_cnt <= 0) { 828 /* 829 * This only happens when someone fed 830 * us an invalid request. 831 */ 832 WARN_ON(1); 833 host->flags &= ~SDHCI_REQ_USE_DMA; 834 } else if (host->flags & SDHCI_USE_ADMA) { 835 sdhci_adma_table_pre(host, data, sg_cnt); 836 837 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 838 if (host->flags & SDHCI_USE_64_BIT_DMA) 839 sdhci_writel(host, 840 (u64)host->adma_addr >> 32, 841 SDHCI_ADMA_ADDRESS_HI); 842 } else { 843 WARN_ON(sg_cnt != 1); 844 sdhci_writel(host, sg_dma_address(data->sg), 845 SDHCI_DMA_ADDRESS); 846 } 847 } 848 849 /* 850 * Always adjust the DMA selection as some controllers 851 * (e.g. JMicron) can't do PIO properly when the selection 852 * is ADMA. 853 */ 854 if (host->version >= SDHCI_SPEC_200) { 855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 856 ctrl &= ~SDHCI_CTRL_DMA_MASK; 857 if ((host->flags & SDHCI_REQ_USE_DMA) && 858 (host->flags & SDHCI_USE_ADMA)) { 859 if (host->flags & SDHCI_USE_64_BIT_DMA) 860 ctrl |= SDHCI_CTRL_ADMA64; 861 else 862 ctrl |= SDHCI_CTRL_ADMA32; 863 } else { 864 ctrl |= SDHCI_CTRL_SDMA; 865 } 866 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 867 } 868 869 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 870 int flags; 871 872 flags = SG_MITER_ATOMIC; 873 if (host->data->flags & MMC_DATA_READ) 874 flags |= SG_MITER_TO_SG; 875 else 876 flags |= SG_MITER_FROM_SG; 877 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 878 host->blocks = data->blocks; 879 } 880 881 sdhci_set_transfer_irqs(host); 882 883 /* Set the DMA boundary value and block size */ 884 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 885 data->blksz), SDHCI_BLOCK_SIZE); 886 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 887 } 888 889 static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 890 struct mmc_request *mrq) 891 { 892 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 893 !mrq->cap_cmd_during_tfr; 894 } 895 896 static void sdhci_set_transfer_mode(struct sdhci_host *host, 897 struct mmc_command *cmd) 898 { 899 u16 mode = 0; 900 struct mmc_data *data = cmd->data; 901 902 if (data == NULL) { 903 if (host->quirks2 & 904 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 905 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 906 } else { 907 /* clear Auto CMD settings for no data CMDs */ 908 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 909 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 910 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 911 } 912 return; 913 } 914 915 WARN_ON(!host->data); 916 917 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 918 mode = SDHCI_TRNS_BLK_CNT_EN; 919 920 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 921 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 922 /* 923 * If we are sending CMD23, CMD12 never gets sent 924 * on successful completion (so no Auto-CMD12). 925 */ 926 if (sdhci_auto_cmd12(host, cmd->mrq) && 927 (cmd->opcode != SD_IO_RW_EXTENDED)) 928 mode |= SDHCI_TRNS_AUTO_CMD12; 929 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 930 mode |= SDHCI_TRNS_AUTO_CMD23; 931 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 932 } 933 } 934 935 if (data->flags & MMC_DATA_READ) 936 mode |= SDHCI_TRNS_READ; 937 if (host->flags & SDHCI_REQ_USE_DMA) 938 mode |= SDHCI_TRNS_DMA; 939 940 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 941 } 942 943 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 944 { 945 return (!(host->flags & SDHCI_DEVICE_DEAD) && 946 ((mrq->cmd && mrq->cmd->error) || 947 (mrq->sbc && mrq->sbc->error) || 948 (mrq->data && ((mrq->data->error && !mrq->data->stop) || 949 (mrq->data->stop && mrq->data->stop->error))) || 950 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 951 } 952 953 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 954 { 955 int i; 956 957 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 958 if (host->mrqs_done[i] == mrq) { 959 WARN_ON(1); 960 return; 961 } 962 } 963 964 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 965 if (!host->mrqs_done[i]) { 966 host->mrqs_done[i] = mrq; 967 break; 968 } 969 } 970 971 WARN_ON(i >= SDHCI_MAX_MRQS); 972 973 tasklet_schedule(&host->finish_tasklet); 974 } 975 976 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 977 { 978 if (host->cmd && host->cmd->mrq == mrq) 979 host->cmd = NULL; 980 981 if (host->data_cmd && host->data_cmd->mrq == mrq) 982 host->data_cmd = NULL; 983 984 if (host->data && host->data->mrq == mrq) 985 host->data = NULL; 986 987 if (sdhci_needs_reset(host, mrq)) 988 host->pending_reset = true; 989 990 __sdhci_finish_mrq(host, mrq); 991 } 992 993 static void sdhci_finish_data(struct sdhci_host *host) 994 { 995 struct mmc_command *data_cmd = host->data_cmd; 996 struct mmc_data *data = host->data; 997 998 host->data = NULL; 999 host->data_cmd = NULL; 1000 1001 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1002 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 1003 sdhci_adma_table_post(host, data); 1004 1005 /* 1006 * The specification states that the block count register must 1007 * be updated, but it does not specify at what point in the 1008 * data flow. That makes the register entirely useless to read 1009 * back so we have to assume that nothing made it to the card 1010 * in the event of an error. 1011 */ 1012 if (data->error) 1013 data->bytes_xfered = 0; 1014 else 1015 data->bytes_xfered = data->blksz * data->blocks; 1016 1017 /* 1018 * Need to send CMD12 if - 1019 * a) open-ended multiblock transfer (no CMD23) 1020 * b) error in multiblock transfer 1021 */ 1022 if (data->stop && 1023 (data->error || 1024 !data->mrq->sbc)) { 1025 1026 /* 1027 * The controller needs a reset of internal state machines 1028 * upon error conditions. 1029 */ 1030 if (data->error) { 1031 if (!host->cmd || host->cmd == data_cmd) 1032 sdhci_do_reset(host, SDHCI_RESET_CMD); 1033 sdhci_do_reset(host, SDHCI_RESET_DATA); 1034 } 1035 1036 /* 1037 * 'cap_cmd_during_tfr' request must not use the command line 1038 * after mmc_command_done() has been called. It is upper layer's 1039 * responsibility to send the stop command if required. 1040 */ 1041 if (data->mrq->cap_cmd_during_tfr) { 1042 sdhci_finish_mrq(host, data->mrq); 1043 } else { 1044 /* Avoid triggering warning in sdhci_send_command() */ 1045 host->cmd = NULL; 1046 sdhci_send_command(host, data->stop); 1047 } 1048 } else { 1049 sdhci_finish_mrq(host, data->mrq); 1050 } 1051 } 1052 1053 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 1054 unsigned long timeout) 1055 { 1056 if (sdhci_data_line_cmd(mrq->cmd)) 1057 mod_timer(&host->data_timer, timeout); 1058 else 1059 mod_timer(&host->timer, timeout); 1060 } 1061 1062 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 1063 { 1064 if (sdhci_data_line_cmd(mrq->cmd)) 1065 del_timer(&host->data_timer); 1066 else 1067 del_timer(&host->timer); 1068 } 1069 1070 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1071 { 1072 int flags; 1073 u32 mask; 1074 unsigned long timeout; 1075 1076 WARN_ON(host->cmd); 1077 1078 /* Initially, a command has no error */ 1079 cmd->error = 0; 1080 1081 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 1082 cmd->opcode == MMC_STOP_TRANSMISSION) 1083 cmd->flags |= MMC_RSP_BUSY; 1084 1085 /* Wait max 10 ms */ 1086 timeout = 10; 1087 1088 mask = SDHCI_CMD_INHIBIT; 1089 if (sdhci_data_line_cmd(cmd)) 1090 mask |= SDHCI_DATA_INHIBIT; 1091 1092 /* We shouldn't wait for data inihibit for stop commands, even 1093 though they might use busy signaling */ 1094 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 1095 mask &= ~SDHCI_DATA_INHIBIT; 1096 1097 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1098 if (timeout == 0) { 1099 pr_err("%s: Controller never released inhibit bit(s).\n", 1100 mmc_hostname(host->mmc)); 1101 sdhci_dumpregs(host); 1102 cmd->error = -EIO; 1103 sdhci_finish_mrq(host, cmd->mrq); 1104 return; 1105 } 1106 timeout--; 1107 mdelay(1); 1108 } 1109 1110 timeout = jiffies; 1111 if (!cmd->data && cmd->busy_timeout > 9000) 1112 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1113 else 1114 timeout += 10 * HZ; 1115 sdhci_mod_timer(host, cmd->mrq, timeout); 1116 1117 host->cmd = cmd; 1118 if (sdhci_data_line_cmd(cmd)) { 1119 WARN_ON(host->data_cmd); 1120 host->data_cmd = cmd; 1121 } 1122 1123 sdhci_prepare_data(host, cmd); 1124 1125 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1126 1127 sdhci_set_transfer_mode(host, cmd); 1128 1129 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1130 pr_err("%s: Unsupported response type!\n", 1131 mmc_hostname(host->mmc)); 1132 cmd->error = -EINVAL; 1133 sdhci_finish_mrq(host, cmd->mrq); 1134 return; 1135 } 1136 1137 if (!(cmd->flags & MMC_RSP_PRESENT)) 1138 flags = SDHCI_CMD_RESP_NONE; 1139 else if (cmd->flags & MMC_RSP_136) 1140 flags = SDHCI_CMD_RESP_LONG; 1141 else if (cmd->flags & MMC_RSP_BUSY) 1142 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1143 else 1144 flags = SDHCI_CMD_RESP_SHORT; 1145 1146 if (cmd->flags & MMC_RSP_CRC) 1147 flags |= SDHCI_CMD_CRC; 1148 if (cmd->flags & MMC_RSP_OPCODE) 1149 flags |= SDHCI_CMD_INDEX; 1150 1151 /* CMD19 is special in that the Data Present Select should be set */ 1152 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1153 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1154 flags |= SDHCI_CMD_DATA; 1155 1156 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1157 } 1158 EXPORT_SYMBOL_GPL(sdhci_send_command); 1159 1160 static void sdhci_finish_command(struct sdhci_host *host) 1161 { 1162 struct mmc_command *cmd = host->cmd; 1163 int i; 1164 1165 host->cmd = NULL; 1166 1167 if (cmd->flags & MMC_RSP_PRESENT) { 1168 if (cmd->flags & MMC_RSP_136) { 1169 /* CRC is stripped so we need to do some shifting. */ 1170 for (i = 0;i < 4;i++) { 1171 cmd->resp[i] = sdhci_readl(host, 1172 SDHCI_RESPONSE + (3-i)*4) << 8; 1173 if (i != 3) 1174 cmd->resp[i] |= 1175 sdhci_readb(host, 1176 SDHCI_RESPONSE + (3-i)*4-1); 1177 } 1178 } else { 1179 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1180 } 1181 } 1182 1183 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 1184 mmc_command_done(host->mmc, cmd->mrq); 1185 1186 /* 1187 * The host can send and interrupt when the busy state has 1188 * ended, allowing us to wait without wasting CPU cycles. 1189 * The busy signal uses DAT0 so this is similar to waiting 1190 * for data to complete. 1191 * 1192 * Note: The 1.0 specification is a bit ambiguous about this 1193 * feature so there might be some problems with older 1194 * controllers. 1195 */ 1196 if (cmd->flags & MMC_RSP_BUSY) { 1197 if (cmd->data) { 1198 DBG("Cannot wait for busy signal when also doing a data transfer"); 1199 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1200 cmd == host->data_cmd) { 1201 /* Command complete before busy is ended */ 1202 return; 1203 } 1204 } 1205 1206 /* Finished CMD23, now send actual command. */ 1207 if (cmd == cmd->mrq->sbc) { 1208 sdhci_send_command(host, cmd->mrq->cmd); 1209 } else { 1210 1211 /* Processed actual command. */ 1212 if (host->data && host->data_early) 1213 sdhci_finish_data(host); 1214 1215 if (!cmd->data) 1216 sdhci_finish_mrq(host, cmd->mrq); 1217 } 1218 } 1219 1220 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1221 { 1222 u16 preset = 0; 1223 1224 switch (host->timing) { 1225 case MMC_TIMING_UHS_SDR12: 1226 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1227 break; 1228 case MMC_TIMING_UHS_SDR25: 1229 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1230 break; 1231 case MMC_TIMING_UHS_SDR50: 1232 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1233 break; 1234 case MMC_TIMING_UHS_SDR104: 1235 case MMC_TIMING_MMC_HS200: 1236 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1237 break; 1238 case MMC_TIMING_UHS_DDR50: 1239 case MMC_TIMING_MMC_DDR52: 1240 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1241 break; 1242 case MMC_TIMING_MMC_HS400: 1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1244 break; 1245 default: 1246 pr_warn("%s: Invalid UHS-I mode selected\n", 1247 mmc_hostname(host->mmc)); 1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1249 break; 1250 } 1251 return preset; 1252 } 1253 1254 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1255 unsigned int *actual_clock) 1256 { 1257 int div = 0; /* Initialized for compiler warning */ 1258 int real_div = div, clk_mul = 1; 1259 u16 clk = 0; 1260 bool switch_base_clk = false; 1261 1262 if (host->version >= SDHCI_SPEC_300) { 1263 if (host->preset_enabled) { 1264 u16 pre_val; 1265 1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1267 pre_val = sdhci_get_preset_value(host); 1268 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1269 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1270 if (host->clk_mul && 1271 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1272 clk = SDHCI_PROG_CLOCK_MODE; 1273 real_div = div + 1; 1274 clk_mul = host->clk_mul; 1275 } else { 1276 real_div = max_t(int, 1, div << 1); 1277 } 1278 goto clock_set; 1279 } 1280 1281 /* 1282 * Check if the Host Controller supports Programmable Clock 1283 * Mode. 1284 */ 1285 if (host->clk_mul) { 1286 for (div = 1; div <= 1024; div++) { 1287 if ((host->max_clk * host->clk_mul / div) 1288 <= clock) 1289 break; 1290 } 1291 if ((host->max_clk * host->clk_mul / div) <= clock) { 1292 /* 1293 * Set Programmable Clock Mode in the Clock 1294 * Control register. 1295 */ 1296 clk = SDHCI_PROG_CLOCK_MODE; 1297 real_div = div; 1298 clk_mul = host->clk_mul; 1299 div--; 1300 } else { 1301 /* 1302 * Divisor can be too small to reach clock 1303 * speed requirement. Then use the base clock. 1304 */ 1305 switch_base_clk = true; 1306 } 1307 } 1308 1309 if (!host->clk_mul || switch_base_clk) { 1310 /* Version 3.00 divisors must be a multiple of 2. */ 1311 if (host->max_clk <= clock) 1312 div = 1; 1313 else { 1314 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1315 div += 2) { 1316 if ((host->max_clk / div) <= clock) 1317 break; 1318 } 1319 } 1320 real_div = div; 1321 div >>= 1; 1322 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1323 && !div && host->max_clk <= 25000000) 1324 div = 1; 1325 } 1326 } else { 1327 /* Version 2.00 divisors must be a power of 2. */ 1328 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1329 if ((host->max_clk / div) <= clock) 1330 break; 1331 } 1332 real_div = div; 1333 div >>= 1; 1334 } 1335 1336 clock_set: 1337 if (real_div) 1338 *actual_clock = (host->max_clk * clk_mul) / real_div; 1339 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1340 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1341 << SDHCI_DIVIDER_HI_SHIFT; 1342 1343 return clk; 1344 } 1345 EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1346 1347 void sdhci_enable_clk(struct sdhci_host *host, u16 clk) 1348 { 1349 unsigned long timeout; 1350 1351 clk |= SDHCI_CLOCK_INT_EN; 1352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1353 1354 /* Wait max 20 ms */ 1355 timeout = 20; 1356 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1357 & SDHCI_CLOCK_INT_STABLE)) { 1358 if (timeout == 0) { 1359 pr_err("%s: Internal clock never stabilised.\n", 1360 mmc_hostname(host->mmc)); 1361 sdhci_dumpregs(host); 1362 return; 1363 } 1364 timeout--; 1365 spin_unlock_irq(&host->lock); 1366 usleep_range(900, 1100); 1367 spin_lock_irq(&host->lock); 1368 } 1369 1370 clk |= SDHCI_CLOCK_CARD_EN; 1371 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1372 } 1373 EXPORT_SYMBOL_GPL(sdhci_enable_clk); 1374 1375 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1376 { 1377 u16 clk; 1378 1379 host->mmc->actual_clock = 0; 1380 1381 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1382 1383 if (clock == 0) 1384 return; 1385 1386 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1387 sdhci_enable_clk(host, clk); 1388 } 1389 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1390 1391 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 1392 unsigned short vdd) 1393 { 1394 struct mmc_host *mmc = host->mmc; 1395 1396 spin_unlock_irq(&host->lock); 1397 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1398 spin_lock_irq(&host->lock); 1399 1400 if (mode != MMC_POWER_OFF) 1401 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1402 else 1403 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1404 } 1405 1406 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 1407 unsigned short vdd) 1408 { 1409 u8 pwr = 0; 1410 1411 if (mode != MMC_POWER_OFF) { 1412 switch (1 << vdd) { 1413 case MMC_VDD_165_195: 1414 pwr = SDHCI_POWER_180; 1415 break; 1416 case MMC_VDD_29_30: 1417 case MMC_VDD_30_31: 1418 pwr = SDHCI_POWER_300; 1419 break; 1420 case MMC_VDD_32_33: 1421 case MMC_VDD_33_34: 1422 pwr = SDHCI_POWER_330; 1423 break; 1424 default: 1425 WARN(1, "%s: Invalid vdd %#x\n", 1426 mmc_hostname(host->mmc), vdd); 1427 break; 1428 } 1429 } 1430 1431 if (host->pwr == pwr) 1432 return; 1433 1434 host->pwr = pwr; 1435 1436 if (pwr == 0) { 1437 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1438 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1439 sdhci_runtime_pm_bus_off(host); 1440 } else { 1441 /* 1442 * Spec says that we should clear the power reg before setting 1443 * a new value. Some controllers don't seem to like this though. 1444 */ 1445 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1446 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1447 1448 /* 1449 * At least the Marvell CaFe chip gets confused if we set the 1450 * voltage and set turn on power at the same time, so set the 1451 * voltage first. 1452 */ 1453 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1454 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1455 1456 pwr |= SDHCI_POWER_ON; 1457 1458 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1459 1460 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1461 sdhci_runtime_pm_bus_on(host); 1462 1463 /* 1464 * Some controllers need an extra 10ms delay of 10ms before 1465 * they can apply clock after applying power 1466 */ 1467 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1468 mdelay(10); 1469 } 1470 } 1471 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); 1472 1473 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1474 unsigned short vdd) 1475 { 1476 if (IS_ERR(host->mmc->supply.vmmc)) 1477 sdhci_set_power_noreg(host, mode, vdd); 1478 else 1479 sdhci_set_power_reg(host, mode, vdd); 1480 } 1481 EXPORT_SYMBOL_GPL(sdhci_set_power); 1482 1483 /*****************************************************************************\ 1484 * * 1485 * MMC callbacks * 1486 * * 1487 \*****************************************************************************/ 1488 1489 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1490 { 1491 struct sdhci_host *host; 1492 int present; 1493 unsigned long flags; 1494 1495 host = mmc_priv(mmc); 1496 1497 /* Firstly check card presence */ 1498 present = mmc->ops->get_cd(mmc); 1499 1500 spin_lock_irqsave(&host->lock, flags); 1501 1502 sdhci_led_activate(host); 1503 1504 /* 1505 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1506 * requests if Auto-CMD12 is enabled. 1507 */ 1508 if (sdhci_auto_cmd12(host, mrq)) { 1509 if (mrq->stop) { 1510 mrq->data->stop = NULL; 1511 mrq->stop = NULL; 1512 } 1513 } 1514 1515 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1516 mrq->cmd->error = -ENOMEDIUM; 1517 sdhci_finish_mrq(host, mrq); 1518 } else { 1519 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1520 sdhci_send_command(host, mrq->sbc); 1521 else 1522 sdhci_send_command(host, mrq->cmd); 1523 } 1524 1525 mmiowb(); 1526 spin_unlock_irqrestore(&host->lock, flags); 1527 } 1528 1529 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1530 { 1531 u8 ctrl; 1532 1533 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1534 if (width == MMC_BUS_WIDTH_8) { 1535 ctrl &= ~SDHCI_CTRL_4BITBUS; 1536 if (host->version >= SDHCI_SPEC_300) 1537 ctrl |= SDHCI_CTRL_8BITBUS; 1538 } else { 1539 if (host->version >= SDHCI_SPEC_300) 1540 ctrl &= ~SDHCI_CTRL_8BITBUS; 1541 if (width == MMC_BUS_WIDTH_4) 1542 ctrl |= SDHCI_CTRL_4BITBUS; 1543 else 1544 ctrl &= ~SDHCI_CTRL_4BITBUS; 1545 } 1546 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1547 } 1548 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1549 1550 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1551 { 1552 u16 ctrl_2; 1553 1554 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1555 /* Select Bus Speed Mode for host */ 1556 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1557 if ((timing == MMC_TIMING_MMC_HS200) || 1558 (timing == MMC_TIMING_UHS_SDR104)) 1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1560 else if (timing == MMC_TIMING_UHS_SDR12) 1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1562 else if (timing == MMC_TIMING_UHS_SDR25) 1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1564 else if (timing == MMC_TIMING_UHS_SDR50) 1565 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1566 else if ((timing == MMC_TIMING_UHS_DDR50) || 1567 (timing == MMC_TIMING_MMC_DDR52)) 1568 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1569 else if (timing == MMC_TIMING_MMC_HS400) 1570 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1571 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1572 } 1573 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1574 1575 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1576 { 1577 struct sdhci_host *host = mmc_priv(mmc); 1578 unsigned long flags; 1579 u8 ctrl; 1580 1581 if (ios->power_mode == MMC_POWER_UNDEFINED) 1582 return; 1583 1584 spin_lock_irqsave(&host->lock, flags); 1585 1586 if (host->flags & SDHCI_DEVICE_DEAD) { 1587 spin_unlock_irqrestore(&host->lock, flags); 1588 if (!IS_ERR(mmc->supply.vmmc) && 1589 ios->power_mode == MMC_POWER_OFF) 1590 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1591 return; 1592 } 1593 1594 /* 1595 * Reset the chip on each power off. 1596 * Should clear out any weird states. 1597 */ 1598 if (ios->power_mode == MMC_POWER_OFF) { 1599 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1600 sdhci_reinit(host); 1601 } 1602 1603 if (host->version >= SDHCI_SPEC_300 && 1604 (ios->power_mode == MMC_POWER_UP) && 1605 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1606 sdhci_enable_preset_value(host, false); 1607 1608 if (!ios->clock || ios->clock != host->clock) { 1609 host->ops->set_clock(host, ios->clock); 1610 host->clock = ios->clock; 1611 1612 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1613 host->clock) { 1614 host->timeout_clk = host->mmc->actual_clock ? 1615 host->mmc->actual_clock / 1000 : 1616 host->clock / 1000; 1617 host->mmc->max_busy_timeout = 1618 host->ops->get_max_timeout_count ? 1619 host->ops->get_max_timeout_count(host) : 1620 1 << 27; 1621 host->mmc->max_busy_timeout /= host->timeout_clk; 1622 } 1623 } 1624 1625 if (host->ops->set_power) 1626 host->ops->set_power(host, ios->power_mode, ios->vdd); 1627 else 1628 sdhci_set_power(host, ios->power_mode, ios->vdd); 1629 1630 if (host->ops->platform_send_init_74_clocks) 1631 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1632 1633 host->ops->set_bus_width(host, ios->bus_width); 1634 1635 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1636 1637 if ((ios->timing == MMC_TIMING_SD_HS || 1638 ios->timing == MMC_TIMING_MMC_HS || 1639 ios->timing == MMC_TIMING_MMC_HS400 || 1640 ios->timing == MMC_TIMING_MMC_HS200 || 1641 ios->timing == MMC_TIMING_MMC_DDR52 || 1642 ios->timing == MMC_TIMING_UHS_SDR50 || 1643 ios->timing == MMC_TIMING_UHS_SDR104 || 1644 ios->timing == MMC_TIMING_UHS_DDR50 || 1645 ios->timing == MMC_TIMING_UHS_SDR25) 1646 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1647 ctrl |= SDHCI_CTRL_HISPD; 1648 else 1649 ctrl &= ~SDHCI_CTRL_HISPD; 1650 1651 if (host->version >= SDHCI_SPEC_300) { 1652 u16 clk, ctrl_2; 1653 1654 if (!host->preset_enabled) { 1655 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1656 /* 1657 * We only need to set Driver Strength if the 1658 * preset value enable is not set. 1659 */ 1660 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1661 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1662 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1663 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1664 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 1665 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1666 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1667 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1668 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 1669 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 1670 else { 1671 pr_warn("%s: invalid driver type, default to driver type B\n", 1672 mmc_hostname(mmc)); 1673 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1674 } 1675 1676 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1677 } else { 1678 /* 1679 * According to SDHC Spec v3.00, if the Preset Value 1680 * Enable in the Host Control 2 register is set, we 1681 * need to reset SD Clock Enable before changing High 1682 * Speed Enable to avoid generating clock gliches. 1683 */ 1684 1685 /* Reset SD Clock Enable */ 1686 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1687 clk &= ~SDHCI_CLOCK_CARD_EN; 1688 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1689 1690 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1691 1692 /* Re-enable SD Clock */ 1693 host->ops->set_clock(host, host->clock); 1694 } 1695 1696 /* Reset SD Clock Enable */ 1697 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1698 clk &= ~SDHCI_CLOCK_CARD_EN; 1699 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1700 1701 host->ops->set_uhs_signaling(host, ios->timing); 1702 host->timing = ios->timing; 1703 1704 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1705 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1706 (ios->timing == MMC_TIMING_UHS_SDR25) || 1707 (ios->timing == MMC_TIMING_UHS_SDR50) || 1708 (ios->timing == MMC_TIMING_UHS_SDR104) || 1709 (ios->timing == MMC_TIMING_UHS_DDR50) || 1710 (ios->timing == MMC_TIMING_MMC_DDR52))) { 1711 u16 preset; 1712 1713 sdhci_enable_preset_value(host, true); 1714 preset = sdhci_get_preset_value(host); 1715 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1716 >> SDHCI_PRESET_DRV_SHIFT; 1717 } 1718 1719 /* Re-enable SD Clock */ 1720 host->ops->set_clock(host, host->clock); 1721 } else 1722 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1723 1724 /* 1725 * Some (ENE) controllers go apeshit on some ios operation, 1726 * signalling timeout and CRC errors even on CMD0. Resetting 1727 * it on each ios seems to solve the problem. 1728 */ 1729 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1730 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1731 1732 mmiowb(); 1733 spin_unlock_irqrestore(&host->lock, flags); 1734 } 1735 1736 static int sdhci_get_cd(struct mmc_host *mmc) 1737 { 1738 struct sdhci_host *host = mmc_priv(mmc); 1739 int gpio_cd = mmc_gpio_get_cd(mmc); 1740 1741 if (host->flags & SDHCI_DEVICE_DEAD) 1742 return 0; 1743 1744 /* If nonremovable, assume that the card is always present. */ 1745 if (!mmc_card_is_removable(host->mmc)) 1746 return 1; 1747 1748 /* 1749 * Try slot gpio detect, if defined it take precedence 1750 * over build in controller functionality 1751 */ 1752 if (gpio_cd >= 0) 1753 return !!gpio_cd; 1754 1755 /* If polling, assume that the card is always present. */ 1756 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1757 return 1; 1758 1759 /* Host native card detect */ 1760 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1761 } 1762 1763 static int sdhci_check_ro(struct sdhci_host *host) 1764 { 1765 unsigned long flags; 1766 int is_readonly; 1767 1768 spin_lock_irqsave(&host->lock, flags); 1769 1770 if (host->flags & SDHCI_DEVICE_DEAD) 1771 is_readonly = 0; 1772 else if (host->ops->get_ro) 1773 is_readonly = host->ops->get_ro(host); 1774 else 1775 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1776 & SDHCI_WRITE_PROTECT); 1777 1778 spin_unlock_irqrestore(&host->lock, flags); 1779 1780 /* This quirk needs to be replaced by a callback-function later */ 1781 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1782 !is_readonly : is_readonly; 1783 } 1784 1785 #define SAMPLE_COUNT 5 1786 1787 static int sdhci_get_ro(struct mmc_host *mmc) 1788 { 1789 struct sdhci_host *host = mmc_priv(mmc); 1790 int i, ro_count; 1791 1792 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1793 return sdhci_check_ro(host); 1794 1795 ro_count = 0; 1796 for (i = 0; i < SAMPLE_COUNT; i++) { 1797 if (sdhci_check_ro(host)) { 1798 if (++ro_count > SAMPLE_COUNT / 2) 1799 return 1; 1800 } 1801 msleep(30); 1802 } 1803 return 0; 1804 } 1805 1806 static void sdhci_hw_reset(struct mmc_host *mmc) 1807 { 1808 struct sdhci_host *host = mmc_priv(mmc); 1809 1810 if (host->ops && host->ops->hw_reset) 1811 host->ops->hw_reset(host); 1812 } 1813 1814 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1815 { 1816 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1817 if (enable) 1818 host->ier |= SDHCI_INT_CARD_INT; 1819 else 1820 host->ier &= ~SDHCI_INT_CARD_INT; 1821 1822 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1823 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1824 mmiowb(); 1825 } 1826 } 1827 1828 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1829 { 1830 struct sdhci_host *host = mmc_priv(mmc); 1831 unsigned long flags; 1832 1833 if (enable) 1834 pm_runtime_get_noresume(host->mmc->parent); 1835 1836 spin_lock_irqsave(&host->lock, flags); 1837 if (enable) 1838 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1839 else 1840 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1841 1842 sdhci_enable_sdio_irq_nolock(host, enable); 1843 spin_unlock_irqrestore(&host->lock, flags); 1844 1845 if (!enable) 1846 pm_runtime_put_noidle(host->mmc->parent); 1847 } 1848 1849 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1850 struct mmc_ios *ios) 1851 { 1852 struct sdhci_host *host = mmc_priv(mmc); 1853 u16 ctrl; 1854 int ret; 1855 1856 /* 1857 * Signal Voltage Switching is only applicable for Host Controllers 1858 * v3.00 and above. 1859 */ 1860 if (host->version < SDHCI_SPEC_300) 1861 return 0; 1862 1863 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1864 1865 switch (ios->signal_voltage) { 1866 case MMC_SIGNAL_VOLTAGE_330: 1867 if (!(host->flags & SDHCI_SIGNALING_330)) 1868 return -EINVAL; 1869 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1870 ctrl &= ~SDHCI_CTRL_VDD_180; 1871 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1872 1873 if (!IS_ERR(mmc->supply.vqmmc)) { 1874 ret = mmc_regulator_set_vqmmc(mmc, ios); 1875 if (ret) { 1876 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1877 mmc_hostname(mmc)); 1878 return -EIO; 1879 } 1880 } 1881 /* Wait for 5ms */ 1882 usleep_range(5000, 5500); 1883 1884 /* 3.3V regulator output should be stable within 5 ms */ 1885 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1886 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1887 return 0; 1888 1889 pr_warn("%s: 3.3V regulator output did not became stable\n", 1890 mmc_hostname(mmc)); 1891 1892 return -EAGAIN; 1893 case MMC_SIGNAL_VOLTAGE_180: 1894 if (!(host->flags & SDHCI_SIGNALING_180)) 1895 return -EINVAL; 1896 if (!IS_ERR(mmc->supply.vqmmc)) { 1897 ret = mmc_regulator_set_vqmmc(mmc, ios); 1898 if (ret) { 1899 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1900 mmc_hostname(mmc)); 1901 return -EIO; 1902 } 1903 } 1904 1905 /* 1906 * Enable 1.8V Signal Enable in the Host Control2 1907 * register 1908 */ 1909 ctrl |= SDHCI_CTRL_VDD_180; 1910 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1911 1912 /* Some controller need to do more when switching */ 1913 if (host->ops->voltage_switch) 1914 host->ops->voltage_switch(host); 1915 1916 /* 1.8V regulator output should be stable within 5 ms */ 1917 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1918 if (ctrl & SDHCI_CTRL_VDD_180) 1919 return 0; 1920 1921 pr_warn("%s: 1.8V regulator output did not became stable\n", 1922 mmc_hostname(mmc)); 1923 1924 return -EAGAIN; 1925 case MMC_SIGNAL_VOLTAGE_120: 1926 if (!(host->flags & SDHCI_SIGNALING_120)) 1927 return -EINVAL; 1928 if (!IS_ERR(mmc->supply.vqmmc)) { 1929 ret = mmc_regulator_set_vqmmc(mmc, ios); 1930 if (ret) { 1931 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1932 mmc_hostname(mmc)); 1933 return -EIO; 1934 } 1935 } 1936 return 0; 1937 default: 1938 /* No signal voltage switch required */ 1939 return 0; 1940 } 1941 } 1942 1943 static int sdhci_card_busy(struct mmc_host *mmc) 1944 { 1945 struct sdhci_host *host = mmc_priv(mmc); 1946 u32 present_state; 1947 1948 /* Check whether DAT[0] is 0 */ 1949 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1950 1951 return !(present_state & SDHCI_DATA_0_LVL_MASK); 1952 } 1953 1954 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1955 { 1956 struct sdhci_host *host = mmc_priv(mmc); 1957 unsigned long flags; 1958 1959 spin_lock_irqsave(&host->lock, flags); 1960 host->flags |= SDHCI_HS400_TUNING; 1961 spin_unlock_irqrestore(&host->lock, flags); 1962 1963 return 0; 1964 } 1965 1966 static void sdhci_start_tuning(struct sdhci_host *host) 1967 { 1968 u16 ctrl; 1969 1970 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1971 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1972 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 1973 ctrl |= SDHCI_CTRL_TUNED_CLK; 1974 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1975 1976 /* 1977 * As per the Host Controller spec v3.00, tuning command 1978 * generates Buffer Read Ready interrupt, so enable that. 1979 * 1980 * Note: The spec clearly says that when tuning sequence 1981 * is being performed, the controller does not generate 1982 * interrupts other than Buffer Read Ready interrupt. But 1983 * to make sure we don't hit a controller bug, we _only_ 1984 * enable Buffer Read Ready interrupt here. 1985 */ 1986 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1987 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1988 } 1989 1990 static void sdhci_end_tuning(struct sdhci_host *host) 1991 { 1992 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1993 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1994 } 1995 1996 static void sdhci_reset_tuning(struct sdhci_host *host) 1997 { 1998 u16 ctrl; 1999 2000 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2001 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2002 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2003 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2004 } 2005 2006 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode, 2007 unsigned long flags) 2008 { 2009 sdhci_reset_tuning(host); 2010 2011 sdhci_do_reset(host, SDHCI_RESET_CMD); 2012 sdhci_do_reset(host, SDHCI_RESET_DATA); 2013 2014 sdhci_end_tuning(host); 2015 2016 spin_unlock_irqrestore(&host->lock, flags); 2017 mmc_abort_tuning(host->mmc, opcode); 2018 spin_lock_irqsave(&host->lock, flags); 2019 } 2020 2021 /* 2022 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI 2023 * tuning command does not have a data payload (or rather the hardware does it 2024 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command 2025 * interrupt setup is different to other commands and there is no timeout 2026 * interrupt so special handling is needed. 2027 */ 2028 static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode, 2029 unsigned long flags) 2030 { 2031 struct mmc_host *mmc = host->mmc; 2032 struct mmc_command cmd = {}; 2033 struct mmc_request mrq = {}; 2034 2035 cmd.opcode = opcode; 2036 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2037 cmd.mrq = &mrq; 2038 2039 mrq.cmd = &cmd; 2040 /* 2041 * In response to CMD19, the card sends 64 bytes of tuning 2042 * block to the Host Controller. So we set the block size 2043 * to 64 here. 2044 */ 2045 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 && 2046 mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2047 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE); 2048 else 2049 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 2050 2051 /* 2052 * The tuning block is sent by the card to the host controller. 2053 * So we set the TRNS_READ bit in the Transfer Mode register. 2054 * This also takes care of setting DMA Enable and Multi Block 2055 * Select in the same register to 0. 2056 */ 2057 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2058 2059 sdhci_send_command(host, &cmd); 2060 2061 host->cmd = NULL; 2062 2063 sdhci_del_timer(host, &mrq); 2064 2065 host->tuning_done = 0; 2066 2067 spin_unlock_irqrestore(&host->lock, flags); 2068 2069 /* Wait for Buffer Read Ready interrupt */ 2070 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), 2071 msecs_to_jiffies(50)); 2072 2073 spin_lock_irqsave(&host->lock, flags); 2074 } 2075 2076 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode, 2077 unsigned long flags) 2078 { 2079 int i; 2080 2081 /* 2082 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 2083 * of loops reaches 40 times. 2084 */ 2085 for (i = 0; i < MAX_TUNING_LOOP; i++) { 2086 u16 ctrl; 2087 2088 sdhci_send_tuning(host, opcode, flags); 2089 2090 if (!host->tuning_done) { 2091 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 2092 mmc_hostname(host->mmc)); 2093 sdhci_abort_tuning(host, opcode, flags); 2094 return; 2095 } 2096 2097 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2098 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 2099 if (ctrl & SDHCI_CTRL_TUNED_CLK) 2100 return; /* Success! */ 2101 break; 2102 } 2103 2104 /* eMMC spec does not require a delay between tuning cycles */ 2105 if (opcode == MMC_SEND_TUNING_BLOCK) 2106 mdelay(1); 2107 } 2108 2109 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 2110 mmc_hostname(host->mmc)); 2111 sdhci_reset_tuning(host); 2112 } 2113 2114 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 2115 { 2116 struct sdhci_host *host = mmc_priv(mmc); 2117 int err = 0; 2118 unsigned long flags; 2119 unsigned int tuning_count = 0; 2120 bool hs400_tuning; 2121 2122 spin_lock_irqsave(&host->lock, flags); 2123 2124 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 2125 2126 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 2127 tuning_count = host->tuning_count; 2128 2129 /* 2130 * The Host Controller needs tuning in case of SDR104 and DDR50 2131 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 2132 * the Capabilities register. 2133 * If the Host Controller supports the HS200 mode then the 2134 * tuning function has to be executed. 2135 */ 2136 switch (host->timing) { 2137 /* HS400 tuning is done in HS200 mode */ 2138 case MMC_TIMING_MMC_HS400: 2139 err = -EINVAL; 2140 goto out_unlock; 2141 2142 case MMC_TIMING_MMC_HS200: 2143 /* 2144 * Periodic re-tuning for HS400 is not expected to be needed, so 2145 * disable it here. 2146 */ 2147 if (hs400_tuning) 2148 tuning_count = 0; 2149 break; 2150 2151 case MMC_TIMING_UHS_SDR104: 2152 case MMC_TIMING_UHS_DDR50: 2153 break; 2154 2155 case MMC_TIMING_UHS_SDR50: 2156 if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 2157 break; 2158 /* FALLTHROUGH */ 2159 2160 default: 2161 goto out_unlock; 2162 } 2163 2164 if (host->ops->platform_execute_tuning) { 2165 spin_unlock_irqrestore(&host->lock, flags); 2166 err = host->ops->platform_execute_tuning(host, opcode); 2167 spin_lock_irqsave(&host->lock, flags); 2168 goto out_unlock; 2169 } 2170 2171 host->mmc->retune_period = tuning_count; 2172 2173 sdhci_start_tuning(host); 2174 2175 __sdhci_execute_tuning(host, opcode, flags); 2176 2177 sdhci_end_tuning(host); 2178 out_unlock: 2179 host->flags &= ~SDHCI_HS400_TUNING; 2180 spin_unlock_irqrestore(&host->lock, flags); 2181 2182 return err; 2183 } 2184 EXPORT_SYMBOL_GPL(sdhci_execute_tuning); 2185 2186 static int sdhci_select_drive_strength(struct mmc_card *card, 2187 unsigned int max_dtr, int host_drv, 2188 int card_drv, int *drv_type) 2189 { 2190 struct sdhci_host *host = mmc_priv(card->host); 2191 2192 if (!host->ops->select_drive_strength) 2193 return 0; 2194 2195 return host->ops->select_drive_strength(host, card, max_dtr, host_drv, 2196 card_drv, drv_type); 2197 } 2198 2199 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2200 { 2201 /* Host Controller v3.00 defines preset value registers */ 2202 if (host->version < SDHCI_SPEC_300) 2203 return; 2204 2205 /* 2206 * We only enable or disable Preset Value if they are not already 2207 * enabled or disabled respectively. Otherwise, we bail out. 2208 */ 2209 if (host->preset_enabled != enable) { 2210 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2211 2212 if (enable) 2213 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2214 else 2215 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2216 2217 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2218 2219 if (enable) 2220 host->flags |= SDHCI_PV_ENABLED; 2221 else 2222 host->flags &= ~SDHCI_PV_ENABLED; 2223 2224 host->preset_enabled = enable; 2225 } 2226 } 2227 2228 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2229 int err) 2230 { 2231 struct sdhci_host *host = mmc_priv(mmc); 2232 struct mmc_data *data = mrq->data; 2233 2234 if (data->host_cookie != COOKIE_UNMAPPED) 2235 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2236 data->flags & MMC_DATA_WRITE ? 2237 DMA_TO_DEVICE : DMA_FROM_DEVICE); 2238 2239 data->host_cookie = COOKIE_UNMAPPED; 2240 } 2241 2242 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 2243 { 2244 struct sdhci_host *host = mmc_priv(mmc); 2245 2246 mrq->data->host_cookie = COOKIE_UNMAPPED; 2247 2248 if (host->flags & SDHCI_REQ_USE_DMA) 2249 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2250 } 2251 2252 static inline bool sdhci_has_requests(struct sdhci_host *host) 2253 { 2254 return host->cmd || host->data_cmd; 2255 } 2256 2257 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 2258 { 2259 if (host->data_cmd) { 2260 host->data_cmd->error = err; 2261 sdhci_finish_mrq(host, host->data_cmd->mrq); 2262 } 2263 2264 if (host->cmd) { 2265 host->cmd->error = err; 2266 sdhci_finish_mrq(host, host->cmd->mrq); 2267 } 2268 } 2269 2270 static void sdhci_card_event(struct mmc_host *mmc) 2271 { 2272 struct sdhci_host *host = mmc_priv(mmc); 2273 unsigned long flags; 2274 int present; 2275 2276 /* First check if client has provided their own card event */ 2277 if (host->ops->card_event) 2278 host->ops->card_event(host); 2279 2280 present = mmc->ops->get_cd(mmc); 2281 2282 spin_lock_irqsave(&host->lock, flags); 2283 2284 /* Check sdhci_has_requests() first in case we are runtime suspended */ 2285 if (sdhci_has_requests(host) && !present) { 2286 pr_err("%s: Card removed during transfer!\n", 2287 mmc_hostname(host->mmc)); 2288 pr_err("%s: Resetting controller.\n", 2289 mmc_hostname(host->mmc)); 2290 2291 sdhci_do_reset(host, SDHCI_RESET_CMD); 2292 sdhci_do_reset(host, SDHCI_RESET_DATA); 2293 2294 sdhci_error_out_mrqs(host, -ENOMEDIUM); 2295 } 2296 2297 spin_unlock_irqrestore(&host->lock, flags); 2298 } 2299 2300 static const struct mmc_host_ops sdhci_ops = { 2301 .request = sdhci_request, 2302 .post_req = sdhci_post_req, 2303 .pre_req = sdhci_pre_req, 2304 .set_ios = sdhci_set_ios, 2305 .get_cd = sdhci_get_cd, 2306 .get_ro = sdhci_get_ro, 2307 .hw_reset = sdhci_hw_reset, 2308 .enable_sdio_irq = sdhci_enable_sdio_irq, 2309 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2310 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2311 .execute_tuning = sdhci_execute_tuning, 2312 .select_drive_strength = sdhci_select_drive_strength, 2313 .card_event = sdhci_card_event, 2314 .card_busy = sdhci_card_busy, 2315 }; 2316 2317 /*****************************************************************************\ 2318 * * 2319 * Tasklets * 2320 * * 2321 \*****************************************************************************/ 2322 2323 static bool sdhci_request_done(struct sdhci_host *host) 2324 { 2325 unsigned long flags; 2326 struct mmc_request *mrq; 2327 int i; 2328 2329 spin_lock_irqsave(&host->lock, flags); 2330 2331 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 2332 mrq = host->mrqs_done[i]; 2333 if (mrq) 2334 break; 2335 } 2336 2337 if (!mrq) { 2338 spin_unlock_irqrestore(&host->lock, flags); 2339 return true; 2340 } 2341 2342 sdhci_del_timer(host, mrq); 2343 2344 /* 2345 * Always unmap the data buffers if they were mapped by 2346 * sdhci_prepare_data() whenever we finish with a request. 2347 * This avoids leaking DMA mappings on error. 2348 */ 2349 if (host->flags & SDHCI_REQ_USE_DMA) { 2350 struct mmc_data *data = mrq->data; 2351 2352 if (data && data->host_cookie == COOKIE_MAPPED) { 2353 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2354 (data->flags & MMC_DATA_READ) ? 2355 DMA_FROM_DEVICE : DMA_TO_DEVICE); 2356 data->host_cookie = COOKIE_UNMAPPED; 2357 } 2358 } 2359 2360 /* 2361 * The controller needs a reset of internal state machines 2362 * upon error conditions. 2363 */ 2364 if (sdhci_needs_reset(host, mrq)) { 2365 /* 2366 * Do not finish until command and data lines are available for 2367 * reset. Note there can only be one other mrq, so it cannot 2368 * also be in mrqs_done, otherwise host->cmd and host->data_cmd 2369 * would both be null. 2370 */ 2371 if (host->cmd || host->data_cmd) { 2372 spin_unlock_irqrestore(&host->lock, flags); 2373 return true; 2374 } 2375 2376 /* Some controllers need this kick or reset won't work here */ 2377 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2378 /* This is to force an update */ 2379 host->ops->set_clock(host, host->clock); 2380 2381 /* Spec says we should do both at the same time, but Ricoh 2382 controllers do not like that. */ 2383 sdhci_do_reset(host, SDHCI_RESET_CMD); 2384 sdhci_do_reset(host, SDHCI_RESET_DATA); 2385 2386 host->pending_reset = false; 2387 } 2388 2389 if (!sdhci_has_requests(host)) 2390 sdhci_led_deactivate(host); 2391 2392 host->mrqs_done[i] = NULL; 2393 2394 mmiowb(); 2395 spin_unlock_irqrestore(&host->lock, flags); 2396 2397 mmc_request_done(host->mmc, mrq); 2398 2399 return false; 2400 } 2401 2402 static void sdhci_tasklet_finish(unsigned long param) 2403 { 2404 struct sdhci_host *host = (struct sdhci_host *)param; 2405 2406 while (!sdhci_request_done(host)) 2407 ; 2408 } 2409 2410 static void sdhci_timeout_timer(unsigned long data) 2411 { 2412 struct sdhci_host *host; 2413 unsigned long flags; 2414 2415 host = (struct sdhci_host*)data; 2416 2417 spin_lock_irqsave(&host->lock, flags); 2418 2419 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2420 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2421 mmc_hostname(host->mmc)); 2422 sdhci_dumpregs(host); 2423 2424 host->cmd->error = -ETIMEDOUT; 2425 sdhci_finish_mrq(host, host->cmd->mrq); 2426 } 2427 2428 mmiowb(); 2429 spin_unlock_irqrestore(&host->lock, flags); 2430 } 2431 2432 static void sdhci_timeout_data_timer(unsigned long data) 2433 { 2434 struct sdhci_host *host; 2435 unsigned long flags; 2436 2437 host = (struct sdhci_host *)data; 2438 2439 spin_lock_irqsave(&host->lock, flags); 2440 2441 if (host->data || host->data_cmd || 2442 (host->cmd && sdhci_data_line_cmd(host->cmd))) { 2443 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2444 mmc_hostname(host->mmc)); 2445 sdhci_dumpregs(host); 2446 2447 if (host->data) { 2448 host->data->error = -ETIMEDOUT; 2449 sdhci_finish_data(host); 2450 } else if (host->data_cmd) { 2451 host->data_cmd->error = -ETIMEDOUT; 2452 sdhci_finish_mrq(host, host->data_cmd->mrq); 2453 } else { 2454 host->cmd->error = -ETIMEDOUT; 2455 sdhci_finish_mrq(host, host->cmd->mrq); 2456 } 2457 } 2458 2459 mmiowb(); 2460 spin_unlock_irqrestore(&host->lock, flags); 2461 } 2462 2463 /*****************************************************************************\ 2464 * * 2465 * Interrupt handling * 2466 * * 2467 \*****************************************************************************/ 2468 2469 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2470 { 2471 if (!host->cmd) { 2472 /* 2473 * SDHCI recovers from errors by resetting the cmd and data 2474 * circuits. Until that is done, there very well might be more 2475 * interrupts, so ignore them in that case. 2476 */ 2477 if (host->pending_reset) 2478 return; 2479 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2480 mmc_hostname(host->mmc), (unsigned)intmask); 2481 sdhci_dumpregs(host); 2482 return; 2483 } 2484 2485 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2486 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 2487 if (intmask & SDHCI_INT_TIMEOUT) 2488 host->cmd->error = -ETIMEDOUT; 2489 else 2490 host->cmd->error = -EILSEQ; 2491 2492 /* 2493 * If this command initiates a data phase and a response 2494 * CRC error is signalled, the card can start transferring 2495 * data - the card may have received the command without 2496 * error. We must not terminate the mmc_request early. 2497 * 2498 * If the card did not receive the command or returned an 2499 * error which prevented it sending data, the data phase 2500 * will time out. 2501 */ 2502 if (host->cmd->data && 2503 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 2504 SDHCI_INT_CRC) { 2505 host->cmd = NULL; 2506 return; 2507 } 2508 2509 sdhci_finish_mrq(host, host->cmd->mrq); 2510 return; 2511 } 2512 2513 if (intmask & SDHCI_INT_RESPONSE) 2514 sdhci_finish_command(host); 2515 } 2516 2517 #ifdef CONFIG_MMC_DEBUG 2518 static void sdhci_adma_show_error(struct sdhci_host *host) 2519 { 2520 const char *name = mmc_hostname(host->mmc); 2521 void *desc = host->adma_table; 2522 2523 sdhci_dumpregs(host); 2524 2525 while (true) { 2526 struct sdhci_adma2_64_desc *dma_desc = desc; 2527 2528 if (host->flags & SDHCI_USE_64_BIT_DMA) 2529 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2530 name, desc, le32_to_cpu(dma_desc->addr_hi), 2531 le32_to_cpu(dma_desc->addr_lo), 2532 le16_to_cpu(dma_desc->len), 2533 le16_to_cpu(dma_desc->cmd)); 2534 else 2535 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2536 name, desc, le32_to_cpu(dma_desc->addr_lo), 2537 le16_to_cpu(dma_desc->len), 2538 le16_to_cpu(dma_desc->cmd)); 2539 2540 desc += host->desc_sz; 2541 2542 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2543 break; 2544 } 2545 } 2546 #else 2547 static void sdhci_adma_show_error(struct sdhci_host *host) { } 2548 #endif 2549 2550 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2551 { 2552 u32 command; 2553 2554 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2555 if (intmask & SDHCI_INT_DATA_AVAIL) { 2556 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2557 if (command == MMC_SEND_TUNING_BLOCK || 2558 command == MMC_SEND_TUNING_BLOCK_HS200) { 2559 host->tuning_done = 1; 2560 wake_up(&host->buf_ready_int); 2561 return; 2562 } 2563 } 2564 2565 if (!host->data) { 2566 struct mmc_command *data_cmd = host->data_cmd; 2567 2568 /* 2569 * The "data complete" interrupt is also used to 2570 * indicate that a busy state has ended. See comment 2571 * above in sdhci_cmd_irq(). 2572 */ 2573 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 2574 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2575 host->data_cmd = NULL; 2576 data_cmd->error = -ETIMEDOUT; 2577 sdhci_finish_mrq(host, data_cmd->mrq); 2578 return; 2579 } 2580 if (intmask & SDHCI_INT_DATA_END) { 2581 host->data_cmd = NULL; 2582 /* 2583 * Some cards handle busy-end interrupt 2584 * before the command completed, so make 2585 * sure we do things in the proper order. 2586 */ 2587 if (host->cmd == data_cmd) 2588 return; 2589 2590 sdhci_finish_mrq(host, data_cmd->mrq); 2591 return; 2592 } 2593 } 2594 2595 /* 2596 * SDHCI recovers from errors by resetting the cmd and data 2597 * circuits. Until that is done, there very well might be more 2598 * interrupts, so ignore them in that case. 2599 */ 2600 if (host->pending_reset) 2601 return; 2602 2603 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2604 mmc_hostname(host->mmc), (unsigned)intmask); 2605 sdhci_dumpregs(host); 2606 2607 return; 2608 } 2609 2610 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2611 host->data->error = -ETIMEDOUT; 2612 else if (intmask & SDHCI_INT_DATA_END_BIT) 2613 host->data->error = -EILSEQ; 2614 else if ((intmask & SDHCI_INT_DATA_CRC) && 2615 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2616 != MMC_BUS_TEST_R) 2617 host->data->error = -EILSEQ; 2618 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2619 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2620 sdhci_adma_show_error(host); 2621 host->data->error = -EIO; 2622 if (host->ops->adma_workaround) 2623 host->ops->adma_workaround(host, intmask); 2624 } 2625 2626 if (host->data->error) 2627 sdhci_finish_data(host); 2628 else { 2629 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2630 sdhci_transfer_pio(host); 2631 2632 /* 2633 * We currently don't do anything fancy with DMA 2634 * boundaries, but as we can't disable the feature 2635 * we need to at least restart the transfer. 2636 * 2637 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2638 * should return a valid address to continue from, but as 2639 * some controllers are faulty, don't trust them. 2640 */ 2641 if (intmask & SDHCI_INT_DMA_END) { 2642 u32 dmastart, dmanow; 2643 dmastart = sg_dma_address(host->data->sg); 2644 dmanow = dmastart + host->data->bytes_xfered; 2645 /* 2646 * Force update to the next DMA block boundary. 2647 */ 2648 dmanow = (dmanow & 2649 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2650 SDHCI_DEFAULT_BOUNDARY_SIZE; 2651 host->data->bytes_xfered = dmanow - dmastart; 2652 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2653 " next 0x%08x\n", 2654 mmc_hostname(host->mmc), dmastart, 2655 host->data->bytes_xfered, dmanow); 2656 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2657 } 2658 2659 if (intmask & SDHCI_INT_DATA_END) { 2660 if (host->cmd == host->data_cmd) { 2661 /* 2662 * Data managed to finish before the 2663 * command completed. Make sure we do 2664 * things in the proper order. 2665 */ 2666 host->data_early = 1; 2667 } else { 2668 sdhci_finish_data(host); 2669 } 2670 } 2671 } 2672 } 2673 2674 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2675 { 2676 irqreturn_t result = IRQ_NONE; 2677 struct sdhci_host *host = dev_id; 2678 u32 intmask, mask, unexpected = 0; 2679 int max_loops = 16; 2680 2681 spin_lock(&host->lock); 2682 2683 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2684 spin_unlock(&host->lock); 2685 return IRQ_NONE; 2686 } 2687 2688 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2689 if (!intmask || intmask == 0xffffffff) { 2690 result = IRQ_NONE; 2691 goto out; 2692 } 2693 2694 do { 2695 /* Clear selected interrupts. */ 2696 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2697 SDHCI_INT_BUS_POWER); 2698 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2699 2700 DBG("*** %s got interrupt: 0x%08x\n", 2701 mmc_hostname(host->mmc), intmask); 2702 2703 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2704 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2705 SDHCI_CARD_PRESENT; 2706 2707 /* 2708 * There is a observation on i.mx esdhc. INSERT 2709 * bit will be immediately set again when it gets 2710 * cleared, if a card is inserted. We have to mask 2711 * the irq to prevent interrupt storm which will 2712 * freeze the system. And the REMOVE gets the 2713 * same situation. 2714 * 2715 * More testing are needed here to ensure it works 2716 * for other platforms though. 2717 */ 2718 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2719 SDHCI_INT_CARD_REMOVE); 2720 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2721 SDHCI_INT_CARD_INSERT; 2722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2724 2725 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2726 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2727 2728 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2729 SDHCI_INT_CARD_REMOVE); 2730 result = IRQ_WAKE_THREAD; 2731 } 2732 2733 if (intmask & SDHCI_INT_CMD_MASK) 2734 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2735 2736 if (intmask & SDHCI_INT_DATA_MASK) 2737 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2738 2739 if (intmask & SDHCI_INT_BUS_POWER) 2740 pr_err("%s: Card is consuming too much power!\n", 2741 mmc_hostname(host->mmc)); 2742 2743 if (intmask & SDHCI_INT_RETUNE) 2744 mmc_retune_needed(host->mmc); 2745 2746 if ((intmask & SDHCI_INT_CARD_INT) && 2747 (host->ier & SDHCI_INT_CARD_INT)) { 2748 sdhci_enable_sdio_irq_nolock(host, false); 2749 host->thread_isr |= SDHCI_INT_CARD_INT; 2750 result = IRQ_WAKE_THREAD; 2751 } 2752 2753 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2754 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2755 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2756 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 2757 2758 if (intmask) { 2759 unexpected |= intmask; 2760 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2761 } 2762 2763 if (result == IRQ_NONE) 2764 result = IRQ_HANDLED; 2765 2766 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2767 } while (intmask && --max_loops); 2768 out: 2769 spin_unlock(&host->lock); 2770 2771 if (unexpected) { 2772 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2773 mmc_hostname(host->mmc), unexpected); 2774 sdhci_dumpregs(host); 2775 } 2776 2777 return result; 2778 } 2779 2780 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2781 { 2782 struct sdhci_host *host = dev_id; 2783 unsigned long flags; 2784 u32 isr; 2785 2786 spin_lock_irqsave(&host->lock, flags); 2787 isr = host->thread_isr; 2788 host->thread_isr = 0; 2789 spin_unlock_irqrestore(&host->lock, flags); 2790 2791 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2792 struct mmc_host *mmc = host->mmc; 2793 2794 mmc->ops->card_event(mmc); 2795 mmc_detect_change(mmc, msecs_to_jiffies(200)); 2796 } 2797 2798 if (isr & SDHCI_INT_CARD_INT) { 2799 sdio_run_irqs(host->mmc); 2800 2801 spin_lock_irqsave(&host->lock, flags); 2802 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2803 sdhci_enable_sdio_irq_nolock(host, true); 2804 spin_unlock_irqrestore(&host->lock, flags); 2805 } 2806 2807 return isr ? IRQ_HANDLED : IRQ_NONE; 2808 } 2809 2810 /*****************************************************************************\ 2811 * * 2812 * Suspend/resume * 2813 * * 2814 \*****************************************************************************/ 2815 2816 #ifdef CONFIG_PM 2817 /* 2818 * To enable wakeup events, the corresponding events have to be enabled in 2819 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 2820 * Table' in the SD Host Controller Standard Specification. 2821 * It is useless to restore SDHCI_INT_ENABLE state in 2822 * sdhci_disable_irq_wakeups() since it will be set by 2823 * sdhci_enable_card_detection() or sdhci_init(). 2824 */ 2825 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2826 { 2827 u8 val; 2828 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2829 | SDHCI_WAKE_ON_INT; 2830 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2831 SDHCI_INT_CARD_INT; 2832 2833 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2834 val |= mask ; 2835 /* Avoid fake wake up */ 2836 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) { 2837 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2838 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2839 } 2840 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2841 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 2842 } 2843 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2844 2845 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2846 { 2847 u8 val; 2848 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2849 | SDHCI_WAKE_ON_INT; 2850 2851 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2852 val &= ~mask; 2853 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2854 } 2855 2856 int sdhci_suspend_host(struct sdhci_host *host) 2857 { 2858 sdhci_disable_card_detection(host); 2859 2860 mmc_retune_timer_stop(host->mmc); 2861 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2862 mmc_retune_needed(host->mmc); 2863 2864 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2865 host->ier = 0; 2866 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2867 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2868 free_irq(host->irq, host); 2869 } else { 2870 sdhci_enable_irq_wakeups(host); 2871 enable_irq_wake(host->irq); 2872 } 2873 return 0; 2874 } 2875 2876 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2877 2878 int sdhci_resume_host(struct sdhci_host *host) 2879 { 2880 struct mmc_host *mmc = host->mmc; 2881 int ret = 0; 2882 2883 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2884 if (host->ops->enable_dma) 2885 host->ops->enable_dma(host); 2886 } 2887 2888 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2889 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2890 /* Card keeps power but host controller does not */ 2891 sdhci_init(host, 0); 2892 host->pwr = 0; 2893 host->clock = 0; 2894 mmc->ops->set_ios(mmc, &mmc->ios); 2895 } else { 2896 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2897 mmiowb(); 2898 } 2899 2900 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2901 ret = request_threaded_irq(host->irq, sdhci_irq, 2902 sdhci_thread_irq, IRQF_SHARED, 2903 mmc_hostname(host->mmc), host); 2904 if (ret) 2905 return ret; 2906 } else { 2907 sdhci_disable_irq_wakeups(host); 2908 disable_irq_wake(host->irq); 2909 } 2910 2911 sdhci_enable_card_detection(host); 2912 2913 return ret; 2914 } 2915 2916 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2917 2918 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2919 { 2920 unsigned long flags; 2921 2922 mmc_retune_timer_stop(host->mmc); 2923 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2924 mmc_retune_needed(host->mmc); 2925 2926 spin_lock_irqsave(&host->lock, flags); 2927 host->ier &= SDHCI_INT_CARD_INT; 2928 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2929 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2930 spin_unlock_irqrestore(&host->lock, flags); 2931 2932 synchronize_hardirq(host->irq); 2933 2934 spin_lock_irqsave(&host->lock, flags); 2935 host->runtime_suspended = true; 2936 spin_unlock_irqrestore(&host->lock, flags); 2937 2938 return 0; 2939 } 2940 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2941 2942 int sdhci_runtime_resume_host(struct sdhci_host *host) 2943 { 2944 struct mmc_host *mmc = host->mmc; 2945 unsigned long flags; 2946 int host_flags = host->flags; 2947 2948 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2949 if (host->ops->enable_dma) 2950 host->ops->enable_dma(host); 2951 } 2952 2953 sdhci_init(host, 0); 2954 2955 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED) { 2956 /* Force clock and power re-program */ 2957 host->pwr = 0; 2958 host->clock = 0; 2959 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 2960 mmc->ops->set_ios(mmc, &mmc->ios); 2961 2962 if ((host_flags & SDHCI_PV_ENABLED) && 2963 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2964 spin_lock_irqsave(&host->lock, flags); 2965 sdhci_enable_preset_value(host, true); 2966 spin_unlock_irqrestore(&host->lock, flags); 2967 } 2968 2969 if ((mmc->caps2 & MMC_CAP2_HS400_ES) && 2970 mmc->ops->hs400_enhanced_strobe) 2971 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); 2972 } 2973 2974 spin_lock_irqsave(&host->lock, flags); 2975 2976 host->runtime_suspended = false; 2977 2978 /* Enable SDIO IRQ */ 2979 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2980 sdhci_enable_sdio_irq_nolock(host, true); 2981 2982 /* Enable Card Detection */ 2983 sdhci_enable_card_detection(host); 2984 2985 spin_unlock_irqrestore(&host->lock, flags); 2986 2987 return 0; 2988 } 2989 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2990 2991 #endif /* CONFIG_PM */ 2992 2993 /*****************************************************************************\ 2994 * * 2995 * Device allocation/registration * 2996 * * 2997 \*****************************************************************************/ 2998 2999 struct sdhci_host *sdhci_alloc_host(struct device *dev, 3000 size_t priv_size) 3001 { 3002 struct mmc_host *mmc; 3003 struct sdhci_host *host; 3004 3005 WARN_ON(dev == NULL); 3006 3007 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 3008 if (!mmc) 3009 return ERR_PTR(-ENOMEM); 3010 3011 host = mmc_priv(mmc); 3012 host->mmc = mmc; 3013 host->mmc_host_ops = sdhci_ops; 3014 mmc->ops = &host->mmc_host_ops; 3015 3016 host->flags = SDHCI_SIGNALING_330; 3017 3018 return host; 3019 } 3020 3021 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 3022 3023 static int sdhci_set_dma_mask(struct sdhci_host *host) 3024 { 3025 struct mmc_host *mmc = host->mmc; 3026 struct device *dev = mmc_dev(mmc); 3027 int ret = -EINVAL; 3028 3029 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 3030 host->flags &= ~SDHCI_USE_64_BIT_DMA; 3031 3032 /* Try 64-bit mask if hardware is capable of it */ 3033 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3034 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 3035 if (ret) { 3036 pr_warn("%s: Failed to set 64-bit DMA mask.\n", 3037 mmc_hostname(mmc)); 3038 host->flags &= ~SDHCI_USE_64_BIT_DMA; 3039 } 3040 } 3041 3042 /* 32-bit mask as default & fallback */ 3043 if (ret) { 3044 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 3045 if (ret) 3046 pr_warn("%s: Failed to set 32-bit DMA mask.\n", 3047 mmc_hostname(mmc)); 3048 } 3049 3050 return ret; 3051 } 3052 3053 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 3054 { 3055 u16 v; 3056 u64 dt_caps_mask = 0; 3057 u64 dt_caps = 0; 3058 3059 if (host->read_caps) 3060 return; 3061 3062 host->read_caps = true; 3063 3064 if (debug_quirks) 3065 host->quirks = debug_quirks; 3066 3067 if (debug_quirks2) 3068 host->quirks2 = debug_quirks2; 3069 3070 sdhci_do_reset(host, SDHCI_RESET_ALL); 3071 3072 of_property_read_u64(mmc_dev(host->mmc)->of_node, 3073 "sdhci-caps-mask", &dt_caps_mask); 3074 of_property_read_u64(mmc_dev(host->mmc)->of_node, 3075 "sdhci-caps", &dt_caps); 3076 3077 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 3078 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 3079 3080 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 3081 return; 3082 3083 if (caps) { 3084 host->caps = *caps; 3085 } else { 3086 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 3087 host->caps &= ~lower_32_bits(dt_caps_mask); 3088 host->caps |= lower_32_bits(dt_caps); 3089 } 3090 3091 if (host->version < SDHCI_SPEC_300) 3092 return; 3093 3094 if (caps1) { 3095 host->caps1 = *caps1; 3096 } else { 3097 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 3098 host->caps1 &= ~upper_32_bits(dt_caps_mask); 3099 host->caps1 |= upper_32_bits(dt_caps); 3100 } 3101 } 3102 EXPORT_SYMBOL_GPL(__sdhci_read_caps); 3103 3104 int sdhci_setup_host(struct sdhci_host *host) 3105 { 3106 struct mmc_host *mmc; 3107 u32 max_current_caps; 3108 unsigned int ocr_avail; 3109 unsigned int override_timeout_clk; 3110 u32 max_clk; 3111 int ret; 3112 3113 WARN_ON(host == NULL); 3114 if (host == NULL) 3115 return -EINVAL; 3116 3117 mmc = host->mmc; 3118 3119 /* 3120 * If there are external regulators, get them. Note this must be done 3121 * early before resetting the host and reading the capabilities so that 3122 * the host can take the appropriate action if regulators are not 3123 * available. 3124 */ 3125 ret = mmc_regulator_get_supply(mmc); 3126 if (ret == -EPROBE_DEFER) 3127 return ret; 3128 3129 sdhci_read_caps(host); 3130 3131 override_timeout_clk = host->timeout_clk; 3132 3133 if (host->version > SDHCI_SPEC_300) { 3134 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 3135 mmc_hostname(mmc), host->version); 3136 } 3137 3138 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3139 host->flags |= SDHCI_USE_SDMA; 3140 else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3141 DBG("Controller doesn't have SDMA capability\n"); 3142 else 3143 host->flags |= SDHCI_USE_SDMA; 3144 3145 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3146 (host->flags & SDHCI_USE_SDMA)) { 3147 DBG("Disabling DMA as it is marked broken\n"); 3148 host->flags &= ~SDHCI_USE_SDMA; 3149 } 3150 3151 if ((host->version >= SDHCI_SPEC_200) && 3152 (host->caps & SDHCI_CAN_DO_ADMA2)) 3153 host->flags |= SDHCI_USE_ADMA; 3154 3155 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 3156 (host->flags & SDHCI_USE_ADMA)) { 3157 DBG("Disabling ADMA as it is marked broken\n"); 3158 host->flags &= ~SDHCI_USE_ADMA; 3159 } 3160 3161 /* 3162 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 3163 * and *must* do 64-bit DMA. A driver has the opportunity to change 3164 * that during the first call to ->enable_dma(). Similarly 3165 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3166 * implement. 3167 */ 3168 if (host->caps & SDHCI_CAN_64BIT) 3169 host->flags |= SDHCI_USE_64_BIT_DMA; 3170 3171 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3172 ret = sdhci_set_dma_mask(host); 3173 3174 if (!ret && host->ops->enable_dma) 3175 ret = host->ops->enable_dma(host); 3176 3177 if (ret) { 3178 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 3179 mmc_hostname(mmc)); 3180 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 3181 3182 ret = 0; 3183 } 3184 } 3185 3186 /* SDMA does not support 64-bit DMA */ 3187 if (host->flags & SDHCI_USE_64_BIT_DMA) 3188 host->flags &= ~SDHCI_USE_SDMA; 3189 3190 if (host->flags & SDHCI_USE_ADMA) { 3191 dma_addr_t dma; 3192 void *buf; 3193 3194 /* 3195 * The DMA descriptor table size is calculated as the maximum 3196 * number of segments times 2, to allow for an alignment 3197 * descriptor for each segment, plus 1 for a nop end descriptor, 3198 * all multipled by the descriptor size. 3199 */ 3200 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3201 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3202 SDHCI_ADMA2_64_DESC_SZ; 3203 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 3204 } else { 3205 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3206 SDHCI_ADMA2_32_DESC_SZ; 3207 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 3208 } 3209 3210 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 3211 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + 3212 host->adma_table_sz, &dma, GFP_KERNEL); 3213 if (!buf) { 3214 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 3215 mmc_hostname(mmc)); 3216 host->flags &= ~SDHCI_USE_ADMA; 3217 } else if ((dma + host->align_buffer_sz) & 3218 (SDHCI_ADMA2_DESC_ALIGN - 1)) { 3219 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 3220 mmc_hostname(mmc)); 3221 host->flags &= ~SDHCI_USE_ADMA; 3222 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3223 host->adma_table_sz, buf, dma); 3224 } else { 3225 host->align_buffer = buf; 3226 host->align_addr = dma; 3227 3228 host->adma_table = buf + host->align_buffer_sz; 3229 host->adma_addr = dma + host->align_buffer_sz; 3230 } 3231 } 3232 3233 /* 3234 * If we use DMA, then it's up to the caller to set the DMA 3235 * mask, but PIO does not need the hw shim so we set a new 3236 * mask here in that case. 3237 */ 3238 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 3239 host->dma_mask = DMA_BIT_MASK(64); 3240 mmc_dev(mmc)->dma_mask = &host->dma_mask; 3241 } 3242 3243 if (host->version >= SDHCI_SPEC_300) 3244 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 3245 >> SDHCI_CLOCK_BASE_SHIFT; 3246 else 3247 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 3248 >> SDHCI_CLOCK_BASE_SHIFT; 3249 3250 host->max_clk *= 1000000; 3251 if (host->max_clk == 0 || host->quirks & 3252 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 3253 if (!host->ops->get_max_clock) { 3254 pr_err("%s: Hardware doesn't specify base clock frequency.\n", 3255 mmc_hostname(mmc)); 3256 ret = -ENODEV; 3257 goto undma; 3258 } 3259 host->max_clk = host->ops->get_max_clock(host); 3260 } 3261 3262 /* 3263 * In case of Host Controller v3.00, find out whether clock 3264 * multiplier is supported. 3265 */ 3266 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 3267 SDHCI_CLOCK_MUL_SHIFT; 3268 3269 /* 3270 * In case the value in Clock Multiplier is 0, then programmable 3271 * clock mode is not supported, otherwise the actual clock 3272 * multiplier is one more than the value of Clock Multiplier 3273 * in the Capabilities Register. 3274 */ 3275 if (host->clk_mul) 3276 host->clk_mul += 1; 3277 3278 /* 3279 * Set host parameters. 3280 */ 3281 max_clk = host->max_clk; 3282 3283 if (host->ops->get_min_clock) 3284 mmc->f_min = host->ops->get_min_clock(host); 3285 else if (host->version >= SDHCI_SPEC_300) { 3286 if (host->clk_mul) { 3287 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3288 max_clk = host->max_clk * host->clk_mul; 3289 } else 3290 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3291 } else 3292 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3293 3294 if (!mmc->f_max || mmc->f_max > max_clk) 3295 mmc->f_max = max_clk; 3296 3297 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3298 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 3299 SDHCI_TIMEOUT_CLK_SHIFT; 3300 if (host->timeout_clk == 0) { 3301 if (host->ops->get_timeout_clock) { 3302 host->timeout_clk = 3303 host->ops->get_timeout_clock(host); 3304 } else { 3305 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3306 mmc_hostname(mmc)); 3307 ret = -ENODEV; 3308 goto undma; 3309 } 3310 } 3311 3312 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 3313 host->timeout_clk *= 1000; 3314 3315 if (override_timeout_clk) 3316 host->timeout_clk = override_timeout_clk; 3317 3318 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3319 host->ops->get_max_timeout_count(host) : 1 << 27; 3320 mmc->max_busy_timeout /= host->timeout_clk; 3321 } 3322 3323 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3324 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3325 3326 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3327 host->flags |= SDHCI_AUTO_CMD12; 3328 3329 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 3330 if ((host->version >= SDHCI_SPEC_300) && 3331 ((host->flags & SDHCI_USE_ADMA) || 3332 !(host->flags & SDHCI_USE_SDMA)) && 3333 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 3334 host->flags |= SDHCI_AUTO_CMD23; 3335 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 3336 } else { 3337 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 3338 } 3339 3340 /* 3341 * A controller may support 8-bit width, but the board itself 3342 * might not have the pins brought out. Boards that support 3343 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3344 * their platform code before calling sdhci_add_host(), and we 3345 * won't assume 8-bit width for hosts without that CAP. 3346 */ 3347 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3348 mmc->caps |= MMC_CAP_4_BIT_DATA; 3349 3350 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3351 mmc->caps &= ~MMC_CAP_CMD23; 3352 3353 if (host->caps & SDHCI_CAN_DO_HISPD) 3354 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3355 3356 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3357 mmc_card_is_removable(mmc) && 3358 mmc_gpio_get_cd(host->mmc) < 0) 3359 mmc->caps |= MMC_CAP_NEEDS_POLL; 3360 3361 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3362 if (!IS_ERR(mmc->supply.vqmmc)) { 3363 ret = regulator_enable(mmc->supply.vqmmc); 3364 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3365 1950000)) 3366 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 3367 SDHCI_SUPPORT_SDR50 | 3368 SDHCI_SUPPORT_DDR50); 3369 if (ret) { 3370 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3371 mmc_hostname(mmc), ret); 3372 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3373 } 3374 } 3375 3376 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 3377 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3378 SDHCI_SUPPORT_DDR50); 3379 } 3380 3381 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3382 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3383 SDHCI_SUPPORT_DDR50)) 3384 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3385 3386 /* SDR104 supports also implies SDR50 support */ 3387 if (host->caps1 & SDHCI_SUPPORT_SDR104) { 3388 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3389 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3390 * field can be promoted to support HS200. 3391 */ 3392 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3393 mmc->caps2 |= MMC_CAP2_HS200; 3394 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 3395 mmc->caps |= MMC_CAP_UHS_SDR50; 3396 } 3397 3398 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3399 (host->caps1 & SDHCI_SUPPORT_HS400)) 3400 mmc->caps2 |= MMC_CAP2_HS400; 3401 3402 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3403 (IS_ERR(mmc->supply.vqmmc) || 3404 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3405 1300000))) 3406 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3407 3408 if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 3409 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3410 mmc->caps |= MMC_CAP_UHS_DDR50; 3411 3412 /* Does the host need tuning for SDR50? */ 3413 if (host->caps1 & SDHCI_USE_SDR50_TUNING) 3414 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3415 3416 /* Driver Type(s) (A, C, D) supported by the host */ 3417 if (host->caps1 & SDHCI_DRIVER_TYPE_A) 3418 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3419 if (host->caps1 & SDHCI_DRIVER_TYPE_C) 3420 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3421 if (host->caps1 & SDHCI_DRIVER_TYPE_D) 3422 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3423 3424 /* Initial value for re-tuning timer count */ 3425 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3426 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3427 3428 /* 3429 * In case Re-tuning Timer is not disabled, the actual value of 3430 * re-tuning timer will be 2 ^ (n - 1). 3431 */ 3432 if (host->tuning_count) 3433 host->tuning_count = 1 << (host->tuning_count - 1); 3434 3435 /* Re-tuning mode supported by the Host Controller */ 3436 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 3437 SDHCI_RETUNING_MODE_SHIFT; 3438 3439 ocr_avail = 0; 3440 3441 /* 3442 * According to SD Host Controller spec v3.00, if the Host System 3443 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3444 * the value is meaningful only if Voltage Support in the Capabilities 3445 * register is set. The actual current value is 4 times the register 3446 * value. 3447 */ 3448 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3449 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3450 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3451 if (curr > 0) { 3452 3453 /* convert to SDHCI_MAX_CURRENT format */ 3454 curr = curr/1000; /* convert to mA */ 3455 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3456 3457 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3458 max_current_caps = 3459 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3460 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3461 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3462 } 3463 } 3464 3465 if (host->caps & SDHCI_CAN_VDD_330) { 3466 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3467 3468 mmc->max_current_330 = ((max_current_caps & 3469 SDHCI_MAX_CURRENT_330_MASK) >> 3470 SDHCI_MAX_CURRENT_330_SHIFT) * 3471 SDHCI_MAX_CURRENT_MULTIPLIER; 3472 } 3473 if (host->caps & SDHCI_CAN_VDD_300) { 3474 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3475 3476 mmc->max_current_300 = ((max_current_caps & 3477 SDHCI_MAX_CURRENT_300_MASK) >> 3478 SDHCI_MAX_CURRENT_300_SHIFT) * 3479 SDHCI_MAX_CURRENT_MULTIPLIER; 3480 } 3481 if (host->caps & SDHCI_CAN_VDD_180) { 3482 ocr_avail |= MMC_VDD_165_195; 3483 3484 mmc->max_current_180 = ((max_current_caps & 3485 SDHCI_MAX_CURRENT_180_MASK) >> 3486 SDHCI_MAX_CURRENT_180_SHIFT) * 3487 SDHCI_MAX_CURRENT_MULTIPLIER; 3488 } 3489 3490 /* If OCR set by host, use it instead. */ 3491 if (host->ocr_mask) 3492 ocr_avail = host->ocr_mask; 3493 3494 /* If OCR set by external regulators, give it highest prio. */ 3495 if (mmc->ocr_avail) 3496 ocr_avail = mmc->ocr_avail; 3497 3498 mmc->ocr_avail = ocr_avail; 3499 mmc->ocr_avail_sdio = ocr_avail; 3500 if (host->ocr_avail_sdio) 3501 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3502 mmc->ocr_avail_sd = ocr_avail; 3503 if (host->ocr_avail_sd) 3504 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3505 else /* normal SD controllers don't support 1.8V */ 3506 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3507 mmc->ocr_avail_mmc = ocr_avail; 3508 if (host->ocr_avail_mmc) 3509 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3510 3511 if (mmc->ocr_avail == 0) { 3512 pr_err("%s: Hardware doesn't report any support voltages.\n", 3513 mmc_hostname(mmc)); 3514 ret = -ENODEV; 3515 goto unreg; 3516 } 3517 3518 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 3519 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 3520 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 3521 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 3522 host->flags |= SDHCI_SIGNALING_180; 3523 3524 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 3525 host->flags |= SDHCI_SIGNALING_120; 3526 3527 spin_lock_init(&host->lock); 3528 3529 /* 3530 * Maximum number of segments. Depends on if the hardware 3531 * can do scatter/gather or not. 3532 */ 3533 if (host->flags & SDHCI_USE_ADMA) 3534 mmc->max_segs = SDHCI_MAX_SEGS; 3535 else if (host->flags & SDHCI_USE_SDMA) 3536 mmc->max_segs = 1; 3537 else /* PIO */ 3538 mmc->max_segs = SDHCI_MAX_SEGS; 3539 3540 /* 3541 * Maximum number of sectors in one transfer. Limited by SDMA boundary 3542 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3543 * is less anyway. 3544 */ 3545 mmc->max_req_size = 524288; 3546 3547 /* 3548 * Maximum segment size. Could be one segment with the maximum number 3549 * of bytes. When doing hardware scatter/gather, each entry cannot 3550 * be larger than 64 KiB though. 3551 */ 3552 if (host->flags & SDHCI_USE_ADMA) { 3553 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3554 mmc->max_seg_size = 65535; 3555 else 3556 mmc->max_seg_size = 65536; 3557 } else { 3558 mmc->max_seg_size = mmc->max_req_size; 3559 } 3560 3561 /* 3562 * Maximum block size. This varies from controller to controller and 3563 * is specified in the capabilities register. 3564 */ 3565 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3566 mmc->max_blk_size = 2; 3567 } else { 3568 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 3569 SDHCI_MAX_BLOCK_SHIFT; 3570 if (mmc->max_blk_size >= 3) { 3571 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3572 mmc_hostname(mmc)); 3573 mmc->max_blk_size = 0; 3574 } 3575 } 3576 3577 mmc->max_blk_size = 512 << mmc->max_blk_size; 3578 3579 /* 3580 * Maximum block count. 3581 */ 3582 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3583 3584 return 0; 3585 3586 unreg: 3587 if (!IS_ERR(mmc->supply.vqmmc)) 3588 regulator_disable(mmc->supply.vqmmc); 3589 undma: 3590 if (host->align_buffer) 3591 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3592 host->adma_table_sz, host->align_buffer, 3593 host->align_addr); 3594 host->adma_table = NULL; 3595 host->align_buffer = NULL; 3596 3597 return ret; 3598 } 3599 EXPORT_SYMBOL_GPL(sdhci_setup_host); 3600 3601 int __sdhci_add_host(struct sdhci_host *host) 3602 { 3603 struct mmc_host *mmc = host->mmc; 3604 int ret; 3605 3606 /* 3607 * Init tasklets. 3608 */ 3609 tasklet_init(&host->finish_tasklet, 3610 sdhci_tasklet_finish, (unsigned long)host); 3611 3612 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3613 setup_timer(&host->data_timer, sdhci_timeout_data_timer, 3614 (unsigned long)host); 3615 3616 init_waitqueue_head(&host->buf_ready_int); 3617 3618 sdhci_init(host, 0); 3619 3620 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3621 IRQF_SHARED, mmc_hostname(mmc), host); 3622 if (ret) { 3623 pr_err("%s: Failed to request IRQ %d: %d\n", 3624 mmc_hostname(mmc), host->irq, ret); 3625 goto untasklet; 3626 } 3627 3628 #ifdef CONFIG_MMC_DEBUG 3629 sdhci_dumpregs(host); 3630 #endif 3631 3632 ret = sdhci_led_register(host); 3633 if (ret) { 3634 pr_err("%s: Failed to register LED device: %d\n", 3635 mmc_hostname(mmc), ret); 3636 goto unirq; 3637 } 3638 3639 mmiowb(); 3640 3641 ret = mmc_add_host(mmc); 3642 if (ret) 3643 goto unled; 3644 3645 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3646 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3647 (host->flags & SDHCI_USE_ADMA) ? 3648 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3649 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3650 3651 sdhci_enable_card_detection(host); 3652 3653 return 0; 3654 3655 unled: 3656 sdhci_led_unregister(host); 3657 unirq: 3658 sdhci_do_reset(host, SDHCI_RESET_ALL); 3659 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3660 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3661 free_irq(host->irq, host); 3662 untasklet: 3663 tasklet_kill(&host->finish_tasklet); 3664 3665 if (!IS_ERR(mmc->supply.vqmmc)) 3666 regulator_disable(mmc->supply.vqmmc); 3667 3668 if (host->align_buffer) 3669 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3670 host->adma_table_sz, host->align_buffer, 3671 host->align_addr); 3672 host->adma_table = NULL; 3673 host->align_buffer = NULL; 3674 3675 return ret; 3676 } 3677 EXPORT_SYMBOL_GPL(__sdhci_add_host); 3678 3679 int sdhci_add_host(struct sdhci_host *host) 3680 { 3681 int ret; 3682 3683 ret = sdhci_setup_host(host); 3684 if (ret) 3685 return ret; 3686 3687 return __sdhci_add_host(host); 3688 } 3689 EXPORT_SYMBOL_GPL(sdhci_add_host); 3690 3691 void sdhci_remove_host(struct sdhci_host *host, int dead) 3692 { 3693 struct mmc_host *mmc = host->mmc; 3694 unsigned long flags; 3695 3696 if (dead) { 3697 spin_lock_irqsave(&host->lock, flags); 3698 3699 host->flags |= SDHCI_DEVICE_DEAD; 3700 3701 if (sdhci_has_requests(host)) { 3702 pr_err("%s: Controller removed during " 3703 " transfer!\n", mmc_hostname(mmc)); 3704 sdhci_error_out_mrqs(host, -ENOMEDIUM); 3705 } 3706 3707 spin_unlock_irqrestore(&host->lock, flags); 3708 } 3709 3710 sdhci_disable_card_detection(host); 3711 3712 mmc_remove_host(mmc); 3713 3714 sdhci_led_unregister(host); 3715 3716 if (!dead) 3717 sdhci_do_reset(host, SDHCI_RESET_ALL); 3718 3719 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3720 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3721 free_irq(host->irq, host); 3722 3723 del_timer_sync(&host->timer); 3724 del_timer_sync(&host->data_timer); 3725 3726 tasklet_kill(&host->finish_tasklet); 3727 3728 if (!IS_ERR(mmc->supply.vqmmc)) 3729 regulator_disable(mmc->supply.vqmmc); 3730 3731 if (host->align_buffer) 3732 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3733 host->adma_table_sz, host->align_buffer, 3734 host->align_addr); 3735 3736 host->adma_table = NULL; 3737 host->align_buffer = NULL; 3738 } 3739 3740 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3741 3742 void sdhci_free_host(struct sdhci_host *host) 3743 { 3744 mmc_free_host(host->mmc); 3745 } 3746 3747 EXPORT_SYMBOL_GPL(sdhci_free_host); 3748 3749 /*****************************************************************************\ 3750 * * 3751 * Driver init/exit * 3752 * * 3753 \*****************************************************************************/ 3754 3755 static int __init sdhci_drv_init(void) 3756 { 3757 pr_info(DRIVER_NAME 3758 ": Secure Digital Host Controller Interface driver\n"); 3759 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3760 3761 return 0; 3762 } 3763 3764 static void __exit sdhci_drv_exit(void) 3765 { 3766 } 3767 3768 module_init(sdhci_drv_init); 3769 module_exit(sdhci_drv_exit); 3770 3771 module_param(debug_quirks, uint, 0444); 3772 module_param(debug_quirks2, uint, 0444); 3773 3774 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3775 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3776 MODULE_LICENSE("GPL"); 3777 3778 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3779 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3780