1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/slot-gpio.h> 32 33 #include "sdhci.h" 34 35 #define DRIVER_NAME "sdhci" 36 37 #define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42 #define SDHCI_USE_LEDS_CLASS 43 #endif 44 45 #define MAX_TUNING_LOOP 40 46 47 static unsigned int debug_quirks = 0; 48 static unsigned int debug_quirks2; 49 50 static void sdhci_finish_data(struct sdhci_host *); 51 52 static void sdhci_finish_command(struct sdhci_host *); 53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 54 static void sdhci_tuning_timer(unsigned long data); 55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 56 57 #ifdef CONFIG_PM 58 static int sdhci_runtime_pm_get(struct sdhci_host *host); 59 static int sdhci_runtime_pm_put(struct sdhci_host *host); 60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 62 #else 63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 64 { 65 return 0; 66 } 67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 68 { 69 return 0; 70 } 71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 72 { 73 } 74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 75 { 76 } 77 #endif 78 79 static void sdhci_dumpregs(struct sdhci_host *host) 80 { 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 82 mmc_hostname(host->mmc)); 83 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 85 sdhci_readl(host, SDHCI_DMA_ADDRESS), 86 sdhci_readw(host, SDHCI_HOST_VERSION)); 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 88 sdhci_readw(host, SDHCI_BLOCK_SIZE), 89 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 91 sdhci_readl(host, SDHCI_ARGUMENT), 92 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 94 sdhci_readl(host, SDHCI_PRESENT_STATE), 95 sdhci_readb(host, SDHCI_HOST_CONTROL)); 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 97 sdhci_readb(host, SDHCI_POWER_CONTROL), 98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 101 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 104 sdhci_readl(host, SDHCI_INT_STATUS)); 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 106 sdhci_readl(host, SDHCI_INT_ENABLE), 107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 109 sdhci_readw(host, SDHCI_ACMD12_ERR), 110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 112 sdhci_readl(host, SDHCI_CAPABILITIES), 113 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 115 sdhci_readw(host, SDHCI_COMMAND), 116 sdhci_readl(host, SDHCI_MAX_CURRENT)); 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 118 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 119 120 if (host->flags & SDHCI_USE_ADMA) { 121 if (host->flags & SDHCI_USE_64_BIT_DMA) 122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 123 readl(host->ioaddr + SDHCI_ADMA_ERROR), 124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 126 else 127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 128 readl(host->ioaddr + SDHCI_ADMA_ERROR), 129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 130 } 131 132 pr_debug(DRIVER_NAME ": ===========================================\n"); 133 } 134 135 /*****************************************************************************\ 136 * * 137 * Low level functions * 138 * * 139 \*****************************************************************************/ 140 141 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 142 { 143 u32 present; 144 145 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 146 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 147 return; 148 149 if (enable) { 150 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 151 SDHCI_CARD_PRESENT; 152 153 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 154 SDHCI_INT_CARD_INSERT; 155 } else { 156 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 157 } 158 159 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 160 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 161 } 162 163 static void sdhci_enable_card_detection(struct sdhci_host *host) 164 { 165 sdhci_set_card_detection(host, true); 166 } 167 168 static void sdhci_disable_card_detection(struct sdhci_host *host) 169 { 170 sdhci_set_card_detection(host, false); 171 } 172 173 void sdhci_reset(struct sdhci_host *host, u8 mask) 174 { 175 unsigned long timeout; 176 177 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 178 179 if (mask & SDHCI_RESET_ALL) { 180 host->clock = 0; 181 /* Reset-all turns off SD Bus Power */ 182 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 183 sdhci_runtime_pm_bus_off(host); 184 } 185 186 /* Wait max 100 ms */ 187 timeout = 100; 188 189 /* hw clears the bit when it's done */ 190 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 191 if (timeout == 0) { 192 pr_err("%s: Reset 0x%x never completed.\n", 193 mmc_hostname(host->mmc), (int)mask); 194 sdhci_dumpregs(host); 195 return; 196 } 197 timeout--; 198 mdelay(1); 199 } 200 } 201 EXPORT_SYMBOL_GPL(sdhci_reset); 202 203 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 204 { 205 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 206 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 207 SDHCI_CARD_PRESENT)) 208 return; 209 } 210 211 host->ops->reset(host, mask); 212 213 if (mask & SDHCI_RESET_ALL) { 214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 215 if (host->ops->enable_dma) 216 host->ops->enable_dma(host); 217 } 218 219 /* Resetting the controller clears many */ 220 host->preset_enabled = false; 221 } 222 } 223 224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 225 226 static void sdhci_init(struct sdhci_host *host, int soft) 227 { 228 if (soft) 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 230 else 231 sdhci_do_reset(host, SDHCI_RESET_ALL); 232 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 237 SDHCI_INT_RESPONSE; 238 239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 241 242 if (soft) { 243 /* force clock reconfiguration */ 244 host->clock = 0; 245 sdhci_set_ios(host->mmc, &host->mmc->ios); 246 } 247 } 248 249 static void sdhci_reinit(struct sdhci_host *host) 250 { 251 sdhci_init(host, 0); 252 /* 253 * Retuning stuffs are affected by different cards inserted and only 254 * applicable to UHS-I cards. So reset these fields to their initial 255 * value when card is removed. 256 */ 257 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 258 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 259 260 del_timer_sync(&host->tuning_timer); 261 host->flags &= ~SDHCI_NEEDS_RETUNING; 262 } 263 sdhci_enable_card_detection(host); 264 } 265 266 static void sdhci_activate_led(struct sdhci_host *host) 267 { 268 u8 ctrl; 269 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 271 ctrl |= SDHCI_CTRL_LED; 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 273 } 274 275 static void sdhci_deactivate_led(struct sdhci_host *host) 276 { 277 u8 ctrl; 278 279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 280 ctrl &= ~SDHCI_CTRL_LED; 281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 282 } 283 284 #ifdef SDHCI_USE_LEDS_CLASS 285 static void sdhci_led_control(struct led_classdev *led, 286 enum led_brightness brightness) 287 { 288 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 289 unsigned long flags; 290 291 spin_lock_irqsave(&host->lock, flags); 292 293 if (host->runtime_suspended) 294 goto out; 295 296 if (brightness == LED_OFF) 297 sdhci_deactivate_led(host); 298 else 299 sdhci_activate_led(host); 300 out: 301 spin_unlock_irqrestore(&host->lock, flags); 302 } 303 #endif 304 305 /*****************************************************************************\ 306 * * 307 * Core functions * 308 * * 309 \*****************************************************************************/ 310 311 static void sdhci_read_block_pio(struct sdhci_host *host) 312 { 313 unsigned long flags; 314 size_t blksize, len, chunk; 315 u32 uninitialized_var(scratch); 316 u8 *buf; 317 318 DBG("PIO reading\n"); 319 320 blksize = host->data->blksz; 321 chunk = 0; 322 323 local_irq_save(flags); 324 325 while (blksize) { 326 if (!sg_miter_next(&host->sg_miter)) 327 BUG(); 328 329 len = min(host->sg_miter.length, blksize); 330 331 blksize -= len; 332 host->sg_miter.consumed = len; 333 334 buf = host->sg_miter.addr; 335 336 while (len) { 337 if (chunk == 0) { 338 scratch = sdhci_readl(host, SDHCI_BUFFER); 339 chunk = 4; 340 } 341 342 *buf = scratch & 0xFF; 343 344 buf++; 345 scratch >>= 8; 346 chunk--; 347 len--; 348 } 349 } 350 351 sg_miter_stop(&host->sg_miter); 352 353 local_irq_restore(flags); 354 } 355 356 static void sdhci_write_block_pio(struct sdhci_host *host) 357 { 358 unsigned long flags; 359 size_t blksize, len, chunk; 360 u32 scratch; 361 u8 *buf; 362 363 DBG("PIO writing\n"); 364 365 blksize = host->data->blksz; 366 chunk = 0; 367 scratch = 0; 368 369 local_irq_save(flags); 370 371 while (blksize) { 372 if (!sg_miter_next(&host->sg_miter)) 373 BUG(); 374 375 len = min(host->sg_miter.length, blksize); 376 377 blksize -= len; 378 host->sg_miter.consumed = len; 379 380 buf = host->sg_miter.addr; 381 382 while (len) { 383 scratch |= (u32)*buf << (chunk * 8); 384 385 buf++; 386 chunk++; 387 len--; 388 389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 390 sdhci_writel(host, scratch, SDHCI_BUFFER); 391 chunk = 0; 392 scratch = 0; 393 } 394 } 395 } 396 397 sg_miter_stop(&host->sg_miter); 398 399 local_irq_restore(flags); 400 } 401 402 static void sdhci_transfer_pio(struct sdhci_host *host) 403 { 404 u32 mask; 405 406 BUG_ON(!host->data); 407 408 if (host->blocks == 0) 409 return; 410 411 if (host->data->flags & MMC_DATA_READ) 412 mask = SDHCI_DATA_AVAILABLE; 413 else 414 mask = SDHCI_SPACE_AVAILABLE; 415 416 /* 417 * Some controllers (JMicron JMB38x) mess up the buffer bits 418 * for transfers < 4 bytes. As long as it is just one block, 419 * we can ignore the bits. 420 */ 421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 422 (host->data->blocks == 1)) 423 mask = ~0; 424 425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 427 udelay(100); 428 429 if (host->data->flags & MMC_DATA_READ) 430 sdhci_read_block_pio(host); 431 else 432 sdhci_write_block_pio(host); 433 434 host->blocks--; 435 if (host->blocks == 0) 436 break; 437 } 438 439 DBG("PIO transfer complete.\n"); 440 } 441 442 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 443 { 444 local_irq_save(*flags); 445 return kmap_atomic(sg_page(sg)) + sg->offset; 446 } 447 448 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 449 { 450 kunmap_atomic(buffer); 451 local_irq_restore(*flags); 452 } 453 454 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 455 dma_addr_t addr, int len, unsigned cmd) 456 { 457 struct sdhci_adma2_64_desc *dma_desc = desc; 458 459 /* 32-bit and 64-bit descriptors have these members in same position */ 460 dma_desc->cmd = cpu_to_le16(cmd); 461 dma_desc->len = cpu_to_le16(len); 462 dma_desc->addr_lo = cpu_to_le32((u32)addr); 463 464 if (host->flags & SDHCI_USE_64_BIT_DMA) 465 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 466 } 467 468 static void sdhci_adma_mark_end(void *desc) 469 { 470 struct sdhci_adma2_64_desc *dma_desc = desc; 471 472 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 473 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 474 } 475 476 static int sdhci_adma_table_pre(struct sdhci_host *host, 477 struct mmc_data *data) 478 { 479 int direction; 480 481 void *desc; 482 void *align; 483 dma_addr_t addr; 484 dma_addr_t align_addr; 485 int len, offset; 486 487 struct scatterlist *sg; 488 int i; 489 char *buffer; 490 unsigned long flags; 491 492 /* 493 * The spec does not specify endianness of descriptor table. 494 * We currently guess that it is LE. 495 */ 496 497 if (data->flags & MMC_DATA_READ) 498 direction = DMA_FROM_DEVICE; 499 else 500 direction = DMA_TO_DEVICE; 501 502 host->align_addr = dma_map_single(mmc_dev(host->mmc), 503 host->align_buffer, host->align_buffer_sz, direction); 504 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 505 goto fail; 506 BUG_ON(host->align_addr & host->align_mask); 507 508 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 509 data->sg, data->sg_len, direction); 510 if (host->sg_count == 0) 511 goto unmap_align; 512 513 desc = host->adma_table; 514 align = host->align_buffer; 515 516 align_addr = host->align_addr; 517 518 for_each_sg(data->sg, sg, host->sg_count, i) { 519 addr = sg_dma_address(sg); 520 len = sg_dma_len(sg); 521 522 /* 523 * The SDHCI specification states that ADMA 524 * addresses must be 32-bit aligned. If they 525 * aren't, then we use a bounce buffer for 526 * the (up to three) bytes that screw up the 527 * alignment. 528 */ 529 offset = (host->align_sz - (addr & host->align_mask)) & 530 host->align_mask; 531 if (offset) { 532 if (data->flags & MMC_DATA_WRITE) { 533 buffer = sdhci_kmap_atomic(sg, &flags); 534 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) > 535 (PAGE_SIZE - offset)); 536 memcpy(align, buffer, offset); 537 sdhci_kunmap_atomic(buffer, &flags); 538 } 539 540 /* tran, valid */ 541 sdhci_adma_write_desc(host, desc, align_addr, offset, 542 ADMA2_TRAN_VALID); 543 544 BUG_ON(offset > 65536); 545 546 align += host->align_sz; 547 align_addr += host->align_sz; 548 549 desc += host->desc_sz; 550 551 addr += offset; 552 len -= offset; 553 } 554 555 BUG_ON(len > 65536); 556 557 /* tran, valid */ 558 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID); 559 desc += host->desc_sz; 560 561 /* 562 * If this triggers then we have a calculation bug 563 * somewhere. :/ 564 */ 565 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 566 } 567 568 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 569 /* 570 * Mark the last descriptor as the terminating descriptor 571 */ 572 if (desc != host->adma_table) { 573 desc -= host->desc_sz; 574 sdhci_adma_mark_end(desc); 575 } 576 } else { 577 /* 578 * Add a terminating entry. 579 */ 580 581 /* nop, end, valid */ 582 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 583 } 584 585 /* 586 * Resync align buffer as we might have changed it. 587 */ 588 if (data->flags & MMC_DATA_WRITE) { 589 dma_sync_single_for_device(mmc_dev(host->mmc), 590 host->align_addr, host->align_buffer_sz, direction); 591 } 592 593 return 0; 594 595 unmap_align: 596 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 597 host->align_buffer_sz, direction); 598 fail: 599 return -EINVAL; 600 } 601 602 static void sdhci_adma_table_post(struct sdhci_host *host, 603 struct mmc_data *data) 604 { 605 int direction; 606 607 struct scatterlist *sg; 608 int i, size; 609 void *align; 610 char *buffer; 611 unsigned long flags; 612 bool has_unaligned; 613 614 if (data->flags & MMC_DATA_READ) 615 direction = DMA_FROM_DEVICE; 616 else 617 direction = DMA_TO_DEVICE; 618 619 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 620 host->align_buffer_sz, direction); 621 622 /* Do a quick scan of the SG list for any unaligned mappings */ 623 has_unaligned = false; 624 for_each_sg(data->sg, sg, host->sg_count, i) 625 if (sg_dma_address(sg) & host->align_mask) { 626 has_unaligned = true; 627 break; 628 } 629 630 if (has_unaligned && data->flags & MMC_DATA_READ) { 631 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 632 data->sg_len, direction); 633 634 align = host->align_buffer; 635 636 for_each_sg(data->sg, sg, host->sg_count, i) { 637 if (sg_dma_address(sg) & host->align_mask) { 638 size = host->align_sz - 639 (sg_dma_address(sg) & host->align_mask); 640 641 buffer = sdhci_kmap_atomic(sg, &flags); 642 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) > 643 (PAGE_SIZE - size)); 644 memcpy(buffer, align, size); 645 sdhci_kunmap_atomic(buffer, &flags); 646 647 align += host->align_sz; 648 } 649 } 650 } 651 652 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 653 data->sg_len, direction); 654 } 655 656 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 657 { 658 u8 count; 659 struct mmc_data *data = cmd->data; 660 unsigned target_timeout, current_timeout; 661 662 /* 663 * If the host controller provides us with an incorrect timeout 664 * value, just skip the check and use 0xE. The hardware may take 665 * longer to time out, but that's much better than having a too-short 666 * timeout value. 667 */ 668 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 669 return 0xE; 670 671 /* Unspecified timeout, assume max */ 672 if (!data && !cmd->busy_timeout) 673 return 0xE; 674 675 /* timeout in us */ 676 if (!data) 677 target_timeout = cmd->busy_timeout * 1000; 678 else { 679 target_timeout = data->timeout_ns / 1000; 680 if (host->clock) 681 target_timeout += data->timeout_clks / host->clock; 682 } 683 684 /* 685 * Figure out needed cycles. 686 * We do this in steps in order to fit inside a 32 bit int. 687 * The first step is the minimum timeout, which will have a 688 * minimum resolution of 6 bits: 689 * (1) 2^13*1000 > 2^22, 690 * (2) host->timeout_clk < 2^16 691 * => 692 * (1) / (2) > 2^6 693 */ 694 count = 0; 695 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 696 while (current_timeout < target_timeout) { 697 count++; 698 current_timeout <<= 1; 699 if (count >= 0xF) 700 break; 701 } 702 703 if (count >= 0xF) { 704 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 705 mmc_hostname(host->mmc), count, cmd->opcode); 706 count = 0xE; 707 } 708 709 return count; 710 } 711 712 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 713 { 714 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 715 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 716 717 if (host->flags & SDHCI_REQ_USE_DMA) 718 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 719 else 720 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 721 722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 724 } 725 726 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 727 { 728 u8 count; 729 730 if (host->ops->set_timeout) { 731 host->ops->set_timeout(host, cmd); 732 } else { 733 count = sdhci_calc_timeout(host, cmd); 734 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 735 } 736 } 737 738 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 739 { 740 u8 ctrl; 741 struct mmc_data *data = cmd->data; 742 int ret; 743 744 WARN_ON(host->data); 745 746 if (data || (cmd->flags & MMC_RSP_BUSY)) 747 sdhci_set_timeout(host, cmd); 748 749 if (!data) 750 return; 751 752 /* Sanity checks */ 753 BUG_ON(data->blksz * data->blocks > 524288); 754 BUG_ON(data->blksz > host->mmc->max_blk_size); 755 BUG_ON(data->blocks > 65535); 756 757 host->data = data; 758 host->data_early = 0; 759 host->data->bytes_xfered = 0; 760 761 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 762 host->flags |= SDHCI_REQ_USE_DMA; 763 764 /* 765 * FIXME: This doesn't account for merging when mapping the 766 * scatterlist. 767 */ 768 if (host->flags & SDHCI_REQ_USE_DMA) { 769 int broken, i; 770 struct scatterlist *sg; 771 772 broken = 0; 773 if (host->flags & SDHCI_USE_ADMA) { 774 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 775 broken = 1; 776 } else { 777 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 778 broken = 1; 779 } 780 781 if (unlikely(broken)) { 782 for_each_sg(data->sg, sg, data->sg_len, i) { 783 if (sg->length & 0x3) { 784 DBG("Reverting to PIO because of " 785 "transfer size (%d)\n", 786 sg->length); 787 host->flags &= ~SDHCI_REQ_USE_DMA; 788 break; 789 } 790 } 791 } 792 } 793 794 /* 795 * The assumption here being that alignment is the same after 796 * translation to device address space. 797 */ 798 if (host->flags & SDHCI_REQ_USE_DMA) { 799 int broken, i; 800 struct scatterlist *sg; 801 802 broken = 0; 803 if (host->flags & SDHCI_USE_ADMA) { 804 /* 805 * As we use 3 byte chunks to work around 806 * alignment problems, we need to check this 807 * quirk. 808 */ 809 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 810 broken = 1; 811 } else { 812 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 813 broken = 1; 814 } 815 816 if (unlikely(broken)) { 817 for_each_sg(data->sg, sg, data->sg_len, i) { 818 if (sg->offset & 0x3) { 819 DBG("Reverting to PIO because of " 820 "bad alignment\n"); 821 host->flags &= ~SDHCI_REQ_USE_DMA; 822 break; 823 } 824 } 825 } 826 } 827 828 if (host->flags & SDHCI_REQ_USE_DMA) { 829 if (host->flags & SDHCI_USE_ADMA) { 830 ret = sdhci_adma_table_pre(host, data); 831 if (ret) { 832 /* 833 * This only happens when someone fed 834 * us an invalid request. 835 */ 836 WARN_ON(1); 837 host->flags &= ~SDHCI_REQ_USE_DMA; 838 } else { 839 sdhci_writel(host, host->adma_addr, 840 SDHCI_ADMA_ADDRESS); 841 if (host->flags & SDHCI_USE_64_BIT_DMA) 842 sdhci_writel(host, 843 (u64)host->adma_addr >> 32, 844 SDHCI_ADMA_ADDRESS_HI); 845 } 846 } else { 847 int sg_cnt; 848 849 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 850 data->sg, data->sg_len, 851 (data->flags & MMC_DATA_READ) ? 852 DMA_FROM_DEVICE : 853 DMA_TO_DEVICE); 854 if (sg_cnt == 0) { 855 /* 856 * This only happens when someone fed 857 * us an invalid request. 858 */ 859 WARN_ON(1); 860 host->flags &= ~SDHCI_REQ_USE_DMA; 861 } else { 862 WARN_ON(sg_cnt != 1); 863 sdhci_writel(host, sg_dma_address(data->sg), 864 SDHCI_DMA_ADDRESS); 865 } 866 } 867 } 868 869 /* 870 * Always adjust the DMA selection as some controllers 871 * (e.g. JMicron) can't do PIO properly when the selection 872 * is ADMA. 873 */ 874 if (host->version >= SDHCI_SPEC_200) { 875 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 876 ctrl &= ~SDHCI_CTRL_DMA_MASK; 877 if ((host->flags & SDHCI_REQ_USE_DMA) && 878 (host->flags & SDHCI_USE_ADMA)) { 879 if (host->flags & SDHCI_USE_64_BIT_DMA) 880 ctrl |= SDHCI_CTRL_ADMA64; 881 else 882 ctrl |= SDHCI_CTRL_ADMA32; 883 } else { 884 ctrl |= SDHCI_CTRL_SDMA; 885 } 886 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 887 } 888 889 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 890 int flags; 891 892 flags = SG_MITER_ATOMIC; 893 if (host->data->flags & MMC_DATA_READ) 894 flags |= SG_MITER_TO_SG; 895 else 896 flags |= SG_MITER_FROM_SG; 897 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 898 host->blocks = data->blocks; 899 } 900 901 sdhci_set_transfer_irqs(host); 902 903 /* Set the DMA boundary value and block size */ 904 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 905 data->blksz), SDHCI_BLOCK_SIZE); 906 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 907 } 908 909 static void sdhci_set_transfer_mode(struct sdhci_host *host, 910 struct mmc_command *cmd) 911 { 912 u16 mode; 913 struct mmc_data *data = cmd->data; 914 915 if (data == NULL) { 916 if (host->quirks2 & 917 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 918 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 919 } else { 920 /* clear Auto CMD settings for no data CMDs */ 921 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 922 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 923 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 924 } 925 return; 926 } 927 928 WARN_ON(!host->data); 929 930 mode = SDHCI_TRNS_BLK_CNT_EN; 931 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 932 mode |= SDHCI_TRNS_MULTI; 933 /* 934 * If we are sending CMD23, CMD12 never gets sent 935 * on successful completion (so no Auto-CMD12). 936 */ 937 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 938 mode |= SDHCI_TRNS_AUTO_CMD12; 939 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 940 mode |= SDHCI_TRNS_AUTO_CMD23; 941 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 942 } 943 } 944 945 if (data->flags & MMC_DATA_READ) 946 mode |= SDHCI_TRNS_READ; 947 if (host->flags & SDHCI_REQ_USE_DMA) 948 mode |= SDHCI_TRNS_DMA; 949 950 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 951 } 952 953 static void sdhci_finish_data(struct sdhci_host *host) 954 { 955 struct mmc_data *data; 956 957 BUG_ON(!host->data); 958 959 data = host->data; 960 host->data = NULL; 961 962 if (host->flags & SDHCI_REQ_USE_DMA) { 963 if (host->flags & SDHCI_USE_ADMA) 964 sdhci_adma_table_post(host, data); 965 else { 966 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 967 data->sg_len, (data->flags & MMC_DATA_READ) ? 968 DMA_FROM_DEVICE : DMA_TO_DEVICE); 969 } 970 } 971 972 /* 973 * The specification states that the block count register must 974 * be updated, but it does not specify at what point in the 975 * data flow. That makes the register entirely useless to read 976 * back so we have to assume that nothing made it to the card 977 * in the event of an error. 978 */ 979 if (data->error) 980 data->bytes_xfered = 0; 981 else 982 data->bytes_xfered = data->blksz * data->blocks; 983 984 /* 985 * Need to send CMD12 if - 986 * a) open-ended multiblock transfer (no CMD23) 987 * b) error in multiblock transfer 988 */ 989 if (data->stop && 990 (data->error || 991 !host->mrq->sbc)) { 992 993 /* 994 * The controller needs a reset of internal state machines 995 * upon error conditions. 996 */ 997 if (data->error) { 998 sdhci_do_reset(host, SDHCI_RESET_CMD); 999 sdhci_do_reset(host, SDHCI_RESET_DATA); 1000 } 1001 1002 sdhci_send_command(host, data->stop); 1003 } else 1004 tasklet_schedule(&host->finish_tasklet); 1005 } 1006 1007 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1008 { 1009 int flags; 1010 u32 mask; 1011 unsigned long timeout; 1012 1013 WARN_ON(host->cmd); 1014 1015 /* Wait max 10 ms */ 1016 timeout = 10; 1017 1018 mask = SDHCI_CMD_INHIBIT; 1019 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 1020 mask |= SDHCI_DATA_INHIBIT; 1021 1022 /* We shouldn't wait for data inihibit for stop commands, even 1023 though they might use busy signaling */ 1024 if (host->mrq->data && (cmd == host->mrq->data->stop)) 1025 mask &= ~SDHCI_DATA_INHIBIT; 1026 1027 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1028 if (timeout == 0) { 1029 pr_err("%s: Controller never released " 1030 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 1031 sdhci_dumpregs(host); 1032 cmd->error = -EIO; 1033 tasklet_schedule(&host->finish_tasklet); 1034 return; 1035 } 1036 timeout--; 1037 mdelay(1); 1038 } 1039 1040 timeout = jiffies; 1041 if (!cmd->data && cmd->busy_timeout > 9000) 1042 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1043 else 1044 timeout += 10 * HZ; 1045 mod_timer(&host->timer, timeout); 1046 1047 host->cmd = cmd; 1048 host->busy_handle = 0; 1049 1050 sdhci_prepare_data(host, cmd); 1051 1052 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1053 1054 sdhci_set_transfer_mode(host, cmd); 1055 1056 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1057 pr_err("%s: Unsupported response type!\n", 1058 mmc_hostname(host->mmc)); 1059 cmd->error = -EINVAL; 1060 tasklet_schedule(&host->finish_tasklet); 1061 return; 1062 } 1063 1064 if (!(cmd->flags & MMC_RSP_PRESENT)) 1065 flags = SDHCI_CMD_RESP_NONE; 1066 else if (cmd->flags & MMC_RSP_136) 1067 flags = SDHCI_CMD_RESP_LONG; 1068 else if (cmd->flags & MMC_RSP_BUSY) 1069 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1070 else 1071 flags = SDHCI_CMD_RESP_SHORT; 1072 1073 if (cmd->flags & MMC_RSP_CRC) 1074 flags |= SDHCI_CMD_CRC; 1075 if (cmd->flags & MMC_RSP_OPCODE) 1076 flags |= SDHCI_CMD_INDEX; 1077 1078 /* CMD19 is special in that the Data Present Select should be set */ 1079 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1080 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1081 flags |= SDHCI_CMD_DATA; 1082 1083 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1084 } 1085 EXPORT_SYMBOL_GPL(sdhci_send_command); 1086 1087 static void sdhci_finish_command(struct sdhci_host *host) 1088 { 1089 int i; 1090 1091 BUG_ON(host->cmd == NULL); 1092 1093 if (host->cmd->flags & MMC_RSP_PRESENT) { 1094 if (host->cmd->flags & MMC_RSP_136) { 1095 /* CRC is stripped so we need to do some shifting. */ 1096 for (i = 0;i < 4;i++) { 1097 host->cmd->resp[i] = sdhci_readl(host, 1098 SDHCI_RESPONSE + (3-i)*4) << 8; 1099 if (i != 3) 1100 host->cmd->resp[i] |= 1101 sdhci_readb(host, 1102 SDHCI_RESPONSE + (3-i)*4-1); 1103 } 1104 } else { 1105 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1106 } 1107 } 1108 1109 host->cmd->error = 0; 1110 1111 /* Finished CMD23, now send actual command. */ 1112 if (host->cmd == host->mrq->sbc) { 1113 host->cmd = NULL; 1114 sdhci_send_command(host, host->mrq->cmd); 1115 } else { 1116 1117 /* Processed actual command. */ 1118 if (host->data && host->data_early) 1119 sdhci_finish_data(host); 1120 1121 if (!host->cmd->data) 1122 tasklet_schedule(&host->finish_tasklet); 1123 1124 host->cmd = NULL; 1125 } 1126 } 1127 1128 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1129 { 1130 u16 preset = 0; 1131 1132 switch (host->timing) { 1133 case MMC_TIMING_UHS_SDR12: 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1135 break; 1136 case MMC_TIMING_UHS_SDR25: 1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1138 break; 1139 case MMC_TIMING_UHS_SDR50: 1140 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1141 break; 1142 case MMC_TIMING_UHS_SDR104: 1143 case MMC_TIMING_MMC_HS200: 1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1145 break; 1146 case MMC_TIMING_UHS_DDR50: 1147 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1148 break; 1149 case MMC_TIMING_MMC_HS400: 1150 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1151 break; 1152 default: 1153 pr_warn("%s: Invalid UHS-I mode selected\n", 1154 mmc_hostname(host->mmc)); 1155 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1156 break; 1157 } 1158 return preset; 1159 } 1160 1161 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1162 { 1163 int div = 0; /* Initialized for compiler warning */ 1164 int real_div = div, clk_mul = 1; 1165 u16 clk = 0; 1166 unsigned long timeout; 1167 1168 host->mmc->actual_clock = 0; 1169 1170 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1171 1172 if (clock == 0) 1173 return; 1174 1175 if (host->version >= SDHCI_SPEC_300) { 1176 if (host->preset_enabled) { 1177 u16 pre_val; 1178 1179 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1180 pre_val = sdhci_get_preset_value(host); 1181 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1182 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1183 if (host->clk_mul && 1184 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1185 clk = SDHCI_PROG_CLOCK_MODE; 1186 real_div = div + 1; 1187 clk_mul = host->clk_mul; 1188 } else { 1189 real_div = max_t(int, 1, div << 1); 1190 } 1191 goto clock_set; 1192 } 1193 1194 /* 1195 * Check if the Host Controller supports Programmable Clock 1196 * Mode. 1197 */ 1198 if (host->clk_mul) { 1199 for (div = 1; div <= 1024; div++) { 1200 if ((host->max_clk * host->clk_mul / div) 1201 <= clock) 1202 break; 1203 } 1204 /* 1205 * Set Programmable Clock Mode in the Clock 1206 * Control register. 1207 */ 1208 clk = SDHCI_PROG_CLOCK_MODE; 1209 real_div = div; 1210 clk_mul = host->clk_mul; 1211 div--; 1212 } else { 1213 /* Version 3.00 divisors must be a multiple of 2. */ 1214 if (host->max_clk <= clock) 1215 div = 1; 1216 else { 1217 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1218 div += 2) { 1219 if ((host->max_clk / div) <= clock) 1220 break; 1221 } 1222 } 1223 real_div = div; 1224 div >>= 1; 1225 } 1226 } else { 1227 /* Version 2.00 divisors must be a power of 2. */ 1228 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1229 if ((host->max_clk / div) <= clock) 1230 break; 1231 } 1232 real_div = div; 1233 div >>= 1; 1234 } 1235 1236 clock_set: 1237 if (real_div) 1238 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1239 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1240 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1241 << SDHCI_DIVIDER_HI_SHIFT; 1242 clk |= SDHCI_CLOCK_INT_EN; 1243 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1244 1245 /* Wait max 20 ms */ 1246 timeout = 20; 1247 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1248 & SDHCI_CLOCK_INT_STABLE)) { 1249 if (timeout == 0) { 1250 pr_err("%s: Internal clock never " 1251 "stabilised.\n", mmc_hostname(host->mmc)); 1252 sdhci_dumpregs(host); 1253 return; 1254 } 1255 timeout--; 1256 mdelay(1); 1257 } 1258 1259 clk |= SDHCI_CLOCK_CARD_EN; 1260 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1261 } 1262 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1263 1264 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1265 unsigned short vdd) 1266 { 1267 struct mmc_host *mmc = host->mmc; 1268 u8 pwr = 0; 1269 1270 if (!IS_ERR(mmc->supply.vmmc)) { 1271 spin_unlock_irq(&host->lock); 1272 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1273 spin_lock_irq(&host->lock); 1274 1275 if (mode != MMC_POWER_OFF) 1276 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1277 else 1278 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1279 1280 return; 1281 } 1282 1283 if (mode != MMC_POWER_OFF) { 1284 switch (1 << vdd) { 1285 case MMC_VDD_165_195: 1286 pwr = SDHCI_POWER_180; 1287 break; 1288 case MMC_VDD_29_30: 1289 case MMC_VDD_30_31: 1290 pwr = SDHCI_POWER_300; 1291 break; 1292 case MMC_VDD_32_33: 1293 case MMC_VDD_33_34: 1294 pwr = SDHCI_POWER_330; 1295 break; 1296 default: 1297 BUG(); 1298 } 1299 } 1300 1301 if (host->pwr == pwr) 1302 return; 1303 1304 host->pwr = pwr; 1305 1306 if (pwr == 0) { 1307 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1308 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1309 sdhci_runtime_pm_bus_off(host); 1310 vdd = 0; 1311 } else { 1312 /* 1313 * Spec says that we should clear the power reg before setting 1314 * a new value. Some controllers don't seem to like this though. 1315 */ 1316 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1317 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1318 1319 /* 1320 * At least the Marvell CaFe chip gets confused if we set the 1321 * voltage and set turn on power at the same time, so set the 1322 * voltage first. 1323 */ 1324 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1325 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1326 1327 pwr |= SDHCI_POWER_ON; 1328 1329 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1330 1331 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1332 sdhci_runtime_pm_bus_on(host); 1333 1334 /* 1335 * Some controllers need an extra 10ms delay of 10ms before 1336 * they can apply clock after applying power 1337 */ 1338 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1339 mdelay(10); 1340 } 1341 } 1342 1343 /*****************************************************************************\ 1344 * * 1345 * MMC callbacks * 1346 * * 1347 \*****************************************************************************/ 1348 1349 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1350 { 1351 struct sdhci_host *host; 1352 int present; 1353 unsigned long flags; 1354 u32 tuning_opcode; 1355 1356 host = mmc_priv(mmc); 1357 1358 sdhci_runtime_pm_get(host); 1359 1360 present = mmc_gpio_get_cd(host->mmc); 1361 1362 spin_lock_irqsave(&host->lock, flags); 1363 1364 WARN_ON(host->mrq != NULL); 1365 1366 #ifndef SDHCI_USE_LEDS_CLASS 1367 sdhci_activate_led(host); 1368 #endif 1369 1370 /* 1371 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1372 * requests if Auto-CMD12 is enabled. 1373 */ 1374 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1375 if (mrq->stop) { 1376 mrq->data->stop = NULL; 1377 mrq->stop = NULL; 1378 } 1379 } 1380 1381 host->mrq = mrq; 1382 1383 /* 1384 * Firstly check card presence from cd-gpio. The return could 1385 * be one of the following possibilities: 1386 * negative: cd-gpio is not available 1387 * zero: cd-gpio is used, and card is removed 1388 * one: cd-gpio is used, and card is present 1389 */ 1390 if (present < 0) { 1391 /* If polling, assume that the card is always present. */ 1392 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1393 present = 1; 1394 else 1395 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1396 SDHCI_CARD_PRESENT; 1397 } 1398 1399 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1400 host->mrq->cmd->error = -ENOMEDIUM; 1401 tasklet_schedule(&host->finish_tasklet); 1402 } else { 1403 u32 present_state; 1404 1405 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1406 /* 1407 * Check if the re-tuning timer has already expired and there 1408 * is no on-going data transfer and DAT0 is not busy. If so, 1409 * we need to execute tuning procedure before sending command. 1410 */ 1411 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1412 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) && 1413 (present_state & SDHCI_DATA_0_LVL_MASK)) { 1414 if (mmc->card) { 1415 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1416 tuning_opcode = 1417 mmc->card->type == MMC_TYPE_MMC ? 1418 MMC_SEND_TUNING_BLOCK_HS200 : 1419 MMC_SEND_TUNING_BLOCK; 1420 1421 /* Here we need to set the host->mrq to NULL, 1422 * in case the pending finish_tasklet 1423 * finishes it incorrectly. 1424 */ 1425 host->mrq = NULL; 1426 1427 spin_unlock_irqrestore(&host->lock, flags); 1428 sdhci_execute_tuning(mmc, tuning_opcode); 1429 spin_lock_irqsave(&host->lock, flags); 1430 1431 /* Restore original mmc_request structure */ 1432 host->mrq = mrq; 1433 } 1434 } 1435 1436 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1437 sdhci_send_command(host, mrq->sbc); 1438 else 1439 sdhci_send_command(host, mrq->cmd); 1440 } 1441 1442 mmiowb(); 1443 spin_unlock_irqrestore(&host->lock, flags); 1444 } 1445 1446 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1447 { 1448 u8 ctrl; 1449 1450 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1451 if (width == MMC_BUS_WIDTH_8) { 1452 ctrl &= ~SDHCI_CTRL_4BITBUS; 1453 if (host->version >= SDHCI_SPEC_300) 1454 ctrl |= SDHCI_CTRL_8BITBUS; 1455 } else { 1456 if (host->version >= SDHCI_SPEC_300) 1457 ctrl &= ~SDHCI_CTRL_8BITBUS; 1458 if (width == MMC_BUS_WIDTH_4) 1459 ctrl |= SDHCI_CTRL_4BITBUS; 1460 else 1461 ctrl &= ~SDHCI_CTRL_4BITBUS; 1462 } 1463 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1464 } 1465 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1466 1467 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1468 { 1469 u16 ctrl_2; 1470 1471 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1472 /* Select Bus Speed Mode for host */ 1473 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1474 if ((timing == MMC_TIMING_MMC_HS200) || 1475 (timing == MMC_TIMING_UHS_SDR104)) 1476 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1477 else if (timing == MMC_TIMING_UHS_SDR12) 1478 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1479 else if (timing == MMC_TIMING_UHS_SDR25) 1480 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1481 else if (timing == MMC_TIMING_UHS_SDR50) 1482 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1483 else if ((timing == MMC_TIMING_UHS_DDR50) || 1484 (timing == MMC_TIMING_MMC_DDR52)) 1485 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1486 else if (timing == MMC_TIMING_MMC_HS400) 1487 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1488 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1489 } 1490 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1491 1492 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1493 { 1494 unsigned long flags; 1495 u8 ctrl; 1496 struct mmc_host *mmc = host->mmc; 1497 1498 spin_lock_irqsave(&host->lock, flags); 1499 1500 if (host->flags & SDHCI_DEVICE_DEAD) { 1501 spin_unlock_irqrestore(&host->lock, flags); 1502 if (!IS_ERR(mmc->supply.vmmc) && 1503 ios->power_mode == MMC_POWER_OFF) 1504 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1505 return; 1506 } 1507 1508 /* 1509 * Reset the chip on each power off. 1510 * Should clear out any weird states. 1511 */ 1512 if (ios->power_mode == MMC_POWER_OFF) { 1513 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1514 sdhci_reinit(host); 1515 } 1516 1517 if (host->version >= SDHCI_SPEC_300 && 1518 (ios->power_mode == MMC_POWER_UP) && 1519 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1520 sdhci_enable_preset_value(host, false); 1521 1522 if (!ios->clock || ios->clock != host->clock) { 1523 host->ops->set_clock(host, ios->clock); 1524 host->clock = ios->clock; 1525 1526 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1527 host->clock) { 1528 host->timeout_clk = host->mmc->actual_clock ? 1529 host->mmc->actual_clock / 1000 : 1530 host->clock / 1000; 1531 host->mmc->max_busy_timeout = 1532 host->ops->get_max_timeout_count ? 1533 host->ops->get_max_timeout_count(host) : 1534 1 << 27; 1535 host->mmc->max_busy_timeout /= host->timeout_clk; 1536 } 1537 } 1538 1539 sdhci_set_power(host, ios->power_mode, ios->vdd); 1540 1541 if (host->ops->platform_send_init_74_clocks) 1542 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1543 1544 host->ops->set_bus_width(host, ios->bus_width); 1545 1546 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1547 1548 if ((ios->timing == MMC_TIMING_SD_HS || 1549 ios->timing == MMC_TIMING_MMC_HS) 1550 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1551 ctrl |= SDHCI_CTRL_HISPD; 1552 else 1553 ctrl &= ~SDHCI_CTRL_HISPD; 1554 1555 if (host->version >= SDHCI_SPEC_300) { 1556 u16 clk, ctrl_2; 1557 1558 /* In case of UHS-I modes, set High Speed Enable */ 1559 if ((ios->timing == MMC_TIMING_MMC_HS400) || 1560 (ios->timing == MMC_TIMING_MMC_HS200) || 1561 (ios->timing == MMC_TIMING_MMC_DDR52) || 1562 (ios->timing == MMC_TIMING_UHS_SDR50) || 1563 (ios->timing == MMC_TIMING_UHS_SDR104) || 1564 (ios->timing == MMC_TIMING_UHS_DDR50) || 1565 (ios->timing == MMC_TIMING_UHS_SDR25)) 1566 ctrl |= SDHCI_CTRL_HISPD; 1567 1568 if (!host->preset_enabled) { 1569 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1570 /* 1571 * We only need to set Driver Strength if the 1572 * preset value enable is not set. 1573 */ 1574 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1575 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1576 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1577 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1578 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1579 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1580 1581 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1582 } else { 1583 /* 1584 * According to SDHC Spec v3.00, if the Preset Value 1585 * Enable in the Host Control 2 register is set, we 1586 * need to reset SD Clock Enable before changing High 1587 * Speed Enable to avoid generating clock gliches. 1588 */ 1589 1590 /* Reset SD Clock Enable */ 1591 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1592 clk &= ~SDHCI_CLOCK_CARD_EN; 1593 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1594 1595 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1596 1597 /* Re-enable SD Clock */ 1598 host->ops->set_clock(host, host->clock); 1599 } 1600 1601 /* Reset SD Clock Enable */ 1602 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1603 clk &= ~SDHCI_CLOCK_CARD_EN; 1604 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1605 1606 host->ops->set_uhs_signaling(host, ios->timing); 1607 host->timing = ios->timing; 1608 1609 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1610 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1611 (ios->timing == MMC_TIMING_UHS_SDR25) || 1612 (ios->timing == MMC_TIMING_UHS_SDR50) || 1613 (ios->timing == MMC_TIMING_UHS_SDR104) || 1614 (ios->timing == MMC_TIMING_UHS_DDR50))) { 1615 u16 preset; 1616 1617 sdhci_enable_preset_value(host, true); 1618 preset = sdhci_get_preset_value(host); 1619 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1620 >> SDHCI_PRESET_DRV_SHIFT; 1621 } 1622 1623 /* Re-enable SD Clock */ 1624 host->ops->set_clock(host, host->clock); 1625 } else 1626 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1627 1628 /* 1629 * Some (ENE) controllers go apeshit on some ios operation, 1630 * signalling timeout and CRC errors even on CMD0. Resetting 1631 * it on each ios seems to solve the problem. 1632 */ 1633 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1634 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1635 1636 mmiowb(); 1637 spin_unlock_irqrestore(&host->lock, flags); 1638 } 1639 1640 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1641 { 1642 struct sdhci_host *host = mmc_priv(mmc); 1643 1644 sdhci_runtime_pm_get(host); 1645 sdhci_do_set_ios(host, ios); 1646 sdhci_runtime_pm_put(host); 1647 } 1648 1649 static int sdhci_do_get_cd(struct sdhci_host *host) 1650 { 1651 int gpio_cd = mmc_gpio_get_cd(host->mmc); 1652 1653 if (host->flags & SDHCI_DEVICE_DEAD) 1654 return 0; 1655 1656 /* If polling/nonremovable, assume that the card is always present. */ 1657 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 1658 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 1659 return 1; 1660 1661 /* Try slot gpio detect */ 1662 if (!IS_ERR_VALUE(gpio_cd)) 1663 return !!gpio_cd; 1664 1665 /* Host native card detect */ 1666 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1667 } 1668 1669 static int sdhci_get_cd(struct mmc_host *mmc) 1670 { 1671 struct sdhci_host *host = mmc_priv(mmc); 1672 int ret; 1673 1674 sdhci_runtime_pm_get(host); 1675 ret = sdhci_do_get_cd(host); 1676 sdhci_runtime_pm_put(host); 1677 return ret; 1678 } 1679 1680 static int sdhci_check_ro(struct sdhci_host *host) 1681 { 1682 unsigned long flags; 1683 int is_readonly; 1684 1685 spin_lock_irqsave(&host->lock, flags); 1686 1687 if (host->flags & SDHCI_DEVICE_DEAD) 1688 is_readonly = 0; 1689 else if (host->ops->get_ro) 1690 is_readonly = host->ops->get_ro(host); 1691 else 1692 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1693 & SDHCI_WRITE_PROTECT); 1694 1695 spin_unlock_irqrestore(&host->lock, flags); 1696 1697 /* This quirk needs to be replaced by a callback-function later */ 1698 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1699 !is_readonly : is_readonly; 1700 } 1701 1702 #define SAMPLE_COUNT 5 1703 1704 static int sdhci_do_get_ro(struct sdhci_host *host) 1705 { 1706 int i, ro_count; 1707 1708 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1709 return sdhci_check_ro(host); 1710 1711 ro_count = 0; 1712 for (i = 0; i < SAMPLE_COUNT; i++) { 1713 if (sdhci_check_ro(host)) { 1714 if (++ro_count > SAMPLE_COUNT / 2) 1715 return 1; 1716 } 1717 msleep(30); 1718 } 1719 return 0; 1720 } 1721 1722 static void sdhci_hw_reset(struct mmc_host *mmc) 1723 { 1724 struct sdhci_host *host = mmc_priv(mmc); 1725 1726 if (host->ops && host->ops->hw_reset) 1727 host->ops->hw_reset(host); 1728 } 1729 1730 static int sdhci_get_ro(struct mmc_host *mmc) 1731 { 1732 struct sdhci_host *host = mmc_priv(mmc); 1733 int ret; 1734 1735 sdhci_runtime_pm_get(host); 1736 ret = sdhci_do_get_ro(host); 1737 sdhci_runtime_pm_put(host); 1738 return ret; 1739 } 1740 1741 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1742 { 1743 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1744 if (enable) 1745 host->ier |= SDHCI_INT_CARD_INT; 1746 else 1747 host->ier &= ~SDHCI_INT_CARD_INT; 1748 1749 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1750 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1751 mmiowb(); 1752 } 1753 } 1754 1755 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1756 { 1757 struct sdhci_host *host = mmc_priv(mmc); 1758 unsigned long flags; 1759 1760 sdhci_runtime_pm_get(host); 1761 1762 spin_lock_irqsave(&host->lock, flags); 1763 if (enable) 1764 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1765 else 1766 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1767 1768 sdhci_enable_sdio_irq_nolock(host, enable); 1769 spin_unlock_irqrestore(&host->lock, flags); 1770 1771 sdhci_runtime_pm_put(host); 1772 } 1773 1774 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1775 struct mmc_ios *ios) 1776 { 1777 struct mmc_host *mmc = host->mmc; 1778 u16 ctrl; 1779 int ret; 1780 1781 /* 1782 * Signal Voltage Switching is only applicable for Host Controllers 1783 * v3.00 and above. 1784 */ 1785 if (host->version < SDHCI_SPEC_300) 1786 return 0; 1787 1788 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1789 1790 switch (ios->signal_voltage) { 1791 case MMC_SIGNAL_VOLTAGE_330: 1792 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1793 ctrl &= ~SDHCI_CTRL_VDD_180; 1794 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1795 1796 if (!IS_ERR(mmc->supply.vqmmc)) { 1797 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, 1798 3600000); 1799 if (ret) { 1800 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1801 mmc_hostname(mmc)); 1802 return -EIO; 1803 } 1804 } 1805 /* Wait for 5ms */ 1806 usleep_range(5000, 5500); 1807 1808 /* 3.3V regulator output should be stable within 5 ms */ 1809 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1810 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1811 return 0; 1812 1813 pr_warn("%s: 3.3V regulator output did not became stable\n", 1814 mmc_hostname(mmc)); 1815 1816 return -EAGAIN; 1817 case MMC_SIGNAL_VOLTAGE_180: 1818 if (!IS_ERR(mmc->supply.vqmmc)) { 1819 ret = regulator_set_voltage(mmc->supply.vqmmc, 1820 1700000, 1950000); 1821 if (ret) { 1822 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1823 mmc_hostname(mmc)); 1824 return -EIO; 1825 } 1826 } 1827 1828 /* 1829 * Enable 1.8V Signal Enable in the Host Control2 1830 * register 1831 */ 1832 ctrl |= SDHCI_CTRL_VDD_180; 1833 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1834 1835 /* 1.8V regulator output should be stable within 5 ms */ 1836 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1837 if (ctrl & SDHCI_CTRL_VDD_180) 1838 return 0; 1839 1840 pr_warn("%s: 1.8V regulator output did not became stable\n", 1841 mmc_hostname(mmc)); 1842 1843 return -EAGAIN; 1844 case MMC_SIGNAL_VOLTAGE_120: 1845 if (!IS_ERR(mmc->supply.vqmmc)) { 1846 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, 1847 1300000); 1848 if (ret) { 1849 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1850 mmc_hostname(mmc)); 1851 return -EIO; 1852 } 1853 } 1854 return 0; 1855 default: 1856 /* No signal voltage switch required */ 1857 return 0; 1858 } 1859 } 1860 1861 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1862 struct mmc_ios *ios) 1863 { 1864 struct sdhci_host *host = mmc_priv(mmc); 1865 int err; 1866 1867 if (host->version < SDHCI_SPEC_300) 1868 return 0; 1869 sdhci_runtime_pm_get(host); 1870 err = sdhci_do_start_signal_voltage_switch(host, ios); 1871 sdhci_runtime_pm_put(host); 1872 return err; 1873 } 1874 1875 static int sdhci_card_busy(struct mmc_host *mmc) 1876 { 1877 struct sdhci_host *host = mmc_priv(mmc); 1878 u32 present_state; 1879 1880 sdhci_runtime_pm_get(host); 1881 /* Check whether DAT[3:0] is 0000 */ 1882 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1883 sdhci_runtime_pm_put(host); 1884 1885 return !(present_state & SDHCI_DATA_LVL_MASK); 1886 } 1887 1888 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1889 { 1890 struct sdhci_host *host = mmc_priv(mmc); 1891 unsigned long flags; 1892 1893 spin_lock_irqsave(&host->lock, flags); 1894 host->flags |= SDHCI_HS400_TUNING; 1895 spin_unlock_irqrestore(&host->lock, flags); 1896 1897 return 0; 1898 } 1899 1900 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1901 { 1902 struct sdhci_host *host = mmc_priv(mmc); 1903 u16 ctrl; 1904 int tuning_loop_counter = MAX_TUNING_LOOP; 1905 int err = 0; 1906 unsigned long flags; 1907 unsigned int tuning_count = 0; 1908 bool hs400_tuning; 1909 1910 sdhci_runtime_pm_get(host); 1911 spin_lock_irqsave(&host->lock, flags); 1912 1913 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1914 host->flags &= ~SDHCI_HS400_TUNING; 1915 1916 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1917 tuning_count = host->tuning_count; 1918 1919 /* 1920 * The Host Controller needs tuning only in case of SDR104 mode 1921 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1922 * Capabilities register. 1923 * If the Host Controller supports the HS200 mode then the 1924 * tuning function has to be executed. 1925 */ 1926 switch (host->timing) { 1927 /* HS400 tuning is done in HS200 mode */ 1928 case MMC_TIMING_MMC_HS400: 1929 err = -EINVAL; 1930 goto out_unlock; 1931 1932 case MMC_TIMING_MMC_HS200: 1933 /* 1934 * Periodic re-tuning for HS400 is not expected to be needed, so 1935 * disable it here. 1936 */ 1937 if (hs400_tuning) 1938 tuning_count = 0; 1939 break; 1940 1941 case MMC_TIMING_UHS_SDR104: 1942 break; 1943 1944 case MMC_TIMING_UHS_SDR50: 1945 if (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1946 host->flags & SDHCI_SDR104_NEEDS_TUNING) 1947 break; 1948 /* FALLTHROUGH */ 1949 1950 default: 1951 goto out_unlock; 1952 } 1953 1954 if (host->ops->platform_execute_tuning) { 1955 spin_unlock_irqrestore(&host->lock, flags); 1956 err = host->ops->platform_execute_tuning(host, opcode); 1957 sdhci_runtime_pm_put(host); 1958 return err; 1959 } 1960 1961 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1962 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1963 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1964 1965 /* 1966 * As per the Host Controller spec v3.00, tuning command 1967 * generates Buffer Read Ready interrupt, so enable that. 1968 * 1969 * Note: The spec clearly says that when tuning sequence 1970 * is being performed, the controller does not generate 1971 * interrupts other than Buffer Read Ready interrupt. But 1972 * to make sure we don't hit a controller bug, we _only_ 1973 * enable Buffer Read Ready interrupt here. 1974 */ 1975 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1976 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1977 1978 /* 1979 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1980 * of loops reaches 40 times or a timeout of 150ms occurs. 1981 */ 1982 do { 1983 struct mmc_command cmd = {0}; 1984 struct mmc_request mrq = {NULL}; 1985 1986 cmd.opcode = opcode; 1987 cmd.arg = 0; 1988 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1989 cmd.retries = 0; 1990 cmd.data = NULL; 1991 cmd.error = 0; 1992 1993 if (tuning_loop_counter-- == 0) 1994 break; 1995 1996 mrq.cmd = &cmd; 1997 host->mrq = &mrq; 1998 1999 /* 2000 * In response to CMD19, the card sends 64 bytes of tuning 2001 * block to the Host Controller. So we set the block size 2002 * to 64 here. 2003 */ 2004 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 2005 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2006 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 2007 SDHCI_BLOCK_SIZE); 2008 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 2009 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 2010 SDHCI_BLOCK_SIZE); 2011 } else { 2012 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 2013 SDHCI_BLOCK_SIZE); 2014 } 2015 2016 /* 2017 * The tuning block is sent by the card to the host controller. 2018 * So we set the TRNS_READ bit in the Transfer Mode register. 2019 * This also takes care of setting DMA Enable and Multi Block 2020 * Select in the same register to 0. 2021 */ 2022 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2023 2024 sdhci_send_command(host, &cmd); 2025 2026 host->cmd = NULL; 2027 host->mrq = NULL; 2028 2029 spin_unlock_irqrestore(&host->lock, flags); 2030 /* Wait for Buffer Read Ready interrupt */ 2031 wait_event_interruptible_timeout(host->buf_ready_int, 2032 (host->tuning_done == 1), 2033 msecs_to_jiffies(50)); 2034 spin_lock_irqsave(&host->lock, flags); 2035 2036 if (!host->tuning_done) { 2037 pr_info(DRIVER_NAME ": Timeout waiting for " 2038 "Buffer Read Ready interrupt during tuning " 2039 "procedure, falling back to fixed sampling " 2040 "clock\n"); 2041 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2042 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2043 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2044 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2045 2046 err = -EIO; 2047 goto out; 2048 } 2049 2050 host->tuning_done = 0; 2051 2052 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2053 2054 /* eMMC spec does not require a delay between tuning cycles */ 2055 if (opcode == MMC_SEND_TUNING_BLOCK) 2056 mdelay(1); 2057 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 2058 2059 /* 2060 * The Host Driver has exhausted the maximum number of loops allowed, 2061 * so use fixed sampling frequency. 2062 */ 2063 if (tuning_loop_counter < 0) { 2064 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2065 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2066 } 2067 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 2068 pr_info(DRIVER_NAME ": Tuning procedure" 2069 " failed, falling back to fixed sampling" 2070 " clock\n"); 2071 err = -EIO; 2072 } 2073 2074 out: 2075 host->flags &= ~SDHCI_NEEDS_RETUNING; 2076 2077 if (tuning_count) { 2078 host->flags |= SDHCI_USING_RETUNING_TIMER; 2079 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ); 2080 } 2081 2082 /* 2083 * In case tuning fails, host controllers which support re-tuning can 2084 * try tuning again at a later time, when the re-tuning timer expires. 2085 * So for these controllers, we return 0. Since there might be other 2086 * controllers who do not have this capability, we return error for 2087 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2088 * a retuning timer to do the retuning for the card. 2089 */ 2090 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2091 err = 0; 2092 2093 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2094 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2095 out_unlock: 2096 spin_unlock_irqrestore(&host->lock, flags); 2097 sdhci_runtime_pm_put(host); 2098 2099 return err; 2100 } 2101 2102 2103 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2104 { 2105 /* Host Controller v3.00 defines preset value registers */ 2106 if (host->version < SDHCI_SPEC_300) 2107 return; 2108 2109 /* 2110 * We only enable or disable Preset Value if they are not already 2111 * enabled or disabled respectively. Otherwise, we bail out. 2112 */ 2113 if (host->preset_enabled != enable) { 2114 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2115 2116 if (enable) 2117 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2118 else 2119 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2120 2121 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2122 2123 if (enable) 2124 host->flags |= SDHCI_PV_ENABLED; 2125 else 2126 host->flags &= ~SDHCI_PV_ENABLED; 2127 2128 host->preset_enabled = enable; 2129 } 2130 } 2131 2132 static void sdhci_card_event(struct mmc_host *mmc) 2133 { 2134 struct sdhci_host *host = mmc_priv(mmc); 2135 unsigned long flags; 2136 int present; 2137 2138 /* First check if client has provided their own card event */ 2139 if (host->ops->card_event) 2140 host->ops->card_event(host); 2141 2142 present = sdhci_do_get_cd(host); 2143 2144 spin_lock_irqsave(&host->lock, flags); 2145 2146 /* Check host->mrq first in case we are runtime suspended */ 2147 if (host->mrq && !present) { 2148 pr_err("%s: Card removed during transfer!\n", 2149 mmc_hostname(host->mmc)); 2150 pr_err("%s: Resetting controller.\n", 2151 mmc_hostname(host->mmc)); 2152 2153 sdhci_do_reset(host, SDHCI_RESET_CMD); 2154 sdhci_do_reset(host, SDHCI_RESET_DATA); 2155 2156 host->mrq->cmd->error = -ENOMEDIUM; 2157 tasklet_schedule(&host->finish_tasklet); 2158 } 2159 2160 spin_unlock_irqrestore(&host->lock, flags); 2161 } 2162 2163 static const struct mmc_host_ops sdhci_ops = { 2164 .request = sdhci_request, 2165 .set_ios = sdhci_set_ios, 2166 .get_cd = sdhci_get_cd, 2167 .get_ro = sdhci_get_ro, 2168 .hw_reset = sdhci_hw_reset, 2169 .enable_sdio_irq = sdhci_enable_sdio_irq, 2170 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2171 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2172 .execute_tuning = sdhci_execute_tuning, 2173 .card_event = sdhci_card_event, 2174 .card_busy = sdhci_card_busy, 2175 }; 2176 2177 /*****************************************************************************\ 2178 * * 2179 * Tasklets * 2180 * * 2181 \*****************************************************************************/ 2182 2183 static void sdhci_tasklet_finish(unsigned long param) 2184 { 2185 struct sdhci_host *host; 2186 unsigned long flags; 2187 struct mmc_request *mrq; 2188 2189 host = (struct sdhci_host*)param; 2190 2191 spin_lock_irqsave(&host->lock, flags); 2192 2193 /* 2194 * If this tasklet gets rescheduled while running, it will 2195 * be run again afterwards but without any active request. 2196 */ 2197 if (!host->mrq) { 2198 spin_unlock_irqrestore(&host->lock, flags); 2199 return; 2200 } 2201 2202 del_timer(&host->timer); 2203 2204 mrq = host->mrq; 2205 2206 /* 2207 * The controller needs a reset of internal state machines 2208 * upon error conditions. 2209 */ 2210 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2211 ((mrq->cmd && mrq->cmd->error) || 2212 (mrq->sbc && mrq->sbc->error) || 2213 (mrq->data && ((mrq->data->error && !mrq->data->stop) || 2214 (mrq->data->stop && mrq->data->stop->error))) || 2215 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2216 2217 /* Some controllers need this kick or reset won't work here */ 2218 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2219 /* This is to force an update */ 2220 host->ops->set_clock(host, host->clock); 2221 2222 /* Spec says we should do both at the same time, but Ricoh 2223 controllers do not like that. */ 2224 sdhci_do_reset(host, SDHCI_RESET_CMD); 2225 sdhci_do_reset(host, SDHCI_RESET_DATA); 2226 } 2227 2228 host->mrq = NULL; 2229 host->cmd = NULL; 2230 host->data = NULL; 2231 2232 #ifndef SDHCI_USE_LEDS_CLASS 2233 sdhci_deactivate_led(host); 2234 #endif 2235 2236 mmiowb(); 2237 spin_unlock_irqrestore(&host->lock, flags); 2238 2239 mmc_request_done(host->mmc, mrq); 2240 sdhci_runtime_pm_put(host); 2241 } 2242 2243 static void sdhci_timeout_timer(unsigned long data) 2244 { 2245 struct sdhci_host *host; 2246 unsigned long flags; 2247 2248 host = (struct sdhci_host*)data; 2249 2250 spin_lock_irqsave(&host->lock, flags); 2251 2252 if (host->mrq) { 2253 pr_err("%s: Timeout waiting for hardware " 2254 "interrupt.\n", mmc_hostname(host->mmc)); 2255 sdhci_dumpregs(host); 2256 2257 if (host->data) { 2258 host->data->error = -ETIMEDOUT; 2259 sdhci_finish_data(host); 2260 } else { 2261 if (host->cmd) 2262 host->cmd->error = -ETIMEDOUT; 2263 else 2264 host->mrq->cmd->error = -ETIMEDOUT; 2265 2266 tasklet_schedule(&host->finish_tasklet); 2267 } 2268 } 2269 2270 mmiowb(); 2271 spin_unlock_irqrestore(&host->lock, flags); 2272 } 2273 2274 static void sdhci_tuning_timer(unsigned long data) 2275 { 2276 struct sdhci_host *host; 2277 unsigned long flags; 2278 2279 host = (struct sdhci_host *)data; 2280 2281 spin_lock_irqsave(&host->lock, flags); 2282 2283 host->flags |= SDHCI_NEEDS_RETUNING; 2284 2285 spin_unlock_irqrestore(&host->lock, flags); 2286 } 2287 2288 /*****************************************************************************\ 2289 * * 2290 * Interrupt handling * 2291 * * 2292 \*****************************************************************************/ 2293 2294 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 2295 { 2296 BUG_ON(intmask == 0); 2297 2298 if (!host->cmd) { 2299 pr_err("%s: Got command interrupt 0x%08x even " 2300 "though no command operation was in progress.\n", 2301 mmc_hostname(host->mmc), (unsigned)intmask); 2302 sdhci_dumpregs(host); 2303 return; 2304 } 2305 2306 if (intmask & SDHCI_INT_TIMEOUT) 2307 host->cmd->error = -ETIMEDOUT; 2308 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2309 SDHCI_INT_INDEX)) 2310 host->cmd->error = -EILSEQ; 2311 2312 if (host->cmd->error) { 2313 tasklet_schedule(&host->finish_tasklet); 2314 return; 2315 } 2316 2317 /* 2318 * The host can send and interrupt when the busy state has 2319 * ended, allowing us to wait without wasting CPU cycles. 2320 * Unfortunately this is overloaded on the "data complete" 2321 * interrupt, so we need to take some care when handling 2322 * it. 2323 * 2324 * Note: The 1.0 specification is a bit ambiguous about this 2325 * feature so there might be some problems with older 2326 * controllers. 2327 */ 2328 if (host->cmd->flags & MMC_RSP_BUSY) { 2329 if (host->cmd->data) 2330 DBG("Cannot wait for busy signal when also " 2331 "doing a data transfer"); 2332 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) 2333 && !host->busy_handle) { 2334 /* Mark that command complete before busy is ended */ 2335 host->busy_handle = 1; 2336 return; 2337 } 2338 2339 /* The controller does not support the end-of-busy IRQ, 2340 * fall through and take the SDHCI_INT_RESPONSE */ 2341 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 2342 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { 2343 *mask &= ~SDHCI_INT_DATA_END; 2344 } 2345 2346 if (intmask & SDHCI_INT_RESPONSE) 2347 sdhci_finish_command(host); 2348 } 2349 2350 #ifdef CONFIG_MMC_DEBUG 2351 static void sdhci_adma_show_error(struct sdhci_host *host) 2352 { 2353 const char *name = mmc_hostname(host->mmc); 2354 void *desc = host->adma_table; 2355 2356 sdhci_dumpregs(host); 2357 2358 while (true) { 2359 struct sdhci_adma2_64_desc *dma_desc = desc; 2360 2361 if (host->flags & SDHCI_USE_64_BIT_DMA) 2362 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2363 name, desc, le32_to_cpu(dma_desc->addr_hi), 2364 le32_to_cpu(dma_desc->addr_lo), 2365 le16_to_cpu(dma_desc->len), 2366 le16_to_cpu(dma_desc->cmd)); 2367 else 2368 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2369 name, desc, le32_to_cpu(dma_desc->addr_lo), 2370 le16_to_cpu(dma_desc->len), 2371 le16_to_cpu(dma_desc->cmd)); 2372 2373 desc += host->desc_sz; 2374 2375 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2376 break; 2377 } 2378 } 2379 #else 2380 static void sdhci_adma_show_error(struct sdhci_host *host) { } 2381 #endif 2382 2383 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2384 { 2385 u32 command; 2386 BUG_ON(intmask == 0); 2387 2388 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2389 if (intmask & SDHCI_INT_DATA_AVAIL) { 2390 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2391 if (command == MMC_SEND_TUNING_BLOCK || 2392 command == MMC_SEND_TUNING_BLOCK_HS200) { 2393 host->tuning_done = 1; 2394 wake_up(&host->buf_ready_int); 2395 return; 2396 } 2397 } 2398 2399 if (!host->data) { 2400 /* 2401 * The "data complete" interrupt is also used to 2402 * indicate that a busy state has ended. See comment 2403 * above in sdhci_cmd_irq(). 2404 */ 2405 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2406 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2407 host->cmd->error = -ETIMEDOUT; 2408 tasklet_schedule(&host->finish_tasklet); 2409 return; 2410 } 2411 if (intmask & SDHCI_INT_DATA_END) { 2412 /* 2413 * Some cards handle busy-end interrupt 2414 * before the command completed, so make 2415 * sure we do things in the proper order. 2416 */ 2417 if (host->busy_handle) 2418 sdhci_finish_command(host); 2419 else 2420 host->busy_handle = 1; 2421 return; 2422 } 2423 } 2424 2425 pr_err("%s: Got data interrupt 0x%08x even " 2426 "though no data operation was in progress.\n", 2427 mmc_hostname(host->mmc), (unsigned)intmask); 2428 sdhci_dumpregs(host); 2429 2430 return; 2431 } 2432 2433 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2434 host->data->error = -ETIMEDOUT; 2435 else if (intmask & SDHCI_INT_DATA_END_BIT) 2436 host->data->error = -EILSEQ; 2437 else if ((intmask & SDHCI_INT_DATA_CRC) && 2438 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2439 != MMC_BUS_TEST_R) 2440 host->data->error = -EILSEQ; 2441 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2442 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2443 sdhci_adma_show_error(host); 2444 host->data->error = -EIO; 2445 if (host->ops->adma_workaround) 2446 host->ops->adma_workaround(host, intmask); 2447 } 2448 2449 if (host->data->error) 2450 sdhci_finish_data(host); 2451 else { 2452 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2453 sdhci_transfer_pio(host); 2454 2455 /* 2456 * We currently don't do anything fancy with DMA 2457 * boundaries, but as we can't disable the feature 2458 * we need to at least restart the transfer. 2459 * 2460 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2461 * should return a valid address to continue from, but as 2462 * some controllers are faulty, don't trust them. 2463 */ 2464 if (intmask & SDHCI_INT_DMA_END) { 2465 u32 dmastart, dmanow; 2466 dmastart = sg_dma_address(host->data->sg); 2467 dmanow = dmastart + host->data->bytes_xfered; 2468 /* 2469 * Force update to the next DMA block boundary. 2470 */ 2471 dmanow = (dmanow & 2472 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2473 SDHCI_DEFAULT_BOUNDARY_SIZE; 2474 host->data->bytes_xfered = dmanow - dmastart; 2475 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2476 " next 0x%08x\n", 2477 mmc_hostname(host->mmc), dmastart, 2478 host->data->bytes_xfered, dmanow); 2479 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2480 } 2481 2482 if (intmask & SDHCI_INT_DATA_END) { 2483 if (host->cmd) { 2484 /* 2485 * Data managed to finish before the 2486 * command completed. Make sure we do 2487 * things in the proper order. 2488 */ 2489 host->data_early = 1; 2490 } else { 2491 sdhci_finish_data(host); 2492 } 2493 } 2494 } 2495 } 2496 2497 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2498 { 2499 irqreturn_t result = IRQ_NONE; 2500 struct sdhci_host *host = dev_id; 2501 u32 intmask, mask, unexpected = 0; 2502 int max_loops = 16; 2503 2504 spin_lock(&host->lock); 2505 2506 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2507 spin_unlock(&host->lock); 2508 return IRQ_NONE; 2509 } 2510 2511 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2512 if (!intmask || intmask == 0xffffffff) { 2513 result = IRQ_NONE; 2514 goto out; 2515 } 2516 2517 do { 2518 /* Clear selected interrupts. */ 2519 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2520 SDHCI_INT_BUS_POWER); 2521 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2522 2523 DBG("*** %s got interrupt: 0x%08x\n", 2524 mmc_hostname(host->mmc), intmask); 2525 2526 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2527 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2528 SDHCI_CARD_PRESENT; 2529 2530 /* 2531 * There is a observation on i.mx esdhc. INSERT 2532 * bit will be immediately set again when it gets 2533 * cleared, if a card is inserted. We have to mask 2534 * the irq to prevent interrupt storm which will 2535 * freeze the system. And the REMOVE gets the 2536 * same situation. 2537 * 2538 * More testing are needed here to ensure it works 2539 * for other platforms though. 2540 */ 2541 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2542 SDHCI_INT_CARD_REMOVE); 2543 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2544 SDHCI_INT_CARD_INSERT; 2545 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2546 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2547 2548 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2549 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2550 2551 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2552 SDHCI_INT_CARD_REMOVE); 2553 result = IRQ_WAKE_THREAD; 2554 } 2555 2556 if (intmask & SDHCI_INT_CMD_MASK) 2557 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, 2558 &intmask); 2559 2560 if (intmask & SDHCI_INT_DATA_MASK) 2561 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2562 2563 if (intmask & SDHCI_INT_BUS_POWER) 2564 pr_err("%s: Card is consuming too much power!\n", 2565 mmc_hostname(host->mmc)); 2566 2567 if (intmask & SDHCI_INT_CARD_INT) { 2568 sdhci_enable_sdio_irq_nolock(host, false); 2569 host->thread_isr |= SDHCI_INT_CARD_INT; 2570 result = IRQ_WAKE_THREAD; 2571 } 2572 2573 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2574 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2575 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2576 SDHCI_INT_CARD_INT); 2577 2578 if (intmask) { 2579 unexpected |= intmask; 2580 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2581 } 2582 2583 if (result == IRQ_NONE) 2584 result = IRQ_HANDLED; 2585 2586 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2587 } while (intmask && --max_loops); 2588 out: 2589 spin_unlock(&host->lock); 2590 2591 if (unexpected) { 2592 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2593 mmc_hostname(host->mmc), unexpected); 2594 sdhci_dumpregs(host); 2595 } 2596 2597 return result; 2598 } 2599 2600 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2601 { 2602 struct sdhci_host *host = dev_id; 2603 unsigned long flags; 2604 u32 isr; 2605 2606 spin_lock_irqsave(&host->lock, flags); 2607 isr = host->thread_isr; 2608 host->thread_isr = 0; 2609 spin_unlock_irqrestore(&host->lock, flags); 2610 2611 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2612 sdhci_card_event(host->mmc); 2613 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2614 } 2615 2616 if (isr & SDHCI_INT_CARD_INT) { 2617 sdio_run_irqs(host->mmc); 2618 2619 spin_lock_irqsave(&host->lock, flags); 2620 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2621 sdhci_enable_sdio_irq_nolock(host, true); 2622 spin_unlock_irqrestore(&host->lock, flags); 2623 } 2624 2625 return isr ? IRQ_HANDLED : IRQ_NONE; 2626 } 2627 2628 /*****************************************************************************\ 2629 * * 2630 * Suspend/resume * 2631 * * 2632 \*****************************************************************************/ 2633 2634 #ifdef CONFIG_PM 2635 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2636 { 2637 u8 val; 2638 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2639 | SDHCI_WAKE_ON_INT; 2640 2641 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2642 val |= mask ; 2643 /* Avoid fake wake up */ 2644 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2645 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2646 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2647 } 2648 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2649 2650 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2651 { 2652 u8 val; 2653 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2654 | SDHCI_WAKE_ON_INT; 2655 2656 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2657 val &= ~mask; 2658 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2659 } 2660 2661 int sdhci_suspend_host(struct sdhci_host *host) 2662 { 2663 sdhci_disable_card_detection(host); 2664 2665 /* Disable tuning since we are suspending */ 2666 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2667 del_timer_sync(&host->tuning_timer); 2668 host->flags &= ~SDHCI_NEEDS_RETUNING; 2669 } 2670 2671 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2672 host->ier = 0; 2673 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2674 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2675 free_irq(host->irq, host); 2676 } else { 2677 sdhci_enable_irq_wakeups(host); 2678 enable_irq_wake(host->irq); 2679 } 2680 return 0; 2681 } 2682 2683 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2684 2685 int sdhci_resume_host(struct sdhci_host *host) 2686 { 2687 int ret = 0; 2688 2689 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2690 if (host->ops->enable_dma) 2691 host->ops->enable_dma(host); 2692 } 2693 2694 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2695 ret = request_threaded_irq(host->irq, sdhci_irq, 2696 sdhci_thread_irq, IRQF_SHARED, 2697 mmc_hostname(host->mmc), host); 2698 if (ret) 2699 return ret; 2700 } else { 2701 sdhci_disable_irq_wakeups(host); 2702 disable_irq_wake(host->irq); 2703 } 2704 2705 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2706 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2707 /* Card keeps power but host controller does not */ 2708 sdhci_init(host, 0); 2709 host->pwr = 0; 2710 host->clock = 0; 2711 sdhci_do_set_ios(host, &host->mmc->ios); 2712 } else { 2713 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2714 mmiowb(); 2715 } 2716 2717 sdhci_enable_card_detection(host); 2718 2719 /* Set the re-tuning expiration flag */ 2720 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2721 host->flags |= SDHCI_NEEDS_RETUNING; 2722 2723 return ret; 2724 } 2725 2726 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2727 2728 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2729 { 2730 return pm_runtime_get_sync(host->mmc->parent); 2731 } 2732 2733 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2734 { 2735 pm_runtime_mark_last_busy(host->mmc->parent); 2736 return pm_runtime_put_autosuspend(host->mmc->parent); 2737 } 2738 2739 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2740 { 2741 if (host->runtime_suspended || host->bus_on) 2742 return; 2743 host->bus_on = true; 2744 pm_runtime_get_noresume(host->mmc->parent); 2745 } 2746 2747 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2748 { 2749 if (host->runtime_suspended || !host->bus_on) 2750 return; 2751 host->bus_on = false; 2752 pm_runtime_put_noidle(host->mmc->parent); 2753 } 2754 2755 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2756 { 2757 unsigned long flags; 2758 2759 /* Disable tuning since we are suspending */ 2760 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2761 del_timer_sync(&host->tuning_timer); 2762 host->flags &= ~SDHCI_NEEDS_RETUNING; 2763 } 2764 2765 spin_lock_irqsave(&host->lock, flags); 2766 host->ier &= SDHCI_INT_CARD_INT; 2767 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2768 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2769 spin_unlock_irqrestore(&host->lock, flags); 2770 2771 synchronize_hardirq(host->irq); 2772 2773 spin_lock_irqsave(&host->lock, flags); 2774 host->runtime_suspended = true; 2775 spin_unlock_irqrestore(&host->lock, flags); 2776 2777 return 0; 2778 } 2779 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2780 2781 int sdhci_runtime_resume_host(struct sdhci_host *host) 2782 { 2783 unsigned long flags; 2784 int host_flags = host->flags; 2785 2786 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2787 if (host->ops->enable_dma) 2788 host->ops->enable_dma(host); 2789 } 2790 2791 sdhci_init(host, 0); 2792 2793 /* Force clock and power re-program */ 2794 host->pwr = 0; 2795 host->clock = 0; 2796 sdhci_do_set_ios(host, &host->mmc->ios); 2797 2798 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2799 if ((host_flags & SDHCI_PV_ENABLED) && 2800 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2801 spin_lock_irqsave(&host->lock, flags); 2802 sdhci_enable_preset_value(host, true); 2803 spin_unlock_irqrestore(&host->lock, flags); 2804 } 2805 2806 /* Set the re-tuning expiration flag */ 2807 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2808 host->flags |= SDHCI_NEEDS_RETUNING; 2809 2810 spin_lock_irqsave(&host->lock, flags); 2811 2812 host->runtime_suspended = false; 2813 2814 /* Enable SDIO IRQ */ 2815 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2816 sdhci_enable_sdio_irq_nolock(host, true); 2817 2818 /* Enable Card Detection */ 2819 sdhci_enable_card_detection(host); 2820 2821 spin_unlock_irqrestore(&host->lock, flags); 2822 2823 return 0; 2824 } 2825 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2826 2827 #endif /* CONFIG_PM */ 2828 2829 /*****************************************************************************\ 2830 * * 2831 * Device allocation/registration * 2832 * * 2833 \*****************************************************************************/ 2834 2835 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2836 size_t priv_size) 2837 { 2838 struct mmc_host *mmc; 2839 struct sdhci_host *host; 2840 2841 WARN_ON(dev == NULL); 2842 2843 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2844 if (!mmc) 2845 return ERR_PTR(-ENOMEM); 2846 2847 host = mmc_priv(mmc); 2848 host->mmc = mmc; 2849 2850 return host; 2851 } 2852 2853 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2854 2855 int sdhci_add_host(struct sdhci_host *host) 2856 { 2857 struct mmc_host *mmc; 2858 u32 caps[2] = {0, 0}; 2859 u32 max_current_caps; 2860 unsigned int ocr_avail; 2861 unsigned int override_timeout_clk; 2862 int ret; 2863 2864 WARN_ON(host == NULL); 2865 if (host == NULL) 2866 return -EINVAL; 2867 2868 mmc = host->mmc; 2869 2870 if (debug_quirks) 2871 host->quirks = debug_quirks; 2872 if (debug_quirks2) 2873 host->quirks2 = debug_quirks2; 2874 2875 override_timeout_clk = host->timeout_clk; 2876 2877 sdhci_do_reset(host, SDHCI_RESET_ALL); 2878 2879 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2880 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2881 >> SDHCI_SPEC_VER_SHIFT; 2882 if (host->version > SDHCI_SPEC_300) { 2883 pr_err("%s: Unknown controller version (%d). " 2884 "You may experience problems.\n", mmc_hostname(mmc), 2885 host->version); 2886 } 2887 2888 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2889 sdhci_readl(host, SDHCI_CAPABILITIES); 2890 2891 if (host->version >= SDHCI_SPEC_300) 2892 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2893 host->caps1 : 2894 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2895 2896 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2897 host->flags |= SDHCI_USE_SDMA; 2898 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2899 DBG("Controller doesn't have SDMA capability\n"); 2900 else 2901 host->flags |= SDHCI_USE_SDMA; 2902 2903 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2904 (host->flags & SDHCI_USE_SDMA)) { 2905 DBG("Disabling DMA as it is marked broken\n"); 2906 host->flags &= ~SDHCI_USE_SDMA; 2907 } 2908 2909 if ((host->version >= SDHCI_SPEC_200) && 2910 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2911 host->flags |= SDHCI_USE_ADMA; 2912 2913 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2914 (host->flags & SDHCI_USE_ADMA)) { 2915 DBG("Disabling ADMA as it is marked broken\n"); 2916 host->flags &= ~SDHCI_USE_ADMA; 2917 } 2918 2919 /* 2920 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 2921 * and *must* do 64-bit DMA. A driver has the opportunity to change 2922 * that during the first call to ->enable_dma(). Similarly 2923 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 2924 * implement. 2925 */ 2926 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) 2927 host->flags |= SDHCI_USE_64_BIT_DMA; 2928 2929 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2930 if (host->ops->enable_dma) { 2931 if (host->ops->enable_dma(host)) { 2932 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 2933 mmc_hostname(mmc)); 2934 host->flags &= 2935 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2936 } 2937 } 2938 } 2939 2940 /* SDMA does not support 64-bit DMA */ 2941 if (host->flags & SDHCI_USE_64_BIT_DMA) 2942 host->flags &= ~SDHCI_USE_SDMA; 2943 2944 if (host->flags & SDHCI_USE_ADMA) { 2945 /* 2946 * The DMA descriptor table size is calculated as the maximum 2947 * number of segments times 2, to allow for an alignment 2948 * descriptor for each segment, plus 1 for a nop end descriptor, 2949 * all multipled by the descriptor size. 2950 */ 2951 if (host->flags & SDHCI_USE_64_BIT_DMA) { 2952 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 2953 SDHCI_ADMA2_64_DESC_SZ; 2954 host->align_buffer_sz = SDHCI_MAX_SEGS * 2955 SDHCI_ADMA2_64_ALIGN; 2956 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 2957 host->align_sz = SDHCI_ADMA2_64_ALIGN; 2958 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1; 2959 } else { 2960 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 2961 SDHCI_ADMA2_32_DESC_SZ; 2962 host->align_buffer_sz = SDHCI_MAX_SEGS * 2963 SDHCI_ADMA2_32_ALIGN; 2964 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 2965 host->align_sz = SDHCI_ADMA2_32_ALIGN; 2966 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1; 2967 } 2968 host->adma_table = dma_alloc_coherent(mmc_dev(mmc), 2969 host->adma_table_sz, 2970 &host->adma_addr, 2971 GFP_KERNEL); 2972 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL); 2973 if (!host->adma_table || !host->align_buffer) { 2974 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, 2975 host->adma_table, host->adma_addr); 2976 kfree(host->align_buffer); 2977 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 2978 mmc_hostname(mmc)); 2979 host->flags &= ~SDHCI_USE_ADMA; 2980 host->adma_table = NULL; 2981 host->align_buffer = NULL; 2982 } else if (host->adma_addr & host->align_mask) { 2983 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 2984 mmc_hostname(mmc)); 2985 host->flags &= ~SDHCI_USE_ADMA; 2986 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, 2987 host->adma_table, host->adma_addr); 2988 kfree(host->align_buffer); 2989 host->adma_table = NULL; 2990 host->align_buffer = NULL; 2991 } 2992 } 2993 2994 /* 2995 * If we use DMA, then it's up to the caller to set the DMA 2996 * mask, but PIO does not need the hw shim so we set a new 2997 * mask here in that case. 2998 */ 2999 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 3000 host->dma_mask = DMA_BIT_MASK(64); 3001 mmc_dev(mmc)->dma_mask = &host->dma_mask; 3002 } 3003 3004 if (host->version >= SDHCI_SPEC_300) 3005 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 3006 >> SDHCI_CLOCK_BASE_SHIFT; 3007 else 3008 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 3009 >> SDHCI_CLOCK_BASE_SHIFT; 3010 3011 host->max_clk *= 1000000; 3012 if (host->max_clk == 0 || host->quirks & 3013 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 3014 if (!host->ops->get_max_clock) { 3015 pr_err("%s: Hardware doesn't specify base clock " 3016 "frequency.\n", mmc_hostname(mmc)); 3017 return -ENODEV; 3018 } 3019 host->max_clk = host->ops->get_max_clock(host); 3020 } 3021 3022 /* 3023 * In case of Host Controller v3.00, find out whether clock 3024 * multiplier is supported. 3025 */ 3026 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 3027 SDHCI_CLOCK_MUL_SHIFT; 3028 3029 /* 3030 * In case the value in Clock Multiplier is 0, then programmable 3031 * clock mode is not supported, otherwise the actual clock 3032 * multiplier is one more than the value of Clock Multiplier 3033 * in the Capabilities Register. 3034 */ 3035 if (host->clk_mul) 3036 host->clk_mul += 1; 3037 3038 /* 3039 * Set host parameters. 3040 */ 3041 mmc->ops = &sdhci_ops; 3042 mmc->f_max = host->max_clk; 3043 if (host->ops->get_min_clock) 3044 mmc->f_min = host->ops->get_min_clock(host); 3045 else if (host->version >= SDHCI_SPEC_300) { 3046 if (host->clk_mul) { 3047 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3048 mmc->f_max = host->max_clk * host->clk_mul; 3049 } else 3050 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3051 } else 3052 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3053 3054 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3055 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> 3056 SDHCI_TIMEOUT_CLK_SHIFT; 3057 if (host->timeout_clk == 0) { 3058 if (host->ops->get_timeout_clock) { 3059 host->timeout_clk = 3060 host->ops->get_timeout_clock(host); 3061 } else { 3062 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3063 mmc_hostname(mmc)); 3064 return -ENODEV; 3065 } 3066 } 3067 3068 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 3069 host->timeout_clk *= 1000; 3070 3071 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3072 host->ops->get_max_timeout_count(host) : 1 << 27; 3073 mmc->max_busy_timeout /= host->timeout_clk; 3074 } 3075 3076 if (override_timeout_clk) 3077 host->timeout_clk = override_timeout_clk; 3078 3079 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3080 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3081 3082 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3083 host->flags |= SDHCI_AUTO_CMD12; 3084 3085 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 3086 if ((host->version >= SDHCI_SPEC_300) && 3087 ((host->flags & SDHCI_USE_ADMA) || 3088 !(host->flags & SDHCI_USE_SDMA))) { 3089 host->flags |= SDHCI_AUTO_CMD23; 3090 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 3091 } else { 3092 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 3093 } 3094 3095 /* 3096 * A controller may support 8-bit width, but the board itself 3097 * might not have the pins brought out. Boards that support 3098 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3099 * their platform code before calling sdhci_add_host(), and we 3100 * won't assume 8-bit width for hosts without that CAP. 3101 */ 3102 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3103 mmc->caps |= MMC_CAP_4_BIT_DATA; 3104 3105 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3106 mmc->caps &= ~MMC_CAP_CMD23; 3107 3108 if (caps[0] & SDHCI_CAN_DO_HISPD) 3109 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3110 3111 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3112 !(mmc->caps & MMC_CAP_NONREMOVABLE)) 3113 mmc->caps |= MMC_CAP_NEEDS_POLL; 3114 3115 /* If there are external regulators, get them */ 3116 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) 3117 return -EPROBE_DEFER; 3118 3119 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3120 if (!IS_ERR(mmc->supply.vqmmc)) { 3121 ret = regulator_enable(mmc->supply.vqmmc); 3122 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3123 1950000)) 3124 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 3125 SDHCI_SUPPORT_SDR50 | 3126 SDHCI_SUPPORT_DDR50); 3127 if (ret) { 3128 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3129 mmc_hostname(mmc), ret); 3130 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3131 } 3132 } 3133 3134 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 3135 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3136 SDHCI_SUPPORT_DDR50); 3137 3138 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3139 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3140 SDHCI_SUPPORT_DDR50)) 3141 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3142 3143 /* SDR104 supports also implies SDR50 support */ 3144 if (caps[1] & SDHCI_SUPPORT_SDR104) { 3145 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3146 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3147 * field can be promoted to support HS200. 3148 */ 3149 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3150 mmc->caps2 |= MMC_CAP2_HS200; 3151 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3152 mmc->caps |= MMC_CAP_UHS_SDR50; 3153 3154 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3155 (caps[1] & SDHCI_SUPPORT_HS400)) 3156 mmc->caps2 |= MMC_CAP2_HS400; 3157 3158 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3159 (IS_ERR(mmc->supply.vqmmc) || 3160 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3161 1300000))) 3162 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3163 3164 if ((caps[1] & SDHCI_SUPPORT_DDR50) && 3165 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3166 mmc->caps |= MMC_CAP_UHS_DDR50; 3167 3168 /* Does the host need tuning for SDR50? */ 3169 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3170 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3171 3172 /* Does the host need tuning for SDR104 / HS200? */ 3173 if (mmc->caps2 & MMC_CAP2_HS200) 3174 host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3175 3176 /* Driver Type(s) (A, C, D) supported by the host */ 3177 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3178 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3179 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3180 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3181 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3182 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3183 3184 /* Initial value for re-tuning timer count */ 3185 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3186 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3187 3188 /* 3189 * In case Re-tuning Timer is not disabled, the actual value of 3190 * re-tuning timer will be 2 ^ (n - 1). 3191 */ 3192 if (host->tuning_count) 3193 host->tuning_count = 1 << (host->tuning_count - 1); 3194 3195 /* Re-tuning mode supported by the Host Controller */ 3196 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3197 SDHCI_RETUNING_MODE_SHIFT; 3198 3199 ocr_avail = 0; 3200 3201 /* 3202 * According to SD Host Controller spec v3.00, if the Host System 3203 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3204 * the value is meaningful only if Voltage Support in the Capabilities 3205 * register is set. The actual current value is 4 times the register 3206 * value. 3207 */ 3208 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3209 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3210 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3211 if (curr > 0) { 3212 3213 /* convert to SDHCI_MAX_CURRENT format */ 3214 curr = curr/1000; /* convert to mA */ 3215 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3216 3217 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3218 max_current_caps = 3219 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3220 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3221 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3222 } 3223 } 3224 3225 if (caps[0] & SDHCI_CAN_VDD_330) { 3226 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3227 3228 mmc->max_current_330 = ((max_current_caps & 3229 SDHCI_MAX_CURRENT_330_MASK) >> 3230 SDHCI_MAX_CURRENT_330_SHIFT) * 3231 SDHCI_MAX_CURRENT_MULTIPLIER; 3232 } 3233 if (caps[0] & SDHCI_CAN_VDD_300) { 3234 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3235 3236 mmc->max_current_300 = ((max_current_caps & 3237 SDHCI_MAX_CURRENT_300_MASK) >> 3238 SDHCI_MAX_CURRENT_300_SHIFT) * 3239 SDHCI_MAX_CURRENT_MULTIPLIER; 3240 } 3241 if (caps[0] & SDHCI_CAN_VDD_180) { 3242 ocr_avail |= MMC_VDD_165_195; 3243 3244 mmc->max_current_180 = ((max_current_caps & 3245 SDHCI_MAX_CURRENT_180_MASK) >> 3246 SDHCI_MAX_CURRENT_180_SHIFT) * 3247 SDHCI_MAX_CURRENT_MULTIPLIER; 3248 } 3249 3250 /* If OCR set by external regulators, use it instead */ 3251 if (mmc->ocr_avail) 3252 ocr_avail = mmc->ocr_avail; 3253 3254 if (host->ocr_mask) 3255 ocr_avail &= host->ocr_mask; 3256 3257 mmc->ocr_avail = ocr_avail; 3258 mmc->ocr_avail_sdio = ocr_avail; 3259 if (host->ocr_avail_sdio) 3260 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3261 mmc->ocr_avail_sd = ocr_avail; 3262 if (host->ocr_avail_sd) 3263 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3264 else /* normal SD controllers don't support 1.8V */ 3265 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3266 mmc->ocr_avail_mmc = ocr_avail; 3267 if (host->ocr_avail_mmc) 3268 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3269 3270 if (mmc->ocr_avail == 0) { 3271 pr_err("%s: Hardware doesn't report any " 3272 "support voltages.\n", mmc_hostname(mmc)); 3273 return -ENODEV; 3274 } 3275 3276 spin_lock_init(&host->lock); 3277 3278 /* 3279 * Maximum number of segments. Depends on if the hardware 3280 * can do scatter/gather or not. 3281 */ 3282 if (host->flags & SDHCI_USE_ADMA) 3283 mmc->max_segs = SDHCI_MAX_SEGS; 3284 else if (host->flags & SDHCI_USE_SDMA) 3285 mmc->max_segs = 1; 3286 else /* PIO */ 3287 mmc->max_segs = SDHCI_MAX_SEGS; 3288 3289 /* 3290 * Maximum number of sectors in one transfer. Limited by SDMA boundary 3291 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3292 * is less anyway. 3293 */ 3294 mmc->max_req_size = 524288; 3295 3296 /* 3297 * Maximum segment size. Could be one segment with the maximum number 3298 * of bytes. When doing hardware scatter/gather, each entry cannot 3299 * be larger than 64 KiB though. 3300 */ 3301 if (host->flags & SDHCI_USE_ADMA) { 3302 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3303 mmc->max_seg_size = 65535; 3304 else 3305 mmc->max_seg_size = 65536; 3306 } else { 3307 mmc->max_seg_size = mmc->max_req_size; 3308 } 3309 3310 /* 3311 * Maximum block size. This varies from controller to controller and 3312 * is specified in the capabilities register. 3313 */ 3314 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3315 mmc->max_blk_size = 2; 3316 } else { 3317 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3318 SDHCI_MAX_BLOCK_SHIFT; 3319 if (mmc->max_blk_size >= 3) { 3320 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3321 mmc_hostname(mmc)); 3322 mmc->max_blk_size = 0; 3323 } 3324 } 3325 3326 mmc->max_blk_size = 512 << mmc->max_blk_size; 3327 3328 /* 3329 * Maximum block count. 3330 */ 3331 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3332 3333 /* 3334 * Init tasklets. 3335 */ 3336 tasklet_init(&host->finish_tasklet, 3337 sdhci_tasklet_finish, (unsigned long)host); 3338 3339 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3340 3341 if (host->version >= SDHCI_SPEC_300) { 3342 init_waitqueue_head(&host->buf_ready_int); 3343 3344 /* Initialize re-tuning timer */ 3345 init_timer(&host->tuning_timer); 3346 host->tuning_timer.data = (unsigned long)host; 3347 host->tuning_timer.function = sdhci_tuning_timer; 3348 } 3349 3350 sdhci_init(host, 0); 3351 3352 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3353 IRQF_SHARED, mmc_hostname(mmc), host); 3354 if (ret) { 3355 pr_err("%s: Failed to request IRQ %d: %d\n", 3356 mmc_hostname(mmc), host->irq, ret); 3357 goto untasklet; 3358 } 3359 3360 #ifdef CONFIG_MMC_DEBUG 3361 sdhci_dumpregs(host); 3362 #endif 3363 3364 #ifdef SDHCI_USE_LEDS_CLASS 3365 snprintf(host->led_name, sizeof(host->led_name), 3366 "%s::", mmc_hostname(mmc)); 3367 host->led.name = host->led_name; 3368 host->led.brightness = LED_OFF; 3369 host->led.default_trigger = mmc_hostname(mmc); 3370 host->led.brightness_set = sdhci_led_control; 3371 3372 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3373 if (ret) { 3374 pr_err("%s: Failed to register LED device: %d\n", 3375 mmc_hostname(mmc), ret); 3376 goto reset; 3377 } 3378 #endif 3379 3380 mmiowb(); 3381 3382 mmc_add_host(mmc); 3383 3384 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3385 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3386 (host->flags & SDHCI_USE_ADMA) ? 3387 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3388 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3389 3390 sdhci_enable_card_detection(host); 3391 3392 return 0; 3393 3394 #ifdef SDHCI_USE_LEDS_CLASS 3395 reset: 3396 sdhci_do_reset(host, SDHCI_RESET_ALL); 3397 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3398 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3399 free_irq(host->irq, host); 3400 #endif 3401 untasklet: 3402 tasklet_kill(&host->finish_tasklet); 3403 3404 return ret; 3405 } 3406 3407 EXPORT_SYMBOL_GPL(sdhci_add_host); 3408 3409 void sdhci_remove_host(struct sdhci_host *host, int dead) 3410 { 3411 struct mmc_host *mmc = host->mmc; 3412 unsigned long flags; 3413 3414 if (dead) { 3415 spin_lock_irqsave(&host->lock, flags); 3416 3417 host->flags |= SDHCI_DEVICE_DEAD; 3418 3419 if (host->mrq) { 3420 pr_err("%s: Controller removed during " 3421 " transfer!\n", mmc_hostname(mmc)); 3422 3423 host->mrq->cmd->error = -ENOMEDIUM; 3424 tasklet_schedule(&host->finish_tasklet); 3425 } 3426 3427 spin_unlock_irqrestore(&host->lock, flags); 3428 } 3429 3430 sdhci_disable_card_detection(host); 3431 3432 mmc_remove_host(mmc); 3433 3434 #ifdef SDHCI_USE_LEDS_CLASS 3435 led_classdev_unregister(&host->led); 3436 #endif 3437 3438 if (!dead) 3439 sdhci_do_reset(host, SDHCI_RESET_ALL); 3440 3441 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3442 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3443 free_irq(host->irq, host); 3444 3445 del_timer_sync(&host->timer); 3446 3447 tasklet_kill(&host->finish_tasklet); 3448 3449 if (!IS_ERR(mmc->supply.vqmmc)) 3450 regulator_disable(mmc->supply.vqmmc); 3451 3452 if (host->adma_table) 3453 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, 3454 host->adma_table, host->adma_addr); 3455 kfree(host->align_buffer); 3456 3457 host->adma_table = NULL; 3458 host->align_buffer = NULL; 3459 } 3460 3461 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3462 3463 void sdhci_free_host(struct sdhci_host *host) 3464 { 3465 mmc_free_host(host->mmc); 3466 } 3467 3468 EXPORT_SYMBOL_GPL(sdhci_free_host); 3469 3470 /*****************************************************************************\ 3471 * * 3472 * Driver init/exit * 3473 * * 3474 \*****************************************************************************/ 3475 3476 static int __init sdhci_drv_init(void) 3477 { 3478 pr_info(DRIVER_NAME 3479 ": Secure Digital Host Controller Interface driver\n"); 3480 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3481 3482 return 0; 3483 } 3484 3485 static void __exit sdhci_drv_exit(void) 3486 { 3487 } 3488 3489 module_init(sdhci_drv_init); 3490 module_exit(sdhci_drv_exit); 3491 3492 module_param(debug_quirks, uint, 0444); 3493 module_param(debug_quirks2, uint, 0444); 3494 3495 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3496 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3497 MODULE_LICENSE("GPL"); 3498 3499 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3500 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3501