1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #include "sdhci.h" 35 36 #define DRIVER_NAME "sdhci" 37 38 #define DBG(f, x...) \ 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 40 41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 42 defined(CONFIG_MMC_SDHCI_MODULE)) 43 #define SDHCI_USE_LEDS_CLASS 44 #endif 45 46 #define MAX_TUNING_LOOP 40 47 48 static unsigned int debug_quirks = 0; 49 static unsigned int debug_quirks2; 50 51 static void sdhci_finish_data(struct sdhci_host *); 52 53 static void sdhci_finish_command(struct sdhci_host *); 54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 56 static int sdhci_do_get_cd(struct sdhci_host *host); 57 58 #ifdef CONFIG_PM 59 static int sdhci_runtime_pm_get(struct sdhci_host *host); 60 static int sdhci_runtime_pm_put(struct sdhci_host *host); 61 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 62 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 63 #else 64 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 65 { 66 return 0; 67 } 68 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 69 { 70 return 0; 71 } 72 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 73 { 74 } 75 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 76 { 77 } 78 #endif 79 80 static void sdhci_dumpregs(struct sdhci_host *host) 81 { 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 83 mmc_hostname(host->mmc)); 84 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 86 sdhci_readl(host, SDHCI_DMA_ADDRESS), 87 sdhci_readw(host, SDHCI_HOST_VERSION)); 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 89 sdhci_readw(host, SDHCI_BLOCK_SIZE), 90 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 92 sdhci_readl(host, SDHCI_ARGUMENT), 93 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 95 sdhci_readl(host, SDHCI_PRESENT_STATE), 96 sdhci_readb(host, SDHCI_HOST_CONTROL)); 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 98 sdhci_readb(host, SDHCI_POWER_CONTROL), 99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 102 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 105 sdhci_readl(host, SDHCI_INT_STATUS)); 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 107 sdhci_readl(host, SDHCI_INT_ENABLE), 108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 110 sdhci_readw(host, SDHCI_ACMD12_ERR), 111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 113 sdhci_readl(host, SDHCI_CAPABILITIES), 114 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 116 sdhci_readw(host, SDHCI_COMMAND), 117 sdhci_readl(host, SDHCI_MAX_CURRENT)); 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 119 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 120 121 if (host->flags & SDHCI_USE_ADMA) { 122 if (host->flags & SDHCI_USE_64_BIT_DMA) 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 124 readl(host->ioaddr + SDHCI_ADMA_ERROR), 125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 127 else 128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 129 readl(host->ioaddr + SDHCI_ADMA_ERROR), 130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 131 } 132 133 pr_debug(DRIVER_NAME ": ===========================================\n"); 134 } 135 136 /*****************************************************************************\ 137 * * 138 * Low level functions * 139 * * 140 \*****************************************************************************/ 141 142 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 143 { 144 u32 present; 145 146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 147 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 148 return; 149 150 if (enable) { 151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 152 SDHCI_CARD_PRESENT; 153 154 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 155 SDHCI_INT_CARD_INSERT; 156 } else { 157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 158 } 159 160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 162 } 163 164 static void sdhci_enable_card_detection(struct sdhci_host *host) 165 { 166 sdhci_set_card_detection(host, true); 167 } 168 169 static void sdhci_disable_card_detection(struct sdhci_host *host) 170 { 171 sdhci_set_card_detection(host, false); 172 } 173 174 void sdhci_reset(struct sdhci_host *host, u8 mask) 175 { 176 unsigned long timeout; 177 178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 179 180 if (mask & SDHCI_RESET_ALL) { 181 host->clock = 0; 182 /* Reset-all turns off SD Bus Power */ 183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 184 sdhci_runtime_pm_bus_off(host); 185 } 186 187 /* Wait max 100 ms */ 188 timeout = 100; 189 190 /* hw clears the bit when it's done */ 191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 192 if (timeout == 0) { 193 pr_err("%s: Reset 0x%x never completed.\n", 194 mmc_hostname(host->mmc), (int)mask); 195 sdhci_dumpregs(host); 196 return; 197 } 198 timeout--; 199 mdelay(1); 200 } 201 } 202 EXPORT_SYMBOL_GPL(sdhci_reset); 203 204 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 205 { 206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 207 if (!sdhci_do_get_cd(host)) 208 return; 209 } 210 211 host->ops->reset(host, mask); 212 213 if (mask & SDHCI_RESET_ALL) { 214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 215 if (host->ops->enable_dma) 216 host->ops->enable_dma(host); 217 } 218 219 /* Resetting the controller clears many */ 220 host->preset_enabled = false; 221 } 222 } 223 224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 225 226 static void sdhci_init(struct sdhci_host *host, int soft) 227 { 228 if (soft) 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 230 else 231 sdhci_do_reset(host, SDHCI_RESET_ALL); 232 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 237 SDHCI_INT_RESPONSE; 238 239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 241 242 if (soft) { 243 /* force clock reconfiguration */ 244 host->clock = 0; 245 sdhci_set_ios(host->mmc, &host->mmc->ios); 246 } 247 } 248 249 static void sdhci_reinit(struct sdhci_host *host) 250 { 251 sdhci_init(host, 0); 252 sdhci_enable_card_detection(host); 253 } 254 255 static void sdhci_activate_led(struct sdhci_host *host) 256 { 257 u8 ctrl; 258 259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 260 ctrl |= SDHCI_CTRL_LED; 261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 262 } 263 264 static void sdhci_deactivate_led(struct sdhci_host *host) 265 { 266 u8 ctrl; 267 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 269 ctrl &= ~SDHCI_CTRL_LED; 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 271 } 272 273 #ifdef SDHCI_USE_LEDS_CLASS 274 static void sdhci_led_control(struct led_classdev *led, 275 enum led_brightness brightness) 276 { 277 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 278 unsigned long flags; 279 280 spin_lock_irqsave(&host->lock, flags); 281 282 if (host->runtime_suspended) 283 goto out; 284 285 if (brightness == LED_OFF) 286 sdhci_deactivate_led(host); 287 else 288 sdhci_activate_led(host); 289 out: 290 spin_unlock_irqrestore(&host->lock, flags); 291 } 292 #endif 293 294 /*****************************************************************************\ 295 * * 296 * Core functions * 297 * * 298 \*****************************************************************************/ 299 300 static void sdhci_read_block_pio(struct sdhci_host *host) 301 { 302 unsigned long flags; 303 size_t blksize, len, chunk; 304 u32 uninitialized_var(scratch); 305 u8 *buf; 306 307 DBG("PIO reading\n"); 308 309 blksize = host->data->blksz; 310 chunk = 0; 311 312 local_irq_save(flags); 313 314 while (blksize) { 315 BUG_ON(!sg_miter_next(&host->sg_miter)); 316 317 len = min(host->sg_miter.length, blksize); 318 319 blksize -= len; 320 host->sg_miter.consumed = len; 321 322 buf = host->sg_miter.addr; 323 324 while (len) { 325 if (chunk == 0) { 326 scratch = sdhci_readl(host, SDHCI_BUFFER); 327 chunk = 4; 328 } 329 330 *buf = scratch & 0xFF; 331 332 buf++; 333 scratch >>= 8; 334 chunk--; 335 len--; 336 } 337 } 338 339 sg_miter_stop(&host->sg_miter); 340 341 local_irq_restore(flags); 342 } 343 344 static void sdhci_write_block_pio(struct sdhci_host *host) 345 { 346 unsigned long flags; 347 size_t blksize, len, chunk; 348 u32 scratch; 349 u8 *buf; 350 351 DBG("PIO writing\n"); 352 353 blksize = host->data->blksz; 354 chunk = 0; 355 scratch = 0; 356 357 local_irq_save(flags); 358 359 while (blksize) { 360 BUG_ON(!sg_miter_next(&host->sg_miter)); 361 362 len = min(host->sg_miter.length, blksize); 363 364 blksize -= len; 365 host->sg_miter.consumed = len; 366 367 buf = host->sg_miter.addr; 368 369 while (len) { 370 scratch |= (u32)*buf << (chunk * 8); 371 372 buf++; 373 chunk++; 374 len--; 375 376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 377 sdhci_writel(host, scratch, SDHCI_BUFFER); 378 chunk = 0; 379 scratch = 0; 380 } 381 } 382 } 383 384 sg_miter_stop(&host->sg_miter); 385 386 local_irq_restore(flags); 387 } 388 389 static void sdhci_transfer_pio(struct sdhci_host *host) 390 { 391 u32 mask; 392 393 BUG_ON(!host->data); 394 395 if (host->blocks == 0) 396 return; 397 398 if (host->data->flags & MMC_DATA_READ) 399 mask = SDHCI_DATA_AVAILABLE; 400 else 401 mask = SDHCI_SPACE_AVAILABLE; 402 403 /* 404 * Some controllers (JMicron JMB38x) mess up the buffer bits 405 * for transfers < 4 bytes. As long as it is just one block, 406 * we can ignore the bits. 407 */ 408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 409 (host->data->blocks == 1)) 410 mask = ~0; 411 412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 414 udelay(100); 415 416 if (host->data->flags & MMC_DATA_READ) 417 sdhci_read_block_pio(host); 418 else 419 sdhci_write_block_pio(host); 420 421 host->blocks--; 422 if (host->blocks == 0) 423 break; 424 } 425 426 DBG("PIO transfer complete.\n"); 427 } 428 429 static int sdhci_pre_dma_transfer(struct sdhci_host *host, 430 struct mmc_data *data, int cookie) 431 { 432 int sg_count; 433 434 /* 435 * If the data buffers are already mapped, return the previous 436 * dma_map_sg() result. 437 */ 438 if (data->host_cookie == COOKIE_PRE_MAPPED) 439 return data->sg_count; 440 441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 442 data->flags & MMC_DATA_WRITE ? 443 DMA_TO_DEVICE : DMA_FROM_DEVICE); 444 445 if (sg_count == 0) 446 return -ENOSPC; 447 448 data->sg_count = sg_count; 449 data->host_cookie = cookie; 450 451 return sg_count; 452 } 453 454 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 455 { 456 local_irq_save(*flags); 457 return kmap_atomic(sg_page(sg)) + sg->offset; 458 } 459 460 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 461 { 462 kunmap_atomic(buffer); 463 local_irq_restore(*flags); 464 } 465 466 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 467 dma_addr_t addr, int len, unsigned cmd) 468 { 469 struct sdhci_adma2_64_desc *dma_desc = desc; 470 471 /* 32-bit and 64-bit descriptors have these members in same position */ 472 dma_desc->cmd = cpu_to_le16(cmd); 473 dma_desc->len = cpu_to_le16(len); 474 dma_desc->addr_lo = cpu_to_le32((u32)addr); 475 476 if (host->flags & SDHCI_USE_64_BIT_DMA) 477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 478 } 479 480 static void sdhci_adma_mark_end(void *desc) 481 { 482 struct sdhci_adma2_64_desc *dma_desc = desc; 483 484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 485 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 486 } 487 488 static void sdhci_adma_table_pre(struct sdhci_host *host, 489 struct mmc_data *data, int sg_count) 490 { 491 struct scatterlist *sg; 492 unsigned long flags; 493 dma_addr_t addr, align_addr; 494 void *desc, *align; 495 char *buffer; 496 int len, offset, i; 497 498 /* 499 * The spec does not specify endianness of descriptor table. 500 * We currently guess that it is LE. 501 */ 502 503 host->sg_count = sg_count; 504 505 desc = host->adma_table; 506 align = host->align_buffer; 507 508 align_addr = host->align_addr; 509 510 for_each_sg(data->sg, sg, host->sg_count, i) { 511 addr = sg_dma_address(sg); 512 len = sg_dma_len(sg); 513 514 /* 515 * The SDHCI specification states that ADMA addresses must 516 * be 32-bit aligned. If they aren't, then we use a bounce 517 * buffer for the (up to three) bytes that screw up the 518 * alignment. 519 */ 520 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 521 SDHCI_ADMA2_MASK; 522 if (offset) { 523 if (data->flags & MMC_DATA_WRITE) { 524 buffer = sdhci_kmap_atomic(sg, &flags); 525 memcpy(align, buffer, offset); 526 sdhci_kunmap_atomic(buffer, &flags); 527 } 528 529 /* tran, valid */ 530 sdhci_adma_write_desc(host, desc, align_addr, offset, 531 ADMA2_TRAN_VALID); 532 533 BUG_ON(offset > 65536); 534 535 align += SDHCI_ADMA2_ALIGN; 536 align_addr += SDHCI_ADMA2_ALIGN; 537 538 desc += host->desc_sz; 539 540 addr += offset; 541 len -= offset; 542 } 543 544 BUG_ON(len > 65536); 545 546 if (len) { 547 /* tran, valid */ 548 sdhci_adma_write_desc(host, desc, addr, len, 549 ADMA2_TRAN_VALID); 550 desc += host->desc_sz; 551 } 552 553 /* 554 * If this triggers then we have a calculation bug 555 * somewhere. :/ 556 */ 557 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 558 } 559 560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 561 /* Mark the last descriptor as the terminating descriptor */ 562 if (desc != host->adma_table) { 563 desc -= host->desc_sz; 564 sdhci_adma_mark_end(desc); 565 } 566 } else { 567 /* Add a terminating entry - nop, end, valid */ 568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 569 } 570 } 571 572 static void sdhci_adma_table_post(struct sdhci_host *host, 573 struct mmc_data *data) 574 { 575 struct scatterlist *sg; 576 int i, size; 577 void *align; 578 char *buffer; 579 unsigned long flags; 580 581 if (data->flags & MMC_DATA_READ) { 582 bool has_unaligned = false; 583 584 /* Do a quick scan of the SG list for any unaligned mappings */ 585 for_each_sg(data->sg, sg, host->sg_count, i) 586 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 587 has_unaligned = true; 588 break; 589 } 590 591 if (has_unaligned) { 592 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 593 data->sg_len, DMA_FROM_DEVICE); 594 595 align = host->align_buffer; 596 597 for_each_sg(data->sg, sg, host->sg_count, i) { 598 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 599 size = SDHCI_ADMA2_ALIGN - 600 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 601 602 buffer = sdhci_kmap_atomic(sg, &flags); 603 memcpy(buffer, align, size); 604 sdhci_kunmap_atomic(buffer, &flags); 605 606 align += SDHCI_ADMA2_ALIGN; 607 } 608 } 609 } 610 } 611 } 612 613 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 614 { 615 u8 count; 616 struct mmc_data *data = cmd->data; 617 unsigned target_timeout, current_timeout; 618 619 /* 620 * If the host controller provides us with an incorrect timeout 621 * value, just skip the check and use 0xE. The hardware may take 622 * longer to time out, but that's much better than having a too-short 623 * timeout value. 624 */ 625 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 626 return 0xE; 627 628 /* Unspecified timeout, assume max */ 629 if (!data && !cmd->busy_timeout) 630 return 0xE; 631 632 /* timeout in us */ 633 if (!data) 634 target_timeout = cmd->busy_timeout * 1000; 635 else { 636 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 637 if (host->clock && data->timeout_clks) { 638 unsigned long long val; 639 640 /* 641 * data->timeout_clks is in units of clock cycles. 642 * host->clock is in Hz. target_timeout is in us. 643 * Hence, us = 1000000 * cycles / Hz. Round up. 644 */ 645 val = 1000000 * data->timeout_clks; 646 if (do_div(val, host->clock)) 647 target_timeout++; 648 target_timeout += val; 649 } 650 } 651 652 /* 653 * Figure out needed cycles. 654 * We do this in steps in order to fit inside a 32 bit int. 655 * The first step is the minimum timeout, which will have a 656 * minimum resolution of 6 bits: 657 * (1) 2^13*1000 > 2^22, 658 * (2) host->timeout_clk < 2^16 659 * => 660 * (1) / (2) > 2^6 661 */ 662 count = 0; 663 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 664 while (current_timeout < target_timeout) { 665 count++; 666 current_timeout <<= 1; 667 if (count >= 0xF) 668 break; 669 } 670 671 if (count >= 0xF) { 672 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 673 mmc_hostname(host->mmc), count, cmd->opcode); 674 count = 0xE; 675 } 676 677 return count; 678 } 679 680 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 681 { 682 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 683 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 684 685 if (host->flags & SDHCI_REQ_USE_DMA) 686 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 687 else 688 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 689 690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 692 } 693 694 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 695 { 696 u8 count; 697 698 if (host->ops->set_timeout) { 699 host->ops->set_timeout(host, cmd); 700 } else { 701 count = sdhci_calc_timeout(host, cmd); 702 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 703 } 704 } 705 706 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 707 { 708 u8 ctrl; 709 struct mmc_data *data = cmd->data; 710 711 WARN_ON(host->data); 712 713 if (data || (cmd->flags & MMC_RSP_BUSY)) 714 sdhci_set_timeout(host, cmd); 715 716 if (!data) 717 return; 718 719 /* Sanity checks */ 720 BUG_ON(data->blksz * data->blocks > 524288); 721 BUG_ON(data->blksz > host->mmc->max_blk_size); 722 BUG_ON(data->blocks > 65535); 723 724 host->data = data; 725 host->data_early = 0; 726 host->data->bytes_xfered = 0; 727 728 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 729 struct scatterlist *sg; 730 unsigned int length_mask, offset_mask; 731 int i; 732 733 host->flags |= SDHCI_REQ_USE_DMA; 734 735 /* 736 * FIXME: This doesn't account for merging when mapping the 737 * scatterlist. 738 * 739 * The assumption here being that alignment and lengths are 740 * the same after DMA mapping to device address space. 741 */ 742 length_mask = 0; 743 offset_mask = 0; 744 if (host->flags & SDHCI_USE_ADMA) { 745 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 746 length_mask = 3; 747 /* 748 * As we use up to 3 byte chunks to work 749 * around alignment problems, we need to 750 * check the offset as well. 751 */ 752 offset_mask = 3; 753 } 754 } else { 755 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 756 length_mask = 3; 757 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 758 offset_mask = 3; 759 } 760 761 if (unlikely(length_mask | offset_mask)) { 762 for_each_sg(data->sg, sg, data->sg_len, i) { 763 if (sg->length & length_mask) { 764 DBG("Reverting to PIO because of transfer size (%d)\n", 765 sg->length); 766 host->flags &= ~SDHCI_REQ_USE_DMA; 767 break; 768 } 769 if (sg->offset & offset_mask) { 770 DBG("Reverting to PIO because of bad alignment\n"); 771 host->flags &= ~SDHCI_REQ_USE_DMA; 772 break; 773 } 774 } 775 } 776 } 777 778 if (host->flags & SDHCI_REQ_USE_DMA) { 779 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 780 781 if (sg_cnt <= 0) { 782 /* 783 * This only happens when someone fed 784 * us an invalid request. 785 */ 786 WARN_ON(1); 787 host->flags &= ~SDHCI_REQ_USE_DMA; 788 } else if (host->flags & SDHCI_USE_ADMA) { 789 sdhci_adma_table_pre(host, data, sg_cnt); 790 791 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 792 if (host->flags & SDHCI_USE_64_BIT_DMA) 793 sdhci_writel(host, 794 (u64)host->adma_addr >> 32, 795 SDHCI_ADMA_ADDRESS_HI); 796 } else { 797 WARN_ON(sg_cnt != 1); 798 sdhci_writel(host, sg_dma_address(data->sg), 799 SDHCI_DMA_ADDRESS); 800 } 801 } 802 803 /* 804 * Always adjust the DMA selection as some controllers 805 * (e.g. JMicron) can't do PIO properly when the selection 806 * is ADMA. 807 */ 808 if (host->version >= SDHCI_SPEC_200) { 809 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 810 ctrl &= ~SDHCI_CTRL_DMA_MASK; 811 if ((host->flags & SDHCI_REQ_USE_DMA) && 812 (host->flags & SDHCI_USE_ADMA)) { 813 if (host->flags & SDHCI_USE_64_BIT_DMA) 814 ctrl |= SDHCI_CTRL_ADMA64; 815 else 816 ctrl |= SDHCI_CTRL_ADMA32; 817 } else { 818 ctrl |= SDHCI_CTRL_SDMA; 819 } 820 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 821 } 822 823 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 824 int flags; 825 826 flags = SG_MITER_ATOMIC; 827 if (host->data->flags & MMC_DATA_READ) 828 flags |= SG_MITER_TO_SG; 829 else 830 flags |= SG_MITER_FROM_SG; 831 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 832 host->blocks = data->blocks; 833 } 834 835 sdhci_set_transfer_irqs(host); 836 837 /* Set the DMA boundary value and block size */ 838 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 839 data->blksz), SDHCI_BLOCK_SIZE); 840 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 841 } 842 843 static void sdhci_set_transfer_mode(struct sdhci_host *host, 844 struct mmc_command *cmd) 845 { 846 u16 mode = 0; 847 struct mmc_data *data = cmd->data; 848 849 if (data == NULL) { 850 if (host->quirks2 & 851 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 852 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 853 } else { 854 /* clear Auto CMD settings for no data CMDs */ 855 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 856 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 857 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 858 } 859 return; 860 } 861 862 WARN_ON(!host->data); 863 864 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 865 mode = SDHCI_TRNS_BLK_CNT_EN; 866 867 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 868 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 869 /* 870 * If we are sending CMD23, CMD12 never gets sent 871 * on successful completion (so no Auto-CMD12). 872 */ 873 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 874 (cmd->opcode != SD_IO_RW_EXTENDED)) 875 mode |= SDHCI_TRNS_AUTO_CMD12; 876 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 877 mode |= SDHCI_TRNS_AUTO_CMD23; 878 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 879 } 880 } 881 882 if (data->flags & MMC_DATA_READ) 883 mode |= SDHCI_TRNS_READ; 884 if (host->flags & SDHCI_REQ_USE_DMA) 885 mode |= SDHCI_TRNS_DMA; 886 887 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 888 } 889 890 static void sdhci_finish_data(struct sdhci_host *host) 891 { 892 struct mmc_data *data; 893 894 BUG_ON(!host->data); 895 896 data = host->data; 897 host->data = NULL; 898 899 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 900 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 901 sdhci_adma_table_post(host, data); 902 903 /* 904 * The specification states that the block count register must 905 * be updated, but it does not specify at what point in the 906 * data flow. That makes the register entirely useless to read 907 * back so we have to assume that nothing made it to the card 908 * in the event of an error. 909 */ 910 if (data->error) 911 data->bytes_xfered = 0; 912 else 913 data->bytes_xfered = data->blksz * data->blocks; 914 915 /* 916 * Need to send CMD12 if - 917 * a) open-ended multiblock transfer (no CMD23) 918 * b) error in multiblock transfer 919 */ 920 if (data->stop && 921 (data->error || 922 !host->mrq->sbc)) { 923 924 /* 925 * The controller needs a reset of internal state machines 926 * upon error conditions. 927 */ 928 if (data->error) { 929 sdhci_do_reset(host, SDHCI_RESET_CMD); 930 sdhci_do_reset(host, SDHCI_RESET_DATA); 931 } 932 933 sdhci_send_command(host, data->stop); 934 } else 935 tasklet_schedule(&host->finish_tasklet); 936 } 937 938 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 939 { 940 int flags; 941 u32 mask; 942 unsigned long timeout; 943 944 WARN_ON(host->cmd); 945 946 /* Initially, a command has no error */ 947 cmd->error = 0; 948 949 /* Wait max 10 ms */ 950 timeout = 10; 951 952 mask = SDHCI_CMD_INHIBIT; 953 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 954 mask |= SDHCI_DATA_INHIBIT; 955 956 /* We shouldn't wait for data inihibit for stop commands, even 957 though they might use busy signaling */ 958 if (host->mrq->data && (cmd == host->mrq->data->stop)) 959 mask &= ~SDHCI_DATA_INHIBIT; 960 961 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 962 if (timeout == 0) { 963 pr_err("%s: Controller never released inhibit bit(s).\n", 964 mmc_hostname(host->mmc)); 965 sdhci_dumpregs(host); 966 cmd->error = -EIO; 967 tasklet_schedule(&host->finish_tasklet); 968 return; 969 } 970 timeout--; 971 mdelay(1); 972 } 973 974 timeout = jiffies; 975 if (!cmd->data && cmd->busy_timeout > 9000) 976 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 977 else 978 timeout += 10 * HZ; 979 mod_timer(&host->timer, timeout); 980 981 host->cmd = cmd; 982 host->busy_handle = 0; 983 984 sdhci_prepare_data(host, cmd); 985 986 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 987 988 sdhci_set_transfer_mode(host, cmd); 989 990 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 991 pr_err("%s: Unsupported response type!\n", 992 mmc_hostname(host->mmc)); 993 cmd->error = -EINVAL; 994 tasklet_schedule(&host->finish_tasklet); 995 return; 996 } 997 998 if (!(cmd->flags & MMC_RSP_PRESENT)) 999 flags = SDHCI_CMD_RESP_NONE; 1000 else if (cmd->flags & MMC_RSP_136) 1001 flags = SDHCI_CMD_RESP_LONG; 1002 else if (cmd->flags & MMC_RSP_BUSY) 1003 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1004 else 1005 flags = SDHCI_CMD_RESP_SHORT; 1006 1007 if (cmd->flags & MMC_RSP_CRC) 1008 flags |= SDHCI_CMD_CRC; 1009 if (cmd->flags & MMC_RSP_OPCODE) 1010 flags |= SDHCI_CMD_INDEX; 1011 1012 /* CMD19 is special in that the Data Present Select should be set */ 1013 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1014 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1015 flags |= SDHCI_CMD_DATA; 1016 1017 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1018 } 1019 EXPORT_SYMBOL_GPL(sdhci_send_command); 1020 1021 static void sdhci_finish_command(struct sdhci_host *host) 1022 { 1023 int i; 1024 1025 BUG_ON(host->cmd == NULL); 1026 1027 if (host->cmd->flags & MMC_RSP_PRESENT) { 1028 if (host->cmd->flags & MMC_RSP_136) { 1029 /* CRC is stripped so we need to do some shifting. */ 1030 for (i = 0;i < 4;i++) { 1031 host->cmd->resp[i] = sdhci_readl(host, 1032 SDHCI_RESPONSE + (3-i)*4) << 8; 1033 if (i != 3) 1034 host->cmd->resp[i] |= 1035 sdhci_readb(host, 1036 SDHCI_RESPONSE + (3-i)*4-1); 1037 } 1038 } else { 1039 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1040 } 1041 } 1042 1043 /* Finished CMD23, now send actual command. */ 1044 if (host->cmd == host->mrq->sbc) { 1045 host->cmd = NULL; 1046 sdhci_send_command(host, host->mrq->cmd); 1047 } else { 1048 1049 /* Processed actual command. */ 1050 if (host->data && host->data_early) 1051 sdhci_finish_data(host); 1052 1053 if (!host->cmd->data) 1054 tasklet_schedule(&host->finish_tasklet); 1055 1056 host->cmd = NULL; 1057 } 1058 } 1059 1060 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1061 { 1062 u16 preset = 0; 1063 1064 switch (host->timing) { 1065 case MMC_TIMING_UHS_SDR12: 1066 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1067 break; 1068 case MMC_TIMING_UHS_SDR25: 1069 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1070 break; 1071 case MMC_TIMING_UHS_SDR50: 1072 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1073 break; 1074 case MMC_TIMING_UHS_SDR104: 1075 case MMC_TIMING_MMC_HS200: 1076 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1077 break; 1078 case MMC_TIMING_UHS_DDR50: 1079 case MMC_TIMING_MMC_DDR52: 1080 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1081 break; 1082 case MMC_TIMING_MMC_HS400: 1083 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1084 break; 1085 default: 1086 pr_warn("%s: Invalid UHS-I mode selected\n", 1087 mmc_hostname(host->mmc)); 1088 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1089 break; 1090 } 1091 return preset; 1092 } 1093 1094 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1095 { 1096 int div = 0; /* Initialized for compiler warning */ 1097 int real_div = div, clk_mul = 1; 1098 u16 clk = 0; 1099 unsigned long timeout; 1100 bool switch_base_clk = false; 1101 1102 host->mmc->actual_clock = 0; 1103 1104 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1105 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST) 1106 mdelay(1); 1107 1108 if (clock == 0) 1109 return; 1110 1111 if (host->version >= SDHCI_SPEC_300) { 1112 if (host->preset_enabled) { 1113 u16 pre_val; 1114 1115 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1116 pre_val = sdhci_get_preset_value(host); 1117 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1118 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1119 if (host->clk_mul && 1120 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1121 clk = SDHCI_PROG_CLOCK_MODE; 1122 real_div = div + 1; 1123 clk_mul = host->clk_mul; 1124 } else { 1125 real_div = max_t(int, 1, div << 1); 1126 } 1127 goto clock_set; 1128 } 1129 1130 /* 1131 * Check if the Host Controller supports Programmable Clock 1132 * Mode. 1133 */ 1134 if (host->clk_mul) { 1135 for (div = 1; div <= 1024; div++) { 1136 if ((host->max_clk * host->clk_mul / div) 1137 <= clock) 1138 break; 1139 } 1140 if ((host->max_clk * host->clk_mul / div) <= clock) { 1141 /* 1142 * Set Programmable Clock Mode in the Clock 1143 * Control register. 1144 */ 1145 clk = SDHCI_PROG_CLOCK_MODE; 1146 real_div = div; 1147 clk_mul = host->clk_mul; 1148 div--; 1149 } else { 1150 /* 1151 * Divisor can be too small to reach clock 1152 * speed requirement. Then use the base clock. 1153 */ 1154 switch_base_clk = true; 1155 } 1156 } 1157 1158 if (!host->clk_mul || switch_base_clk) { 1159 /* Version 3.00 divisors must be a multiple of 2. */ 1160 if (host->max_clk <= clock) 1161 div = 1; 1162 else { 1163 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1164 div += 2) { 1165 if ((host->max_clk / div) <= clock) 1166 break; 1167 } 1168 } 1169 real_div = div; 1170 div >>= 1; 1171 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1172 && !div && host->max_clk <= 25000000) 1173 div = 1; 1174 } 1175 } else { 1176 /* Version 2.00 divisors must be a power of 2. */ 1177 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1178 if ((host->max_clk / div) <= clock) 1179 break; 1180 } 1181 real_div = div; 1182 div >>= 1; 1183 } 1184 1185 clock_set: 1186 if (real_div) 1187 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1188 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1189 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1190 << SDHCI_DIVIDER_HI_SHIFT; 1191 clk |= SDHCI_CLOCK_INT_EN; 1192 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1193 1194 /* Wait max 20 ms */ 1195 timeout = 20; 1196 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1197 & SDHCI_CLOCK_INT_STABLE)) { 1198 if (timeout == 0) { 1199 pr_err("%s: Internal clock never stabilised.\n", 1200 mmc_hostname(host->mmc)); 1201 sdhci_dumpregs(host); 1202 return; 1203 } 1204 timeout--; 1205 mdelay(1); 1206 } 1207 1208 clk |= SDHCI_CLOCK_CARD_EN; 1209 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1210 } 1211 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1212 1213 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1214 unsigned short vdd) 1215 { 1216 struct mmc_host *mmc = host->mmc; 1217 u8 pwr = 0; 1218 1219 if (mode != MMC_POWER_OFF) { 1220 switch (1 << vdd) { 1221 case MMC_VDD_165_195: 1222 pwr = SDHCI_POWER_180; 1223 break; 1224 case MMC_VDD_29_30: 1225 case MMC_VDD_30_31: 1226 pwr = SDHCI_POWER_300; 1227 break; 1228 case MMC_VDD_32_33: 1229 case MMC_VDD_33_34: 1230 pwr = SDHCI_POWER_330; 1231 break; 1232 default: 1233 WARN(1, "%s: Invalid vdd %#x\n", 1234 mmc_hostname(host->mmc), vdd); 1235 break; 1236 } 1237 } 1238 1239 if (host->pwr == pwr) 1240 return; 1241 1242 host->pwr = pwr; 1243 1244 if (pwr == 0) { 1245 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1246 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1247 sdhci_runtime_pm_bus_off(host); 1248 vdd = 0; 1249 } else { 1250 /* 1251 * Spec says that we should clear the power reg before setting 1252 * a new value. Some controllers don't seem to like this though. 1253 */ 1254 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1255 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1256 1257 /* 1258 * At least the Marvell CaFe chip gets confused if we set the 1259 * voltage and set turn on power at the same time, so set the 1260 * voltage first. 1261 */ 1262 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1263 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1264 1265 pwr |= SDHCI_POWER_ON; 1266 1267 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1268 1269 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1270 sdhci_runtime_pm_bus_on(host); 1271 1272 /* 1273 * Some controllers need an extra 10ms delay of 10ms before 1274 * they can apply clock after applying power 1275 */ 1276 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1277 mdelay(10); 1278 } 1279 1280 if (!IS_ERR(mmc->supply.vmmc)) { 1281 spin_unlock_irq(&host->lock); 1282 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1283 spin_lock_irq(&host->lock); 1284 } 1285 } 1286 1287 /*****************************************************************************\ 1288 * * 1289 * MMC callbacks * 1290 * * 1291 \*****************************************************************************/ 1292 1293 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1294 { 1295 struct sdhci_host *host; 1296 int present; 1297 unsigned long flags; 1298 1299 host = mmc_priv(mmc); 1300 1301 sdhci_runtime_pm_get(host); 1302 1303 /* Firstly check card presence */ 1304 present = mmc->ops->get_cd(mmc); 1305 1306 spin_lock_irqsave(&host->lock, flags); 1307 1308 WARN_ON(host->mrq != NULL); 1309 1310 #ifndef SDHCI_USE_LEDS_CLASS 1311 sdhci_activate_led(host); 1312 #endif 1313 1314 /* 1315 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1316 * requests if Auto-CMD12 is enabled. 1317 */ 1318 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1319 if (mrq->stop) { 1320 mrq->data->stop = NULL; 1321 mrq->stop = NULL; 1322 } 1323 } 1324 1325 host->mrq = mrq; 1326 1327 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1328 host->mrq->cmd->error = -ENOMEDIUM; 1329 tasklet_schedule(&host->finish_tasklet); 1330 } else { 1331 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1332 sdhci_send_command(host, mrq->sbc); 1333 else 1334 sdhci_send_command(host, mrq->cmd); 1335 } 1336 1337 mmiowb(); 1338 spin_unlock_irqrestore(&host->lock, flags); 1339 } 1340 1341 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1342 { 1343 u8 ctrl; 1344 1345 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1346 if (width == MMC_BUS_WIDTH_8) { 1347 ctrl &= ~SDHCI_CTRL_4BITBUS; 1348 if (host->version >= SDHCI_SPEC_300) 1349 ctrl |= SDHCI_CTRL_8BITBUS; 1350 } else { 1351 if (host->version >= SDHCI_SPEC_300) 1352 ctrl &= ~SDHCI_CTRL_8BITBUS; 1353 if (width == MMC_BUS_WIDTH_4) 1354 ctrl |= SDHCI_CTRL_4BITBUS; 1355 else 1356 ctrl &= ~SDHCI_CTRL_4BITBUS; 1357 } 1358 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1359 } 1360 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1361 1362 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1363 { 1364 u16 ctrl_2; 1365 1366 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1367 /* Select Bus Speed Mode for host */ 1368 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1369 if ((timing == MMC_TIMING_MMC_HS200) || 1370 (timing == MMC_TIMING_UHS_SDR104)) 1371 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1372 else if (timing == MMC_TIMING_UHS_SDR12) 1373 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1374 else if (timing == MMC_TIMING_UHS_SDR25) 1375 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1376 else if (timing == MMC_TIMING_UHS_SDR50) 1377 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1378 else if ((timing == MMC_TIMING_UHS_DDR50) || 1379 (timing == MMC_TIMING_MMC_DDR52)) 1380 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1381 else if (timing == MMC_TIMING_MMC_HS400) 1382 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1383 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1384 } 1385 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1386 1387 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1388 { 1389 unsigned long flags; 1390 u8 ctrl; 1391 struct mmc_host *mmc = host->mmc; 1392 1393 spin_lock_irqsave(&host->lock, flags); 1394 1395 if (host->flags & SDHCI_DEVICE_DEAD) { 1396 spin_unlock_irqrestore(&host->lock, flags); 1397 if (!IS_ERR(mmc->supply.vmmc) && 1398 ios->power_mode == MMC_POWER_OFF) 1399 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1400 return; 1401 } 1402 1403 /* 1404 * Reset the chip on each power off. 1405 * Should clear out any weird states. 1406 */ 1407 if (ios->power_mode == MMC_POWER_OFF) { 1408 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1409 sdhci_reinit(host); 1410 } 1411 1412 if (host->version >= SDHCI_SPEC_300 && 1413 (ios->power_mode == MMC_POWER_UP) && 1414 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1415 sdhci_enable_preset_value(host, false); 1416 1417 if (!ios->clock || ios->clock != host->clock) { 1418 host->ops->set_clock(host, ios->clock); 1419 host->clock = ios->clock; 1420 1421 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1422 host->clock) { 1423 host->timeout_clk = host->mmc->actual_clock ? 1424 host->mmc->actual_clock / 1000 : 1425 host->clock / 1000; 1426 host->mmc->max_busy_timeout = 1427 host->ops->get_max_timeout_count ? 1428 host->ops->get_max_timeout_count(host) : 1429 1 << 27; 1430 host->mmc->max_busy_timeout /= host->timeout_clk; 1431 } 1432 } 1433 1434 sdhci_set_power(host, ios->power_mode, ios->vdd); 1435 1436 if (host->ops->platform_send_init_74_clocks) 1437 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1438 1439 host->ops->set_bus_width(host, ios->bus_width); 1440 1441 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1442 1443 if ((ios->timing == MMC_TIMING_SD_HS || 1444 ios->timing == MMC_TIMING_MMC_HS) 1445 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1446 ctrl |= SDHCI_CTRL_HISPD; 1447 else 1448 ctrl &= ~SDHCI_CTRL_HISPD; 1449 1450 if (host->version >= SDHCI_SPEC_300) { 1451 u16 clk, ctrl_2; 1452 1453 /* In case of UHS-I modes, set High Speed Enable */ 1454 if ((ios->timing == MMC_TIMING_MMC_HS400) || 1455 (ios->timing == MMC_TIMING_MMC_HS200) || 1456 (ios->timing == MMC_TIMING_MMC_DDR52) || 1457 (ios->timing == MMC_TIMING_UHS_SDR50) || 1458 (ios->timing == MMC_TIMING_UHS_SDR104) || 1459 (ios->timing == MMC_TIMING_UHS_DDR50) || 1460 (ios->timing == MMC_TIMING_UHS_SDR25)) 1461 ctrl |= SDHCI_CTRL_HISPD; 1462 1463 if (!host->preset_enabled) { 1464 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1465 /* 1466 * We only need to set Driver Strength if the 1467 * preset value enable is not set. 1468 */ 1469 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1470 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1471 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1472 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1473 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 1474 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1475 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1476 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1477 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 1478 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 1479 else { 1480 pr_warn("%s: invalid driver type, default to driver type B\n", 1481 mmc_hostname(mmc)); 1482 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1483 } 1484 1485 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1486 } else { 1487 /* 1488 * According to SDHC Spec v3.00, if the Preset Value 1489 * Enable in the Host Control 2 register is set, we 1490 * need to reset SD Clock Enable before changing High 1491 * Speed Enable to avoid generating clock gliches. 1492 */ 1493 1494 /* Reset SD Clock Enable */ 1495 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1496 clk &= ~SDHCI_CLOCK_CARD_EN; 1497 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1498 1499 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1500 1501 /* Re-enable SD Clock */ 1502 host->ops->set_clock(host, host->clock); 1503 } 1504 1505 /* Reset SD Clock Enable */ 1506 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1507 clk &= ~SDHCI_CLOCK_CARD_EN; 1508 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1509 1510 host->ops->set_uhs_signaling(host, ios->timing); 1511 host->timing = ios->timing; 1512 1513 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1514 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1515 (ios->timing == MMC_TIMING_UHS_SDR25) || 1516 (ios->timing == MMC_TIMING_UHS_SDR50) || 1517 (ios->timing == MMC_TIMING_UHS_SDR104) || 1518 (ios->timing == MMC_TIMING_UHS_DDR50) || 1519 (ios->timing == MMC_TIMING_MMC_DDR52))) { 1520 u16 preset; 1521 1522 sdhci_enable_preset_value(host, true); 1523 preset = sdhci_get_preset_value(host); 1524 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1525 >> SDHCI_PRESET_DRV_SHIFT; 1526 } 1527 1528 /* Re-enable SD Clock */ 1529 host->ops->set_clock(host, host->clock); 1530 } else 1531 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1532 1533 /* 1534 * Some (ENE) controllers go apeshit on some ios operation, 1535 * signalling timeout and CRC errors even on CMD0. Resetting 1536 * it on each ios seems to solve the problem. 1537 */ 1538 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1539 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1540 1541 mmiowb(); 1542 spin_unlock_irqrestore(&host->lock, flags); 1543 } 1544 1545 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1546 { 1547 struct sdhci_host *host = mmc_priv(mmc); 1548 1549 sdhci_runtime_pm_get(host); 1550 sdhci_do_set_ios(host, ios); 1551 sdhci_runtime_pm_put(host); 1552 } 1553 1554 static int sdhci_do_get_cd(struct sdhci_host *host) 1555 { 1556 int gpio_cd = mmc_gpio_get_cd(host->mmc); 1557 1558 if (host->flags & SDHCI_DEVICE_DEAD) 1559 return 0; 1560 1561 /* If nonremovable, assume that the card is always present. */ 1562 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 1563 return 1; 1564 1565 /* 1566 * Try slot gpio detect, if defined it take precedence 1567 * over build in controller functionality 1568 */ 1569 if (!IS_ERR_VALUE(gpio_cd)) 1570 return !!gpio_cd; 1571 1572 /* If polling, assume that the card is always present. */ 1573 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1574 return 1; 1575 1576 /* Host native card detect */ 1577 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1578 } 1579 1580 static int sdhci_get_cd(struct mmc_host *mmc) 1581 { 1582 struct sdhci_host *host = mmc_priv(mmc); 1583 int ret; 1584 1585 sdhci_runtime_pm_get(host); 1586 ret = sdhci_do_get_cd(host); 1587 sdhci_runtime_pm_put(host); 1588 return ret; 1589 } 1590 1591 static int sdhci_check_ro(struct sdhci_host *host) 1592 { 1593 unsigned long flags; 1594 int is_readonly; 1595 1596 spin_lock_irqsave(&host->lock, flags); 1597 1598 if (host->flags & SDHCI_DEVICE_DEAD) 1599 is_readonly = 0; 1600 else if (host->ops->get_ro) 1601 is_readonly = host->ops->get_ro(host); 1602 else 1603 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1604 & SDHCI_WRITE_PROTECT); 1605 1606 spin_unlock_irqrestore(&host->lock, flags); 1607 1608 /* This quirk needs to be replaced by a callback-function later */ 1609 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1610 !is_readonly : is_readonly; 1611 } 1612 1613 #define SAMPLE_COUNT 5 1614 1615 static int sdhci_do_get_ro(struct sdhci_host *host) 1616 { 1617 int i, ro_count; 1618 1619 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1620 return sdhci_check_ro(host); 1621 1622 ro_count = 0; 1623 for (i = 0; i < SAMPLE_COUNT; i++) { 1624 if (sdhci_check_ro(host)) { 1625 if (++ro_count > SAMPLE_COUNT / 2) 1626 return 1; 1627 } 1628 msleep(30); 1629 } 1630 return 0; 1631 } 1632 1633 static void sdhci_hw_reset(struct mmc_host *mmc) 1634 { 1635 struct sdhci_host *host = mmc_priv(mmc); 1636 1637 if (host->ops && host->ops->hw_reset) 1638 host->ops->hw_reset(host); 1639 } 1640 1641 static int sdhci_get_ro(struct mmc_host *mmc) 1642 { 1643 struct sdhci_host *host = mmc_priv(mmc); 1644 int ret; 1645 1646 sdhci_runtime_pm_get(host); 1647 ret = sdhci_do_get_ro(host); 1648 sdhci_runtime_pm_put(host); 1649 return ret; 1650 } 1651 1652 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1653 { 1654 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1655 if (enable) 1656 host->ier |= SDHCI_INT_CARD_INT; 1657 else 1658 host->ier &= ~SDHCI_INT_CARD_INT; 1659 1660 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1661 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1662 mmiowb(); 1663 } 1664 } 1665 1666 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1667 { 1668 struct sdhci_host *host = mmc_priv(mmc); 1669 unsigned long flags; 1670 1671 sdhci_runtime_pm_get(host); 1672 1673 spin_lock_irqsave(&host->lock, flags); 1674 if (enable) 1675 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1676 else 1677 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1678 1679 sdhci_enable_sdio_irq_nolock(host, enable); 1680 spin_unlock_irqrestore(&host->lock, flags); 1681 1682 sdhci_runtime_pm_put(host); 1683 } 1684 1685 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1686 struct mmc_ios *ios) 1687 { 1688 struct mmc_host *mmc = host->mmc; 1689 u16 ctrl; 1690 int ret; 1691 1692 /* 1693 * Signal Voltage Switching is only applicable for Host Controllers 1694 * v3.00 and above. 1695 */ 1696 if (host->version < SDHCI_SPEC_300) 1697 return 0; 1698 1699 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1700 1701 switch (ios->signal_voltage) { 1702 case MMC_SIGNAL_VOLTAGE_330: 1703 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1704 ctrl &= ~SDHCI_CTRL_VDD_180; 1705 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1706 1707 if (!IS_ERR(mmc->supply.vqmmc)) { 1708 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, 1709 3600000); 1710 if (ret) { 1711 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1712 mmc_hostname(mmc)); 1713 return -EIO; 1714 } 1715 } 1716 /* Wait for 5ms */ 1717 usleep_range(5000, 5500); 1718 1719 /* 3.3V regulator output should be stable within 5 ms */ 1720 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1721 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1722 return 0; 1723 1724 pr_warn("%s: 3.3V regulator output did not became stable\n", 1725 mmc_hostname(mmc)); 1726 1727 return -EAGAIN; 1728 case MMC_SIGNAL_VOLTAGE_180: 1729 if (!IS_ERR(mmc->supply.vqmmc)) { 1730 ret = regulator_set_voltage(mmc->supply.vqmmc, 1731 1700000, 1950000); 1732 if (ret) { 1733 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1734 mmc_hostname(mmc)); 1735 return -EIO; 1736 } 1737 } 1738 1739 /* 1740 * Enable 1.8V Signal Enable in the Host Control2 1741 * register 1742 */ 1743 ctrl |= SDHCI_CTRL_VDD_180; 1744 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1745 1746 /* Some controller need to do more when switching */ 1747 if (host->ops->voltage_switch) 1748 host->ops->voltage_switch(host); 1749 1750 /* 1.8V regulator output should be stable within 5 ms */ 1751 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1752 if (ctrl & SDHCI_CTRL_VDD_180) 1753 return 0; 1754 1755 pr_warn("%s: 1.8V regulator output did not became stable\n", 1756 mmc_hostname(mmc)); 1757 1758 return -EAGAIN; 1759 case MMC_SIGNAL_VOLTAGE_120: 1760 if (!IS_ERR(mmc->supply.vqmmc)) { 1761 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, 1762 1300000); 1763 if (ret) { 1764 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1765 mmc_hostname(mmc)); 1766 return -EIO; 1767 } 1768 } 1769 return 0; 1770 default: 1771 /* No signal voltage switch required */ 1772 return 0; 1773 } 1774 } 1775 1776 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1777 struct mmc_ios *ios) 1778 { 1779 struct sdhci_host *host = mmc_priv(mmc); 1780 int err; 1781 1782 if (host->version < SDHCI_SPEC_300) 1783 return 0; 1784 sdhci_runtime_pm_get(host); 1785 err = sdhci_do_start_signal_voltage_switch(host, ios); 1786 sdhci_runtime_pm_put(host); 1787 return err; 1788 } 1789 1790 static int sdhci_card_busy(struct mmc_host *mmc) 1791 { 1792 struct sdhci_host *host = mmc_priv(mmc); 1793 u32 present_state; 1794 1795 sdhci_runtime_pm_get(host); 1796 /* Check whether DAT[3:0] is 0000 */ 1797 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1798 sdhci_runtime_pm_put(host); 1799 1800 return !(present_state & SDHCI_DATA_LVL_MASK); 1801 } 1802 1803 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1804 { 1805 struct sdhci_host *host = mmc_priv(mmc); 1806 unsigned long flags; 1807 1808 spin_lock_irqsave(&host->lock, flags); 1809 host->flags |= SDHCI_HS400_TUNING; 1810 spin_unlock_irqrestore(&host->lock, flags); 1811 1812 return 0; 1813 } 1814 1815 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1816 { 1817 struct sdhci_host *host = mmc_priv(mmc); 1818 u16 ctrl; 1819 int tuning_loop_counter = MAX_TUNING_LOOP; 1820 int err = 0; 1821 unsigned long flags; 1822 unsigned int tuning_count = 0; 1823 bool hs400_tuning; 1824 1825 sdhci_runtime_pm_get(host); 1826 spin_lock_irqsave(&host->lock, flags); 1827 1828 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1829 host->flags &= ~SDHCI_HS400_TUNING; 1830 1831 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1832 tuning_count = host->tuning_count; 1833 1834 /* 1835 * The Host Controller needs tuning in case of SDR104 and DDR50 1836 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 1837 * the Capabilities register. 1838 * If the Host Controller supports the HS200 mode then the 1839 * tuning function has to be executed. 1840 */ 1841 switch (host->timing) { 1842 /* HS400 tuning is done in HS200 mode */ 1843 case MMC_TIMING_MMC_HS400: 1844 err = -EINVAL; 1845 goto out_unlock; 1846 1847 case MMC_TIMING_MMC_HS200: 1848 /* 1849 * Periodic re-tuning for HS400 is not expected to be needed, so 1850 * disable it here. 1851 */ 1852 if (hs400_tuning) 1853 tuning_count = 0; 1854 break; 1855 1856 case MMC_TIMING_UHS_SDR104: 1857 case MMC_TIMING_UHS_DDR50: 1858 break; 1859 1860 case MMC_TIMING_UHS_SDR50: 1861 if (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1862 host->flags & SDHCI_SDR104_NEEDS_TUNING) 1863 break; 1864 /* FALLTHROUGH */ 1865 1866 default: 1867 goto out_unlock; 1868 } 1869 1870 if (host->ops->platform_execute_tuning) { 1871 spin_unlock_irqrestore(&host->lock, flags); 1872 err = host->ops->platform_execute_tuning(host, opcode); 1873 sdhci_runtime_pm_put(host); 1874 return err; 1875 } 1876 1877 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1878 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1879 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 1880 ctrl |= SDHCI_CTRL_TUNED_CLK; 1881 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1882 1883 /* 1884 * As per the Host Controller spec v3.00, tuning command 1885 * generates Buffer Read Ready interrupt, so enable that. 1886 * 1887 * Note: The spec clearly says that when tuning sequence 1888 * is being performed, the controller does not generate 1889 * interrupts other than Buffer Read Ready interrupt. But 1890 * to make sure we don't hit a controller bug, we _only_ 1891 * enable Buffer Read Ready interrupt here. 1892 */ 1893 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1894 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1895 1896 /* 1897 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1898 * of loops reaches 40 times or a timeout of 150ms occurs. 1899 */ 1900 do { 1901 struct mmc_command cmd = {0}; 1902 struct mmc_request mrq = {NULL}; 1903 1904 cmd.opcode = opcode; 1905 cmd.arg = 0; 1906 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1907 cmd.retries = 0; 1908 cmd.data = NULL; 1909 cmd.error = 0; 1910 1911 if (tuning_loop_counter-- == 0) 1912 break; 1913 1914 mrq.cmd = &cmd; 1915 host->mrq = &mrq; 1916 1917 /* 1918 * In response to CMD19, the card sends 64 bytes of tuning 1919 * block to the Host Controller. So we set the block size 1920 * to 64 here. 1921 */ 1922 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1923 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1924 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1925 SDHCI_BLOCK_SIZE); 1926 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1927 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1928 SDHCI_BLOCK_SIZE); 1929 } else { 1930 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1931 SDHCI_BLOCK_SIZE); 1932 } 1933 1934 /* 1935 * The tuning block is sent by the card to the host controller. 1936 * So we set the TRNS_READ bit in the Transfer Mode register. 1937 * This also takes care of setting DMA Enable and Multi Block 1938 * Select in the same register to 0. 1939 */ 1940 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1941 1942 sdhci_send_command(host, &cmd); 1943 1944 host->cmd = NULL; 1945 host->mrq = NULL; 1946 1947 spin_unlock_irqrestore(&host->lock, flags); 1948 /* Wait for Buffer Read Ready interrupt */ 1949 wait_event_interruptible_timeout(host->buf_ready_int, 1950 (host->tuning_done == 1), 1951 msecs_to_jiffies(50)); 1952 spin_lock_irqsave(&host->lock, flags); 1953 1954 if (!host->tuning_done) { 1955 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); 1956 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1957 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1958 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1959 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1960 1961 err = -EIO; 1962 goto out; 1963 } 1964 1965 host->tuning_done = 0; 1966 1967 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1968 1969 /* eMMC spec does not require a delay between tuning cycles */ 1970 if (opcode == MMC_SEND_TUNING_BLOCK) 1971 mdelay(1); 1972 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1973 1974 /* 1975 * The Host Driver has exhausted the maximum number of loops allowed, 1976 * so use fixed sampling frequency. 1977 */ 1978 if (tuning_loop_counter < 0) { 1979 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1980 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1981 } 1982 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1983 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); 1984 err = -EIO; 1985 } 1986 1987 out: 1988 if (tuning_count) { 1989 /* 1990 * In case tuning fails, host controllers which support 1991 * re-tuning can try tuning again at a later time, when the 1992 * re-tuning timer expires. So for these controllers, we 1993 * return 0. Since there might be other controllers who do not 1994 * have this capability, we return error for them. 1995 */ 1996 err = 0; 1997 } 1998 1999 host->mmc->retune_period = err ? 0 : tuning_count; 2000 2001 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2002 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2003 out_unlock: 2004 spin_unlock_irqrestore(&host->lock, flags); 2005 sdhci_runtime_pm_put(host); 2006 2007 return err; 2008 } 2009 2010 static int sdhci_select_drive_strength(struct mmc_card *card, 2011 unsigned int max_dtr, int host_drv, 2012 int card_drv, int *drv_type) 2013 { 2014 struct sdhci_host *host = mmc_priv(card->host); 2015 2016 if (!host->ops->select_drive_strength) 2017 return 0; 2018 2019 return host->ops->select_drive_strength(host, card, max_dtr, host_drv, 2020 card_drv, drv_type); 2021 } 2022 2023 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2024 { 2025 /* Host Controller v3.00 defines preset value registers */ 2026 if (host->version < SDHCI_SPEC_300) 2027 return; 2028 2029 /* 2030 * We only enable or disable Preset Value if they are not already 2031 * enabled or disabled respectively. Otherwise, we bail out. 2032 */ 2033 if (host->preset_enabled != enable) { 2034 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2035 2036 if (enable) 2037 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2038 else 2039 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2040 2041 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2042 2043 if (enable) 2044 host->flags |= SDHCI_PV_ENABLED; 2045 else 2046 host->flags &= ~SDHCI_PV_ENABLED; 2047 2048 host->preset_enabled = enable; 2049 } 2050 } 2051 2052 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2053 int err) 2054 { 2055 struct sdhci_host *host = mmc_priv(mmc); 2056 struct mmc_data *data = mrq->data; 2057 2058 if (data->host_cookie != COOKIE_UNMAPPED) 2059 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2060 data->flags & MMC_DATA_WRITE ? 2061 DMA_TO_DEVICE : DMA_FROM_DEVICE); 2062 2063 data->host_cookie = COOKIE_UNMAPPED; 2064 } 2065 2066 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 2067 bool is_first_req) 2068 { 2069 struct sdhci_host *host = mmc_priv(mmc); 2070 2071 mrq->data->host_cookie = COOKIE_UNMAPPED; 2072 2073 if (host->flags & SDHCI_REQ_USE_DMA) 2074 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2075 } 2076 2077 static void sdhci_card_event(struct mmc_host *mmc) 2078 { 2079 struct sdhci_host *host = mmc_priv(mmc); 2080 unsigned long flags; 2081 int present; 2082 2083 /* First check if client has provided their own card event */ 2084 if (host->ops->card_event) 2085 host->ops->card_event(host); 2086 2087 present = sdhci_do_get_cd(host); 2088 2089 spin_lock_irqsave(&host->lock, flags); 2090 2091 /* Check host->mrq first in case we are runtime suspended */ 2092 if (host->mrq && !present) { 2093 pr_err("%s: Card removed during transfer!\n", 2094 mmc_hostname(host->mmc)); 2095 pr_err("%s: Resetting controller.\n", 2096 mmc_hostname(host->mmc)); 2097 2098 sdhci_do_reset(host, SDHCI_RESET_CMD); 2099 sdhci_do_reset(host, SDHCI_RESET_DATA); 2100 2101 host->mrq->cmd->error = -ENOMEDIUM; 2102 tasklet_schedule(&host->finish_tasklet); 2103 } 2104 2105 spin_unlock_irqrestore(&host->lock, flags); 2106 } 2107 2108 static const struct mmc_host_ops sdhci_ops = { 2109 .request = sdhci_request, 2110 .post_req = sdhci_post_req, 2111 .pre_req = sdhci_pre_req, 2112 .set_ios = sdhci_set_ios, 2113 .get_cd = sdhci_get_cd, 2114 .get_ro = sdhci_get_ro, 2115 .hw_reset = sdhci_hw_reset, 2116 .enable_sdio_irq = sdhci_enable_sdio_irq, 2117 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2118 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2119 .execute_tuning = sdhci_execute_tuning, 2120 .select_drive_strength = sdhci_select_drive_strength, 2121 .card_event = sdhci_card_event, 2122 .card_busy = sdhci_card_busy, 2123 }; 2124 2125 /*****************************************************************************\ 2126 * * 2127 * Tasklets * 2128 * * 2129 \*****************************************************************************/ 2130 2131 static void sdhci_tasklet_finish(unsigned long param) 2132 { 2133 struct sdhci_host *host; 2134 unsigned long flags; 2135 struct mmc_request *mrq; 2136 2137 host = (struct sdhci_host*)param; 2138 2139 spin_lock_irqsave(&host->lock, flags); 2140 2141 /* 2142 * If this tasklet gets rescheduled while running, it will 2143 * be run again afterwards but without any active request. 2144 */ 2145 if (!host->mrq) { 2146 spin_unlock_irqrestore(&host->lock, flags); 2147 return; 2148 } 2149 2150 del_timer(&host->timer); 2151 2152 mrq = host->mrq; 2153 2154 /* 2155 * Always unmap the data buffers if they were mapped by 2156 * sdhci_prepare_data() whenever we finish with a request. 2157 * This avoids leaking DMA mappings on error. 2158 */ 2159 if (host->flags & SDHCI_REQ_USE_DMA) { 2160 struct mmc_data *data = mrq->data; 2161 2162 if (data && data->host_cookie == COOKIE_MAPPED) { 2163 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2164 (data->flags & MMC_DATA_READ) ? 2165 DMA_FROM_DEVICE : DMA_TO_DEVICE); 2166 data->host_cookie = COOKIE_UNMAPPED; 2167 } 2168 } 2169 2170 /* 2171 * The controller needs a reset of internal state machines 2172 * upon error conditions. 2173 */ 2174 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2175 ((mrq->cmd && mrq->cmd->error) || 2176 (mrq->sbc && mrq->sbc->error) || 2177 (mrq->data && ((mrq->data->error && !mrq->data->stop) || 2178 (mrq->data->stop && mrq->data->stop->error))) || 2179 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2180 2181 /* Some controllers need this kick or reset won't work here */ 2182 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2183 /* This is to force an update */ 2184 host->ops->set_clock(host, host->clock); 2185 2186 /* Spec says we should do both at the same time, but Ricoh 2187 controllers do not like that. */ 2188 sdhci_do_reset(host, SDHCI_RESET_CMD); 2189 sdhci_do_reset(host, SDHCI_RESET_DATA); 2190 } 2191 2192 host->mrq = NULL; 2193 host->cmd = NULL; 2194 host->data = NULL; 2195 2196 #ifndef SDHCI_USE_LEDS_CLASS 2197 sdhci_deactivate_led(host); 2198 #endif 2199 2200 mmiowb(); 2201 spin_unlock_irqrestore(&host->lock, flags); 2202 2203 mmc_request_done(host->mmc, mrq); 2204 sdhci_runtime_pm_put(host); 2205 } 2206 2207 static void sdhci_timeout_timer(unsigned long data) 2208 { 2209 struct sdhci_host *host; 2210 unsigned long flags; 2211 2212 host = (struct sdhci_host*)data; 2213 2214 spin_lock_irqsave(&host->lock, flags); 2215 2216 if (host->mrq) { 2217 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2218 mmc_hostname(host->mmc)); 2219 sdhci_dumpregs(host); 2220 2221 if (host->data) { 2222 host->data->error = -ETIMEDOUT; 2223 sdhci_finish_data(host); 2224 } else { 2225 if (host->cmd) 2226 host->cmd->error = -ETIMEDOUT; 2227 else 2228 host->mrq->cmd->error = -ETIMEDOUT; 2229 2230 tasklet_schedule(&host->finish_tasklet); 2231 } 2232 } 2233 2234 mmiowb(); 2235 spin_unlock_irqrestore(&host->lock, flags); 2236 } 2237 2238 /*****************************************************************************\ 2239 * * 2240 * Interrupt handling * 2241 * * 2242 \*****************************************************************************/ 2243 2244 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 2245 { 2246 BUG_ON(intmask == 0); 2247 2248 if (!host->cmd) { 2249 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2250 mmc_hostname(host->mmc), (unsigned)intmask); 2251 sdhci_dumpregs(host); 2252 return; 2253 } 2254 2255 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2256 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 2257 if (intmask & SDHCI_INT_TIMEOUT) 2258 host->cmd->error = -ETIMEDOUT; 2259 else 2260 host->cmd->error = -EILSEQ; 2261 2262 /* 2263 * If this command initiates a data phase and a response 2264 * CRC error is signalled, the card can start transferring 2265 * data - the card may have received the command without 2266 * error. We must not terminate the mmc_request early. 2267 * 2268 * If the card did not receive the command or returned an 2269 * error which prevented it sending data, the data phase 2270 * will time out. 2271 */ 2272 if (host->cmd->data && 2273 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 2274 SDHCI_INT_CRC) { 2275 host->cmd = NULL; 2276 return; 2277 } 2278 2279 tasklet_schedule(&host->finish_tasklet); 2280 return; 2281 } 2282 2283 /* 2284 * The host can send and interrupt when the busy state has 2285 * ended, allowing us to wait without wasting CPU cycles. 2286 * Unfortunately this is overloaded on the "data complete" 2287 * interrupt, so we need to take some care when handling 2288 * it. 2289 * 2290 * Note: The 1.0 specification is a bit ambiguous about this 2291 * feature so there might be some problems with older 2292 * controllers. 2293 */ 2294 if (host->cmd->flags & MMC_RSP_BUSY) { 2295 if (host->cmd->data) 2296 DBG("Cannot wait for busy signal when also doing a data transfer"); 2297 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) 2298 && !host->busy_handle) { 2299 /* Mark that command complete before busy is ended */ 2300 host->busy_handle = 1; 2301 return; 2302 } 2303 2304 /* The controller does not support the end-of-busy IRQ, 2305 * fall through and take the SDHCI_INT_RESPONSE */ 2306 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 2307 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { 2308 *mask &= ~SDHCI_INT_DATA_END; 2309 } 2310 2311 if (intmask & SDHCI_INT_RESPONSE) 2312 sdhci_finish_command(host); 2313 } 2314 2315 #ifdef CONFIG_MMC_DEBUG 2316 static void sdhci_adma_show_error(struct sdhci_host *host) 2317 { 2318 const char *name = mmc_hostname(host->mmc); 2319 void *desc = host->adma_table; 2320 2321 sdhci_dumpregs(host); 2322 2323 while (true) { 2324 struct sdhci_adma2_64_desc *dma_desc = desc; 2325 2326 if (host->flags & SDHCI_USE_64_BIT_DMA) 2327 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2328 name, desc, le32_to_cpu(dma_desc->addr_hi), 2329 le32_to_cpu(dma_desc->addr_lo), 2330 le16_to_cpu(dma_desc->len), 2331 le16_to_cpu(dma_desc->cmd)); 2332 else 2333 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2334 name, desc, le32_to_cpu(dma_desc->addr_lo), 2335 le16_to_cpu(dma_desc->len), 2336 le16_to_cpu(dma_desc->cmd)); 2337 2338 desc += host->desc_sz; 2339 2340 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2341 break; 2342 } 2343 } 2344 #else 2345 static void sdhci_adma_show_error(struct sdhci_host *host) { } 2346 #endif 2347 2348 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2349 { 2350 u32 command; 2351 BUG_ON(intmask == 0); 2352 2353 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2354 if (intmask & SDHCI_INT_DATA_AVAIL) { 2355 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2356 if (command == MMC_SEND_TUNING_BLOCK || 2357 command == MMC_SEND_TUNING_BLOCK_HS200) { 2358 host->tuning_done = 1; 2359 wake_up(&host->buf_ready_int); 2360 return; 2361 } 2362 } 2363 2364 if (!host->data) { 2365 /* 2366 * The "data complete" interrupt is also used to 2367 * indicate that a busy state has ended. See comment 2368 * above in sdhci_cmd_irq(). 2369 */ 2370 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2371 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2372 host->cmd->error = -ETIMEDOUT; 2373 tasklet_schedule(&host->finish_tasklet); 2374 return; 2375 } 2376 if (intmask & SDHCI_INT_DATA_END) { 2377 /* 2378 * Some cards handle busy-end interrupt 2379 * before the command completed, so make 2380 * sure we do things in the proper order. 2381 */ 2382 if (host->busy_handle) 2383 sdhci_finish_command(host); 2384 else 2385 host->busy_handle = 1; 2386 return; 2387 } 2388 } 2389 2390 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2391 mmc_hostname(host->mmc), (unsigned)intmask); 2392 sdhci_dumpregs(host); 2393 2394 return; 2395 } 2396 2397 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2398 host->data->error = -ETIMEDOUT; 2399 else if (intmask & SDHCI_INT_DATA_END_BIT) 2400 host->data->error = -EILSEQ; 2401 else if ((intmask & SDHCI_INT_DATA_CRC) && 2402 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2403 != MMC_BUS_TEST_R) 2404 host->data->error = -EILSEQ; 2405 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2406 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2407 sdhci_adma_show_error(host); 2408 host->data->error = -EIO; 2409 if (host->ops->adma_workaround) 2410 host->ops->adma_workaround(host, intmask); 2411 } 2412 2413 if (host->data->error) 2414 sdhci_finish_data(host); 2415 else { 2416 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2417 sdhci_transfer_pio(host); 2418 2419 /* 2420 * We currently don't do anything fancy with DMA 2421 * boundaries, but as we can't disable the feature 2422 * we need to at least restart the transfer. 2423 * 2424 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2425 * should return a valid address to continue from, but as 2426 * some controllers are faulty, don't trust them. 2427 */ 2428 if (intmask & SDHCI_INT_DMA_END) { 2429 u32 dmastart, dmanow; 2430 dmastart = sg_dma_address(host->data->sg); 2431 dmanow = dmastart + host->data->bytes_xfered; 2432 /* 2433 * Force update to the next DMA block boundary. 2434 */ 2435 dmanow = (dmanow & 2436 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2437 SDHCI_DEFAULT_BOUNDARY_SIZE; 2438 host->data->bytes_xfered = dmanow - dmastart; 2439 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2440 " next 0x%08x\n", 2441 mmc_hostname(host->mmc), dmastart, 2442 host->data->bytes_xfered, dmanow); 2443 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2444 } 2445 2446 if (intmask & SDHCI_INT_DATA_END) { 2447 if (host->cmd) { 2448 /* 2449 * Data managed to finish before the 2450 * command completed. Make sure we do 2451 * things in the proper order. 2452 */ 2453 host->data_early = 1; 2454 } else { 2455 sdhci_finish_data(host); 2456 } 2457 } 2458 } 2459 } 2460 2461 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2462 { 2463 irqreturn_t result = IRQ_NONE; 2464 struct sdhci_host *host = dev_id; 2465 u32 intmask, mask, unexpected = 0; 2466 int max_loops = 16; 2467 2468 spin_lock(&host->lock); 2469 2470 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2471 spin_unlock(&host->lock); 2472 return IRQ_NONE; 2473 } 2474 2475 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2476 if (!intmask || intmask == 0xffffffff) { 2477 result = IRQ_NONE; 2478 goto out; 2479 } 2480 2481 do { 2482 /* Clear selected interrupts. */ 2483 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2484 SDHCI_INT_BUS_POWER); 2485 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2486 2487 DBG("*** %s got interrupt: 0x%08x\n", 2488 mmc_hostname(host->mmc), intmask); 2489 2490 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2491 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2492 SDHCI_CARD_PRESENT; 2493 2494 /* 2495 * There is a observation on i.mx esdhc. INSERT 2496 * bit will be immediately set again when it gets 2497 * cleared, if a card is inserted. We have to mask 2498 * the irq to prevent interrupt storm which will 2499 * freeze the system. And the REMOVE gets the 2500 * same situation. 2501 * 2502 * More testing are needed here to ensure it works 2503 * for other platforms though. 2504 */ 2505 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2506 SDHCI_INT_CARD_REMOVE); 2507 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2508 SDHCI_INT_CARD_INSERT; 2509 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2510 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2511 2512 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2513 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2514 2515 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2516 SDHCI_INT_CARD_REMOVE); 2517 result = IRQ_WAKE_THREAD; 2518 } 2519 2520 if (intmask & SDHCI_INT_CMD_MASK) 2521 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, 2522 &intmask); 2523 2524 if (intmask & SDHCI_INT_DATA_MASK) 2525 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2526 2527 if (intmask & SDHCI_INT_BUS_POWER) 2528 pr_err("%s: Card is consuming too much power!\n", 2529 mmc_hostname(host->mmc)); 2530 2531 if (intmask & SDHCI_INT_CARD_INT) { 2532 sdhci_enable_sdio_irq_nolock(host, false); 2533 host->thread_isr |= SDHCI_INT_CARD_INT; 2534 result = IRQ_WAKE_THREAD; 2535 } 2536 2537 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2538 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2539 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2540 SDHCI_INT_CARD_INT); 2541 2542 if (intmask) { 2543 unexpected |= intmask; 2544 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2545 } 2546 2547 if (result == IRQ_NONE) 2548 result = IRQ_HANDLED; 2549 2550 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2551 } while (intmask && --max_loops); 2552 out: 2553 spin_unlock(&host->lock); 2554 2555 if (unexpected) { 2556 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2557 mmc_hostname(host->mmc), unexpected); 2558 sdhci_dumpregs(host); 2559 } 2560 2561 return result; 2562 } 2563 2564 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2565 { 2566 struct sdhci_host *host = dev_id; 2567 unsigned long flags; 2568 u32 isr; 2569 2570 spin_lock_irqsave(&host->lock, flags); 2571 isr = host->thread_isr; 2572 host->thread_isr = 0; 2573 spin_unlock_irqrestore(&host->lock, flags); 2574 2575 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2576 sdhci_card_event(host->mmc); 2577 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2578 } 2579 2580 if (isr & SDHCI_INT_CARD_INT) { 2581 sdio_run_irqs(host->mmc); 2582 2583 spin_lock_irqsave(&host->lock, flags); 2584 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2585 sdhci_enable_sdio_irq_nolock(host, true); 2586 spin_unlock_irqrestore(&host->lock, flags); 2587 } 2588 2589 return isr ? IRQ_HANDLED : IRQ_NONE; 2590 } 2591 2592 /*****************************************************************************\ 2593 * * 2594 * Suspend/resume * 2595 * * 2596 \*****************************************************************************/ 2597 2598 #ifdef CONFIG_PM 2599 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2600 { 2601 u8 val; 2602 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2603 | SDHCI_WAKE_ON_INT; 2604 2605 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2606 val |= mask ; 2607 /* Avoid fake wake up */ 2608 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2609 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2610 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2611 } 2612 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2613 2614 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2615 { 2616 u8 val; 2617 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2618 | SDHCI_WAKE_ON_INT; 2619 2620 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2621 val &= ~mask; 2622 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2623 } 2624 2625 int sdhci_suspend_host(struct sdhci_host *host) 2626 { 2627 sdhci_disable_card_detection(host); 2628 2629 mmc_retune_timer_stop(host->mmc); 2630 mmc_retune_needed(host->mmc); 2631 2632 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2633 host->ier = 0; 2634 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2635 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2636 free_irq(host->irq, host); 2637 } else { 2638 sdhci_enable_irq_wakeups(host); 2639 enable_irq_wake(host->irq); 2640 } 2641 return 0; 2642 } 2643 2644 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2645 2646 int sdhci_resume_host(struct sdhci_host *host) 2647 { 2648 int ret = 0; 2649 2650 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2651 if (host->ops->enable_dma) 2652 host->ops->enable_dma(host); 2653 } 2654 2655 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2656 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2657 /* Card keeps power but host controller does not */ 2658 sdhci_init(host, 0); 2659 host->pwr = 0; 2660 host->clock = 0; 2661 sdhci_do_set_ios(host, &host->mmc->ios); 2662 } else { 2663 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2664 mmiowb(); 2665 } 2666 2667 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2668 ret = request_threaded_irq(host->irq, sdhci_irq, 2669 sdhci_thread_irq, IRQF_SHARED, 2670 mmc_hostname(host->mmc), host); 2671 if (ret) 2672 return ret; 2673 } else { 2674 sdhci_disable_irq_wakeups(host); 2675 disable_irq_wake(host->irq); 2676 } 2677 2678 sdhci_enable_card_detection(host); 2679 2680 return ret; 2681 } 2682 2683 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2684 2685 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2686 { 2687 return pm_runtime_get_sync(host->mmc->parent); 2688 } 2689 2690 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2691 { 2692 pm_runtime_mark_last_busy(host->mmc->parent); 2693 return pm_runtime_put_autosuspend(host->mmc->parent); 2694 } 2695 2696 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2697 { 2698 if (host->bus_on) 2699 return; 2700 host->bus_on = true; 2701 pm_runtime_get_noresume(host->mmc->parent); 2702 } 2703 2704 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2705 { 2706 if (!host->bus_on) 2707 return; 2708 host->bus_on = false; 2709 pm_runtime_put_noidle(host->mmc->parent); 2710 } 2711 2712 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2713 { 2714 unsigned long flags; 2715 2716 mmc_retune_timer_stop(host->mmc); 2717 mmc_retune_needed(host->mmc); 2718 2719 spin_lock_irqsave(&host->lock, flags); 2720 host->ier &= SDHCI_INT_CARD_INT; 2721 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2722 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2723 spin_unlock_irqrestore(&host->lock, flags); 2724 2725 synchronize_hardirq(host->irq); 2726 2727 spin_lock_irqsave(&host->lock, flags); 2728 host->runtime_suspended = true; 2729 spin_unlock_irqrestore(&host->lock, flags); 2730 2731 return 0; 2732 } 2733 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2734 2735 int sdhci_runtime_resume_host(struct sdhci_host *host) 2736 { 2737 unsigned long flags; 2738 int host_flags = host->flags; 2739 2740 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2741 if (host->ops->enable_dma) 2742 host->ops->enable_dma(host); 2743 } 2744 2745 sdhci_init(host, 0); 2746 2747 /* Force clock and power re-program */ 2748 host->pwr = 0; 2749 host->clock = 0; 2750 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2751 sdhci_do_set_ios(host, &host->mmc->ios); 2752 2753 if ((host_flags & SDHCI_PV_ENABLED) && 2754 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2755 spin_lock_irqsave(&host->lock, flags); 2756 sdhci_enable_preset_value(host, true); 2757 spin_unlock_irqrestore(&host->lock, flags); 2758 } 2759 2760 spin_lock_irqsave(&host->lock, flags); 2761 2762 host->runtime_suspended = false; 2763 2764 /* Enable SDIO IRQ */ 2765 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2766 sdhci_enable_sdio_irq_nolock(host, true); 2767 2768 /* Enable Card Detection */ 2769 sdhci_enable_card_detection(host); 2770 2771 spin_unlock_irqrestore(&host->lock, flags); 2772 2773 return 0; 2774 } 2775 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2776 2777 #endif /* CONFIG_PM */ 2778 2779 /*****************************************************************************\ 2780 * * 2781 * Device allocation/registration * 2782 * * 2783 \*****************************************************************************/ 2784 2785 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2786 size_t priv_size) 2787 { 2788 struct mmc_host *mmc; 2789 struct sdhci_host *host; 2790 2791 WARN_ON(dev == NULL); 2792 2793 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2794 if (!mmc) 2795 return ERR_PTR(-ENOMEM); 2796 2797 host = mmc_priv(mmc); 2798 host->mmc = mmc; 2799 host->mmc_host_ops = sdhci_ops; 2800 mmc->ops = &host->mmc_host_ops; 2801 2802 return host; 2803 } 2804 2805 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2806 2807 static int sdhci_set_dma_mask(struct sdhci_host *host) 2808 { 2809 struct mmc_host *mmc = host->mmc; 2810 struct device *dev = mmc_dev(mmc); 2811 int ret = -EINVAL; 2812 2813 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 2814 host->flags &= ~SDHCI_USE_64_BIT_DMA; 2815 2816 /* Try 64-bit mask if hardware is capable of it */ 2817 if (host->flags & SDHCI_USE_64_BIT_DMA) { 2818 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 2819 if (ret) { 2820 pr_warn("%s: Failed to set 64-bit DMA mask.\n", 2821 mmc_hostname(mmc)); 2822 host->flags &= ~SDHCI_USE_64_BIT_DMA; 2823 } 2824 } 2825 2826 /* 32-bit mask as default & fallback */ 2827 if (ret) { 2828 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 2829 if (ret) 2830 pr_warn("%s: Failed to set 32-bit DMA mask.\n", 2831 mmc_hostname(mmc)); 2832 } 2833 2834 return ret; 2835 } 2836 2837 int sdhci_add_host(struct sdhci_host *host) 2838 { 2839 struct mmc_host *mmc; 2840 u32 caps[2] = {0, 0}; 2841 u32 max_current_caps; 2842 unsigned int ocr_avail; 2843 unsigned int override_timeout_clk; 2844 u32 max_clk; 2845 int ret; 2846 2847 WARN_ON(host == NULL); 2848 if (host == NULL) 2849 return -EINVAL; 2850 2851 mmc = host->mmc; 2852 2853 if (debug_quirks) 2854 host->quirks = debug_quirks; 2855 if (debug_quirks2) 2856 host->quirks2 = debug_quirks2; 2857 2858 override_timeout_clk = host->timeout_clk; 2859 2860 sdhci_do_reset(host, SDHCI_RESET_ALL); 2861 2862 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2863 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2864 >> SDHCI_SPEC_VER_SHIFT; 2865 if (host->version > SDHCI_SPEC_300) { 2866 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 2867 mmc_hostname(mmc), host->version); 2868 } 2869 2870 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2871 sdhci_readl(host, SDHCI_CAPABILITIES); 2872 2873 if (host->version >= SDHCI_SPEC_300) 2874 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2875 host->caps1 : 2876 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2877 2878 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2879 host->flags |= SDHCI_USE_SDMA; 2880 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2881 DBG("Controller doesn't have SDMA capability\n"); 2882 else 2883 host->flags |= SDHCI_USE_SDMA; 2884 2885 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2886 (host->flags & SDHCI_USE_SDMA)) { 2887 DBG("Disabling DMA as it is marked broken\n"); 2888 host->flags &= ~SDHCI_USE_SDMA; 2889 } 2890 2891 if ((host->version >= SDHCI_SPEC_200) && 2892 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2893 host->flags |= SDHCI_USE_ADMA; 2894 2895 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2896 (host->flags & SDHCI_USE_ADMA)) { 2897 DBG("Disabling ADMA as it is marked broken\n"); 2898 host->flags &= ~SDHCI_USE_ADMA; 2899 } 2900 2901 /* 2902 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 2903 * and *must* do 64-bit DMA. A driver has the opportunity to change 2904 * that during the first call to ->enable_dma(). Similarly 2905 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 2906 * implement. 2907 */ 2908 if (caps[0] & SDHCI_CAN_64BIT) 2909 host->flags |= SDHCI_USE_64_BIT_DMA; 2910 2911 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2912 ret = sdhci_set_dma_mask(host); 2913 2914 if (!ret && host->ops->enable_dma) 2915 ret = host->ops->enable_dma(host); 2916 2917 if (ret) { 2918 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 2919 mmc_hostname(mmc)); 2920 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2921 2922 ret = 0; 2923 } 2924 } 2925 2926 /* SDMA does not support 64-bit DMA */ 2927 if (host->flags & SDHCI_USE_64_BIT_DMA) 2928 host->flags &= ~SDHCI_USE_SDMA; 2929 2930 if (host->flags & SDHCI_USE_ADMA) { 2931 dma_addr_t dma; 2932 void *buf; 2933 2934 /* 2935 * The DMA descriptor table size is calculated as the maximum 2936 * number of segments times 2, to allow for an alignment 2937 * descriptor for each segment, plus 1 for a nop end descriptor, 2938 * all multipled by the descriptor size. 2939 */ 2940 if (host->flags & SDHCI_USE_64_BIT_DMA) { 2941 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 2942 SDHCI_ADMA2_64_DESC_SZ; 2943 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 2944 } else { 2945 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 2946 SDHCI_ADMA2_32_DESC_SZ; 2947 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 2948 } 2949 2950 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 2951 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + 2952 host->adma_table_sz, &dma, GFP_KERNEL); 2953 if (!buf) { 2954 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 2955 mmc_hostname(mmc)); 2956 host->flags &= ~SDHCI_USE_ADMA; 2957 } else if ((dma + host->align_buffer_sz) & 2958 (SDHCI_ADMA2_DESC_ALIGN - 1)) { 2959 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 2960 mmc_hostname(mmc)); 2961 host->flags &= ~SDHCI_USE_ADMA; 2962 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 2963 host->adma_table_sz, buf, dma); 2964 } else { 2965 host->align_buffer = buf; 2966 host->align_addr = dma; 2967 2968 host->adma_table = buf + host->align_buffer_sz; 2969 host->adma_addr = dma + host->align_buffer_sz; 2970 } 2971 } 2972 2973 /* 2974 * If we use DMA, then it's up to the caller to set the DMA 2975 * mask, but PIO does not need the hw shim so we set a new 2976 * mask here in that case. 2977 */ 2978 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2979 host->dma_mask = DMA_BIT_MASK(64); 2980 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2981 } 2982 2983 if (host->version >= SDHCI_SPEC_300) 2984 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2985 >> SDHCI_CLOCK_BASE_SHIFT; 2986 else 2987 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2988 >> SDHCI_CLOCK_BASE_SHIFT; 2989 2990 host->max_clk *= 1000000; 2991 if (host->max_clk == 0 || host->quirks & 2992 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2993 if (!host->ops->get_max_clock) { 2994 pr_err("%s: Hardware doesn't specify base clock frequency.\n", 2995 mmc_hostname(mmc)); 2996 return -ENODEV; 2997 } 2998 host->max_clk = host->ops->get_max_clock(host); 2999 } 3000 3001 /* 3002 * In case of Host Controller v3.00, find out whether clock 3003 * multiplier is supported. 3004 */ 3005 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 3006 SDHCI_CLOCK_MUL_SHIFT; 3007 3008 /* 3009 * In case the value in Clock Multiplier is 0, then programmable 3010 * clock mode is not supported, otherwise the actual clock 3011 * multiplier is one more than the value of Clock Multiplier 3012 * in the Capabilities Register. 3013 */ 3014 if (host->clk_mul) 3015 host->clk_mul += 1; 3016 3017 /* 3018 * Set host parameters. 3019 */ 3020 max_clk = host->max_clk; 3021 3022 if (host->ops->get_min_clock) 3023 mmc->f_min = host->ops->get_min_clock(host); 3024 else if (host->version >= SDHCI_SPEC_300) { 3025 if (host->clk_mul) { 3026 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3027 max_clk = host->max_clk * host->clk_mul; 3028 } else 3029 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3030 } else 3031 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3032 3033 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk))) 3034 mmc->f_max = max_clk; 3035 3036 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3037 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> 3038 SDHCI_TIMEOUT_CLK_SHIFT; 3039 if (host->timeout_clk == 0) { 3040 if (host->ops->get_timeout_clock) { 3041 host->timeout_clk = 3042 host->ops->get_timeout_clock(host); 3043 } else { 3044 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3045 mmc_hostname(mmc)); 3046 return -ENODEV; 3047 } 3048 } 3049 3050 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 3051 host->timeout_clk *= 1000; 3052 3053 if (override_timeout_clk) 3054 host->timeout_clk = override_timeout_clk; 3055 3056 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3057 host->ops->get_max_timeout_count(host) : 1 << 27; 3058 mmc->max_busy_timeout /= host->timeout_clk; 3059 } 3060 3061 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3062 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3063 3064 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3065 host->flags |= SDHCI_AUTO_CMD12; 3066 3067 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 3068 if ((host->version >= SDHCI_SPEC_300) && 3069 ((host->flags & SDHCI_USE_ADMA) || 3070 !(host->flags & SDHCI_USE_SDMA)) && 3071 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 3072 host->flags |= SDHCI_AUTO_CMD23; 3073 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 3074 } else { 3075 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 3076 } 3077 3078 /* 3079 * A controller may support 8-bit width, but the board itself 3080 * might not have the pins brought out. Boards that support 3081 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3082 * their platform code before calling sdhci_add_host(), and we 3083 * won't assume 8-bit width for hosts without that CAP. 3084 */ 3085 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3086 mmc->caps |= MMC_CAP_4_BIT_DATA; 3087 3088 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3089 mmc->caps &= ~MMC_CAP_CMD23; 3090 3091 if (caps[0] & SDHCI_CAN_DO_HISPD) 3092 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3093 3094 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3095 !(mmc->caps & MMC_CAP_NONREMOVABLE) && 3096 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) 3097 mmc->caps |= MMC_CAP_NEEDS_POLL; 3098 3099 /* If there are external regulators, get them */ 3100 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) 3101 return -EPROBE_DEFER; 3102 3103 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3104 if (!IS_ERR(mmc->supply.vqmmc)) { 3105 ret = regulator_enable(mmc->supply.vqmmc); 3106 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3107 1950000)) 3108 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 3109 SDHCI_SUPPORT_SDR50 | 3110 SDHCI_SUPPORT_DDR50); 3111 if (ret) { 3112 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3113 mmc_hostname(mmc), ret); 3114 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3115 } 3116 } 3117 3118 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 3119 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3120 SDHCI_SUPPORT_DDR50); 3121 3122 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3123 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3124 SDHCI_SUPPORT_DDR50)) 3125 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3126 3127 /* SDR104 supports also implies SDR50 support */ 3128 if (caps[1] & SDHCI_SUPPORT_SDR104) { 3129 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3130 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3131 * field can be promoted to support HS200. 3132 */ 3133 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3134 mmc->caps2 |= MMC_CAP2_HS200; 3135 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3136 mmc->caps |= MMC_CAP_UHS_SDR50; 3137 3138 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3139 (caps[1] & SDHCI_SUPPORT_HS400)) 3140 mmc->caps2 |= MMC_CAP2_HS400; 3141 3142 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3143 (IS_ERR(mmc->supply.vqmmc) || 3144 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3145 1300000))) 3146 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3147 3148 if ((caps[1] & SDHCI_SUPPORT_DDR50) && 3149 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3150 mmc->caps |= MMC_CAP_UHS_DDR50; 3151 3152 /* Does the host need tuning for SDR50? */ 3153 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3154 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3155 3156 /* Does the host need tuning for SDR104 / HS200? */ 3157 if (mmc->caps2 & MMC_CAP2_HS200) 3158 host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3159 3160 /* Driver Type(s) (A, C, D) supported by the host */ 3161 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3162 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3163 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3164 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3165 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3166 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3167 3168 /* Initial value for re-tuning timer count */ 3169 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3170 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3171 3172 /* 3173 * In case Re-tuning Timer is not disabled, the actual value of 3174 * re-tuning timer will be 2 ^ (n - 1). 3175 */ 3176 if (host->tuning_count) 3177 host->tuning_count = 1 << (host->tuning_count - 1); 3178 3179 /* Re-tuning mode supported by the Host Controller */ 3180 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3181 SDHCI_RETUNING_MODE_SHIFT; 3182 3183 ocr_avail = 0; 3184 3185 /* 3186 * According to SD Host Controller spec v3.00, if the Host System 3187 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3188 * the value is meaningful only if Voltage Support in the Capabilities 3189 * register is set. The actual current value is 4 times the register 3190 * value. 3191 */ 3192 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3193 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3194 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3195 if (curr > 0) { 3196 3197 /* convert to SDHCI_MAX_CURRENT format */ 3198 curr = curr/1000; /* convert to mA */ 3199 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3200 3201 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3202 max_current_caps = 3203 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3204 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3205 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3206 } 3207 } 3208 3209 if (caps[0] & SDHCI_CAN_VDD_330) { 3210 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3211 3212 mmc->max_current_330 = ((max_current_caps & 3213 SDHCI_MAX_CURRENT_330_MASK) >> 3214 SDHCI_MAX_CURRENT_330_SHIFT) * 3215 SDHCI_MAX_CURRENT_MULTIPLIER; 3216 } 3217 if (caps[0] & SDHCI_CAN_VDD_300) { 3218 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3219 3220 mmc->max_current_300 = ((max_current_caps & 3221 SDHCI_MAX_CURRENT_300_MASK) >> 3222 SDHCI_MAX_CURRENT_300_SHIFT) * 3223 SDHCI_MAX_CURRENT_MULTIPLIER; 3224 } 3225 if (caps[0] & SDHCI_CAN_VDD_180) { 3226 ocr_avail |= MMC_VDD_165_195; 3227 3228 mmc->max_current_180 = ((max_current_caps & 3229 SDHCI_MAX_CURRENT_180_MASK) >> 3230 SDHCI_MAX_CURRENT_180_SHIFT) * 3231 SDHCI_MAX_CURRENT_MULTIPLIER; 3232 } 3233 3234 /* If OCR set by host, use it instead. */ 3235 if (host->ocr_mask) 3236 ocr_avail = host->ocr_mask; 3237 3238 /* If OCR set by external regulators, give it highest prio. */ 3239 if (mmc->ocr_avail) 3240 ocr_avail = mmc->ocr_avail; 3241 3242 mmc->ocr_avail = ocr_avail; 3243 mmc->ocr_avail_sdio = ocr_avail; 3244 if (host->ocr_avail_sdio) 3245 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3246 mmc->ocr_avail_sd = ocr_avail; 3247 if (host->ocr_avail_sd) 3248 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3249 else /* normal SD controllers don't support 1.8V */ 3250 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3251 mmc->ocr_avail_mmc = ocr_avail; 3252 if (host->ocr_avail_mmc) 3253 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3254 3255 if (mmc->ocr_avail == 0) { 3256 pr_err("%s: Hardware doesn't report any support voltages.\n", 3257 mmc_hostname(mmc)); 3258 return -ENODEV; 3259 } 3260 3261 spin_lock_init(&host->lock); 3262 3263 /* 3264 * Maximum number of segments. Depends on if the hardware 3265 * can do scatter/gather or not. 3266 */ 3267 if (host->flags & SDHCI_USE_ADMA) 3268 mmc->max_segs = SDHCI_MAX_SEGS; 3269 else if (host->flags & SDHCI_USE_SDMA) 3270 mmc->max_segs = 1; 3271 else /* PIO */ 3272 mmc->max_segs = SDHCI_MAX_SEGS; 3273 3274 /* 3275 * Maximum number of sectors in one transfer. Limited by SDMA boundary 3276 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3277 * is less anyway. 3278 */ 3279 mmc->max_req_size = 524288; 3280 3281 /* 3282 * Maximum segment size. Could be one segment with the maximum number 3283 * of bytes. When doing hardware scatter/gather, each entry cannot 3284 * be larger than 64 KiB though. 3285 */ 3286 if (host->flags & SDHCI_USE_ADMA) { 3287 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3288 mmc->max_seg_size = 65535; 3289 else 3290 mmc->max_seg_size = 65536; 3291 } else { 3292 mmc->max_seg_size = mmc->max_req_size; 3293 } 3294 3295 /* 3296 * Maximum block size. This varies from controller to controller and 3297 * is specified in the capabilities register. 3298 */ 3299 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3300 mmc->max_blk_size = 2; 3301 } else { 3302 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3303 SDHCI_MAX_BLOCK_SHIFT; 3304 if (mmc->max_blk_size >= 3) { 3305 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3306 mmc_hostname(mmc)); 3307 mmc->max_blk_size = 0; 3308 } 3309 } 3310 3311 mmc->max_blk_size = 512 << mmc->max_blk_size; 3312 3313 /* 3314 * Maximum block count. 3315 */ 3316 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3317 3318 /* 3319 * Init tasklets. 3320 */ 3321 tasklet_init(&host->finish_tasklet, 3322 sdhci_tasklet_finish, (unsigned long)host); 3323 3324 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3325 3326 init_waitqueue_head(&host->buf_ready_int); 3327 3328 sdhci_init(host, 0); 3329 3330 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3331 IRQF_SHARED, mmc_hostname(mmc), host); 3332 if (ret) { 3333 pr_err("%s: Failed to request IRQ %d: %d\n", 3334 mmc_hostname(mmc), host->irq, ret); 3335 goto untasklet; 3336 } 3337 3338 #ifdef CONFIG_MMC_DEBUG 3339 sdhci_dumpregs(host); 3340 #endif 3341 3342 #ifdef SDHCI_USE_LEDS_CLASS 3343 snprintf(host->led_name, sizeof(host->led_name), 3344 "%s::", mmc_hostname(mmc)); 3345 host->led.name = host->led_name; 3346 host->led.brightness = LED_OFF; 3347 host->led.default_trigger = mmc_hostname(mmc); 3348 host->led.brightness_set = sdhci_led_control; 3349 3350 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3351 if (ret) { 3352 pr_err("%s: Failed to register LED device: %d\n", 3353 mmc_hostname(mmc), ret); 3354 goto reset; 3355 } 3356 #endif 3357 3358 mmiowb(); 3359 3360 mmc_add_host(mmc); 3361 3362 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3363 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3364 (host->flags & SDHCI_USE_ADMA) ? 3365 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3366 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3367 3368 sdhci_enable_card_detection(host); 3369 3370 return 0; 3371 3372 #ifdef SDHCI_USE_LEDS_CLASS 3373 reset: 3374 sdhci_do_reset(host, SDHCI_RESET_ALL); 3375 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3376 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3377 free_irq(host->irq, host); 3378 #endif 3379 untasklet: 3380 tasklet_kill(&host->finish_tasklet); 3381 3382 return ret; 3383 } 3384 3385 EXPORT_SYMBOL_GPL(sdhci_add_host); 3386 3387 void sdhci_remove_host(struct sdhci_host *host, int dead) 3388 { 3389 struct mmc_host *mmc = host->mmc; 3390 unsigned long flags; 3391 3392 if (dead) { 3393 spin_lock_irqsave(&host->lock, flags); 3394 3395 host->flags |= SDHCI_DEVICE_DEAD; 3396 3397 if (host->mrq) { 3398 pr_err("%s: Controller removed during " 3399 " transfer!\n", mmc_hostname(mmc)); 3400 3401 host->mrq->cmd->error = -ENOMEDIUM; 3402 tasklet_schedule(&host->finish_tasklet); 3403 } 3404 3405 spin_unlock_irqrestore(&host->lock, flags); 3406 } 3407 3408 sdhci_disable_card_detection(host); 3409 3410 mmc_remove_host(mmc); 3411 3412 #ifdef SDHCI_USE_LEDS_CLASS 3413 led_classdev_unregister(&host->led); 3414 #endif 3415 3416 if (!dead) 3417 sdhci_do_reset(host, SDHCI_RESET_ALL); 3418 3419 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3420 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3421 free_irq(host->irq, host); 3422 3423 del_timer_sync(&host->timer); 3424 3425 tasklet_kill(&host->finish_tasklet); 3426 3427 if (!IS_ERR(mmc->supply.vqmmc)) 3428 regulator_disable(mmc->supply.vqmmc); 3429 3430 if (host->align_buffer) 3431 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3432 host->adma_table_sz, host->align_buffer, 3433 host->align_addr); 3434 3435 host->adma_table = NULL; 3436 host->align_buffer = NULL; 3437 } 3438 3439 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3440 3441 void sdhci_free_host(struct sdhci_host *host) 3442 { 3443 mmc_free_host(host->mmc); 3444 } 3445 3446 EXPORT_SYMBOL_GPL(sdhci_free_host); 3447 3448 /*****************************************************************************\ 3449 * * 3450 * Driver init/exit * 3451 * * 3452 \*****************************************************************************/ 3453 3454 static int __init sdhci_drv_init(void) 3455 { 3456 pr_info(DRIVER_NAME 3457 ": Secure Digital Host Controller Interface driver\n"); 3458 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3459 3460 return 0; 3461 } 3462 3463 static void __exit sdhci_drv_exit(void) 3464 { 3465 } 3466 3467 module_init(sdhci_drv_init); 3468 module_exit(sdhci_drv_exit); 3469 3470 module_param(debug_quirks, uint, 0444); 3471 module_param(debug_quirks2, uint, 0444); 3472 3473 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3474 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3475 MODULE_LICENSE("GPL"); 3476 3477 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3478 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3479