1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/slot-gpio.h> 32 33 #include "sdhci.h" 34 35 #define DRIVER_NAME "sdhci" 36 37 #define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42 #define SDHCI_USE_LEDS_CLASS 43 #endif 44 45 #define MAX_TUNING_LOOP 40 46 47 static unsigned int debug_quirks = 0; 48 static unsigned int debug_quirks2; 49 50 static void sdhci_finish_data(struct sdhci_host *); 51 52 static void sdhci_finish_command(struct sdhci_host *); 53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 54 static void sdhci_tuning_timer(unsigned long data); 55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 56 57 #ifdef CONFIG_PM_RUNTIME 58 static int sdhci_runtime_pm_get(struct sdhci_host *host); 59 static int sdhci_runtime_pm_put(struct sdhci_host *host); 60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 62 #else 63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 64 { 65 return 0; 66 } 67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 68 { 69 return 0; 70 } 71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 72 { 73 } 74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 75 { 76 } 77 #endif 78 79 static void sdhci_dumpregs(struct sdhci_host *host) 80 { 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 82 mmc_hostname(host->mmc)); 83 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 85 sdhci_readl(host, SDHCI_DMA_ADDRESS), 86 sdhci_readw(host, SDHCI_HOST_VERSION)); 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 88 sdhci_readw(host, SDHCI_BLOCK_SIZE), 89 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 91 sdhci_readl(host, SDHCI_ARGUMENT), 92 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 94 sdhci_readl(host, SDHCI_PRESENT_STATE), 95 sdhci_readb(host, SDHCI_HOST_CONTROL)); 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 97 sdhci_readb(host, SDHCI_POWER_CONTROL), 98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 101 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 104 sdhci_readl(host, SDHCI_INT_STATUS)); 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 106 sdhci_readl(host, SDHCI_INT_ENABLE), 107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 109 sdhci_readw(host, SDHCI_ACMD12_ERR), 110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 112 sdhci_readl(host, SDHCI_CAPABILITIES), 113 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 115 sdhci_readw(host, SDHCI_COMMAND), 116 sdhci_readl(host, SDHCI_MAX_CURRENT)); 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 118 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 119 120 if (host->flags & SDHCI_USE_ADMA) 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 122 readl(host->ioaddr + SDHCI_ADMA_ERROR), 123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 124 125 pr_debug(DRIVER_NAME ": ===========================================\n"); 126 } 127 128 /*****************************************************************************\ 129 * * 130 * Low level functions * 131 * * 132 \*****************************************************************************/ 133 134 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 135 { 136 u32 ier; 137 138 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 139 ier &= ~clear; 140 ier |= set; 141 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 142 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 143 } 144 145 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 146 { 147 sdhci_clear_set_irqs(host, 0, irqs); 148 } 149 150 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 151 { 152 sdhci_clear_set_irqs(host, irqs, 0); 153 } 154 155 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 156 { 157 u32 present, irqs; 158 159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 160 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 161 return; 162 163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 164 SDHCI_CARD_PRESENT; 165 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; 166 167 if (enable) 168 sdhci_unmask_irqs(host, irqs); 169 else 170 sdhci_mask_irqs(host, irqs); 171 } 172 173 static void sdhci_enable_card_detection(struct sdhci_host *host) 174 { 175 sdhci_set_card_detection(host, true); 176 } 177 178 static void sdhci_disable_card_detection(struct sdhci_host *host) 179 { 180 sdhci_set_card_detection(host, false); 181 } 182 183 static void sdhci_reset(struct sdhci_host *host, u8 mask) 184 { 185 unsigned long timeout; 186 u32 uninitialized_var(ier); 187 188 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 189 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 190 SDHCI_CARD_PRESENT)) 191 return; 192 } 193 194 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 195 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 196 197 if (host->ops->platform_reset_enter) 198 host->ops->platform_reset_enter(host, mask); 199 200 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 201 202 if (mask & SDHCI_RESET_ALL) { 203 host->clock = 0; 204 /* Reset-all turns off SD Bus Power */ 205 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 206 sdhci_runtime_pm_bus_off(host); 207 } 208 209 /* Wait max 100 ms */ 210 timeout = 100; 211 212 /* hw clears the bit when it's done */ 213 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 214 if (timeout == 0) { 215 pr_err("%s: Reset 0x%x never completed.\n", 216 mmc_hostname(host->mmc), (int)mask); 217 sdhci_dumpregs(host); 218 return; 219 } 220 timeout--; 221 mdelay(1); 222 } 223 224 if (host->ops->platform_reset_exit) 225 host->ops->platform_reset_exit(host, mask); 226 227 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 229 230 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 231 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) 232 host->ops->enable_dma(host); 233 } 234 } 235 236 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 237 238 static void sdhci_init(struct sdhci_host *host, int soft) 239 { 240 if (soft) 241 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 242 else 243 sdhci_reset(host, SDHCI_RESET_ALL); 244 245 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 246 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 247 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 248 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 249 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 250 251 if (soft) { 252 /* force clock reconfiguration */ 253 host->clock = 0; 254 sdhci_set_ios(host->mmc, &host->mmc->ios); 255 } 256 } 257 258 static void sdhci_reinit(struct sdhci_host *host) 259 { 260 sdhci_init(host, 0); 261 /* 262 * Retuning stuffs are affected by different cards inserted and only 263 * applicable to UHS-I cards. So reset these fields to their initial 264 * value when card is removed. 265 */ 266 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 267 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 268 269 del_timer_sync(&host->tuning_timer); 270 host->flags &= ~SDHCI_NEEDS_RETUNING; 271 host->mmc->max_blk_count = 272 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 273 } 274 sdhci_enable_card_detection(host); 275 } 276 277 static void sdhci_activate_led(struct sdhci_host *host) 278 { 279 u8 ctrl; 280 281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 282 ctrl |= SDHCI_CTRL_LED; 283 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 284 } 285 286 static void sdhci_deactivate_led(struct sdhci_host *host) 287 { 288 u8 ctrl; 289 290 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 291 ctrl &= ~SDHCI_CTRL_LED; 292 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 293 } 294 295 #ifdef SDHCI_USE_LEDS_CLASS 296 static void sdhci_led_control(struct led_classdev *led, 297 enum led_brightness brightness) 298 { 299 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 300 unsigned long flags; 301 302 spin_lock_irqsave(&host->lock, flags); 303 304 if (host->runtime_suspended) 305 goto out; 306 307 if (brightness == LED_OFF) 308 sdhci_deactivate_led(host); 309 else 310 sdhci_activate_led(host); 311 out: 312 spin_unlock_irqrestore(&host->lock, flags); 313 } 314 #endif 315 316 /*****************************************************************************\ 317 * * 318 * Core functions * 319 * * 320 \*****************************************************************************/ 321 322 static void sdhci_read_block_pio(struct sdhci_host *host) 323 { 324 unsigned long flags; 325 size_t blksize, len, chunk; 326 u32 uninitialized_var(scratch); 327 u8 *buf; 328 329 DBG("PIO reading\n"); 330 331 blksize = host->data->blksz; 332 chunk = 0; 333 334 local_irq_save(flags); 335 336 while (blksize) { 337 if (!sg_miter_next(&host->sg_miter)) 338 BUG(); 339 340 len = min(host->sg_miter.length, blksize); 341 342 blksize -= len; 343 host->sg_miter.consumed = len; 344 345 buf = host->sg_miter.addr; 346 347 while (len) { 348 if (chunk == 0) { 349 scratch = sdhci_readl(host, SDHCI_BUFFER); 350 chunk = 4; 351 } 352 353 *buf = scratch & 0xFF; 354 355 buf++; 356 scratch >>= 8; 357 chunk--; 358 len--; 359 } 360 } 361 362 sg_miter_stop(&host->sg_miter); 363 364 local_irq_restore(flags); 365 } 366 367 static void sdhci_write_block_pio(struct sdhci_host *host) 368 { 369 unsigned long flags; 370 size_t blksize, len, chunk; 371 u32 scratch; 372 u8 *buf; 373 374 DBG("PIO writing\n"); 375 376 blksize = host->data->blksz; 377 chunk = 0; 378 scratch = 0; 379 380 local_irq_save(flags); 381 382 while (blksize) { 383 if (!sg_miter_next(&host->sg_miter)) 384 BUG(); 385 386 len = min(host->sg_miter.length, blksize); 387 388 blksize -= len; 389 host->sg_miter.consumed = len; 390 391 buf = host->sg_miter.addr; 392 393 while (len) { 394 scratch |= (u32)*buf << (chunk * 8); 395 396 buf++; 397 chunk++; 398 len--; 399 400 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 401 sdhci_writel(host, scratch, SDHCI_BUFFER); 402 chunk = 0; 403 scratch = 0; 404 } 405 } 406 } 407 408 sg_miter_stop(&host->sg_miter); 409 410 local_irq_restore(flags); 411 } 412 413 static void sdhci_transfer_pio(struct sdhci_host *host) 414 { 415 u32 mask; 416 417 BUG_ON(!host->data); 418 419 if (host->blocks == 0) 420 return; 421 422 if (host->data->flags & MMC_DATA_READ) 423 mask = SDHCI_DATA_AVAILABLE; 424 else 425 mask = SDHCI_SPACE_AVAILABLE; 426 427 /* 428 * Some controllers (JMicron JMB38x) mess up the buffer bits 429 * for transfers < 4 bytes. As long as it is just one block, 430 * we can ignore the bits. 431 */ 432 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 433 (host->data->blocks == 1)) 434 mask = ~0; 435 436 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 437 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 438 udelay(100); 439 440 if (host->data->flags & MMC_DATA_READ) 441 sdhci_read_block_pio(host); 442 else 443 sdhci_write_block_pio(host); 444 445 host->blocks--; 446 if (host->blocks == 0) 447 break; 448 } 449 450 DBG("PIO transfer complete.\n"); 451 } 452 453 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 454 { 455 local_irq_save(*flags); 456 return kmap_atomic(sg_page(sg)) + sg->offset; 457 } 458 459 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 460 { 461 kunmap_atomic(buffer); 462 local_irq_restore(*flags); 463 } 464 465 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 466 { 467 __le32 *dataddr = (__le32 __force *)(desc + 4); 468 __le16 *cmdlen = (__le16 __force *)desc; 469 470 /* SDHCI specification says ADMA descriptors should be 4 byte 471 * aligned, so using 16 or 32bit operations should be safe. */ 472 473 cmdlen[0] = cpu_to_le16(cmd); 474 cmdlen[1] = cpu_to_le16(len); 475 476 dataddr[0] = cpu_to_le32(addr); 477 } 478 479 static int sdhci_adma_table_pre(struct sdhci_host *host, 480 struct mmc_data *data) 481 { 482 int direction; 483 484 u8 *desc; 485 u8 *align; 486 dma_addr_t addr; 487 dma_addr_t align_addr; 488 int len, offset; 489 490 struct scatterlist *sg; 491 int i; 492 char *buffer; 493 unsigned long flags; 494 495 /* 496 * The spec does not specify endianness of descriptor table. 497 * We currently guess that it is LE. 498 */ 499 500 if (data->flags & MMC_DATA_READ) 501 direction = DMA_FROM_DEVICE; 502 else 503 direction = DMA_TO_DEVICE; 504 505 /* 506 * The ADMA descriptor table is mapped further down as we 507 * need to fill it with data first. 508 */ 509 510 host->align_addr = dma_map_single(mmc_dev(host->mmc), 511 host->align_buffer, 128 * 4, direction); 512 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 513 goto fail; 514 BUG_ON(host->align_addr & 0x3); 515 516 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 517 data->sg, data->sg_len, direction); 518 if (host->sg_count == 0) 519 goto unmap_align; 520 521 desc = host->adma_desc; 522 align = host->align_buffer; 523 524 align_addr = host->align_addr; 525 526 for_each_sg(data->sg, sg, host->sg_count, i) { 527 addr = sg_dma_address(sg); 528 len = sg_dma_len(sg); 529 530 /* 531 * The SDHCI specification states that ADMA 532 * addresses must be 32-bit aligned. If they 533 * aren't, then we use a bounce buffer for 534 * the (up to three) bytes that screw up the 535 * alignment. 536 */ 537 offset = (4 - (addr & 0x3)) & 0x3; 538 if (offset) { 539 if (data->flags & MMC_DATA_WRITE) { 540 buffer = sdhci_kmap_atomic(sg, &flags); 541 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 542 memcpy(align, buffer, offset); 543 sdhci_kunmap_atomic(buffer, &flags); 544 } 545 546 /* tran, valid */ 547 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 548 549 BUG_ON(offset > 65536); 550 551 align += 4; 552 align_addr += 4; 553 554 desc += 8; 555 556 addr += offset; 557 len -= offset; 558 } 559 560 BUG_ON(len > 65536); 561 562 /* tran, valid */ 563 sdhci_set_adma_desc(desc, addr, len, 0x21); 564 desc += 8; 565 566 /* 567 * If this triggers then we have a calculation bug 568 * somewhere. :/ 569 */ 570 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 571 } 572 573 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 574 /* 575 * Mark the last descriptor as the terminating descriptor 576 */ 577 if (desc != host->adma_desc) { 578 desc -= 8; 579 desc[0] |= 0x2; /* end */ 580 } 581 } else { 582 /* 583 * Add a terminating entry. 584 */ 585 586 /* nop, end, valid */ 587 sdhci_set_adma_desc(desc, 0, 0, 0x3); 588 } 589 590 /* 591 * Resync align buffer as we might have changed it. 592 */ 593 if (data->flags & MMC_DATA_WRITE) { 594 dma_sync_single_for_device(mmc_dev(host->mmc), 595 host->align_addr, 128 * 4, direction); 596 } 597 598 host->adma_addr = dma_map_single(mmc_dev(host->mmc), 599 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 600 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 601 goto unmap_entries; 602 BUG_ON(host->adma_addr & 0x3); 603 604 return 0; 605 606 unmap_entries: 607 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 608 data->sg_len, direction); 609 unmap_align: 610 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 611 128 * 4, direction); 612 fail: 613 return -EINVAL; 614 } 615 616 static void sdhci_adma_table_post(struct sdhci_host *host, 617 struct mmc_data *data) 618 { 619 int direction; 620 621 struct scatterlist *sg; 622 int i, size; 623 u8 *align; 624 char *buffer; 625 unsigned long flags; 626 627 if (data->flags & MMC_DATA_READ) 628 direction = DMA_FROM_DEVICE; 629 else 630 direction = DMA_TO_DEVICE; 631 632 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 633 (128 * 2 + 1) * 4, DMA_TO_DEVICE); 634 635 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 636 128 * 4, direction); 637 638 if (data->flags & MMC_DATA_READ) { 639 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 640 data->sg_len, direction); 641 642 align = host->align_buffer; 643 644 for_each_sg(data->sg, sg, host->sg_count, i) { 645 if (sg_dma_address(sg) & 0x3) { 646 size = 4 - (sg_dma_address(sg) & 0x3); 647 648 buffer = sdhci_kmap_atomic(sg, &flags); 649 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 650 memcpy(buffer, align, size); 651 sdhci_kunmap_atomic(buffer, &flags); 652 653 align += 4; 654 } 655 } 656 } 657 658 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 659 data->sg_len, direction); 660 } 661 662 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 663 { 664 u8 count; 665 struct mmc_data *data = cmd->data; 666 unsigned target_timeout, current_timeout; 667 668 /* 669 * If the host controller provides us with an incorrect timeout 670 * value, just skip the check and use 0xE. The hardware may take 671 * longer to time out, but that's much better than having a too-short 672 * timeout value. 673 */ 674 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 675 return 0xE; 676 677 /* Unspecified timeout, assume max */ 678 if (!data && !cmd->cmd_timeout_ms) 679 return 0xE; 680 681 /* timeout in us */ 682 if (!data) 683 target_timeout = cmd->cmd_timeout_ms * 1000; 684 else { 685 target_timeout = data->timeout_ns / 1000; 686 if (host->clock) 687 target_timeout += data->timeout_clks / host->clock; 688 } 689 690 /* 691 * Figure out needed cycles. 692 * We do this in steps in order to fit inside a 32 bit int. 693 * The first step is the minimum timeout, which will have a 694 * minimum resolution of 6 bits: 695 * (1) 2^13*1000 > 2^22, 696 * (2) host->timeout_clk < 2^16 697 * => 698 * (1) / (2) > 2^6 699 */ 700 count = 0; 701 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 702 while (current_timeout < target_timeout) { 703 count++; 704 current_timeout <<= 1; 705 if (count >= 0xF) 706 break; 707 } 708 709 if (count >= 0xF) { 710 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 711 mmc_hostname(host->mmc), count, cmd->opcode); 712 count = 0xE; 713 } 714 715 return count; 716 } 717 718 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 719 { 720 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 721 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 722 723 if (host->flags & SDHCI_REQ_USE_DMA) 724 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 725 else 726 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 727 } 728 729 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 730 { 731 u8 count; 732 u8 ctrl; 733 struct mmc_data *data = cmd->data; 734 int ret; 735 736 WARN_ON(host->data); 737 738 if (data || (cmd->flags & MMC_RSP_BUSY)) { 739 count = sdhci_calc_timeout(host, cmd); 740 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 741 } 742 743 if (!data) 744 return; 745 746 /* Sanity checks */ 747 BUG_ON(data->blksz * data->blocks > 524288); 748 BUG_ON(data->blksz > host->mmc->max_blk_size); 749 BUG_ON(data->blocks > 65535); 750 751 host->data = data; 752 host->data_early = 0; 753 host->data->bytes_xfered = 0; 754 755 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 756 host->flags |= SDHCI_REQ_USE_DMA; 757 758 /* 759 * FIXME: This doesn't account for merging when mapping the 760 * scatterlist. 761 */ 762 if (host->flags & SDHCI_REQ_USE_DMA) { 763 int broken, i; 764 struct scatterlist *sg; 765 766 broken = 0; 767 if (host->flags & SDHCI_USE_ADMA) { 768 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 769 broken = 1; 770 } else { 771 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 772 broken = 1; 773 } 774 775 if (unlikely(broken)) { 776 for_each_sg(data->sg, sg, data->sg_len, i) { 777 if (sg->length & 0x3) { 778 DBG("Reverting to PIO because of " 779 "transfer size (%d)\n", 780 sg->length); 781 host->flags &= ~SDHCI_REQ_USE_DMA; 782 break; 783 } 784 } 785 } 786 } 787 788 /* 789 * The assumption here being that alignment is the same after 790 * translation to device address space. 791 */ 792 if (host->flags & SDHCI_REQ_USE_DMA) { 793 int broken, i; 794 struct scatterlist *sg; 795 796 broken = 0; 797 if (host->flags & SDHCI_USE_ADMA) { 798 /* 799 * As we use 3 byte chunks to work around 800 * alignment problems, we need to check this 801 * quirk. 802 */ 803 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 804 broken = 1; 805 } else { 806 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 807 broken = 1; 808 } 809 810 if (unlikely(broken)) { 811 for_each_sg(data->sg, sg, data->sg_len, i) { 812 if (sg->offset & 0x3) { 813 DBG("Reverting to PIO because of " 814 "bad alignment\n"); 815 host->flags &= ~SDHCI_REQ_USE_DMA; 816 break; 817 } 818 } 819 } 820 } 821 822 if (host->flags & SDHCI_REQ_USE_DMA) { 823 if (host->flags & SDHCI_USE_ADMA) { 824 ret = sdhci_adma_table_pre(host, data); 825 if (ret) { 826 /* 827 * This only happens when someone fed 828 * us an invalid request. 829 */ 830 WARN_ON(1); 831 host->flags &= ~SDHCI_REQ_USE_DMA; 832 } else { 833 sdhci_writel(host, host->adma_addr, 834 SDHCI_ADMA_ADDRESS); 835 } 836 } else { 837 int sg_cnt; 838 839 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 840 data->sg, data->sg_len, 841 (data->flags & MMC_DATA_READ) ? 842 DMA_FROM_DEVICE : 843 DMA_TO_DEVICE); 844 if (sg_cnt == 0) { 845 /* 846 * This only happens when someone fed 847 * us an invalid request. 848 */ 849 WARN_ON(1); 850 host->flags &= ~SDHCI_REQ_USE_DMA; 851 } else { 852 WARN_ON(sg_cnt != 1); 853 sdhci_writel(host, sg_dma_address(data->sg), 854 SDHCI_DMA_ADDRESS); 855 } 856 } 857 } 858 859 /* 860 * Always adjust the DMA selection as some controllers 861 * (e.g. JMicron) can't do PIO properly when the selection 862 * is ADMA. 863 */ 864 if (host->version >= SDHCI_SPEC_200) { 865 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 866 ctrl &= ~SDHCI_CTRL_DMA_MASK; 867 if ((host->flags & SDHCI_REQ_USE_DMA) && 868 (host->flags & SDHCI_USE_ADMA)) 869 ctrl |= SDHCI_CTRL_ADMA32; 870 else 871 ctrl |= SDHCI_CTRL_SDMA; 872 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 873 } 874 875 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 876 int flags; 877 878 flags = SG_MITER_ATOMIC; 879 if (host->data->flags & MMC_DATA_READ) 880 flags |= SG_MITER_TO_SG; 881 else 882 flags |= SG_MITER_FROM_SG; 883 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 884 host->blocks = data->blocks; 885 } 886 887 sdhci_set_transfer_irqs(host); 888 889 /* Set the DMA boundary value and block size */ 890 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 891 data->blksz), SDHCI_BLOCK_SIZE); 892 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 893 } 894 895 static void sdhci_set_transfer_mode(struct sdhci_host *host, 896 struct mmc_command *cmd) 897 { 898 u16 mode; 899 struct mmc_data *data = cmd->data; 900 901 if (data == NULL) 902 return; 903 904 WARN_ON(!host->data); 905 906 mode = SDHCI_TRNS_BLK_CNT_EN; 907 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 908 mode |= SDHCI_TRNS_MULTI; 909 /* 910 * If we are sending CMD23, CMD12 never gets sent 911 * on successful completion (so no Auto-CMD12). 912 */ 913 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 914 mode |= SDHCI_TRNS_AUTO_CMD12; 915 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 916 mode |= SDHCI_TRNS_AUTO_CMD23; 917 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 918 } 919 } 920 921 if (data->flags & MMC_DATA_READ) 922 mode |= SDHCI_TRNS_READ; 923 if (host->flags & SDHCI_REQ_USE_DMA) 924 mode |= SDHCI_TRNS_DMA; 925 926 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 927 } 928 929 static void sdhci_finish_data(struct sdhci_host *host) 930 { 931 struct mmc_data *data; 932 933 BUG_ON(!host->data); 934 935 data = host->data; 936 host->data = NULL; 937 938 if (host->flags & SDHCI_REQ_USE_DMA) { 939 if (host->flags & SDHCI_USE_ADMA) 940 sdhci_adma_table_post(host, data); 941 else { 942 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 943 data->sg_len, (data->flags & MMC_DATA_READ) ? 944 DMA_FROM_DEVICE : DMA_TO_DEVICE); 945 } 946 } 947 948 /* 949 * The specification states that the block count register must 950 * be updated, but it does not specify at what point in the 951 * data flow. That makes the register entirely useless to read 952 * back so we have to assume that nothing made it to the card 953 * in the event of an error. 954 */ 955 if (data->error) 956 data->bytes_xfered = 0; 957 else 958 data->bytes_xfered = data->blksz * data->blocks; 959 960 /* 961 * Need to send CMD12 if - 962 * a) open-ended multiblock transfer (no CMD23) 963 * b) error in multiblock transfer 964 */ 965 if (data->stop && 966 (data->error || 967 !host->mrq->sbc)) { 968 969 /* 970 * The controller needs a reset of internal state machines 971 * upon error conditions. 972 */ 973 if (data->error) { 974 sdhci_reset(host, SDHCI_RESET_CMD); 975 sdhci_reset(host, SDHCI_RESET_DATA); 976 } 977 978 sdhci_send_command(host, data->stop); 979 } else 980 tasklet_schedule(&host->finish_tasklet); 981 } 982 983 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 984 { 985 int flags; 986 u32 mask; 987 unsigned long timeout; 988 989 WARN_ON(host->cmd); 990 991 /* Wait max 10 ms */ 992 timeout = 10; 993 994 mask = SDHCI_CMD_INHIBIT; 995 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 996 mask |= SDHCI_DATA_INHIBIT; 997 998 /* We shouldn't wait for data inihibit for stop commands, even 999 though they might use busy signaling */ 1000 if (host->mrq->data && (cmd == host->mrq->data->stop)) 1001 mask &= ~SDHCI_DATA_INHIBIT; 1002 1003 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1004 if (timeout == 0) { 1005 pr_err("%s: Controller never released " 1006 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 1007 sdhci_dumpregs(host); 1008 cmd->error = -EIO; 1009 tasklet_schedule(&host->finish_tasklet); 1010 return; 1011 } 1012 timeout--; 1013 mdelay(1); 1014 } 1015 1016 mod_timer(&host->timer, jiffies + 10 * HZ); 1017 1018 host->cmd = cmd; 1019 1020 sdhci_prepare_data(host, cmd); 1021 1022 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1023 1024 sdhci_set_transfer_mode(host, cmd); 1025 1026 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1027 pr_err("%s: Unsupported response type!\n", 1028 mmc_hostname(host->mmc)); 1029 cmd->error = -EINVAL; 1030 tasklet_schedule(&host->finish_tasklet); 1031 return; 1032 } 1033 1034 if (!(cmd->flags & MMC_RSP_PRESENT)) 1035 flags = SDHCI_CMD_RESP_NONE; 1036 else if (cmd->flags & MMC_RSP_136) 1037 flags = SDHCI_CMD_RESP_LONG; 1038 else if (cmd->flags & MMC_RSP_BUSY) 1039 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1040 else 1041 flags = SDHCI_CMD_RESP_SHORT; 1042 1043 if (cmd->flags & MMC_RSP_CRC) 1044 flags |= SDHCI_CMD_CRC; 1045 if (cmd->flags & MMC_RSP_OPCODE) 1046 flags |= SDHCI_CMD_INDEX; 1047 1048 /* CMD19 is special in that the Data Present Select should be set */ 1049 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1050 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1051 flags |= SDHCI_CMD_DATA; 1052 1053 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1054 } 1055 EXPORT_SYMBOL_GPL(sdhci_send_command); 1056 1057 static void sdhci_finish_command(struct sdhci_host *host) 1058 { 1059 int i; 1060 1061 BUG_ON(host->cmd == NULL); 1062 1063 if (host->cmd->flags & MMC_RSP_PRESENT) { 1064 if (host->cmd->flags & MMC_RSP_136) { 1065 /* CRC is stripped so we need to do some shifting. */ 1066 for (i = 0;i < 4;i++) { 1067 host->cmd->resp[i] = sdhci_readl(host, 1068 SDHCI_RESPONSE + (3-i)*4) << 8; 1069 if (i != 3) 1070 host->cmd->resp[i] |= 1071 sdhci_readb(host, 1072 SDHCI_RESPONSE + (3-i)*4-1); 1073 } 1074 } else { 1075 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1076 } 1077 } 1078 1079 host->cmd->error = 0; 1080 1081 /* Finished CMD23, now send actual command. */ 1082 if (host->cmd == host->mrq->sbc) { 1083 host->cmd = NULL; 1084 sdhci_send_command(host, host->mrq->cmd); 1085 } else { 1086 1087 /* Processed actual command. */ 1088 if (host->data && host->data_early) 1089 sdhci_finish_data(host); 1090 1091 if (!host->cmd->data) 1092 tasklet_schedule(&host->finish_tasklet); 1093 1094 host->cmd = NULL; 1095 } 1096 } 1097 1098 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1099 { 1100 u16 ctrl, preset = 0; 1101 1102 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1103 1104 switch (ctrl & SDHCI_CTRL_UHS_MASK) { 1105 case SDHCI_CTRL_UHS_SDR12: 1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1107 break; 1108 case SDHCI_CTRL_UHS_SDR25: 1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1110 break; 1111 case SDHCI_CTRL_UHS_SDR50: 1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1113 break; 1114 case SDHCI_CTRL_UHS_SDR104: 1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1116 break; 1117 case SDHCI_CTRL_UHS_DDR50: 1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1119 break; 1120 default: 1121 pr_warn("%s: Invalid UHS-I mode selected\n", 1122 mmc_hostname(host->mmc)); 1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1124 break; 1125 } 1126 return preset; 1127 } 1128 1129 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1130 { 1131 int div = 0; /* Initialized for compiler warning */ 1132 int real_div = div, clk_mul = 1; 1133 u16 clk = 0; 1134 unsigned long timeout; 1135 1136 if (clock && clock == host->clock) 1137 return; 1138 1139 host->mmc->actual_clock = 0; 1140 1141 if (host->ops->set_clock) { 1142 host->ops->set_clock(host, clock); 1143 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 1144 return; 1145 } 1146 1147 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1148 1149 if (clock == 0) 1150 goto out; 1151 1152 if (host->version >= SDHCI_SPEC_300) { 1153 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & 1154 SDHCI_CTRL_PRESET_VAL_ENABLE) { 1155 u16 pre_val; 1156 1157 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1158 pre_val = sdhci_get_preset_value(host); 1159 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1160 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1161 if (host->clk_mul && 1162 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1163 clk = SDHCI_PROG_CLOCK_MODE; 1164 real_div = div + 1; 1165 clk_mul = host->clk_mul; 1166 } else { 1167 real_div = max_t(int, 1, div << 1); 1168 } 1169 goto clock_set; 1170 } 1171 1172 /* 1173 * Check if the Host Controller supports Programmable Clock 1174 * Mode. 1175 */ 1176 if (host->clk_mul) { 1177 for (div = 1; div <= 1024; div++) { 1178 if ((host->max_clk * host->clk_mul / div) 1179 <= clock) 1180 break; 1181 } 1182 /* 1183 * Set Programmable Clock Mode in the Clock 1184 * Control register. 1185 */ 1186 clk = SDHCI_PROG_CLOCK_MODE; 1187 real_div = div; 1188 clk_mul = host->clk_mul; 1189 div--; 1190 } else { 1191 /* Version 3.00 divisors must be a multiple of 2. */ 1192 if (host->max_clk <= clock) 1193 div = 1; 1194 else { 1195 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1196 div += 2) { 1197 if ((host->max_clk / div) <= clock) 1198 break; 1199 } 1200 } 1201 real_div = div; 1202 div >>= 1; 1203 } 1204 } else { 1205 /* Version 2.00 divisors must be a power of 2. */ 1206 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1207 if ((host->max_clk / div) <= clock) 1208 break; 1209 } 1210 real_div = div; 1211 div >>= 1; 1212 } 1213 1214 clock_set: 1215 if (real_div) 1216 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1217 1218 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1219 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1220 << SDHCI_DIVIDER_HI_SHIFT; 1221 clk |= SDHCI_CLOCK_INT_EN; 1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1223 1224 /* Wait max 20 ms */ 1225 timeout = 20; 1226 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1227 & SDHCI_CLOCK_INT_STABLE)) { 1228 if (timeout == 0) { 1229 pr_err("%s: Internal clock never " 1230 "stabilised.\n", mmc_hostname(host->mmc)); 1231 sdhci_dumpregs(host); 1232 return; 1233 } 1234 timeout--; 1235 mdelay(1); 1236 } 1237 1238 clk |= SDHCI_CLOCK_CARD_EN; 1239 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1240 1241 out: 1242 host->clock = clock; 1243 } 1244 1245 static inline void sdhci_update_clock(struct sdhci_host *host) 1246 { 1247 unsigned int clock; 1248 1249 clock = host->clock; 1250 host->clock = 0; 1251 sdhci_set_clock(host, clock); 1252 } 1253 1254 static int sdhci_set_power(struct sdhci_host *host, unsigned short power) 1255 { 1256 u8 pwr = 0; 1257 1258 if (power != (unsigned short)-1) { 1259 switch (1 << power) { 1260 case MMC_VDD_165_195: 1261 pwr = SDHCI_POWER_180; 1262 break; 1263 case MMC_VDD_29_30: 1264 case MMC_VDD_30_31: 1265 pwr = SDHCI_POWER_300; 1266 break; 1267 case MMC_VDD_32_33: 1268 case MMC_VDD_33_34: 1269 pwr = SDHCI_POWER_330; 1270 break; 1271 default: 1272 BUG(); 1273 } 1274 } 1275 1276 if (host->pwr == pwr) 1277 return -1; 1278 1279 host->pwr = pwr; 1280 1281 if (pwr == 0) { 1282 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1283 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1284 sdhci_runtime_pm_bus_off(host); 1285 return 0; 1286 } 1287 1288 /* 1289 * Spec says that we should clear the power reg before setting 1290 * a new value. Some controllers don't seem to like this though. 1291 */ 1292 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1293 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1294 1295 /* 1296 * At least the Marvell CaFe chip gets confused if we set the voltage 1297 * and set turn on power at the same time, so set the voltage first. 1298 */ 1299 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1300 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1301 1302 pwr |= SDHCI_POWER_ON; 1303 1304 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1305 1306 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1307 sdhci_runtime_pm_bus_on(host); 1308 1309 /* 1310 * Some controllers need an extra 10ms delay of 10ms before they 1311 * can apply clock after applying power 1312 */ 1313 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1314 mdelay(10); 1315 1316 return power; 1317 } 1318 1319 /*****************************************************************************\ 1320 * * 1321 * MMC callbacks * 1322 * * 1323 \*****************************************************************************/ 1324 1325 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1326 { 1327 struct sdhci_host *host; 1328 int present; 1329 unsigned long flags; 1330 u32 tuning_opcode; 1331 1332 host = mmc_priv(mmc); 1333 1334 sdhci_runtime_pm_get(host); 1335 1336 spin_lock_irqsave(&host->lock, flags); 1337 1338 WARN_ON(host->mrq != NULL); 1339 1340 #ifndef SDHCI_USE_LEDS_CLASS 1341 sdhci_activate_led(host); 1342 #endif 1343 1344 /* 1345 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1346 * requests if Auto-CMD12 is enabled. 1347 */ 1348 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1349 if (mrq->stop) { 1350 mrq->data->stop = NULL; 1351 mrq->stop = NULL; 1352 } 1353 } 1354 1355 host->mrq = mrq; 1356 1357 /* 1358 * Firstly check card presence from cd-gpio. The return could 1359 * be one of the following possibilities: 1360 * negative: cd-gpio is not available 1361 * zero: cd-gpio is used, and card is removed 1362 * one: cd-gpio is used, and card is present 1363 */ 1364 present = mmc_gpio_get_cd(host->mmc); 1365 if (present < 0) { 1366 /* If polling, assume that the card is always present. */ 1367 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1368 present = 1; 1369 else 1370 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1371 SDHCI_CARD_PRESENT; 1372 } 1373 1374 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1375 host->mrq->cmd->error = -ENOMEDIUM; 1376 tasklet_schedule(&host->finish_tasklet); 1377 } else { 1378 u32 present_state; 1379 1380 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1381 /* 1382 * Check if the re-tuning timer has already expired and there 1383 * is no on-going data transfer. If so, we need to execute 1384 * tuning procedure before sending command. 1385 */ 1386 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1387 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1388 if (mmc->card) { 1389 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1390 tuning_opcode = 1391 mmc->card->type == MMC_TYPE_MMC ? 1392 MMC_SEND_TUNING_BLOCK_HS200 : 1393 MMC_SEND_TUNING_BLOCK; 1394 spin_unlock_irqrestore(&host->lock, flags); 1395 sdhci_execute_tuning(mmc, tuning_opcode); 1396 spin_lock_irqsave(&host->lock, flags); 1397 1398 /* Restore original mmc_request structure */ 1399 host->mrq = mrq; 1400 } 1401 } 1402 1403 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1404 sdhci_send_command(host, mrq->sbc); 1405 else 1406 sdhci_send_command(host, mrq->cmd); 1407 } 1408 1409 mmiowb(); 1410 spin_unlock_irqrestore(&host->lock, flags); 1411 } 1412 1413 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1414 { 1415 unsigned long flags; 1416 int vdd_bit = -1; 1417 u8 ctrl; 1418 1419 spin_lock_irqsave(&host->lock, flags); 1420 1421 if (host->flags & SDHCI_DEVICE_DEAD) { 1422 spin_unlock_irqrestore(&host->lock, flags); 1423 if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1424 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1425 return; 1426 } 1427 1428 /* 1429 * Reset the chip on each power off. 1430 * Should clear out any weird states. 1431 */ 1432 if (ios->power_mode == MMC_POWER_OFF) { 1433 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1434 sdhci_reinit(host); 1435 } 1436 1437 if (host->version >= SDHCI_SPEC_300 && 1438 (ios->power_mode == MMC_POWER_UP) && 1439 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1440 sdhci_enable_preset_value(host, false); 1441 1442 sdhci_set_clock(host, ios->clock); 1443 1444 if (ios->power_mode == MMC_POWER_OFF) 1445 vdd_bit = sdhci_set_power(host, -1); 1446 else 1447 vdd_bit = sdhci_set_power(host, ios->vdd); 1448 1449 if (host->vmmc && vdd_bit != -1) { 1450 spin_unlock_irqrestore(&host->lock, flags); 1451 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); 1452 spin_lock_irqsave(&host->lock, flags); 1453 } 1454 1455 if (host->ops->platform_send_init_74_clocks) 1456 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1457 1458 /* 1459 * If your platform has 8-bit width support but is not a v3 controller, 1460 * or if it requires special setup code, you should implement that in 1461 * platform_bus_width(). 1462 */ 1463 if (host->ops->platform_bus_width) { 1464 host->ops->platform_bus_width(host, ios->bus_width); 1465 } else { 1466 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1467 if (ios->bus_width == MMC_BUS_WIDTH_8) { 1468 ctrl &= ~SDHCI_CTRL_4BITBUS; 1469 if (host->version >= SDHCI_SPEC_300) 1470 ctrl |= SDHCI_CTRL_8BITBUS; 1471 } else { 1472 if (host->version >= SDHCI_SPEC_300) 1473 ctrl &= ~SDHCI_CTRL_8BITBUS; 1474 if (ios->bus_width == MMC_BUS_WIDTH_4) 1475 ctrl |= SDHCI_CTRL_4BITBUS; 1476 else 1477 ctrl &= ~SDHCI_CTRL_4BITBUS; 1478 } 1479 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1480 } 1481 1482 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1483 1484 if ((ios->timing == MMC_TIMING_SD_HS || 1485 ios->timing == MMC_TIMING_MMC_HS) 1486 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1487 ctrl |= SDHCI_CTRL_HISPD; 1488 else 1489 ctrl &= ~SDHCI_CTRL_HISPD; 1490 1491 if (host->version >= SDHCI_SPEC_300) { 1492 u16 clk, ctrl_2; 1493 1494 /* In case of UHS-I modes, set High Speed Enable */ 1495 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1496 (ios->timing == MMC_TIMING_UHS_SDR50) || 1497 (ios->timing == MMC_TIMING_UHS_SDR104) || 1498 (ios->timing == MMC_TIMING_UHS_DDR50) || 1499 (ios->timing == MMC_TIMING_UHS_SDR25)) 1500 ctrl |= SDHCI_CTRL_HISPD; 1501 1502 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1503 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1504 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1505 /* 1506 * We only need to set Driver Strength if the 1507 * preset value enable is not set. 1508 */ 1509 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1510 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1512 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1513 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1514 1515 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1516 } else { 1517 /* 1518 * According to SDHC Spec v3.00, if the Preset Value 1519 * Enable in the Host Control 2 register is set, we 1520 * need to reset SD Clock Enable before changing High 1521 * Speed Enable to avoid generating clock gliches. 1522 */ 1523 1524 /* Reset SD Clock Enable */ 1525 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1526 clk &= ~SDHCI_CLOCK_CARD_EN; 1527 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1528 1529 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1530 1531 /* Re-enable SD Clock */ 1532 sdhci_update_clock(host); 1533 } 1534 1535 1536 /* Reset SD Clock Enable */ 1537 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1538 clk &= ~SDHCI_CLOCK_CARD_EN; 1539 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1540 1541 if (host->ops->set_uhs_signaling) 1542 host->ops->set_uhs_signaling(host, ios->timing); 1543 else { 1544 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1545 /* Select Bus Speed Mode for host */ 1546 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1547 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1548 (ios->timing == MMC_TIMING_UHS_SDR104)) 1549 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1550 else if (ios->timing == MMC_TIMING_UHS_SDR12) 1551 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1552 else if (ios->timing == MMC_TIMING_UHS_SDR25) 1553 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1554 else if (ios->timing == MMC_TIMING_UHS_SDR50) 1555 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1556 else if (ios->timing == MMC_TIMING_UHS_DDR50) 1557 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1558 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1559 } 1560 1561 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1562 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1563 (ios->timing == MMC_TIMING_UHS_SDR25) || 1564 (ios->timing == MMC_TIMING_UHS_SDR50) || 1565 (ios->timing == MMC_TIMING_UHS_SDR104) || 1566 (ios->timing == MMC_TIMING_UHS_DDR50))) { 1567 u16 preset; 1568 1569 sdhci_enable_preset_value(host, true); 1570 preset = sdhci_get_preset_value(host); 1571 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1572 >> SDHCI_PRESET_DRV_SHIFT; 1573 } 1574 1575 /* Re-enable SD Clock */ 1576 sdhci_update_clock(host); 1577 } else 1578 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1579 1580 /* 1581 * Some (ENE) controllers go apeshit on some ios operation, 1582 * signalling timeout and CRC errors even on CMD0. Resetting 1583 * it on each ios seems to solve the problem. 1584 */ 1585 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1586 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1587 1588 mmiowb(); 1589 spin_unlock_irqrestore(&host->lock, flags); 1590 } 1591 1592 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1593 { 1594 struct sdhci_host *host = mmc_priv(mmc); 1595 1596 sdhci_runtime_pm_get(host); 1597 sdhci_do_set_ios(host, ios); 1598 sdhci_runtime_pm_put(host); 1599 } 1600 1601 static int sdhci_do_get_cd(struct sdhci_host *host) 1602 { 1603 int gpio_cd = mmc_gpio_get_cd(host->mmc); 1604 1605 if (host->flags & SDHCI_DEVICE_DEAD) 1606 return 0; 1607 1608 /* If polling/nonremovable, assume that the card is always present. */ 1609 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 1610 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 1611 return 1; 1612 1613 /* Try slot gpio detect */ 1614 if (!IS_ERR_VALUE(gpio_cd)) 1615 return !!gpio_cd; 1616 1617 /* Host native card detect */ 1618 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1619 } 1620 1621 static int sdhci_get_cd(struct mmc_host *mmc) 1622 { 1623 struct sdhci_host *host = mmc_priv(mmc); 1624 int ret; 1625 1626 sdhci_runtime_pm_get(host); 1627 ret = sdhci_do_get_cd(host); 1628 sdhci_runtime_pm_put(host); 1629 return ret; 1630 } 1631 1632 static int sdhci_check_ro(struct sdhci_host *host) 1633 { 1634 unsigned long flags; 1635 int is_readonly; 1636 1637 spin_lock_irqsave(&host->lock, flags); 1638 1639 if (host->flags & SDHCI_DEVICE_DEAD) 1640 is_readonly = 0; 1641 else if (host->ops->get_ro) 1642 is_readonly = host->ops->get_ro(host); 1643 else 1644 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1645 & SDHCI_WRITE_PROTECT); 1646 1647 spin_unlock_irqrestore(&host->lock, flags); 1648 1649 /* This quirk needs to be replaced by a callback-function later */ 1650 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1651 !is_readonly : is_readonly; 1652 } 1653 1654 #define SAMPLE_COUNT 5 1655 1656 static int sdhci_do_get_ro(struct sdhci_host *host) 1657 { 1658 int i, ro_count; 1659 1660 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1661 return sdhci_check_ro(host); 1662 1663 ro_count = 0; 1664 for (i = 0; i < SAMPLE_COUNT; i++) { 1665 if (sdhci_check_ro(host)) { 1666 if (++ro_count > SAMPLE_COUNT / 2) 1667 return 1; 1668 } 1669 msleep(30); 1670 } 1671 return 0; 1672 } 1673 1674 static void sdhci_hw_reset(struct mmc_host *mmc) 1675 { 1676 struct sdhci_host *host = mmc_priv(mmc); 1677 1678 if (host->ops && host->ops->hw_reset) 1679 host->ops->hw_reset(host); 1680 } 1681 1682 static int sdhci_get_ro(struct mmc_host *mmc) 1683 { 1684 struct sdhci_host *host = mmc_priv(mmc); 1685 int ret; 1686 1687 sdhci_runtime_pm_get(host); 1688 ret = sdhci_do_get_ro(host); 1689 sdhci_runtime_pm_put(host); 1690 return ret; 1691 } 1692 1693 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1694 { 1695 if (host->flags & SDHCI_DEVICE_DEAD) 1696 goto out; 1697 1698 if (enable) 1699 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1700 else 1701 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1702 1703 /* SDIO IRQ will be enabled as appropriate in runtime resume */ 1704 if (host->runtime_suspended) 1705 goto out; 1706 1707 if (enable) 1708 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 1709 else 1710 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 1711 out: 1712 mmiowb(); 1713 } 1714 1715 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1716 { 1717 struct sdhci_host *host = mmc_priv(mmc); 1718 unsigned long flags; 1719 1720 spin_lock_irqsave(&host->lock, flags); 1721 sdhci_enable_sdio_irq_nolock(host, enable); 1722 spin_unlock_irqrestore(&host->lock, flags); 1723 } 1724 1725 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1726 struct mmc_ios *ios) 1727 { 1728 u16 ctrl; 1729 int ret; 1730 1731 /* 1732 * Signal Voltage Switching is only applicable for Host Controllers 1733 * v3.00 and above. 1734 */ 1735 if (host->version < SDHCI_SPEC_300) 1736 return 0; 1737 1738 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1739 1740 switch (ios->signal_voltage) { 1741 case MMC_SIGNAL_VOLTAGE_330: 1742 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1743 ctrl &= ~SDHCI_CTRL_VDD_180; 1744 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1745 1746 if (host->vqmmc) { 1747 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 1748 if (ret) { 1749 pr_warning("%s: Switching to 3.3V signalling voltage " 1750 " failed\n", mmc_hostname(host->mmc)); 1751 return -EIO; 1752 } 1753 } 1754 /* Wait for 5ms */ 1755 usleep_range(5000, 5500); 1756 1757 /* 3.3V regulator output should be stable within 5 ms */ 1758 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1759 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1760 return 0; 1761 1762 pr_warning("%s: 3.3V regulator output did not became stable\n", 1763 mmc_hostname(host->mmc)); 1764 1765 return -EAGAIN; 1766 case MMC_SIGNAL_VOLTAGE_180: 1767 if (host->vqmmc) { 1768 ret = regulator_set_voltage(host->vqmmc, 1769 1700000, 1950000); 1770 if (ret) { 1771 pr_warning("%s: Switching to 1.8V signalling voltage " 1772 " failed\n", mmc_hostname(host->mmc)); 1773 return -EIO; 1774 } 1775 } 1776 1777 /* 1778 * Enable 1.8V Signal Enable in the Host Control2 1779 * register 1780 */ 1781 ctrl |= SDHCI_CTRL_VDD_180; 1782 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1783 1784 /* Wait for 5ms */ 1785 usleep_range(5000, 5500); 1786 1787 /* 1.8V regulator output should be stable within 5 ms */ 1788 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1789 if (ctrl & SDHCI_CTRL_VDD_180) 1790 return 0; 1791 1792 pr_warning("%s: 1.8V regulator output did not became stable\n", 1793 mmc_hostname(host->mmc)); 1794 1795 return -EAGAIN; 1796 case MMC_SIGNAL_VOLTAGE_120: 1797 if (host->vqmmc) { 1798 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); 1799 if (ret) { 1800 pr_warning("%s: Switching to 1.2V signalling voltage " 1801 " failed\n", mmc_hostname(host->mmc)); 1802 return -EIO; 1803 } 1804 } 1805 return 0; 1806 default: 1807 /* No signal voltage switch required */ 1808 return 0; 1809 } 1810 } 1811 1812 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1813 struct mmc_ios *ios) 1814 { 1815 struct sdhci_host *host = mmc_priv(mmc); 1816 int err; 1817 1818 if (host->version < SDHCI_SPEC_300) 1819 return 0; 1820 sdhci_runtime_pm_get(host); 1821 err = sdhci_do_start_signal_voltage_switch(host, ios); 1822 sdhci_runtime_pm_put(host); 1823 return err; 1824 } 1825 1826 static int sdhci_card_busy(struct mmc_host *mmc) 1827 { 1828 struct sdhci_host *host = mmc_priv(mmc); 1829 u32 present_state; 1830 1831 sdhci_runtime_pm_get(host); 1832 /* Check whether DAT[3:0] is 0000 */ 1833 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1834 sdhci_runtime_pm_put(host); 1835 1836 return !(present_state & SDHCI_DATA_LVL_MASK); 1837 } 1838 1839 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1840 { 1841 struct sdhci_host *host; 1842 u16 ctrl; 1843 u32 ier; 1844 int tuning_loop_counter = MAX_TUNING_LOOP; 1845 unsigned long timeout; 1846 int err = 0; 1847 bool requires_tuning_nonuhs = false; 1848 1849 host = mmc_priv(mmc); 1850 1851 sdhci_runtime_pm_get(host); 1852 disable_irq(host->irq); 1853 spin_lock(&host->lock); 1854 1855 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1856 1857 /* 1858 * The Host Controller needs tuning only in case of SDR104 mode 1859 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1860 * Capabilities register. 1861 * If the Host Controller supports the HS200 mode then the 1862 * tuning function has to be executed. 1863 */ 1864 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1865 (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1866 host->flags & SDHCI_SDR104_NEEDS_TUNING)) 1867 requires_tuning_nonuhs = true; 1868 1869 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1870 requires_tuning_nonuhs) 1871 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1872 else { 1873 spin_unlock(&host->lock); 1874 enable_irq(host->irq); 1875 sdhci_runtime_pm_put(host); 1876 return 0; 1877 } 1878 1879 if (host->ops->platform_execute_tuning) { 1880 spin_unlock(&host->lock); 1881 enable_irq(host->irq); 1882 err = host->ops->platform_execute_tuning(host, opcode); 1883 sdhci_runtime_pm_put(host); 1884 return err; 1885 } 1886 1887 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1888 1889 /* 1890 * As per the Host Controller spec v3.00, tuning command 1891 * generates Buffer Read Ready interrupt, so enable that. 1892 * 1893 * Note: The spec clearly says that when tuning sequence 1894 * is being performed, the controller does not generate 1895 * interrupts other than Buffer Read Ready interrupt. But 1896 * to make sure we don't hit a controller bug, we _only_ 1897 * enable Buffer Read Ready interrupt here. 1898 */ 1899 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1900 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1901 1902 /* 1903 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1904 * of loops reaches 40 times or a timeout of 150ms occurs. 1905 */ 1906 timeout = 150; 1907 do { 1908 struct mmc_command cmd = {0}; 1909 struct mmc_request mrq = {NULL}; 1910 1911 if (!tuning_loop_counter && !timeout) 1912 break; 1913 1914 cmd.opcode = opcode; 1915 cmd.arg = 0; 1916 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1917 cmd.retries = 0; 1918 cmd.data = NULL; 1919 cmd.error = 0; 1920 1921 mrq.cmd = &cmd; 1922 host->mrq = &mrq; 1923 1924 /* 1925 * In response to CMD19, the card sends 64 bytes of tuning 1926 * block to the Host Controller. So we set the block size 1927 * to 64 here. 1928 */ 1929 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1930 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1931 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1932 SDHCI_BLOCK_SIZE); 1933 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1934 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1935 SDHCI_BLOCK_SIZE); 1936 } else { 1937 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1938 SDHCI_BLOCK_SIZE); 1939 } 1940 1941 /* 1942 * The tuning block is sent by the card to the host controller. 1943 * So we set the TRNS_READ bit in the Transfer Mode register. 1944 * This also takes care of setting DMA Enable and Multi Block 1945 * Select in the same register to 0. 1946 */ 1947 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1948 1949 sdhci_send_command(host, &cmd); 1950 1951 host->cmd = NULL; 1952 host->mrq = NULL; 1953 1954 spin_unlock(&host->lock); 1955 enable_irq(host->irq); 1956 1957 /* Wait for Buffer Read Ready interrupt */ 1958 wait_event_interruptible_timeout(host->buf_ready_int, 1959 (host->tuning_done == 1), 1960 msecs_to_jiffies(50)); 1961 disable_irq(host->irq); 1962 spin_lock(&host->lock); 1963 1964 if (!host->tuning_done) { 1965 pr_info(DRIVER_NAME ": Timeout waiting for " 1966 "Buffer Read Ready interrupt during tuning " 1967 "procedure, falling back to fixed sampling " 1968 "clock\n"); 1969 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1970 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1971 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1972 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1973 1974 err = -EIO; 1975 goto out; 1976 } 1977 1978 host->tuning_done = 0; 1979 1980 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1981 tuning_loop_counter--; 1982 timeout--; 1983 mdelay(1); 1984 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1985 1986 /* 1987 * The Host Driver has exhausted the maximum number of loops allowed, 1988 * so use fixed sampling frequency. 1989 */ 1990 if (!tuning_loop_counter || !timeout) { 1991 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1992 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1993 err = -EIO; 1994 } else { 1995 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1996 pr_info(DRIVER_NAME ": Tuning procedure" 1997 " failed, falling back to fixed sampling" 1998 " clock\n"); 1999 err = -EIO; 2000 } 2001 } 2002 2003 out: 2004 /* 2005 * If this is the very first time we are here, we start the retuning 2006 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 2007 * flag won't be set, we check this condition before actually starting 2008 * the timer. 2009 */ 2010 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 2011 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 2012 host->flags |= SDHCI_USING_RETUNING_TIMER; 2013 mod_timer(&host->tuning_timer, jiffies + 2014 host->tuning_count * HZ); 2015 /* Tuning mode 1 limits the maximum data length to 4MB */ 2016 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 2017 } else { 2018 host->flags &= ~SDHCI_NEEDS_RETUNING; 2019 /* Reload the new initial value for timer */ 2020 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 2021 mod_timer(&host->tuning_timer, jiffies + 2022 host->tuning_count * HZ); 2023 } 2024 2025 /* 2026 * In case tuning fails, host controllers which support re-tuning can 2027 * try tuning again at a later time, when the re-tuning timer expires. 2028 * So for these controllers, we return 0. Since there might be other 2029 * controllers who do not have this capability, we return error for 2030 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2031 * a retuning timer to do the retuning for the card. 2032 */ 2033 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2034 err = 0; 2035 2036 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 2037 spin_unlock(&host->lock); 2038 enable_irq(host->irq); 2039 sdhci_runtime_pm_put(host); 2040 2041 return err; 2042 } 2043 2044 2045 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2046 { 2047 u16 ctrl; 2048 2049 /* Host Controller v3.00 defines preset value registers */ 2050 if (host->version < SDHCI_SPEC_300) 2051 return; 2052 2053 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2054 2055 /* 2056 * We only enable or disable Preset Value if they are not already 2057 * enabled or disabled respectively. Otherwise, we bail out. 2058 */ 2059 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 2060 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2061 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2062 host->flags |= SDHCI_PV_ENABLED; 2063 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 2064 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2065 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2066 host->flags &= ~SDHCI_PV_ENABLED; 2067 } 2068 } 2069 2070 static void sdhci_card_event(struct mmc_host *mmc) 2071 { 2072 struct sdhci_host *host = mmc_priv(mmc); 2073 unsigned long flags; 2074 2075 /* First check if client has provided their own card event */ 2076 if (host->ops->card_event) 2077 host->ops->card_event(host); 2078 2079 spin_lock_irqsave(&host->lock, flags); 2080 2081 /* Check host->mrq first in case we are runtime suspended */ 2082 if (host->mrq && !sdhci_do_get_cd(host)) { 2083 pr_err("%s: Card removed during transfer!\n", 2084 mmc_hostname(host->mmc)); 2085 pr_err("%s: Resetting controller.\n", 2086 mmc_hostname(host->mmc)); 2087 2088 sdhci_reset(host, SDHCI_RESET_CMD); 2089 sdhci_reset(host, SDHCI_RESET_DATA); 2090 2091 host->mrq->cmd->error = -ENOMEDIUM; 2092 tasklet_schedule(&host->finish_tasklet); 2093 } 2094 2095 spin_unlock_irqrestore(&host->lock, flags); 2096 } 2097 2098 static const struct mmc_host_ops sdhci_ops = { 2099 .request = sdhci_request, 2100 .set_ios = sdhci_set_ios, 2101 .get_cd = sdhci_get_cd, 2102 .get_ro = sdhci_get_ro, 2103 .hw_reset = sdhci_hw_reset, 2104 .enable_sdio_irq = sdhci_enable_sdio_irq, 2105 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2106 .execute_tuning = sdhci_execute_tuning, 2107 .card_event = sdhci_card_event, 2108 .card_busy = sdhci_card_busy, 2109 }; 2110 2111 /*****************************************************************************\ 2112 * * 2113 * Tasklets * 2114 * * 2115 \*****************************************************************************/ 2116 2117 static void sdhci_tasklet_card(unsigned long param) 2118 { 2119 struct sdhci_host *host = (struct sdhci_host*)param; 2120 2121 sdhci_card_event(host->mmc); 2122 2123 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2124 } 2125 2126 static void sdhci_tasklet_finish(unsigned long param) 2127 { 2128 struct sdhci_host *host; 2129 unsigned long flags; 2130 struct mmc_request *mrq; 2131 2132 host = (struct sdhci_host*)param; 2133 2134 spin_lock_irqsave(&host->lock, flags); 2135 2136 /* 2137 * If this tasklet gets rescheduled while running, it will 2138 * be run again afterwards but without any active request. 2139 */ 2140 if (!host->mrq) { 2141 spin_unlock_irqrestore(&host->lock, flags); 2142 return; 2143 } 2144 2145 del_timer(&host->timer); 2146 2147 mrq = host->mrq; 2148 2149 /* 2150 * The controller needs a reset of internal state machines 2151 * upon error conditions. 2152 */ 2153 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2154 ((mrq->cmd && mrq->cmd->error) || 2155 (mrq->data && (mrq->data->error || 2156 (mrq->data->stop && mrq->data->stop->error))) || 2157 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2158 2159 /* Some controllers need this kick or reset won't work here */ 2160 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2161 /* This is to force an update */ 2162 sdhci_update_clock(host); 2163 2164 /* Spec says we should do both at the same time, but Ricoh 2165 controllers do not like that. */ 2166 sdhci_reset(host, SDHCI_RESET_CMD); 2167 sdhci_reset(host, SDHCI_RESET_DATA); 2168 } 2169 2170 host->mrq = NULL; 2171 host->cmd = NULL; 2172 host->data = NULL; 2173 2174 #ifndef SDHCI_USE_LEDS_CLASS 2175 sdhci_deactivate_led(host); 2176 #endif 2177 2178 mmiowb(); 2179 spin_unlock_irqrestore(&host->lock, flags); 2180 2181 mmc_request_done(host->mmc, mrq); 2182 sdhci_runtime_pm_put(host); 2183 } 2184 2185 static void sdhci_timeout_timer(unsigned long data) 2186 { 2187 struct sdhci_host *host; 2188 unsigned long flags; 2189 2190 host = (struct sdhci_host*)data; 2191 2192 spin_lock_irqsave(&host->lock, flags); 2193 2194 if (host->mrq) { 2195 pr_err("%s: Timeout waiting for hardware " 2196 "interrupt.\n", mmc_hostname(host->mmc)); 2197 sdhci_dumpregs(host); 2198 2199 if (host->data) { 2200 host->data->error = -ETIMEDOUT; 2201 sdhci_finish_data(host); 2202 } else { 2203 if (host->cmd) 2204 host->cmd->error = -ETIMEDOUT; 2205 else 2206 host->mrq->cmd->error = -ETIMEDOUT; 2207 2208 tasklet_schedule(&host->finish_tasklet); 2209 } 2210 } 2211 2212 mmiowb(); 2213 spin_unlock_irqrestore(&host->lock, flags); 2214 } 2215 2216 static void sdhci_tuning_timer(unsigned long data) 2217 { 2218 struct sdhci_host *host; 2219 unsigned long flags; 2220 2221 host = (struct sdhci_host *)data; 2222 2223 spin_lock_irqsave(&host->lock, flags); 2224 2225 host->flags |= SDHCI_NEEDS_RETUNING; 2226 2227 spin_unlock_irqrestore(&host->lock, flags); 2228 } 2229 2230 /*****************************************************************************\ 2231 * * 2232 * Interrupt handling * 2233 * * 2234 \*****************************************************************************/ 2235 2236 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2237 { 2238 BUG_ON(intmask == 0); 2239 2240 if (!host->cmd) { 2241 pr_err("%s: Got command interrupt 0x%08x even " 2242 "though no command operation was in progress.\n", 2243 mmc_hostname(host->mmc), (unsigned)intmask); 2244 sdhci_dumpregs(host); 2245 return; 2246 } 2247 2248 if (intmask & SDHCI_INT_TIMEOUT) 2249 host->cmd->error = -ETIMEDOUT; 2250 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2251 SDHCI_INT_INDEX)) 2252 host->cmd->error = -EILSEQ; 2253 2254 if (host->cmd->error) { 2255 tasklet_schedule(&host->finish_tasklet); 2256 return; 2257 } 2258 2259 /* 2260 * The host can send and interrupt when the busy state has 2261 * ended, allowing us to wait without wasting CPU cycles. 2262 * Unfortunately this is overloaded on the "data complete" 2263 * interrupt, so we need to take some care when handling 2264 * it. 2265 * 2266 * Note: The 1.0 specification is a bit ambiguous about this 2267 * feature so there might be some problems with older 2268 * controllers. 2269 */ 2270 if (host->cmd->flags & MMC_RSP_BUSY) { 2271 if (host->cmd->data) 2272 DBG("Cannot wait for busy signal when also " 2273 "doing a data transfer"); 2274 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2275 return; 2276 2277 /* The controller does not support the end-of-busy IRQ, 2278 * fall through and take the SDHCI_INT_RESPONSE */ 2279 } 2280 2281 if (intmask & SDHCI_INT_RESPONSE) 2282 sdhci_finish_command(host); 2283 } 2284 2285 #ifdef CONFIG_MMC_DEBUG 2286 static void sdhci_show_adma_error(struct sdhci_host *host) 2287 { 2288 const char *name = mmc_hostname(host->mmc); 2289 u8 *desc = host->adma_desc; 2290 __le32 *dma; 2291 __le16 *len; 2292 u8 attr; 2293 2294 sdhci_dumpregs(host); 2295 2296 while (true) { 2297 dma = (__le32 *)(desc + 4); 2298 len = (__le16 *)(desc + 2); 2299 attr = *desc; 2300 2301 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2302 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2303 2304 desc += 8; 2305 2306 if (attr & 2) 2307 break; 2308 } 2309 } 2310 #else 2311 static void sdhci_show_adma_error(struct sdhci_host *host) { } 2312 #endif 2313 2314 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2315 { 2316 u32 command; 2317 BUG_ON(intmask == 0); 2318 2319 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2320 if (intmask & SDHCI_INT_DATA_AVAIL) { 2321 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2322 if (command == MMC_SEND_TUNING_BLOCK || 2323 command == MMC_SEND_TUNING_BLOCK_HS200) { 2324 host->tuning_done = 1; 2325 wake_up(&host->buf_ready_int); 2326 return; 2327 } 2328 } 2329 2330 if (!host->data) { 2331 /* 2332 * The "data complete" interrupt is also used to 2333 * indicate that a busy state has ended. See comment 2334 * above in sdhci_cmd_irq(). 2335 */ 2336 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2337 if (intmask & SDHCI_INT_DATA_END) { 2338 sdhci_finish_command(host); 2339 return; 2340 } 2341 } 2342 2343 pr_err("%s: Got data interrupt 0x%08x even " 2344 "though no data operation was in progress.\n", 2345 mmc_hostname(host->mmc), (unsigned)intmask); 2346 sdhci_dumpregs(host); 2347 2348 return; 2349 } 2350 2351 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2352 host->data->error = -ETIMEDOUT; 2353 else if (intmask & SDHCI_INT_DATA_END_BIT) 2354 host->data->error = -EILSEQ; 2355 else if ((intmask & SDHCI_INT_DATA_CRC) && 2356 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2357 != MMC_BUS_TEST_R) 2358 host->data->error = -EILSEQ; 2359 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2360 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2361 sdhci_show_adma_error(host); 2362 host->data->error = -EIO; 2363 if (host->ops->adma_workaround) 2364 host->ops->adma_workaround(host, intmask); 2365 } 2366 2367 if (host->data->error) 2368 sdhci_finish_data(host); 2369 else { 2370 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2371 sdhci_transfer_pio(host); 2372 2373 /* 2374 * We currently don't do anything fancy with DMA 2375 * boundaries, but as we can't disable the feature 2376 * we need to at least restart the transfer. 2377 * 2378 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2379 * should return a valid address to continue from, but as 2380 * some controllers are faulty, don't trust them. 2381 */ 2382 if (intmask & SDHCI_INT_DMA_END) { 2383 u32 dmastart, dmanow; 2384 dmastart = sg_dma_address(host->data->sg); 2385 dmanow = dmastart + host->data->bytes_xfered; 2386 /* 2387 * Force update to the next DMA block boundary. 2388 */ 2389 dmanow = (dmanow & 2390 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2391 SDHCI_DEFAULT_BOUNDARY_SIZE; 2392 host->data->bytes_xfered = dmanow - dmastart; 2393 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2394 " next 0x%08x\n", 2395 mmc_hostname(host->mmc), dmastart, 2396 host->data->bytes_xfered, dmanow); 2397 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2398 } 2399 2400 if (intmask & SDHCI_INT_DATA_END) { 2401 if (host->cmd) { 2402 /* 2403 * Data managed to finish before the 2404 * command completed. Make sure we do 2405 * things in the proper order. 2406 */ 2407 host->data_early = 1; 2408 } else { 2409 sdhci_finish_data(host); 2410 } 2411 } 2412 } 2413 } 2414 2415 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2416 { 2417 irqreturn_t result; 2418 struct sdhci_host *host = dev_id; 2419 u32 intmask, unexpected = 0; 2420 int cardint = 0, max_loops = 16; 2421 2422 spin_lock(&host->lock); 2423 2424 if (host->runtime_suspended) { 2425 spin_unlock(&host->lock); 2426 pr_warning("%s: got irq while runtime suspended\n", 2427 mmc_hostname(host->mmc)); 2428 return IRQ_HANDLED; 2429 } 2430 2431 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2432 2433 if (!intmask || intmask == 0xffffffff) { 2434 result = IRQ_NONE; 2435 goto out; 2436 } 2437 2438 again: 2439 DBG("*** %s got interrupt: 0x%08x\n", 2440 mmc_hostname(host->mmc), intmask); 2441 2442 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2443 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2444 SDHCI_CARD_PRESENT; 2445 2446 /* 2447 * There is a observation on i.mx esdhc. INSERT bit will be 2448 * immediately set again when it gets cleared, if a card is 2449 * inserted. We have to mask the irq to prevent interrupt 2450 * storm which will freeze the system. And the REMOVE gets 2451 * the same situation. 2452 * 2453 * More testing are needed here to ensure it works for other 2454 * platforms though. 2455 */ 2456 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : 2457 SDHCI_INT_CARD_REMOVE); 2458 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : 2459 SDHCI_INT_CARD_INSERT); 2460 2461 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2462 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2463 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2464 tasklet_schedule(&host->card_tasklet); 2465 } 2466 2467 if (intmask & SDHCI_INT_CMD_MASK) { 2468 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, 2469 SDHCI_INT_STATUS); 2470 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2471 } 2472 2473 if (intmask & SDHCI_INT_DATA_MASK) { 2474 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, 2475 SDHCI_INT_STATUS); 2476 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2477 } 2478 2479 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 2480 2481 intmask &= ~SDHCI_INT_ERROR; 2482 2483 if (intmask & SDHCI_INT_BUS_POWER) { 2484 pr_err("%s: Card is consuming too much power!\n", 2485 mmc_hostname(host->mmc)); 2486 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); 2487 } 2488 2489 intmask &= ~SDHCI_INT_BUS_POWER; 2490 2491 if (intmask & SDHCI_INT_CARD_INT) 2492 cardint = 1; 2493 2494 intmask &= ~SDHCI_INT_CARD_INT; 2495 2496 if (intmask) { 2497 unexpected |= intmask; 2498 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2499 } 2500 2501 result = IRQ_HANDLED; 2502 2503 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2504 2505 /* 2506 * If we know we'll call the driver to signal SDIO IRQ, disregard 2507 * further indications of Card Interrupt in the status to avoid a 2508 * needless loop. 2509 */ 2510 if (cardint) 2511 intmask &= ~SDHCI_INT_CARD_INT; 2512 if (intmask && --max_loops) 2513 goto again; 2514 out: 2515 spin_unlock(&host->lock); 2516 2517 if (unexpected) { 2518 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2519 mmc_hostname(host->mmc), unexpected); 2520 sdhci_dumpregs(host); 2521 } 2522 /* 2523 * We have to delay this as it calls back into the driver. 2524 */ 2525 if (cardint) 2526 mmc_signal_sdio_irq(host->mmc); 2527 2528 return result; 2529 } 2530 2531 /*****************************************************************************\ 2532 * * 2533 * Suspend/resume * 2534 * * 2535 \*****************************************************************************/ 2536 2537 #ifdef CONFIG_PM 2538 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2539 { 2540 u8 val; 2541 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2542 | SDHCI_WAKE_ON_INT; 2543 2544 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2545 val |= mask ; 2546 /* Avoid fake wake up */ 2547 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2548 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2549 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2550 } 2551 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2552 2553 void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2554 { 2555 u8 val; 2556 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2557 | SDHCI_WAKE_ON_INT; 2558 2559 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2560 val &= ~mask; 2561 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2562 } 2563 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); 2564 2565 int sdhci_suspend_host(struct sdhci_host *host) 2566 { 2567 if (host->ops->platform_suspend) 2568 host->ops->platform_suspend(host); 2569 2570 sdhci_disable_card_detection(host); 2571 2572 /* Disable tuning since we are suspending */ 2573 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2574 del_timer_sync(&host->tuning_timer); 2575 host->flags &= ~SDHCI_NEEDS_RETUNING; 2576 } 2577 2578 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2579 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2580 free_irq(host->irq, host); 2581 } else { 2582 sdhci_enable_irq_wakeups(host); 2583 enable_irq_wake(host->irq); 2584 } 2585 return 0; 2586 } 2587 2588 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2589 2590 int sdhci_resume_host(struct sdhci_host *host) 2591 { 2592 int ret = 0; 2593 2594 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2595 if (host->ops->enable_dma) 2596 host->ops->enable_dma(host); 2597 } 2598 2599 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2600 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2601 mmc_hostname(host->mmc), host); 2602 if (ret) 2603 return ret; 2604 } else { 2605 sdhci_disable_irq_wakeups(host); 2606 disable_irq_wake(host->irq); 2607 } 2608 2609 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2610 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2611 /* Card keeps power but host controller does not */ 2612 sdhci_init(host, 0); 2613 host->pwr = 0; 2614 host->clock = 0; 2615 sdhci_do_set_ios(host, &host->mmc->ios); 2616 } else { 2617 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2618 mmiowb(); 2619 } 2620 2621 sdhci_enable_card_detection(host); 2622 2623 if (host->ops->platform_resume) 2624 host->ops->platform_resume(host); 2625 2626 /* Set the re-tuning expiration flag */ 2627 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2628 host->flags |= SDHCI_NEEDS_RETUNING; 2629 2630 return ret; 2631 } 2632 2633 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2634 #endif /* CONFIG_PM */ 2635 2636 #ifdef CONFIG_PM_RUNTIME 2637 2638 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2639 { 2640 return pm_runtime_get_sync(host->mmc->parent); 2641 } 2642 2643 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2644 { 2645 pm_runtime_mark_last_busy(host->mmc->parent); 2646 return pm_runtime_put_autosuspend(host->mmc->parent); 2647 } 2648 2649 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2650 { 2651 if (host->runtime_suspended || host->bus_on) 2652 return; 2653 host->bus_on = true; 2654 pm_runtime_get_noresume(host->mmc->parent); 2655 } 2656 2657 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2658 { 2659 if (host->runtime_suspended || !host->bus_on) 2660 return; 2661 host->bus_on = false; 2662 pm_runtime_put_noidle(host->mmc->parent); 2663 } 2664 2665 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2666 { 2667 unsigned long flags; 2668 int ret = 0; 2669 2670 /* Disable tuning since we are suspending */ 2671 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2672 del_timer_sync(&host->tuning_timer); 2673 host->flags &= ~SDHCI_NEEDS_RETUNING; 2674 } 2675 2676 spin_lock_irqsave(&host->lock, flags); 2677 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2678 spin_unlock_irqrestore(&host->lock, flags); 2679 2680 synchronize_irq(host->irq); 2681 2682 spin_lock_irqsave(&host->lock, flags); 2683 host->runtime_suspended = true; 2684 spin_unlock_irqrestore(&host->lock, flags); 2685 2686 return ret; 2687 } 2688 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2689 2690 int sdhci_runtime_resume_host(struct sdhci_host *host) 2691 { 2692 unsigned long flags; 2693 int ret = 0, host_flags = host->flags; 2694 2695 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2696 if (host->ops->enable_dma) 2697 host->ops->enable_dma(host); 2698 } 2699 2700 sdhci_init(host, 0); 2701 2702 /* Force clock and power re-program */ 2703 host->pwr = 0; 2704 host->clock = 0; 2705 sdhci_do_set_ios(host, &host->mmc->ios); 2706 2707 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2708 if ((host_flags & SDHCI_PV_ENABLED) && 2709 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2710 spin_lock_irqsave(&host->lock, flags); 2711 sdhci_enable_preset_value(host, true); 2712 spin_unlock_irqrestore(&host->lock, flags); 2713 } 2714 2715 /* Set the re-tuning expiration flag */ 2716 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2717 host->flags |= SDHCI_NEEDS_RETUNING; 2718 2719 spin_lock_irqsave(&host->lock, flags); 2720 2721 host->runtime_suspended = false; 2722 2723 /* Enable SDIO IRQ */ 2724 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) 2725 sdhci_enable_sdio_irq_nolock(host, true); 2726 2727 /* Enable Card Detection */ 2728 sdhci_enable_card_detection(host); 2729 2730 spin_unlock_irqrestore(&host->lock, flags); 2731 2732 return ret; 2733 } 2734 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2735 2736 #endif 2737 2738 /*****************************************************************************\ 2739 * * 2740 * Device allocation/registration * 2741 * * 2742 \*****************************************************************************/ 2743 2744 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2745 size_t priv_size) 2746 { 2747 struct mmc_host *mmc; 2748 struct sdhci_host *host; 2749 2750 WARN_ON(dev == NULL); 2751 2752 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2753 if (!mmc) 2754 return ERR_PTR(-ENOMEM); 2755 2756 host = mmc_priv(mmc); 2757 host->mmc = mmc; 2758 2759 return host; 2760 } 2761 2762 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2763 2764 int sdhci_add_host(struct sdhci_host *host) 2765 { 2766 struct mmc_host *mmc; 2767 u32 caps[2] = {0, 0}; 2768 u32 max_current_caps; 2769 unsigned int ocr_avail; 2770 int ret; 2771 2772 WARN_ON(host == NULL); 2773 if (host == NULL) 2774 return -EINVAL; 2775 2776 mmc = host->mmc; 2777 2778 if (debug_quirks) 2779 host->quirks = debug_quirks; 2780 if (debug_quirks2) 2781 host->quirks2 = debug_quirks2; 2782 2783 sdhci_reset(host, SDHCI_RESET_ALL); 2784 2785 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2786 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2787 >> SDHCI_SPEC_VER_SHIFT; 2788 if (host->version > SDHCI_SPEC_300) { 2789 pr_err("%s: Unknown controller version (%d). " 2790 "You may experience problems.\n", mmc_hostname(mmc), 2791 host->version); 2792 } 2793 2794 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2795 sdhci_readl(host, SDHCI_CAPABILITIES); 2796 2797 if (host->version >= SDHCI_SPEC_300) 2798 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2799 host->caps1 : 2800 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2801 2802 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2803 host->flags |= SDHCI_USE_SDMA; 2804 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2805 DBG("Controller doesn't have SDMA capability\n"); 2806 else 2807 host->flags |= SDHCI_USE_SDMA; 2808 2809 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2810 (host->flags & SDHCI_USE_SDMA)) { 2811 DBG("Disabling DMA as it is marked broken\n"); 2812 host->flags &= ~SDHCI_USE_SDMA; 2813 } 2814 2815 if ((host->version >= SDHCI_SPEC_200) && 2816 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2817 host->flags |= SDHCI_USE_ADMA; 2818 2819 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2820 (host->flags & SDHCI_USE_ADMA)) { 2821 DBG("Disabling ADMA as it is marked broken\n"); 2822 host->flags &= ~SDHCI_USE_ADMA; 2823 } 2824 2825 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2826 if (host->ops->enable_dma) { 2827 if (host->ops->enable_dma(host)) { 2828 pr_warning("%s: No suitable DMA " 2829 "available. Falling back to PIO.\n", 2830 mmc_hostname(mmc)); 2831 host->flags &= 2832 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2833 } 2834 } 2835 } 2836 2837 if (host->flags & SDHCI_USE_ADMA) { 2838 /* 2839 * We need to allocate descriptors for all sg entries 2840 * (128) and potentially one alignment transfer for 2841 * each of those entries. 2842 */ 2843 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 2844 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2845 if (!host->adma_desc || !host->align_buffer) { 2846 kfree(host->adma_desc); 2847 kfree(host->align_buffer); 2848 pr_warning("%s: Unable to allocate ADMA " 2849 "buffers. Falling back to standard DMA.\n", 2850 mmc_hostname(mmc)); 2851 host->flags &= ~SDHCI_USE_ADMA; 2852 } 2853 } 2854 2855 /* 2856 * If we use DMA, then it's up to the caller to set the DMA 2857 * mask, but PIO does not need the hw shim so we set a new 2858 * mask here in that case. 2859 */ 2860 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2861 host->dma_mask = DMA_BIT_MASK(64); 2862 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2863 } 2864 2865 if (host->version >= SDHCI_SPEC_300) 2866 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2867 >> SDHCI_CLOCK_BASE_SHIFT; 2868 else 2869 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2870 >> SDHCI_CLOCK_BASE_SHIFT; 2871 2872 host->max_clk *= 1000000; 2873 if (host->max_clk == 0 || host->quirks & 2874 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2875 if (!host->ops->get_max_clock) { 2876 pr_err("%s: Hardware doesn't specify base clock " 2877 "frequency.\n", mmc_hostname(mmc)); 2878 return -ENODEV; 2879 } 2880 host->max_clk = host->ops->get_max_clock(host); 2881 } 2882 2883 /* 2884 * In case of Host Controller v3.00, find out whether clock 2885 * multiplier is supported. 2886 */ 2887 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2888 SDHCI_CLOCK_MUL_SHIFT; 2889 2890 /* 2891 * In case the value in Clock Multiplier is 0, then programmable 2892 * clock mode is not supported, otherwise the actual clock 2893 * multiplier is one more than the value of Clock Multiplier 2894 * in the Capabilities Register. 2895 */ 2896 if (host->clk_mul) 2897 host->clk_mul += 1; 2898 2899 /* 2900 * Set host parameters. 2901 */ 2902 mmc->ops = &sdhci_ops; 2903 mmc->f_max = host->max_clk; 2904 if (host->ops->get_min_clock) 2905 mmc->f_min = host->ops->get_min_clock(host); 2906 else if (host->version >= SDHCI_SPEC_300) { 2907 if (host->clk_mul) { 2908 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2909 mmc->f_max = host->max_clk * host->clk_mul; 2910 } else 2911 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2912 } else 2913 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2914 2915 host->timeout_clk = 2916 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2917 if (host->timeout_clk == 0) { 2918 if (host->ops->get_timeout_clock) { 2919 host->timeout_clk = host->ops->get_timeout_clock(host); 2920 } else if (!(host->quirks & 2921 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2922 pr_err("%s: Hardware doesn't specify timeout clock " 2923 "frequency.\n", mmc_hostname(mmc)); 2924 return -ENODEV; 2925 } 2926 } 2927 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2928 host->timeout_clk *= 1000; 2929 2930 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 2931 host->timeout_clk = mmc->f_max / 1000; 2932 2933 mmc->max_discard_to = (1 << 27) / host->timeout_clk; 2934 2935 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2936 2937 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2938 host->flags |= SDHCI_AUTO_CMD12; 2939 2940 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2941 if ((host->version >= SDHCI_SPEC_300) && 2942 ((host->flags & SDHCI_USE_ADMA) || 2943 !(host->flags & SDHCI_USE_SDMA))) { 2944 host->flags |= SDHCI_AUTO_CMD23; 2945 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2946 } else { 2947 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2948 } 2949 2950 /* 2951 * A controller may support 8-bit width, but the board itself 2952 * might not have the pins brought out. Boards that support 2953 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2954 * their platform code before calling sdhci_add_host(), and we 2955 * won't assume 8-bit width for hosts without that CAP. 2956 */ 2957 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2958 mmc->caps |= MMC_CAP_4_BIT_DATA; 2959 2960 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 2961 mmc->caps &= ~MMC_CAP_CMD23; 2962 2963 if (caps[0] & SDHCI_CAN_DO_HISPD) 2964 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2965 2966 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2967 !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 2968 mmc->caps |= MMC_CAP_NEEDS_POLL; 2969 2970 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 2971 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc"); 2972 if (IS_ERR_OR_NULL(host->vqmmc)) { 2973 if (PTR_ERR(host->vqmmc) < 0) { 2974 pr_info("%s: no vqmmc regulator found\n", 2975 mmc_hostname(mmc)); 2976 host->vqmmc = NULL; 2977 } 2978 } else { 2979 ret = regulator_enable(host->vqmmc); 2980 if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2981 1950000)) 2982 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 2983 SDHCI_SUPPORT_SDR50 | 2984 SDHCI_SUPPORT_DDR50); 2985 if (ret) { 2986 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 2987 mmc_hostname(mmc), ret); 2988 host->vqmmc = NULL; 2989 } 2990 } 2991 2992 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 2993 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2994 SDHCI_SUPPORT_DDR50); 2995 2996 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 2997 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2998 SDHCI_SUPPORT_DDR50)) 2999 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3000 3001 /* SDR104 supports also implies SDR50 support */ 3002 if (caps[1] & SDHCI_SUPPORT_SDR104) { 3003 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3004 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3005 * field can be promoted to support HS200. 3006 */ 3007 mmc->caps2 |= MMC_CAP2_HS200; 3008 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3009 mmc->caps |= MMC_CAP_UHS_SDR50; 3010 3011 if (caps[1] & SDHCI_SUPPORT_DDR50) 3012 mmc->caps |= MMC_CAP_UHS_DDR50; 3013 3014 /* Does the host need tuning for SDR50? */ 3015 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3016 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3017 3018 /* Does the host need tuning for SDR104 / HS200? */ 3019 if (mmc->caps2 & MMC_CAP2_HS200) 3020 host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3021 3022 /* Driver Type(s) (A, C, D) supported by the host */ 3023 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3024 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3025 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3026 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3027 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3028 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3029 3030 /* Initial value for re-tuning timer count */ 3031 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3032 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3033 3034 /* 3035 * In case Re-tuning Timer is not disabled, the actual value of 3036 * re-tuning timer will be 2 ^ (n - 1). 3037 */ 3038 if (host->tuning_count) 3039 host->tuning_count = 1 << (host->tuning_count - 1); 3040 3041 /* Re-tuning mode supported by the Host Controller */ 3042 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3043 SDHCI_RETUNING_MODE_SHIFT; 3044 3045 ocr_avail = 0; 3046 3047 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc"); 3048 if (IS_ERR_OR_NULL(host->vmmc)) { 3049 if (PTR_ERR(host->vmmc) < 0) { 3050 pr_info("%s: no vmmc regulator found\n", 3051 mmc_hostname(mmc)); 3052 host->vmmc = NULL; 3053 } 3054 } 3055 3056 #ifdef CONFIG_REGULATOR 3057 /* 3058 * Voltage range check makes sense only if regulator reports 3059 * any voltage value. 3060 */ 3061 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { 3062 ret = regulator_is_supported_voltage(host->vmmc, 2700000, 3063 3600000); 3064 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 3065 caps[0] &= ~SDHCI_CAN_VDD_330; 3066 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 3067 caps[0] &= ~SDHCI_CAN_VDD_300; 3068 ret = regulator_is_supported_voltage(host->vmmc, 1700000, 3069 1950000); 3070 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 3071 caps[0] &= ~SDHCI_CAN_VDD_180; 3072 } 3073 #endif /* CONFIG_REGULATOR */ 3074 3075 /* 3076 * According to SD Host Controller spec v3.00, if the Host System 3077 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3078 * the value is meaningful only if Voltage Support in the Capabilities 3079 * register is set. The actual current value is 4 times the register 3080 * value. 3081 */ 3082 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3083 if (!max_current_caps && host->vmmc) { 3084 u32 curr = regulator_get_current_limit(host->vmmc); 3085 if (curr > 0) { 3086 3087 /* convert to SDHCI_MAX_CURRENT format */ 3088 curr = curr/1000; /* convert to mA */ 3089 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3090 3091 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3092 max_current_caps = 3093 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3094 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3095 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3096 } 3097 } 3098 3099 if (caps[0] & SDHCI_CAN_VDD_330) { 3100 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3101 3102 mmc->max_current_330 = ((max_current_caps & 3103 SDHCI_MAX_CURRENT_330_MASK) >> 3104 SDHCI_MAX_CURRENT_330_SHIFT) * 3105 SDHCI_MAX_CURRENT_MULTIPLIER; 3106 } 3107 if (caps[0] & SDHCI_CAN_VDD_300) { 3108 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3109 3110 mmc->max_current_300 = ((max_current_caps & 3111 SDHCI_MAX_CURRENT_300_MASK) >> 3112 SDHCI_MAX_CURRENT_300_SHIFT) * 3113 SDHCI_MAX_CURRENT_MULTIPLIER; 3114 } 3115 if (caps[0] & SDHCI_CAN_VDD_180) { 3116 ocr_avail |= MMC_VDD_165_195; 3117 3118 mmc->max_current_180 = ((max_current_caps & 3119 SDHCI_MAX_CURRENT_180_MASK) >> 3120 SDHCI_MAX_CURRENT_180_SHIFT) * 3121 SDHCI_MAX_CURRENT_MULTIPLIER; 3122 } 3123 3124 if (host->ocr_mask) 3125 ocr_avail = host->ocr_mask; 3126 3127 mmc->ocr_avail = ocr_avail; 3128 mmc->ocr_avail_sdio = ocr_avail; 3129 if (host->ocr_avail_sdio) 3130 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3131 mmc->ocr_avail_sd = ocr_avail; 3132 if (host->ocr_avail_sd) 3133 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3134 else /* normal SD controllers don't support 1.8V */ 3135 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3136 mmc->ocr_avail_mmc = ocr_avail; 3137 if (host->ocr_avail_mmc) 3138 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3139 3140 if (mmc->ocr_avail == 0) { 3141 pr_err("%s: Hardware doesn't report any " 3142 "support voltages.\n", mmc_hostname(mmc)); 3143 return -ENODEV; 3144 } 3145 3146 spin_lock_init(&host->lock); 3147 3148 /* 3149 * Maximum number of segments. Depends on if the hardware 3150 * can do scatter/gather or not. 3151 */ 3152 if (host->flags & SDHCI_USE_ADMA) 3153 mmc->max_segs = 128; 3154 else if (host->flags & SDHCI_USE_SDMA) 3155 mmc->max_segs = 1; 3156 else /* PIO */ 3157 mmc->max_segs = 128; 3158 3159 /* 3160 * Maximum number of sectors in one transfer. Limited by DMA boundary 3161 * size (512KiB). 3162 */ 3163 mmc->max_req_size = 524288; 3164 3165 /* 3166 * Maximum segment size. Could be one segment with the maximum number 3167 * of bytes. When doing hardware scatter/gather, each entry cannot 3168 * be larger than 64 KiB though. 3169 */ 3170 if (host->flags & SDHCI_USE_ADMA) { 3171 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3172 mmc->max_seg_size = 65535; 3173 else 3174 mmc->max_seg_size = 65536; 3175 } else { 3176 mmc->max_seg_size = mmc->max_req_size; 3177 } 3178 3179 /* 3180 * Maximum block size. This varies from controller to controller and 3181 * is specified in the capabilities register. 3182 */ 3183 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3184 mmc->max_blk_size = 2; 3185 } else { 3186 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3187 SDHCI_MAX_BLOCK_SHIFT; 3188 if (mmc->max_blk_size >= 3) { 3189 pr_warning("%s: Invalid maximum block size, " 3190 "assuming 512 bytes\n", mmc_hostname(mmc)); 3191 mmc->max_blk_size = 0; 3192 } 3193 } 3194 3195 mmc->max_blk_size = 512 << mmc->max_blk_size; 3196 3197 /* 3198 * Maximum block count. 3199 */ 3200 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3201 3202 /* 3203 * Init tasklets. 3204 */ 3205 tasklet_init(&host->card_tasklet, 3206 sdhci_tasklet_card, (unsigned long)host); 3207 tasklet_init(&host->finish_tasklet, 3208 sdhci_tasklet_finish, (unsigned long)host); 3209 3210 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3211 3212 if (host->version >= SDHCI_SPEC_300) { 3213 init_waitqueue_head(&host->buf_ready_int); 3214 3215 /* Initialize re-tuning timer */ 3216 init_timer(&host->tuning_timer); 3217 host->tuning_timer.data = (unsigned long)host; 3218 host->tuning_timer.function = sdhci_tuning_timer; 3219 } 3220 3221 sdhci_init(host, 0); 3222 3223 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 3224 mmc_hostname(mmc), host); 3225 if (ret) { 3226 pr_err("%s: Failed to request IRQ %d: %d\n", 3227 mmc_hostname(mmc), host->irq, ret); 3228 goto untasklet; 3229 } 3230 3231 #ifdef CONFIG_MMC_DEBUG 3232 sdhci_dumpregs(host); 3233 #endif 3234 3235 #ifdef SDHCI_USE_LEDS_CLASS 3236 snprintf(host->led_name, sizeof(host->led_name), 3237 "%s::", mmc_hostname(mmc)); 3238 host->led.name = host->led_name; 3239 host->led.brightness = LED_OFF; 3240 host->led.default_trigger = mmc_hostname(mmc); 3241 host->led.brightness_set = sdhci_led_control; 3242 3243 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3244 if (ret) { 3245 pr_err("%s: Failed to register LED device: %d\n", 3246 mmc_hostname(mmc), ret); 3247 goto reset; 3248 } 3249 #endif 3250 3251 mmiowb(); 3252 3253 mmc_add_host(mmc); 3254 3255 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3256 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3257 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3258 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3259 3260 sdhci_enable_card_detection(host); 3261 3262 return 0; 3263 3264 #ifdef SDHCI_USE_LEDS_CLASS 3265 reset: 3266 sdhci_reset(host, SDHCI_RESET_ALL); 3267 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 3268 free_irq(host->irq, host); 3269 #endif 3270 untasklet: 3271 tasklet_kill(&host->card_tasklet); 3272 tasklet_kill(&host->finish_tasklet); 3273 3274 return ret; 3275 } 3276 3277 EXPORT_SYMBOL_GPL(sdhci_add_host); 3278 3279 void sdhci_remove_host(struct sdhci_host *host, int dead) 3280 { 3281 unsigned long flags; 3282 3283 if (dead) { 3284 spin_lock_irqsave(&host->lock, flags); 3285 3286 host->flags |= SDHCI_DEVICE_DEAD; 3287 3288 if (host->mrq) { 3289 pr_err("%s: Controller removed during " 3290 " transfer!\n", mmc_hostname(host->mmc)); 3291 3292 host->mrq->cmd->error = -ENOMEDIUM; 3293 tasklet_schedule(&host->finish_tasklet); 3294 } 3295 3296 spin_unlock_irqrestore(&host->lock, flags); 3297 } 3298 3299 sdhci_disable_card_detection(host); 3300 3301 mmc_remove_host(host->mmc); 3302 3303 #ifdef SDHCI_USE_LEDS_CLASS 3304 led_classdev_unregister(&host->led); 3305 #endif 3306 3307 if (!dead) 3308 sdhci_reset(host, SDHCI_RESET_ALL); 3309 3310 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 3311 free_irq(host->irq, host); 3312 3313 del_timer_sync(&host->timer); 3314 3315 tasklet_kill(&host->card_tasklet); 3316 tasklet_kill(&host->finish_tasklet); 3317 3318 if (host->vmmc) { 3319 regulator_disable(host->vmmc); 3320 regulator_put(host->vmmc); 3321 } 3322 3323 if (host->vqmmc) { 3324 regulator_disable(host->vqmmc); 3325 regulator_put(host->vqmmc); 3326 } 3327 3328 kfree(host->adma_desc); 3329 kfree(host->align_buffer); 3330 3331 host->adma_desc = NULL; 3332 host->align_buffer = NULL; 3333 } 3334 3335 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3336 3337 void sdhci_free_host(struct sdhci_host *host) 3338 { 3339 mmc_free_host(host->mmc); 3340 } 3341 3342 EXPORT_SYMBOL_GPL(sdhci_free_host); 3343 3344 /*****************************************************************************\ 3345 * * 3346 * Driver init/exit * 3347 * * 3348 \*****************************************************************************/ 3349 3350 static int __init sdhci_drv_init(void) 3351 { 3352 pr_info(DRIVER_NAME 3353 ": Secure Digital Host Controller Interface driver\n"); 3354 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3355 3356 return 0; 3357 } 3358 3359 static void __exit sdhci_drv_exit(void) 3360 { 3361 } 3362 3363 module_init(sdhci_drv_init); 3364 module_exit(sdhci_drv_exit); 3365 3366 module_param(debug_quirks, uint, 0444); 3367 module_param(debug_quirks2, uint, 0444); 3368 3369 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3370 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3371 MODULE_LICENSE("GPL"); 3372 3373 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3374 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3375