11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 4b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 81c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 91c6a0718SPierre Ossman * your option) any later version. 1084c46a53SPierre Ossman * 1184c46a53SPierre Ossman * Thanks to the following companies for their support: 1284c46a53SPierre Ossman * 1384c46a53SPierre Ossman * - JMicron (hardware and technical support) 141c6a0718SPierre Ossman */ 151c6a0718SPierre Ossman 161c6a0718SPierre Ossman #include <linux/delay.h> 171c6a0718SPierre Ossman #include <linux/highmem.h> 18b8c86fc5SPierre Ossman #include <linux/io.h> 1988b47679SPaul Gortmaker #include <linux/module.h> 201c6a0718SPierre Ossman #include <linux/dma-mapping.h> 215a0e3ad6STejun Heo #include <linux/slab.h> 2211763609SRalf Baechle #include <linux/scatterlist.h> 239bea3c85SMarek Szyprowski #include <linux/regulator/consumer.h> 2466fd8ad5SAdrian Hunter #include <linux/pm_runtime.h> 251c6a0718SPierre Ossman 262f730fecSPierre Ossman #include <linux/leds.h> 272f730fecSPierre Ossman 2822113efdSAries Lee #include <linux/mmc/mmc.h> 291c6a0718SPierre Ossman #include <linux/mmc/host.h> 30473b095aSAaron Lu #include <linux/mmc/card.h> 31bec9d4e5SGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #include "sdhci.h" 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define DRIVER_NAME "sdhci" 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define DBG(f, x...) \ 381c6a0718SPierre Ossman pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 391c6a0718SPierre Ossman 40f9134319SPierre Ossman #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41f9134319SPierre Ossman defined(CONFIG_MMC_SDHCI_MODULE)) 42f9134319SPierre Ossman #define SDHCI_USE_LEDS_CLASS 43f9134319SPierre Ossman #endif 44f9134319SPierre Ossman 45b513ea25SArindam Nath #define MAX_TUNING_LOOP 40 46b513ea25SArindam Nath 471c6a0718SPierre Ossman static unsigned int debug_quirks = 0; 4866fd8ad5SAdrian Hunter static unsigned int debug_quirks2; 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *); 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *); 53069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 54cf2b5eeaSArindam Nath static void sdhci_tuning_timer(unsigned long data); 5552983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 561c6a0718SPierre Ossman 5766fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 5866fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host); 5966fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host); 60f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 61f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 6266fd8ad5SAdrian Hunter #else 6366fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 6466fd8ad5SAdrian Hunter { 6566fd8ad5SAdrian Hunter return 0; 6666fd8ad5SAdrian Hunter } 6766fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 6866fd8ad5SAdrian Hunter { 6966fd8ad5SAdrian Hunter return 0; 7066fd8ad5SAdrian Hunter } 71f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 72f0710a55SAdrian Hunter { 73f0710a55SAdrian Hunter } 74f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 75f0710a55SAdrian Hunter { 76f0710a55SAdrian Hunter } 7766fd8ad5SAdrian Hunter #endif 7866fd8ad5SAdrian Hunter 791c6a0718SPierre Ossman static void sdhci_dumpregs(struct sdhci_host *host) 801c6a0718SPierre Ossman { 81a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 82412ab659SPhilip Rakity mmc_hostname(host->mmc)); 831c6a0718SPierre Ossman 84a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 854e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_DMA_ADDRESS), 864e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_HOST_VERSION)); 87a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 884e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_SIZE), 894e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_COUNT)); 90a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 914e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_ARGUMENT), 924e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_TRANSFER_MODE)); 93a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 944e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_PRESENT_STATE), 954e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_HOST_CONTROL)); 96a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 974e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_POWER_CONTROL), 984e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 99a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 1004e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 1014e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 102a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 1034e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 1044e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_STATUS)); 105a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 1064e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_ENABLE), 1074e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 108a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 1094e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_ACMD12_ERR), 1104e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 111a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 1124e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_CAPABILITIES), 113e8120ad1SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1)); 114a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 115e8120ad1SPhilip Rakity sdhci_readw(host, SDHCI_COMMAND), 1164e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_MAX_CURRENT)); 117a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 118f2119df6SArindam Nath sdhci_readw(host, SDHCI_HOST_CONTROL2)); 1191c6a0718SPierre Ossman 120be3f4ae0SBen Dooks if (host->flags & SDHCI_USE_ADMA) 121a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 122be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ERROR), 123be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 124be3f4ae0SBen Dooks 125a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ===========================================\n"); 1261c6a0718SPierre Ossman } 1271c6a0718SPierre Ossman 1281c6a0718SPierre Ossman /*****************************************************************************\ 1291c6a0718SPierre Ossman * * 1301c6a0718SPierre Ossman * Low level functions * 1311c6a0718SPierre Ossman * * 1321c6a0718SPierre Ossman \*****************************************************************************/ 1331c6a0718SPierre Ossman 1347260cf5eSAnton Vorontsov static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 1357260cf5eSAnton Vorontsov { 1367260cf5eSAnton Vorontsov u32 ier; 1377260cf5eSAnton Vorontsov 1387260cf5eSAnton Vorontsov ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1397260cf5eSAnton Vorontsov ier &= ~clear; 1407260cf5eSAnton Vorontsov ier |= set; 1417260cf5eSAnton Vorontsov sdhci_writel(host, ier, SDHCI_INT_ENABLE); 1427260cf5eSAnton Vorontsov sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 1437260cf5eSAnton Vorontsov } 1447260cf5eSAnton Vorontsov 1457260cf5eSAnton Vorontsov static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 1467260cf5eSAnton Vorontsov { 1477260cf5eSAnton Vorontsov sdhci_clear_set_irqs(host, 0, irqs); 1487260cf5eSAnton Vorontsov } 1497260cf5eSAnton Vorontsov 1507260cf5eSAnton Vorontsov static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 1517260cf5eSAnton Vorontsov { 1527260cf5eSAnton Vorontsov sdhci_clear_set_irqs(host, irqs, 0); 1537260cf5eSAnton Vorontsov } 1547260cf5eSAnton Vorontsov 1557260cf5eSAnton Vorontsov static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 1567260cf5eSAnton Vorontsov { 157d25928d1SShawn Guo u32 present, irqs; 1587260cf5eSAnton Vorontsov 159c79396c1SAdrian Hunter if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 16087b87a3fSDaniel Drake (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 16166fd8ad5SAdrian Hunter return; 16266fd8ad5SAdrian Hunter 163d25928d1SShawn Guo present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 164d25928d1SShawn Guo SDHCI_CARD_PRESENT; 165d25928d1SShawn Guo irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; 166d25928d1SShawn Guo 1677260cf5eSAnton Vorontsov if (enable) 1687260cf5eSAnton Vorontsov sdhci_unmask_irqs(host, irqs); 1697260cf5eSAnton Vorontsov else 1707260cf5eSAnton Vorontsov sdhci_mask_irqs(host, irqs); 1717260cf5eSAnton Vorontsov } 1727260cf5eSAnton Vorontsov 1737260cf5eSAnton Vorontsov static void sdhci_enable_card_detection(struct sdhci_host *host) 1747260cf5eSAnton Vorontsov { 1757260cf5eSAnton Vorontsov sdhci_set_card_detection(host, true); 1767260cf5eSAnton Vorontsov } 1777260cf5eSAnton Vorontsov 1787260cf5eSAnton Vorontsov static void sdhci_disable_card_detection(struct sdhci_host *host) 1797260cf5eSAnton Vorontsov { 1807260cf5eSAnton Vorontsov sdhci_set_card_detection(host, false); 1817260cf5eSAnton Vorontsov } 1827260cf5eSAnton Vorontsov 1831c6a0718SPierre Ossman static void sdhci_reset(struct sdhci_host *host, u8 mask) 1841c6a0718SPierre Ossman { 1851c6a0718SPierre Ossman unsigned long timeout; 186063a9dbbSAnton Vorontsov u32 uninitialized_var(ier); 1871c6a0718SPierre Ossman 188b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 1894e4141a5SAnton Vorontsov if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 1901c6a0718SPierre Ossman SDHCI_CARD_PRESENT)) 1911c6a0718SPierre Ossman return; 1921c6a0718SPierre Ossman } 1931c6a0718SPierre Ossman 194063a9dbbSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 195063a9dbbSAnton Vorontsov ier = sdhci_readl(host, SDHCI_INT_ENABLE); 196063a9dbbSAnton Vorontsov 197393c1a34SPhilip Rakity if (host->ops->platform_reset_enter) 198393c1a34SPhilip Rakity host->ops->platform_reset_enter(host, mask); 199393c1a34SPhilip Rakity 2004e4141a5SAnton Vorontsov sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 2011c6a0718SPierre Ossman 202f0710a55SAdrian Hunter if (mask & SDHCI_RESET_ALL) { 2031c6a0718SPierre Ossman host->clock = 0; 204f0710a55SAdrian Hunter /* Reset-all turns off SD Bus Power */ 205f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 206f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 207f0710a55SAdrian Hunter } 2081c6a0718SPierre Ossman 2091c6a0718SPierre Ossman /* Wait max 100 ms */ 2101c6a0718SPierre Ossman timeout = 100; 2111c6a0718SPierre Ossman 2121c6a0718SPierre Ossman /* hw clears the bit when it's done */ 2134e4141a5SAnton Vorontsov while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 2141c6a0718SPierre Ossman if (timeout == 0) { 215a3c76eb9SGirish K S pr_err("%s: Reset 0x%x never completed.\n", 2161c6a0718SPierre Ossman mmc_hostname(host->mmc), (int)mask); 2171c6a0718SPierre Ossman sdhci_dumpregs(host); 2181c6a0718SPierre Ossman return; 2191c6a0718SPierre Ossman } 2201c6a0718SPierre Ossman timeout--; 2211c6a0718SPierre Ossman mdelay(1); 2221c6a0718SPierre Ossman } 223063a9dbbSAnton Vorontsov 224393c1a34SPhilip Rakity if (host->ops->platform_reset_exit) 225393c1a34SPhilip Rakity host->ops->platform_reset_exit(host, mask); 226393c1a34SPhilip Rakity 227063a9dbbSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 228063a9dbbSAnton Vorontsov sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 2293abc1e80SShaohui Xie 2303abc1e80SShaohui Xie if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2313abc1e80SShaohui Xie if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) 2323abc1e80SShaohui Xie host->ops->enable_dma(host); 2333abc1e80SShaohui Xie } 2341c6a0718SPierre Ossman } 2351c6a0718SPierre Ossman 2362f4cbb3dSNicolas Pitre static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 2372f4cbb3dSNicolas Pitre 2382f4cbb3dSNicolas Pitre static void sdhci_init(struct sdhci_host *host, int soft) 2391c6a0718SPierre Ossman { 2402f4cbb3dSNicolas Pitre if (soft) 2412f4cbb3dSNicolas Pitre sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 2422f4cbb3dSNicolas Pitre else 2431c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 2441c6a0718SPierre Ossman 2457260cf5eSAnton Vorontsov sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 2467260cf5eSAnton Vorontsov SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 2471c6a0718SPierre Ossman SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 2481c6a0718SPierre Ossman SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 2496aa943abSAnton Vorontsov SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 2502f4cbb3dSNicolas Pitre 2512f4cbb3dSNicolas Pitre if (soft) { 2522f4cbb3dSNicolas Pitre /* force clock reconfiguration */ 2532f4cbb3dSNicolas Pitre host->clock = 0; 2542f4cbb3dSNicolas Pitre sdhci_set_ios(host->mmc, &host->mmc->ios); 2552f4cbb3dSNicolas Pitre } 2567260cf5eSAnton Vorontsov } 2571c6a0718SPierre Ossman 2587260cf5eSAnton Vorontsov static void sdhci_reinit(struct sdhci_host *host) 2597260cf5eSAnton Vorontsov { 2602f4cbb3dSNicolas Pitre sdhci_init(host, 0); 261b67c6b41SAaron Lu /* 262b67c6b41SAaron Lu * Retuning stuffs are affected by different cards inserted and only 263b67c6b41SAaron Lu * applicable to UHS-I cards. So reset these fields to their initial 264b67c6b41SAaron Lu * value when card is removed. 265b67c6b41SAaron Lu */ 266973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 267973905feSAaron Lu host->flags &= ~SDHCI_USING_RETUNING_TIMER; 268973905feSAaron Lu 269b67c6b41SAaron Lu del_timer_sync(&host->tuning_timer); 270b67c6b41SAaron Lu host->flags &= ~SDHCI_NEEDS_RETUNING; 271b67c6b41SAaron Lu host->mmc->max_blk_count = 272b67c6b41SAaron Lu (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 273b67c6b41SAaron Lu } 2747260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 2751c6a0718SPierre Ossman } 2761c6a0718SPierre Ossman 2771c6a0718SPierre Ossman static void sdhci_activate_led(struct sdhci_host *host) 2781c6a0718SPierre Ossman { 2791c6a0718SPierre Ossman u8 ctrl; 2801c6a0718SPierre Ossman 2814e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2821c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_LED; 2834e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2841c6a0718SPierre Ossman } 2851c6a0718SPierre Ossman 2861c6a0718SPierre Ossman static void sdhci_deactivate_led(struct sdhci_host *host) 2871c6a0718SPierre Ossman { 2881c6a0718SPierre Ossman u8 ctrl; 2891c6a0718SPierre Ossman 2904e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2911c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_LED; 2924e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2931c6a0718SPierre Ossman } 2941c6a0718SPierre Ossman 295f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 2962f730fecSPierre Ossman static void sdhci_led_control(struct led_classdev *led, 2972f730fecSPierre Ossman enum led_brightness brightness) 2982f730fecSPierre Ossman { 2992f730fecSPierre Ossman struct sdhci_host *host = container_of(led, struct sdhci_host, led); 3002f730fecSPierre Ossman unsigned long flags; 3012f730fecSPierre Ossman 3022f730fecSPierre Ossman spin_lock_irqsave(&host->lock, flags); 3032f730fecSPierre Ossman 30466fd8ad5SAdrian Hunter if (host->runtime_suspended) 30566fd8ad5SAdrian Hunter goto out; 30666fd8ad5SAdrian Hunter 3072f730fecSPierre Ossman if (brightness == LED_OFF) 3082f730fecSPierre Ossman sdhci_deactivate_led(host); 3092f730fecSPierre Ossman else 3102f730fecSPierre Ossman sdhci_activate_led(host); 31166fd8ad5SAdrian Hunter out: 3122f730fecSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 3132f730fecSPierre Ossman } 3142f730fecSPierre Ossman #endif 3152f730fecSPierre Ossman 3161c6a0718SPierre Ossman /*****************************************************************************\ 3171c6a0718SPierre Ossman * * 3181c6a0718SPierre Ossman * Core functions * 3191c6a0718SPierre Ossman * * 3201c6a0718SPierre Ossman \*****************************************************************************/ 3211c6a0718SPierre Ossman 3221c6a0718SPierre Ossman static void sdhci_read_block_pio(struct sdhci_host *host) 3231c6a0718SPierre Ossman { 3247659150cSPierre Ossman unsigned long flags; 3257659150cSPierre Ossman size_t blksize, len, chunk; 3267244b85bSSteven Noonan u32 uninitialized_var(scratch); 3277659150cSPierre Ossman u8 *buf; 3281c6a0718SPierre Ossman 3291c6a0718SPierre Ossman DBG("PIO reading\n"); 3301c6a0718SPierre Ossman 3311c6a0718SPierre Ossman blksize = host->data->blksz; 3327659150cSPierre Ossman chunk = 0; 3331c6a0718SPierre Ossman 3347659150cSPierre Ossman local_irq_save(flags); 3351c6a0718SPierre Ossman 3361c6a0718SPierre Ossman while (blksize) { 3377659150cSPierre Ossman if (!sg_miter_next(&host->sg_miter)) 3387659150cSPierre Ossman BUG(); 3397659150cSPierre Ossman 3407659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3417659150cSPierre Ossman 3427659150cSPierre Ossman blksize -= len; 3437659150cSPierre Ossman host->sg_miter.consumed = len; 3447659150cSPierre Ossman 3457659150cSPierre Ossman buf = host->sg_miter.addr; 3467659150cSPierre Ossman 3477659150cSPierre Ossman while (len) { 3487659150cSPierre Ossman if (chunk == 0) { 3494e4141a5SAnton Vorontsov scratch = sdhci_readl(host, SDHCI_BUFFER); 3507659150cSPierre Ossman chunk = 4; 3511c6a0718SPierre Ossman } 3521c6a0718SPierre Ossman 3537659150cSPierre Ossman *buf = scratch & 0xFF; 3541c6a0718SPierre Ossman 3557659150cSPierre Ossman buf++; 3567659150cSPierre Ossman scratch >>= 8; 3577659150cSPierre Ossman chunk--; 3587659150cSPierre Ossman len--; 3597659150cSPierre Ossman } 3601c6a0718SPierre Ossman } 3611c6a0718SPierre Ossman 3627659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3637659150cSPierre Ossman 3647659150cSPierre Ossman local_irq_restore(flags); 3651c6a0718SPierre Ossman } 3661c6a0718SPierre Ossman 3671c6a0718SPierre Ossman static void sdhci_write_block_pio(struct sdhci_host *host) 3681c6a0718SPierre Ossman { 3697659150cSPierre Ossman unsigned long flags; 3707659150cSPierre Ossman size_t blksize, len, chunk; 3717659150cSPierre Ossman u32 scratch; 3727659150cSPierre Ossman u8 *buf; 3731c6a0718SPierre Ossman 3741c6a0718SPierre Ossman DBG("PIO writing\n"); 3751c6a0718SPierre Ossman 3761c6a0718SPierre Ossman blksize = host->data->blksz; 3777659150cSPierre Ossman chunk = 0; 3787659150cSPierre Ossman scratch = 0; 3791c6a0718SPierre Ossman 3807659150cSPierre Ossman local_irq_save(flags); 3811c6a0718SPierre Ossman 3821c6a0718SPierre Ossman while (blksize) { 3837659150cSPierre Ossman if (!sg_miter_next(&host->sg_miter)) 3847659150cSPierre Ossman BUG(); 3851c6a0718SPierre Ossman 3867659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3871c6a0718SPierre Ossman 3887659150cSPierre Ossman blksize -= len; 3897659150cSPierre Ossman host->sg_miter.consumed = len; 3907659150cSPierre Ossman 3917659150cSPierre Ossman buf = host->sg_miter.addr; 3927659150cSPierre Ossman 3937659150cSPierre Ossman while (len) { 3947659150cSPierre Ossman scratch |= (u32)*buf << (chunk * 8); 3957659150cSPierre Ossman 3967659150cSPierre Ossman buf++; 3977659150cSPierre Ossman chunk++; 3987659150cSPierre Ossman len--; 3997659150cSPierre Ossman 4007659150cSPierre Ossman if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 4014e4141a5SAnton Vorontsov sdhci_writel(host, scratch, SDHCI_BUFFER); 4027659150cSPierre Ossman chunk = 0; 4037659150cSPierre Ossman scratch = 0; 4047659150cSPierre Ossman } 4057659150cSPierre Ossman } 4061c6a0718SPierre Ossman } 4071c6a0718SPierre Ossman 4087659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 4091c6a0718SPierre Ossman 4107659150cSPierre Ossman local_irq_restore(flags); 4111c6a0718SPierre Ossman } 4121c6a0718SPierre Ossman 4131c6a0718SPierre Ossman static void sdhci_transfer_pio(struct sdhci_host *host) 4141c6a0718SPierre Ossman { 4151c6a0718SPierre Ossman u32 mask; 4161c6a0718SPierre Ossman 4171c6a0718SPierre Ossman BUG_ON(!host->data); 4181c6a0718SPierre Ossman 4197659150cSPierre Ossman if (host->blocks == 0) 4201c6a0718SPierre Ossman return; 4211c6a0718SPierre Ossman 4221c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4231c6a0718SPierre Ossman mask = SDHCI_DATA_AVAILABLE; 4241c6a0718SPierre Ossman else 4251c6a0718SPierre Ossman mask = SDHCI_SPACE_AVAILABLE; 4261c6a0718SPierre Ossman 4274a3cba32SPierre Ossman /* 4284a3cba32SPierre Ossman * Some controllers (JMicron JMB38x) mess up the buffer bits 4294a3cba32SPierre Ossman * for transfers < 4 bytes. As long as it is just one block, 4304a3cba32SPierre Ossman * we can ignore the bits. 4314a3cba32SPierre Ossman */ 4324a3cba32SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 4334a3cba32SPierre Ossman (host->data->blocks == 1)) 4344a3cba32SPierre Ossman mask = ~0; 4354a3cba32SPierre Ossman 4364e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 4373e3bf207SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 4383e3bf207SAnton Vorontsov udelay(100); 4393e3bf207SAnton Vorontsov 4401c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4411c6a0718SPierre Ossman sdhci_read_block_pio(host); 4421c6a0718SPierre Ossman else 4431c6a0718SPierre Ossman sdhci_write_block_pio(host); 4441c6a0718SPierre Ossman 4457659150cSPierre Ossman host->blocks--; 4467659150cSPierre Ossman if (host->blocks == 0) 4471c6a0718SPierre Ossman break; 4481c6a0718SPierre Ossman } 4491c6a0718SPierre Ossman 4501c6a0718SPierre Ossman DBG("PIO transfer complete.\n"); 4511c6a0718SPierre Ossman } 4521c6a0718SPierre Ossman 4532134a922SPierre Ossman static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 4542134a922SPierre Ossman { 4552134a922SPierre Ossman local_irq_save(*flags); 456482fce99SCong Wang return kmap_atomic(sg_page(sg)) + sg->offset; 4572134a922SPierre Ossman } 4582134a922SPierre Ossman 4592134a922SPierre Ossman static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 4602134a922SPierre Ossman { 461482fce99SCong Wang kunmap_atomic(buffer); 4622134a922SPierre Ossman local_irq_restore(*flags); 4632134a922SPierre Ossman } 4642134a922SPierre Ossman 465118cd17dSBen Dooks static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 466118cd17dSBen Dooks { 4679e506f35SBen Dooks __le32 *dataddr = (__le32 __force *)(desc + 4); 4689e506f35SBen Dooks __le16 *cmdlen = (__le16 __force *)desc; 469118cd17dSBen Dooks 4709e506f35SBen Dooks /* SDHCI specification says ADMA descriptors should be 4 byte 4719e506f35SBen Dooks * aligned, so using 16 or 32bit operations should be safe. */ 472118cd17dSBen Dooks 4739e506f35SBen Dooks cmdlen[0] = cpu_to_le16(cmd); 4749e506f35SBen Dooks cmdlen[1] = cpu_to_le16(len); 4759e506f35SBen Dooks 4769e506f35SBen Dooks dataddr[0] = cpu_to_le32(addr); 477118cd17dSBen Dooks } 478118cd17dSBen Dooks 4798f1934ceSPierre Ossman static int sdhci_adma_table_pre(struct sdhci_host *host, 4802134a922SPierre Ossman struct mmc_data *data) 4812134a922SPierre Ossman { 4822134a922SPierre Ossman int direction; 4832134a922SPierre Ossman 4842134a922SPierre Ossman u8 *desc; 4852134a922SPierre Ossman u8 *align; 4862134a922SPierre Ossman dma_addr_t addr; 4872134a922SPierre Ossman dma_addr_t align_addr; 4882134a922SPierre Ossman int len, offset; 4892134a922SPierre Ossman 4902134a922SPierre Ossman struct scatterlist *sg; 4912134a922SPierre Ossman int i; 4922134a922SPierre Ossman char *buffer; 4932134a922SPierre Ossman unsigned long flags; 4942134a922SPierre Ossman 4952134a922SPierre Ossman /* 4962134a922SPierre Ossman * The spec does not specify endianness of descriptor table. 4972134a922SPierre Ossman * We currently guess that it is LE. 4982134a922SPierre Ossman */ 4992134a922SPierre Ossman 5002134a922SPierre Ossman if (data->flags & MMC_DATA_READ) 5012134a922SPierre Ossman direction = DMA_FROM_DEVICE; 5022134a922SPierre Ossman else 5032134a922SPierre Ossman direction = DMA_TO_DEVICE; 5042134a922SPierre Ossman 5052134a922SPierre Ossman /* 5062134a922SPierre Ossman * The ADMA descriptor table is mapped further down as we 5072134a922SPierre Ossman * need to fill it with data first. 5082134a922SPierre Ossman */ 5092134a922SPierre Ossman 5102134a922SPierre Ossman host->align_addr = dma_map_single(mmc_dev(host->mmc), 5112134a922SPierre Ossman host->align_buffer, 128 * 4, direction); 5128d8bb39bSFUJITA Tomonori if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 5138f1934ceSPierre Ossman goto fail; 5142134a922SPierre Ossman BUG_ON(host->align_addr & 0x3); 5152134a922SPierre Ossman 5162134a922SPierre Ossman host->sg_count = dma_map_sg(mmc_dev(host->mmc), 5172134a922SPierre Ossman data->sg, data->sg_len, direction); 5188f1934ceSPierre Ossman if (host->sg_count == 0) 5198f1934ceSPierre Ossman goto unmap_align; 5202134a922SPierre Ossman 5212134a922SPierre Ossman desc = host->adma_desc; 5222134a922SPierre Ossman align = host->align_buffer; 5232134a922SPierre Ossman 5242134a922SPierre Ossman align_addr = host->align_addr; 5252134a922SPierre Ossman 5262134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 5272134a922SPierre Ossman addr = sg_dma_address(sg); 5282134a922SPierre Ossman len = sg_dma_len(sg); 5292134a922SPierre Ossman 5302134a922SPierre Ossman /* 5312134a922SPierre Ossman * The SDHCI specification states that ADMA 5322134a922SPierre Ossman * addresses must be 32-bit aligned. If they 5332134a922SPierre Ossman * aren't, then we use a bounce buffer for 5342134a922SPierre Ossman * the (up to three) bytes that screw up the 5352134a922SPierre Ossman * alignment. 5362134a922SPierre Ossman */ 5372134a922SPierre Ossman offset = (4 - (addr & 0x3)) & 0x3; 5382134a922SPierre Ossman if (offset) { 5392134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5402134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 5416cefd05fSPierre Ossman WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 5422134a922SPierre Ossman memcpy(align, buffer, offset); 5432134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 5442134a922SPierre Ossman } 5452134a922SPierre Ossman 546118cd17dSBen Dooks /* tran, valid */ 547118cd17dSBen Dooks sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 5482134a922SPierre Ossman 5492134a922SPierre Ossman BUG_ON(offset > 65536); 5502134a922SPierre Ossman 5512134a922SPierre Ossman align += 4; 5522134a922SPierre Ossman align_addr += 4; 5532134a922SPierre Ossman 5542134a922SPierre Ossman desc += 8; 5552134a922SPierre Ossman 5562134a922SPierre Ossman addr += offset; 5572134a922SPierre Ossman len -= offset; 5582134a922SPierre Ossman } 5592134a922SPierre Ossman 5602134a922SPierre Ossman BUG_ON(len > 65536); 5612134a922SPierre Ossman 562118cd17dSBen Dooks /* tran, valid */ 563118cd17dSBen Dooks sdhci_set_adma_desc(desc, addr, len, 0x21); 5642134a922SPierre Ossman desc += 8; 5652134a922SPierre Ossman 5662134a922SPierre Ossman /* 5672134a922SPierre Ossman * If this triggers then we have a calculation bug 5682134a922SPierre Ossman * somewhere. :/ 5692134a922SPierre Ossman */ 5702134a922SPierre Ossman WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 5712134a922SPierre Ossman } 5722134a922SPierre Ossman 57370764a90SThomas Abraham if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 57470764a90SThomas Abraham /* 57570764a90SThomas Abraham * Mark the last descriptor as the terminating descriptor 57670764a90SThomas Abraham */ 57770764a90SThomas Abraham if (desc != host->adma_desc) { 57870764a90SThomas Abraham desc -= 8; 57970764a90SThomas Abraham desc[0] |= 0x2; /* end */ 58070764a90SThomas Abraham } 58170764a90SThomas Abraham } else { 5822134a922SPierre Ossman /* 5832134a922SPierre Ossman * Add a terminating entry. 5842134a922SPierre Ossman */ 5852134a922SPierre Ossman 586118cd17dSBen Dooks /* nop, end, valid */ 587118cd17dSBen Dooks sdhci_set_adma_desc(desc, 0, 0, 0x3); 58870764a90SThomas Abraham } 5892134a922SPierre Ossman 5902134a922SPierre Ossman /* 5912134a922SPierre Ossman * Resync align buffer as we might have changed it. 5922134a922SPierre Ossman */ 5932134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5942134a922SPierre Ossman dma_sync_single_for_device(mmc_dev(host->mmc), 5952134a922SPierre Ossman host->align_addr, 128 * 4, direction); 5962134a922SPierre Ossman } 5972134a922SPierre Ossman 5982134a922SPierre Ossman host->adma_addr = dma_map_single(mmc_dev(host->mmc), 5992134a922SPierre Ossman host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 600980167b7SPierre Ossman if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 6018f1934ceSPierre Ossman goto unmap_entries; 6022134a922SPierre Ossman BUG_ON(host->adma_addr & 0x3); 6038f1934ceSPierre Ossman 6048f1934ceSPierre Ossman return 0; 6058f1934ceSPierre Ossman 6068f1934ceSPierre Ossman unmap_entries: 6078f1934ceSPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 6088f1934ceSPierre Ossman data->sg_len, direction); 6098f1934ceSPierre Ossman unmap_align: 6108f1934ceSPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 6118f1934ceSPierre Ossman 128 * 4, direction); 6128f1934ceSPierre Ossman fail: 6138f1934ceSPierre Ossman return -EINVAL; 6142134a922SPierre Ossman } 6152134a922SPierre Ossman 6162134a922SPierre Ossman static void sdhci_adma_table_post(struct sdhci_host *host, 6172134a922SPierre Ossman struct mmc_data *data) 6182134a922SPierre Ossman { 6192134a922SPierre Ossman int direction; 6202134a922SPierre Ossman 6212134a922SPierre Ossman struct scatterlist *sg; 6222134a922SPierre Ossman int i, size; 6232134a922SPierre Ossman u8 *align; 6242134a922SPierre Ossman char *buffer; 6252134a922SPierre Ossman unsigned long flags; 6262134a922SPierre Ossman 6272134a922SPierre Ossman if (data->flags & MMC_DATA_READ) 6282134a922SPierre Ossman direction = DMA_FROM_DEVICE; 6292134a922SPierre Ossman else 6302134a922SPierre Ossman direction = DMA_TO_DEVICE; 6312134a922SPierre Ossman 6322134a922SPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 6332134a922SPierre Ossman (128 * 2 + 1) * 4, DMA_TO_DEVICE); 6342134a922SPierre Ossman 6352134a922SPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 6362134a922SPierre Ossman 128 * 4, direction); 6372134a922SPierre Ossman 6382134a922SPierre Ossman if (data->flags & MMC_DATA_READ) { 6392134a922SPierre Ossman dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 6402134a922SPierre Ossman data->sg_len, direction); 6412134a922SPierre Ossman 6422134a922SPierre Ossman align = host->align_buffer; 6432134a922SPierre Ossman 6442134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 6452134a922SPierre Ossman if (sg_dma_address(sg) & 0x3) { 6462134a922SPierre Ossman size = 4 - (sg_dma_address(sg) & 0x3); 6472134a922SPierre Ossman 6482134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 6496cefd05fSPierre Ossman WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 6502134a922SPierre Ossman memcpy(buffer, align, size); 6512134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 6522134a922SPierre Ossman 6532134a922SPierre Ossman align += 4; 6542134a922SPierre Ossman } 6552134a922SPierre Ossman } 6562134a922SPierre Ossman } 6572134a922SPierre Ossman 6582134a922SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 6592134a922SPierre Ossman data->sg_len, direction); 6602134a922SPierre Ossman } 6612134a922SPierre Ossman 662a3c7778fSAndrei Warkentin static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 6631c6a0718SPierre Ossman { 6641c6a0718SPierre Ossman u8 count; 665a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 6661c6a0718SPierre Ossman unsigned target_timeout, current_timeout; 6671c6a0718SPierre Ossman 668ee53ab5dSPierre Ossman /* 669ee53ab5dSPierre Ossman * If the host controller provides us with an incorrect timeout 670ee53ab5dSPierre Ossman * value, just skip the check and use 0xE. The hardware may take 671ee53ab5dSPierre Ossman * longer to time out, but that's much better than having a too-short 672ee53ab5dSPierre Ossman * timeout value. 673ee53ab5dSPierre Ossman */ 67411a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 675ee53ab5dSPierre Ossman return 0xE; 676e538fbe8SPierre Ossman 677a3c7778fSAndrei Warkentin /* Unspecified timeout, assume max */ 6781d4d7744SUlf Hansson if (!data && !cmd->busy_timeout) 679a3c7778fSAndrei Warkentin return 0xE; 680a3c7778fSAndrei Warkentin 6811c6a0718SPierre Ossman /* timeout in us */ 682a3c7778fSAndrei Warkentin if (!data) 6831d4d7744SUlf Hansson target_timeout = cmd->busy_timeout * 1000; 68478a2ca27SAndy Shevchenko else { 68578a2ca27SAndy Shevchenko target_timeout = data->timeout_ns / 1000; 68678a2ca27SAndy Shevchenko if (host->clock) 68778a2ca27SAndy Shevchenko target_timeout += data->timeout_clks / host->clock; 68878a2ca27SAndy Shevchenko } 6891c6a0718SPierre Ossman 6901c6a0718SPierre Ossman /* 6911c6a0718SPierre Ossman * Figure out needed cycles. 6921c6a0718SPierre Ossman * We do this in steps in order to fit inside a 32 bit int. 6931c6a0718SPierre Ossman * The first step is the minimum timeout, which will have a 6941c6a0718SPierre Ossman * minimum resolution of 6 bits: 6951c6a0718SPierre Ossman * (1) 2^13*1000 > 2^22, 6961c6a0718SPierre Ossman * (2) host->timeout_clk < 2^16 6971c6a0718SPierre Ossman * => 6981c6a0718SPierre Ossman * (1) / (2) > 2^6 6991c6a0718SPierre Ossman */ 7001c6a0718SPierre Ossman count = 0; 7011c6a0718SPierre Ossman current_timeout = (1 << 13) * 1000 / host->timeout_clk; 7021c6a0718SPierre Ossman while (current_timeout < target_timeout) { 7031c6a0718SPierre Ossman count++; 7041c6a0718SPierre Ossman current_timeout <<= 1; 7051c6a0718SPierre Ossman if (count >= 0xF) 7061c6a0718SPierre Ossman break; 7071c6a0718SPierre Ossman } 7081c6a0718SPierre Ossman 7091c6a0718SPierre Ossman if (count >= 0xF) { 71009eeff52SChris Ball DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 71102145977SMark Brown mmc_hostname(host->mmc), count, cmd->opcode); 7121c6a0718SPierre Ossman count = 0xE; 7131c6a0718SPierre Ossman } 7141c6a0718SPierre Ossman 715ee53ab5dSPierre Ossman return count; 716ee53ab5dSPierre Ossman } 717ee53ab5dSPierre Ossman 7186aa943abSAnton Vorontsov static void sdhci_set_transfer_irqs(struct sdhci_host *host) 7196aa943abSAnton Vorontsov { 7206aa943abSAnton Vorontsov u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 7216aa943abSAnton Vorontsov u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 7226aa943abSAnton Vorontsov 7236aa943abSAnton Vorontsov if (host->flags & SDHCI_REQ_USE_DMA) 7246aa943abSAnton Vorontsov sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 7256aa943abSAnton Vorontsov else 7266aa943abSAnton Vorontsov sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 7276aa943abSAnton Vorontsov } 7286aa943abSAnton Vorontsov 729a3c7778fSAndrei Warkentin static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 730ee53ab5dSPierre Ossman { 731ee53ab5dSPierre Ossman u8 count; 7322134a922SPierre Ossman u8 ctrl; 733a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 7348f1934ceSPierre Ossman int ret; 735ee53ab5dSPierre Ossman 736ee53ab5dSPierre Ossman WARN_ON(host->data); 737ee53ab5dSPierre Ossman 738a3c7778fSAndrei Warkentin if (data || (cmd->flags & MMC_RSP_BUSY)) { 739a3c7778fSAndrei Warkentin count = sdhci_calc_timeout(host, cmd); 740a3c7778fSAndrei Warkentin sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 741a3c7778fSAndrei Warkentin } 742a3c7778fSAndrei Warkentin 743a3c7778fSAndrei Warkentin if (!data) 744ee53ab5dSPierre Ossman return; 745ee53ab5dSPierre Ossman 746ee53ab5dSPierre Ossman /* Sanity checks */ 747ee53ab5dSPierre Ossman BUG_ON(data->blksz * data->blocks > 524288); 748ee53ab5dSPierre Ossman BUG_ON(data->blksz > host->mmc->max_blk_size); 749ee53ab5dSPierre Ossman BUG_ON(data->blocks > 65535); 750ee53ab5dSPierre Ossman 751ee53ab5dSPierre Ossman host->data = data; 752ee53ab5dSPierre Ossman host->data_early = 0; 753f6a03cbfSMikko Vinni host->data->bytes_xfered = 0; 754ee53ab5dSPierre Ossman 755a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 756c9fddbc4SPierre Ossman host->flags |= SDHCI_REQ_USE_DMA; 757c9fddbc4SPierre Ossman 7582134a922SPierre Ossman /* 7592134a922SPierre Ossman * FIXME: This doesn't account for merging when mapping the 7602134a922SPierre Ossman * scatterlist. 7612134a922SPierre Ossman */ 7622134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7632134a922SPierre Ossman int broken, i; 7642134a922SPierre Ossman struct scatterlist *sg; 7652134a922SPierre Ossman 7662134a922SPierre Ossman broken = 0; 7672134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7682134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7692134a922SPierre Ossman broken = 1; 7702134a922SPierre Ossman } else { 7712134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 7722134a922SPierre Ossman broken = 1; 7732134a922SPierre Ossman } 7742134a922SPierre Ossman 7752134a922SPierre Ossman if (unlikely(broken)) { 7762134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 7772134a922SPierre Ossman if (sg->length & 0x3) { 7782134a922SPierre Ossman DBG("Reverting to PIO because of " 7792134a922SPierre Ossman "transfer size (%d)\n", 7802134a922SPierre Ossman sg->length); 781c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 7822134a922SPierre Ossman break; 7832134a922SPierre Ossman } 7842134a922SPierre Ossman } 7852134a922SPierre Ossman } 786c9fddbc4SPierre Ossman } 787c9fddbc4SPierre Ossman 788c9fddbc4SPierre Ossman /* 789c9fddbc4SPierre Ossman * The assumption here being that alignment is the same after 790c9fddbc4SPierre Ossman * translation to device address space. 791c9fddbc4SPierre Ossman */ 7922134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7932134a922SPierre Ossman int broken, i; 7942134a922SPierre Ossman struct scatterlist *sg; 7952134a922SPierre Ossman 7962134a922SPierre Ossman broken = 0; 7972134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7982134a922SPierre Ossman /* 7992134a922SPierre Ossman * As we use 3 byte chunks to work around 8002134a922SPierre Ossman * alignment problems, we need to check this 8012134a922SPierre Ossman * quirk. 8022134a922SPierre Ossman */ 8032134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 8042134a922SPierre Ossman broken = 1; 8052134a922SPierre Ossman } else { 8062134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 8072134a922SPierre Ossman broken = 1; 8082134a922SPierre Ossman } 8092134a922SPierre Ossman 8102134a922SPierre Ossman if (unlikely(broken)) { 8112134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 8122134a922SPierre Ossman if (sg->offset & 0x3) { 8132134a922SPierre Ossman DBG("Reverting to PIO because of " 8142134a922SPierre Ossman "bad alignment\n"); 815c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8162134a922SPierre Ossman break; 8172134a922SPierre Ossman } 8182134a922SPierre Ossman } 8192134a922SPierre Ossman } 8202134a922SPierre Ossman } 8212134a922SPierre Ossman 8228f1934ceSPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 8238f1934ceSPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 8248f1934ceSPierre Ossman ret = sdhci_adma_table_pre(host, data); 8258f1934ceSPierre Ossman if (ret) { 8268f1934ceSPierre Ossman /* 8278f1934ceSPierre Ossman * This only happens when someone fed 8288f1934ceSPierre Ossman * us an invalid request. 8298f1934ceSPierre Ossman */ 8308f1934ceSPierre Ossman WARN_ON(1); 831ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8328f1934ceSPierre Ossman } else { 8334e4141a5SAnton Vorontsov sdhci_writel(host, host->adma_addr, 8344e4141a5SAnton Vorontsov SDHCI_ADMA_ADDRESS); 8358f1934ceSPierre Ossman } 8368f1934ceSPierre Ossman } else { 837c8b3e02eSTomas Winkler int sg_cnt; 8388f1934ceSPierre Ossman 839c8b3e02eSTomas Winkler sg_cnt = dma_map_sg(mmc_dev(host->mmc), 8408f1934ceSPierre Ossman data->sg, data->sg_len, 8418f1934ceSPierre Ossman (data->flags & MMC_DATA_READ) ? 8428f1934ceSPierre Ossman DMA_FROM_DEVICE : 8438f1934ceSPierre Ossman DMA_TO_DEVICE); 844c8b3e02eSTomas Winkler if (sg_cnt == 0) { 8458f1934ceSPierre Ossman /* 8468f1934ceSPierre Ossman * This only happens when someone fed 8478f1934ceSPierre Ossman * us an invalid request. 8488f1934ceSPierre Ossman */ 8498f1934ceSPierre Ossman WARN_ON(1); 850ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8518f1934ceSPierre Ossman } else { 852719a61b4SPierre Ossman WARN_ON(sg_cnt != 1); 8534e4141a5SAnton Vorontsov sdhci_writel(host, sg_dma_address(data->sg), 8544e4141a5SAnton Vorontsov SDHCI_DMA_ADDRESS); 8558f1934ceSPierre Ossman } 8568f1934ceSPierre Ossman } 8578f1934ceSPierre Ossman } 8588f1934ceSPierre Ossman 8592134a922SPierre Ossman /* 8602134a922SPierre Ossman * Always adjust the DMA selection as some controllers 8612134a922SPierre Ossman * (e.g. JMicron) can't do PIO properly when the selection 8622134a922SPierre Ossman * is ADMA. 8632134a922SPierre Ossman */ 8642134a922SPierre Ossman if (host->version >= SDHCI_SPEC_200) { 8654e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 8662134a922SPierre Ossman ctrl &= ~SDHCI_CTRL_DMA_MASK; 8672134a922SPierre Ossman if ((host->flags & SDHCI_REQ_USE_DMA) && 8682134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) 8692134a922SPierre Ossman ctrl |= SDHCI_CTRL_ADMA32; 8702134a922SPierre Ossman else 8712134a922SPierre Ossman ctrl |= SDHCI_CTRL_SDMA; 8724e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 873c9fddbc4SPierre Ossman } 874c9fddbc4SPierre Ossman 8758f1934ceSPierre Ossman if (!(host->flags & SDHCI_REQ_USE_DMA)) { 876da60a91dSSebastian Andrzej Siewior int flags; 877da60a91dSSebastian Andrzej Siewior 878da60a91dSSebastian Andrzej Siewior flags = SG_MITER_ATOMIC; 879da60a91dSSebastian Andrzej Siewior if (host->data->flags & MMC_DATA_READ) 880da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_TO_SG; 881da60a91dSSebastian Andrzej Siewior else 882da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_FROM_SG; 883da60a91dSSebastian Andrzej Siewior sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 8847659150cSPierre Ossman host->blocks = data->blocks; 8851c6a0718SPierre Ossman } 8861c6a0718SPierre Ossman 8876aa943abSAnton Vorontsov sdhci_set_transfer_irqs(host); 8886aa943abSAnton Vorontsov 889f6a03cbfSMikko Vinni /* Set the DMA boundary value and block size */ 890f6a03cbfSMikko Vinni sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 891f6a03cbfSMikko Vinni data->blksz), SDHCI_BLOCK_SIZE); 8924e4141a5SAnton Vorontsov sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 8931c6a0718SPierre Ossman } 8941c6a0718SPierre Ossman 8951c6a0718SPierre Ossman static void sdhci_set_transfer_mode(struct sdhci_host *host, 896e89d456fSAndrei Warkentin struct mmc_command *cmd) 8971c6a0718SPierre Ossman { 8981c6a0718SPierre Ossman u16 mode; 899e89d456fSAndrei Warkentin struct mmc_data *data = cmd->data; 9001c6a0718SPierre Ossman 9012b558c13SDong Aisheng if (data == NULL) { 9022b558c13SDong Aisheng /* clear Auto CMD settings for no data CMDs */ 9032b558c13SDong Aisheng mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 9042b558c13SDong Aisheng sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 9052b558c13SDong Aisheng SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 9061c6a0718SPierre Ossman return; 9072b558c13SDong Aisheng } 9081c6a0718SPierre Ossman 909e538fbe8SPierre Ossman WARN_ON(!host->data); 910e538fbe8SPierre Ossman 9111c6a0718SPierre Ossman mode = SDHCI_TRNS_BLK_CNT_EN; 912e89d456fSAndrei Warkentin if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 9131c6a0718SPierre Ossman mode |= SDHCI_TRNS_MULTI; 914e89d456fSAndrei Warkentin /* 915e89d456fSAndrei Warkentin * If we are sending CMD23, CMD12 never gets sent 916e89d456fSAndrei Warkentin * on successful completion (so no Auto-CMD12). 917e89d456fSAndrei Warkentin */ 918e89d456fSAndrei Warkentin if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 919e89d456fSAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD12; 9208edf6371SAndrei Warkentin else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 9218edf6371SAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD23; 9228edf6371SAndrei Warkentin sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 923c4512f79SJerry Huang } 9248edf6371SAndrei Warkentin } 9258edf6371SAndrei Warkentin 9261c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 9271c6a0718SPierre Ossman mode |= SDHCI_TRNS_READ; 928c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) 9291c6a0718SPierre Ossman mode |= SDHCI_TRNS_DMA; 9301c6a0718SPierre Ossman 9314e4141a5SAnton Vorontsov sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 9321c6a0718SPierre Ossman } 9331c6a0718SPierre Ossman 9341c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *host) 9351c6a0718SPierre Ossman { 9361c6a0718SPierre Ossman struct mmc_data *data; 9371c6a0718SPierre Ossman 9381c6a0718SPierre Ossman BUG_ON(!host->data); 9391c6a0718SPierre Ossman 9401c6a0718SPierre Ossman data = host->data; 9411c6a0718SPierre Ossman host->data = NULL; 9421c6a0718SPierre Ossman 943c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 9442134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 9452134a922SPierre Ossman sdhci_adma_table_post(host, data); 9462134a922SPierre Ossman else { 9472134a922SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 9482134a922SPierre Ossman data->sg_len, (data->flags & MMC_DATA_READ) ? 949b8c86fc5SPierre Ossman DMA_FROM_DEVICE : DMA_TO_DEVICE); 9501c6a0718SPierre Ossman } 9512134a922SPierre Ossman } 9521c6a0718SPierre Ossman 9531c6a0718SPierre Ossman /* 954c9b74c5bSPierre Ossman * The specification states that the block count register must 955c9b74c5bSPierre Ossman * be updated, but it does not specify at what point in the 956c9b74c5bSPierre Ossman * data flow. That makes the register entirely useless to read 957c9b74c5bSPierre Ossman * back so we have to assume that nothing made it to the card 958c9b74c5bSPierre Ossman * in the event of an error. 9591c6a0718SPierre Ossman */ 960c9b74c5bSPierre Ossman if (data->error) 961c9b74c5bSPierre Ossman data->bytes_xfered = 0; 9621c6a0718SPierre Ossman else 963c9b74c5bSPierre Ossman data->bytes_xfered = data->blksz * data->blocks; 9641c6a0718SPierre Ossman 965e89d456fSAndrei Warkentin /* 966e89d456fSAndrei Warkentin * Need to send CMD12 if - 967e89d456fSAndrei Warkentin * a) open-ended multiblock transfer (no CMD23) 968e89d456fSAndrei Warkentin * b) error in multiblock transfer 969e89d456fSAndrei Warkentin */ 970e89d456fSAndrei Warkentin if (data->stop && 971e89d456fSAndrei Warkentin (data->error || 972e89d456fSAndrei Warkentin !host->mrq->sbc)) { 973e89d456fSAndrei Warkentin 9741c6a0718SPierre Ossman /* 9751c6a0718SPierre Ossman * The controller needs a reset of internal state machines 9761c6a0718SPierre Ossman * upon error conditions. 9771c6a0718SPierre Ossman */ 97817b0429dSPierre Ossman if (data->error) { 9791c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_CMD); 9801c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_DATA); 9811c6a0718SPierre Ossman } 9821c6a0718SPierre Ossman 9831c6a0718SPierre Ossman sdhci_send_command(host, data->stop); 9841c6a0718SPierre Ossman } else 9851c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 9861c6a0718SPierre Ossman } 9871c6a0718SPierre Ossman 988c0e55129SDong Aisheng void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 9891c6a0718SPierre Ossman { 9901c6a0718SPierre Ossman int flags; 9911c6a0718SPierre Ossman u32 mask; 9921c6a0718SPierre Ossman unsigned long timeout; 9931c6a0718SPierre Ossman 9941c6a0718SPierre Ossman WARN_ON(host->cmd); 9951c6a0718SPierre Ossman 9961c6a0718SPierre Ossman /* Wait max 10 ms */ 9971c6a0718SPierre Ossman timeout = 10; 9981c6a0718SPierre Ossman 9991c6a0718SPierre Ossman mask = SDHCI_CMD_INHIBIT; 10001c6a0718SPierre Ossman if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 10011c6a0718SPierre Ossman mask |= SDHCI_DATA_INHIBIT; 10021c6a0718SPierre Ossman 10031c6a0718SPierre Ossman /* We shouldn't wait for data inihibit for stop commands, even 10041c6a0718SPierre Ossman though they might use busy signaling */ 10051c6a0718SPierre Ossman if (host->mrq->data && (cmd == host->mrq->data->stop)) 10061c6a0718SPierre Ossman mask &= ~SDHCI_DATA_INHIBIT; 10071c6a0718SPierre Ossman 10084e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 10091c6a0718SPierre Ossman if (timeout == 0) { 1010a3c76eb9SGirish K S pr_err("%s: Controller never released " 10111c6a0718SPierre Ossman "inhibit bit(s).\n", mmc_hostname(host->mmc)); 10121c6a0718SPierre Ossman sdhci_dumpregs(host); 101317b0429dSPierre Ossman cmd->error = -EIO; 10141c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10151c6a0718SPierre Ossman return; 10161c6a0718SPierre Ossman } 10171c6a0718SPierre Ossman timeout--; 10181c6a0718SPierre Ossman mdelay(1); 10191c6a0718SPierre Ossman } 10201c6a0718SPierre Ossman 10213e1a6892SAdrian Hunter timeout = jiffies; 10221d4d7744SUlf Hansson if (!cmd->data && cmd->busy_timeout > 9000) 10231d4d7744SUlf Hansson timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 10243e1a6892SAdrian Hunter else 10253e1a6892SAdrian Hunter timeout += 10 * HZ; 10263e1a6892SAdrian Hunter mod_timer(&host->timer, timeout); 10271c6a0718SPierre Ossman 10281c6a0718SPierre Ossman host->cmd = cmd; 10291c6a0718SPierre Ossman 1030a3c7778fSAndrei Warkentin sdhci_prepare_data(host, cmd); 10311c6a0718SPierre Ossman 10324e4141a5SAnton Vorontsov sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 10331c6a0718SPierre Ossman 1034e89d456fSAndrei Warkentin sdhci_set_transfer_mode(host, cmd); 10351c6a0718SPierre Ossman 10361c6a0718SPierre Ossman if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1037a3c76eb9SGirish K S pr_err("%s: Unsupported response type!\n", 10381c6a0718SPierre Ossman mmc_hostname(host->mmc)); 103917b0429dSPierre Ossman cmd->error = -EINVAL; 10401c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10411c6a0718SPierre Ossman return; 10421c6a0718SPierre Ossman } 10431c6a0718SPierre Ossman 10441c6a0718SPierre Ossman if (!(cmd->flags & MMC_RSP_PRESENT)) 10451c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_NONE; 10461c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_136) 10471c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_LONG; 10481c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_BUSY) 10491c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT_BUSY; 10501c6a0718SPierre Ossman else 10511c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT; 10521c6a0718SPierre Ossman 10531c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_CRC) 10541c6a0718SPierre Ossman flags |= SDHCI_CMD_CRC; 10551c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_OPCODE) 10561c6a0718SPierre Ossman flags |= SDHCI_CMD_INDEX; 1057b513ea25SArindam Nath 1058b513ea25SArindam Nath /* CMD19 is special in that the Data Present Select should be set */ 1059069c9f14SGirish K S if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1060069c9f14SGirish K S cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 10611c6a0718SPierre Ossman flags |= SDHCI_CMD_DATA; 10621c6a0718SPierre Ossman 10634e4141a5SAnton Vorontsov sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 10641c6a0718SPierre Ossman } 1065c0e55129SDong Aisheng EXPORT_SYMBOL_GPL(sdhci_send_command); 10661c6a0718SPierre Ossman 10671c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *host) 10681c6a0718SPierre Ossman { 10691c6a0718SPierre Ossman int i; 10701c6a0718SPierre Ossman 10711c6a0718SPierre Ossman BUG_ON(host->cmd == NULL); 10721c6a0718SPierre Ossman 10731c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_PRESENT) { 10741c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_136) { 10751c6a0718SPierre Ossman /* CRC is stripped so we need to do some shifting. */ 10761c6a0718SPierre Ossman for (i = 0;i < 4;i++) { 10774e4141a5SAnton Vorontsov host->cmd->resp[i] = sdhci_readl(host, 10781c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4) << 8; 10791c6a0718SPierre Ossman if (i != 3) 10801c6a0718SPierre Ossman host->cmd->resp[i] |= 10814e4141a5SAnton Vorontsov sdhci_readb(host, 10821c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4-1); 10831c6a0718SPierre Ossman } 10841c6a0718SPierre Ossman } else { 10854e4141a5SAnton Vorontsov host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 10861c6a0718SPierre Ossman } 10871c6a0718SPierre Ossman } 10881c6a0718SPierre Ossman 108917b0429dSPierre Ossman host->cmd->error = 0; 10901c6a0718SPierre Ossman 1091e89d456fSAndrei Warkentin /* Finished CMD23, now send actual command. */ 1092e89d456fSAndrei Warkentin if (host->cmd == host->mrq->sbc) { 1093e89d456fSAndrei Warkentin host->cmd = NULL; 1094e89d456fSAndrei Warkentin sdhci_send_command(host, host->mrq->cmd); 1095e89d456fSAndrei Warkentin } else { 1096e89d456fSAndrei Warkentin 1097e89d456fSAndrei Warkentin /* Processed actual command. */ 1098e538fbe8SPierre Ossman if (host->data && host->data_early) 1099e538fbe8SPierre Ossman sdhci_finish_data(host); 1100e538fbe8SPierre Ossman 1101e538fbe8SPierre Ossman if (!host->cmd->data) 11021c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 11031c6a0718SPierre Ossman 11041c6a0718SPierre Ossman host->cmd = NULL; 11051c6a0718SPierre Ossman } 1106e89d456fSAndrei Warkentin } 11071c6a0718SPierre Ossman 110852983382SKevin Liu static u16 sdhci_get_preset_value(struct sdhci_host *host) 110952983382SKevin Liu { 111052983382SKevin Liu u16 ctrl, preset = 0; 111152983382SKevin Liu 111252983382SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 111352983382SKevin Liu 111452983382SKevin Liu switch (ctrl & SDHCI_CTRL_UHS_MASK) { 111552983382SKevin Liu case SDHCI_CTRL_UHS_SDR12: 111652983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 111752983382SKevin Liu break; 111852983382SKevin Liu case SDHCI_CTRL_UHS_SDR25: 111952983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 112052983382SKevin Liu break; 112152983382SKevin Liu case SDHCI_CTRL_UHS_SDR50: 112252983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 112352983382SKevin Liu break; 112452983382SKevin Liu case SDHCI_CTRL_UHS_SDR104: 112552983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 112652983382SKevin Liu break; 112752983382SKevin Liu case SDHCI_CTRL_UHS_DDR50: 112852983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 112952983382SKevin Liu break; 113052983382SKevin Liu default: 113152983382SKevin Liu pr_warn("%s: Invalid UHS-I mode selected\n", 113252983382SKevin Liu mmc_hostname(host->mmc)); 113352983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 113452983382SKevin Liu break; 113552983382SKevin Liu } 113652983382SKevin Liu return preset; 113752983382SKevin Liu } 113852983382SKevin Liu 11391c6a0718SPierre Ossman static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 11401c6a0718SPierre Ossman { 1141c3ed3877SArindam Nath int div = 0; /* Initialized for compiler warning */ 1142df16219fSGiuseppe CAVALLARO int real_div = div, clk_mul = 1; 1143c3ed3877SArindam Nath u16 clk = 0; 11441c6a0718SPierre Ossman unsigned long timeout; 11451c6a0718SPierre Ossman 114630832ab5STodd Poynor if (clock && clock == host->clock) 11471c6a0718SPierre Ossman return; 11481c6a0718SPierre Ossman 1149df16219fSGiuseppe CAVALLARO host->mmc->actual_clock = 0; 1150df16219fSGiuseppe CAVALLARO 11518114634cSAnton Vorontsov if (host->ops->set_clock) { 11528114634cSAnton Vorontsov host->ops->set_clock(host, clock); 11538114634cSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 11548114634cSAnton Vorontsov return; 11558114634cSAnton Vorontsov } 11568114634cSAnton Vorontsov 11574e4141a5SAnton Vorontsov sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 11581c6a0718SPierre Ossman 11591c6a0718SPierre Ossman if (clock == 0) 11601c6a0718SPierre Ossman goto out; 11611c6a0718SPierre Ossman 116285105c53SZhangfei Gao if (host->version >= SDHCI_SPEC_300) { 116352983382SKevin Liu if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & 116452983382SKevin Liu SDHCI_CTRL_PRESET_VAL_ENABLE) { 116552983382SKevin Liu u16 pre_val; 116652983382SKevin Liu 116752983382SKevin Liu clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 116852983382SKevin Liu pre_val = sdhci_get_preset_value(host); 116952983382SKevin Liu div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 117052983382SKevin Liu >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 117152983382SKevin Liu if (host->clk_mul && 117252983382SKevin Liu (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 117352983382SKevin Liu clk = SDHCI_PROG_CLOCK_MODE; 117452983382SKevin Liu real_div = div + 1; 117552983382SKevin Liu clk_mul = host->clk_mul; 117652983382SKevin Liu } else { 117752983382SKevin Liu real_div = max_t(int, 1, div << 1); 117852983382SKevin Liu } 117952983382SKevin Liu goto clock_set; 118052983382SKevin Liu } 118152983382SKevin Liu 1182c3ed3877SArindam Nath /* 1183c3ed3877SArindam Nath * Check if the Host Controller supports Programmable Clock 1184c3ed3877SArindam Nath * Mode. 1185c3ed3877SArindam Nath */ 1186c3ed3877SArindam Nath if (host->clk_mul) { 1187c3ed3877SArindam Nath for (div = 1; div <= 1024; div++) { 118852983382SKevin Liu if ((host->max_clk * host->clk_mul / div) 118952983382SKevin Liu <= clock) 1190c3ed3877SArindam Nath break; 1191c3ed3877SArindam Nath } 1192c3ed3877SArindam Nath /* 1193c3ed3877SArindam Nath * Set Programmable Clock Mode in the Clock 1194c3ed3877SArindam Nath * Control register. 1195c3ed3877SArindam Nath */ 1196c3ed3877SArindam Nath clk = SDHCI_PROG_CLOCK_MODE; 1197df16219fSGiuseppe CAVALLARO real_div = div; 1198df16219fSGiuseppe CAVALLARO clk_mul = host->clk_mul; 1199c3ed3877SArindam Nath div--; 1200c3ed3877SArindam Nath } else { 120185105c53SZhangfei Gao /* Version 3.00 divisors must be a multiple of 2. */ 120285105c53SZhangfei Gao if (host->max_clk <= clock) 120385105c53SZhangfei Gao div = 1; 120485105c53SZhangfei Gao else { 1205c3ed3877SArindam Nath for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1206c3ed3877SArindam Nath div += 2) { 120785105c53SZhangfei Gao if ((host->max_clk / div) <= clock) 120885105c53SZhangfei Gao break; 120985105c53SZhangfei Gao } 121085105c53SZhangfei Gao } 1211df16219fSGiuseppe CAVALLARO real_div = div; 1212c3ed3877SArindam Nath div >>= 1; 1213c3ed3877SArindam Nath } 121485105c53SZhangfei Gao } else { 121585105c53SZhangfei Gao /* Version 2.00 divisors must be a power of 2. */ 12160397526dSZhangfei Gao for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 12171c6a0718SPierre Ossman if ((host->max_clk / div) <= clock) 12181c6a0718SPierre Ossman break; 12191c6a0718SPierre Ossman } 1220df16219fSGiuseppe CAVALLARO real_div = div; 12211c6a0718SPierre Ossman div >>= 1; 1222c3ed3877SArindam Nath } 12231c6a0718SPierre Ossman 122452983382SKevin Liu clock_set: 1225df16219fSGiuseppe CAVALLARO if (real_div) 1226df16219fSGiuseppe CAVALLARO host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1227df16219fSGiuseppe CAVALLARO 1228c3ed3877SArindam Nath clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 122985105c53SZhangfei Gao clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 123085105c53SZhangfei Gao << SDHCI_DIVIDER_HI_SHIFT; 12311c6a0718SPierre Ossman clk |= SDHCI_CLOCK_INT_EN; 12324e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12331c6a0718SPierre Ossman 123427f6cb16SChris Ball /* Wait max 20 ms */ 123527f6cb16SChris Ball timeout = 20; 12364e4141a5SAnton Vorontsov while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 12371c6a0718SPierre Ossman & SDHCI_CLOCK_INT_STABLE)) { 12381c6a0718SPierre Ossman if (timeout == 0) { 1239a3c76eb9SGirish K S pr_err("%s: Internal clock never " 12401c6a0718SPierre Ossman "stabilised.\n", mmc_hostname(host->mmc)); 12411c6a0718SPierre Ossman sdhci_dumpregs(host); 12421c6a0718SPierre Ossman return; 12431c6a0718SPierre Ossman } 12441c6a0718SPierre Ossman timeout--; 12451c6a0718SPierre Ossman mdelay(1); 12461c6a0718SPierre Ossman } 12471c6a0718SPierre Ossman 12481c6a0718SPierre Ossman clk |= SDHCI_CLOCK_CARD_EN; 12494e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12501c6a0718SPierre Ossman 12511c6a0718SPierre Ossman out: 12521c6a0718SPierre Ossman host->clock = clock; 12531c6a0718SPierre Ossman } 12541c6a0718SPierre Ossman 12558213af3bSAndy Shevchenko static inline void sdhci_update_clock(struct sdhci_host *host) 12568213af3bSAndy Shevchenko { 12578213af3bSAndy Shevchenko unsigned int clock; 12588213af3bSAndy Shevchenko 12598213af3bSAndy Shevchenko clock = host->clock; 12608213af3bSAndy Shevchenko host->clock = 0; 12618213af3bSAndy Shevchenko sdhci_set_clock(host, clock); 12628213af3bSAndy Shevchenko } 12638213af3bSAndy Shevchenko 1264ceb6143bSAdrian Hunter static int sdhci_set_power(struct sdhci_host *host, unsigned short power) 12651c6a0718SPierre Ossman { 12668364248aSGiuseppe Cavallaro u8 pwr = 0; 12671c6a0718SPierre Ossman 12688364248aSGiuseppe Cavallaro if (power != (unsigned short)-1) { 1269ae628903SPierre Ossman switch (1 << power) { 1270ae628903SPierre Ossman case MMC_VDD_165_195: 1271ae628903SPierre Ossman pwr = SDHCI_POWER_180; 1272ae628903SPierre Ossman break; 1273ae628903SPierre Ossman case MMC_VDD_29_30: 1274ae628903SPierre Ossman case MMC_VDD_30_31: 1275ae628903SPierre Ossman pwr = SDHCI_POWER_300; 1276ae628903SPierre Ossman break; 1277ae628903SPierre Ossman case MMC_VDD_32_33: 1278ae628903SPierre Ossman case MMC_VDD_33_34: 1279ae628903SPierre Ossman pwr = SDHCI_POWER_330; 1280ae628903SPierre Ossman break; 1281ae628903SPierre Ossman default: 1282ae628903SPierre Ossman BUG(); 1283ae628903SPierre Ossman } 1284ae628903SPierre Ossman } 1285ae628903SPierre Ossman 1286ae628903SPierre Ossman if (host->pwr == pwr) 1287ceb6143bSAdrian Hunter return -1; 12881c6a0718SPierre Ossman 1289ae628903SPierre Ossman host->pwr = pwr; 1290ae628903SPierre Ossman 1291ae628903SPierre Ossman if (pwr == 0) { 12924e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1293f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1294f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 1295ceb6143bSAdrian Hunter return 0; 12961c6a0718SPierre Ossman } 12971c6a0718SPierre Ossman 12981c6a0718SPierre Ossman /* 12991c6a0718SPierre Ossman * Spec says that we should clear the power reg before setting 13001c6a0718SPierre Ossman * a new value. Some controllers don't seem to like this though. 13011c6a0718SPierre Ossman */ 1302b8c86fc5SPierre Ossman if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 13034e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 13041c6a0718SPierre Ossman 1305e08c1694SAndres Salomon /* 1306c71f6512SAndres Salomon * At least the Marvell CaFe chip gets confused if we set the voltage 1307e08c1694SAndres Salomon * and set turn on power at the same time, so set the voltage first. 1308e08c1694SAndres Salomon */ 130911a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 13104e4141a5SAnton Vorontsov sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 13111c6a0718SPierre Ossman 1312ae628903SPierre Ossman pwr |= SDHCI_POWER_ON; 1313ae628903SPierre Ossman 1314ae628903SPierre Ossman sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1315557b0697SHarald Welte 1316f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1317f0710a55SAdrian Hunter sdhci_runtime_pm_bus_on(host); 1318f0710a55SAdrian Hunter 1319557b0697SHarald Welte /* 1320557b0697SHarald Welte * Some controllers need an extra 10ms delay of 10ms before they 1321557b0697SHarald Welte * can apply clock after applying power 1322557b0697SHarald Welte */ 132311a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1324557b0697SHarald Welte mdelay(10); 1325ceb6143bSAdrian Hunter 1326ceb6143bSAdrian Hunter return power; 13271c6a0718SPierre Ossman } 13281c6a0718SPierre Ossman 13291c6a0718SPierre Ossman /*****************************************************************************\ 13301c6a0718SPierre Ossman * * 13311c6a0718SPierre Ossman * MMC callbacks * 13321c6a0718SPierre Ossman * * 13331c6a0718SPierre Ossman \*****************************************************************************/ 13341c6a0718SPierre Ossman 13351c6a0718SPierre Ossman static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13361c6a0718SPierre Ossman { 13371c6a0718SPierre Ossman struct sdhci_host *host; 1338505a8680SShawn Guo int present; 13391c6a0718SPierre Ossman unsigned long flags; 1340473b095aSAaron Lu u32 tuning_opcode; 13411c6a0718SPierre Ossman 13421c6a0718SPierre Ossman host = mmc_priv(mmc); 13431c6a0718SPierre Ossman 134466fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 134566fd8ad5SAdrian Hunter 13461c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 13471c6a0718SPierre Ossman 13481c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13491c6a0718SPierre Ossman 1350f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 13511c6a0718SPierre Ossman sdhci_activate_led(host); 13522f730fecSPierre Ossman #endif 1353e89d456fSAndrei Warkentin 1354e89d456fSAndrei Warkentin /* 1355e89d456fSAndrei Warkentin * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1356e89d456fSAndrei Warkentin * requests if Auto-CMD12 is enabled. 1357e89d456fSAndrei Warkentin */ 1358e89d456fSAndrei Warkentin if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1359c4512f79SJerry Huang if (mrq->stop) { 1360c4512f79SJerry Huang mrq->data->stop = NULL; 1361c4512f79SJerry Huang mrq->stop = NULL; 1362c4512f79SJerry Huang } 1363c4512f79SJerry Huang } 13641c6a0718SPierre Ossman 13651c6a0718SPierre Ossman host->mrq = mrq; 13661c6a0718SPierre Ossman 1367505a8680SShawn Guo /* 1368505a8680SShawn Guo * Firstly check card presence from cd-gpio. The return could 1369505a8680SShawn Guo * be one of the following possibilities: 1370505a8680SShawn Guo * negative: cd-gpio is not available 1371505a8680SShawn Guo * zero: cd-gpio is used, and card is removed 1372505a8680SShawn Guo * one: cd-gpio is used, and card is present 1373505a8680SShawn Guo */ 1374505a8680SShawn Guo present = mmc_gpio_get_cd(host->mmc); 1375505a8680SShawn Guo if (present < 0) { 137668d1fb7eSAnton Vorontsov /* If polling, assume that the card is always present. */ 137768d1fb7eSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1378505a8680SShawn Guo present = 1; 137968d1fb7eSAnton Vorontsov else 138068d1fb7eSAnton Vorontsov present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 138168d1fb7eSAnton Vorontsov SDHCI_CARD_PRESENT; 1382bec9d4e5SGuennadi Liakhovetski } 1383bec9d4e5SGuennadi Liakhovetski 138468d1fb7eSAnton Vorontsov if (!present || host->flags & SDHCI_DEVICE_DEAD) { 138517b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 13861c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 1387cf2b5eeaSArindam Nath } else { 1388cf2b5eeaSArindam Nath u32 present_state; 1389cf2b5eeaSArindam Nath 1390cf2b5eeaSArindam Nath present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1391cf2b5eeaSArindam Nath /* 1392cf2b5eeaSArindam Nath * Check if the re-tuning timer has already expired and there 1393cf2b5eeaSArindam Nath * is no on-going data transfer. If so, we need to execute 1394cf2b5eeaSArindam Nath * tuning procedure before sending command. 1395cf2b5eeaSArindam Nath */ 1396cf2b5eeaSArindam Nath if ((host->flags & SDHCI_NEEDS_RETUNING) && 1397cf2b5eeaSArindam Nath !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 139814efd957SChris Ball if (mmc->card) { 139914efd957SChris Ball /* eMMC uses cmd21 but sd and sdio use cmd19 */ 140014efd957SChris Ball tuning_opcode = 140114efd957SChris Ball mmc->card->type == MMC_TYPE_MMC ? 1402473b095aSAaron Lu MMC_SEND_TUNING_BLOCK_HS200 : 1403473b095aSAaron Lu MMC_SEND_TUNING_BLOCK; 140463c21180SChuansheng Liu 140563c21180SChuansheng Liu /* Here we need to set the host->mrq to NULL, 140663c21180SChuansheng Liu * in case the pending finish_tasklet 140763c21180SChuansheng Liu * finishes it incorrectly. 140863c21180SChuansheng Liu */ 140963c21180SChuansheng Liu host->mrq = NULL; 141063c21180SChuansheng Liu 1411cf2b5eeaSArindam Nath spin_unlock_irqrestore(&host->lock, flags); 1412473b095aSAaron Lu sdhci_execute_tuning(mmc, tuning_opcode); 1413cf2b5eeaSArindam Nath spin_lock_irqsave(&host->lock, flags); 1414cf2b5eeaSArindam Nath 1415cf2b5eeaSArindam Nath /* Restore original mmc_request structure */ 1416cf2b5eeaSArindam Nath host->mrq = mrq; 1417cf2b5eeaSArindam Nath } 141814efd957SChris Ball } 1419cf2b5eeaSArindam Nath 14208edf6371SAndrei Warkentin if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1421e89d456fSAndrei Warkentin sdhci_send_command(host, mrq->sbc); 1422e89d456fSAndrei Warkentin else 14231c6a0718SPierre Ossman sdhci_send_command(host, mrq->cmd); 1424cf2b5eeaSArindam Nath } 14251c6a0718SPierre Ossman 14261c6a0718SPierre Ossman mmiowb(); 14271c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 14281c6a0718SPierre Ossman } 14291c6a0718SPierre Ossman 143066fd8ad5SAdrian Hunter static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 14311c6a0718SPierre Ossman { 14321c6a0718SPierre Ossman unsigned long flags; 1433ceb6143bSAdrian Hunter int vdd_bit = -1; 14341c6a0718SPierre Ossman u8 ctrl; 14351c6a0718SPierre Ossman 14361c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 14371c6a0718SPierre Ossman 1438ceb6143bSAdrian Hunter if (host->flags & SDHCI_DEVICE_DEAD) { 1439ceb6143bSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 1440ceb6143bSAdrian Hunter if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1441ceb6143bSAdrian Hunter mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1442ceb6143bSAdrian Hunter return; 1443ceb6143bSAdrian Hunter } 14441e72859eSPierre Ossman 14451c6a0718SPierre Ossman /* 14461c6a0718SPierre Ossman * Reset the chip on each power off. 14471c6a0718SPierre Ossman * Should clear out any weird states. 14481c6a0718SPierre Ossman */ 14491c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) { 14504e4141a5SAnton Vorontsov sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 14517260cf5eSAnton Vorontsov sdhci_reinit(host); 14521c6a0718SPierre Ossman } 14531c6a0718SPierre Ossman 145452983382SKevin Liu if (host->version >= SDHCI_SPEC_300 && 1455372c4634SDong Aisheng (ios->power_mode == MMC_POWER_UP) && 1456372c4634SDong Aisheng !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 145752983382SKevin Liu sdhci_enable_preset_value(host, false); 145852983382SKevin Liu 14591c6a0718SPierre Ossman sdhci_set_clock(host, ios->clock); 14601c6a0718SPierre Ossman 14611c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) 1462ceb6143bSAdrian Hunter vdd_bit = sdhci_set_power(host, -1); 14631c6a0718SPierre Ossman else 1464ceb6143bSAdrian Hunter vdd_bit = sdhci_set_power(host, ios->vdd); 1465ceb6143bSAdrian Hunter 1466ceb6143bSAdrian Hunter if (host->vmmc && vdd_bit != -1) { 1467ceb6143bSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 1468ceb6143bSAdrian Hunter mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); 1469ceb6143bSAdrian Hunter spin_lock_irqsave(&host->lock, flags); 1470ceb6143bSAdrian Hunter } 14711c6a0718SPierre Ossman 1472643a81ffSPhilip Rakity if (host->ops->platform_send_init_74_clocks) 1473643a81ffSPhilip Rakity host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1474643a81ffSPhilip Rakity 147515ec4461SPhilip Rakity /* 147615ec4461SPhilip Rakity * If your platform has 8-bit width support but is not a v3 controller, 147715ec4461SPhilip Rakity * or if it requires special setup code, you should implement that in 14787bc088d3SSascha Hauer * platform_bus_width(). 147915ec4461SPhilip Rakity */ 14807bc088d3SSascha Hauer if (host->ops->platform_bus_width) { 14817bc088d3SSascha Hauer host->ops->platform_bus_width(host, ios->bus_width); 14827bc088d3SSascha Hauer } else { 14834e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 148415ec4461SPhilip Rakity if (ios->bus_width == MMC_BUS_WIDTH_8) { 148515ec4461SPhilip Rakity ctrl &= ~SDHCI_CTRL_4BITBUS; 148615ec4461SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 1487ae6d6c92SKyungmin Park ctrl |= SDHCI_CTRL_8BITBUS; 148815ec4461SPhilip Rakity } else { 148915ec4461SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 1490ae6d6c92SKyungmin Park ctrl &= ~SDHCI_CTRL_8BITBUS; 14911c6a0718SPierre Ossman if (ios->bus_width == MMC_BUS_WIDTH_4) 14921c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_4BITBUS; 14931c6a0718SPierre Ossman else 14941c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_4BITBUS; 149515ec4461SPhilip Rakity } 149615ec4461SPhilip Rakity sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 149715ec4461SPhilip Rakity } 149815ec4461SPhilip Rakity 149915ec4461SPhilip Rakity ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 15001c6a0718SPierre Ossman 15013ab9c8daSPhilip Rakity if ((ios->timing == MMC_TIMING_SD_HS || 15023ab9c8daSPhilip Rakity ios->timing == MMC_TIMING_MMC_HS) 15033ab9c8daSPhilip Rakity && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 15041c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_HISPD; 15051c6a0718SPierre Ossman else 15061c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_HISPD; 15071c6a0718SPierre Ossman 1508d6d50a15SArindam Nath if (host->version >= SDHCI_SPEC_300) { 150949c468fcSArindam Nath u16 clk, ctrl_2; 151049c468fcSArindam Nath 151149c468fcSArindam Nath /* In case of UHS-I modes, set High Speed Enable */ 1512069c9f14SGirish K S if ((ios->timing == MMC_TIMING_MMC_HS200) || 1513bb8175a8SSeungwon Jeon (ios->timing == MMC_TIMING_MMC_DDR52) || 1514069c9f14SGirish K S (ios->timing == MMC_TIMING_UHS_SDR50) || 151549c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_SDR104) || 151649c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_DDR50) || 1517dd8df17fSAlexander Elbs (ios->timing == MMC_TIMING_UHS_SDR25)) 151849c468fcSArindam Nath ctrl |= SDHCI_CTRL_HISPD; 1519d6d50a15SArindam Nath 1520d6d50a15SArindam Nath ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1521d6d50a15SArindam Nath if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1522758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1523d6d50a15SArindam Nath /* 1524d6d50a15SArindam Nath * We only need to set Driver Strength if the 1525d6d50a15SArindam Nath * preset value enable is not set. 1526d6d50a15SArindam Nath */ 1527d6d50a15SArindam Nath ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1528d6d50a15SArindam Nath if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1529d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1530d6d50a15SArindam Nath else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1531d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1532d6d50a15SArindam Nath 1533d6d50a15SArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1534758535c4SArindam Nath } else { 1535758535c4SArindam Nath /* 1536758535c4SArindam Nath * According to SDHC Spec v3.00, if the Preset Value 1537758535c4SArindam Nath * Enable in the Host Control 2 register is set, we 1538758535c4SArindam Nath * need to reset SD Clock Enable before changing High 1539758535c4SArindam Nath * Speed Enable to avoid generating clock gliches. 1540758535c4SArindam Nath */ 1541758535c4SArindam Nath 1542758535c4SArindam Nath /* Reset SD Clock Enable */ 1543758535c4SArindam Nath clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1544758535c4SArindam Nath clk &= ~SDHCI_CLOCK_CARD_EN; 1545758535c4SArindam Nath sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1546758535c4SArindam Nath 1547758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1548758535c4SArindam Nath 1549758535c4SArindam Nath /* Re-enable SD Clock */ 15508213af3bSAndy Shevchenko sdhci_update_clock(host); 1551d6d50a15SArindam Nath } 155249c468fcSArindam Nath 155349c468fcSArindam Nath 15546322cdd0SPhilip Rakity /* Reset SD Clock Enable */ 15556322cdd0SPhilip Rakity clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 15566322cdd0SPhilip Rakity clk &= ~SDHCI_CLOCK_CARD_EN; 15576322cdd0SPhilip Rakity sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 15586322cdd0SPhilip Rakity 15596322cdd0SPhilip Rakity if (host->ops->set_uhs_signaling) 15606322cdd0SPhilip Rakity host->ops->set_uhs_signaling(host, ios->timing); 15616322cdd0SPhilip Rakity else { 15626322cdd0SPhilip Rakity ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 156349c468fcSArindam Nath /* Select Bus Speed Mode for host */ 156449c468fcSArindam Nath ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 156559911568SGiuseppe CAVALLARO if ((ios->timing == MMC_TIMING_MMC_HS200) || 156659911568SGiuseppe CAVALLARO (ios->timing == MMC_TIMING_UHS_SDR104)) 156759911568SGiuseppe CAVALLARO ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1568069c9f14SGirish K S else if (ios->timing == MMC_TIMING_UHS_SDR12) 156949c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 157049c468fcSArindam Nath else if (ios->timing == MMC_TIMING_UHS_SDR25) 157149c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 157249c468fcSArindam Nath else if (ios->timing == MMC_TIMING_UHS_SDR50) 157349c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1574bb8175a8SSeungwon Jeon else if ((ios->timing == MMC_TIMING_UHS_DDR50) || 1575bb8175a8SSeungwon Jeon (ios->timing == MMC_TIMING_MMC_DDR52)) 157649c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 157749c468fcSArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 15786322cdd0SPhilip Rakity } 157949c468fcSArindam Nath 158052983382SKevin Liu if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 158152983382SKevin Liu ((ios->timing == MMC_TIMING_UHS_SDR12) || 158252983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR25) || 158352983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR50) || 158452983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR104) || 158552983382SKevin Liu (ios->timing == MMC_TIMING_UHS_DDR50))) { 158652983382SKevin Liu u16 preset; 158752983382SKevin Liu 158852983382SKevin Liu sdhci_enable_preset_value(host, true); 158952983382SKevin Liu preset = sdhci_get_preset_value(host); 159052983382SKevin Liu ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 159152983382SKevin Liu >> SDHCI_PRESET_DRV_SHIFT; 159252983382SKevin Liu } 159352983382SKevin Liu 159449c468fcSArindam Nath /* Re-enable SD Clock */ 15958213af3bSAndy Shevchenko sdhci_update_clock(host); 1596758535c4SArindam Nath } else 1597758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1598d6d50a15SArindam Nath 1599b8352260SLeandro Dorileo /* 1600b8352260SLeandro Dorileo * Some (ENE) controllers go apeshit on some ios operation, 1601b8352260SLeandro Dorileo * signalling timeout and CRC errors even on CMD0. Resetting 1602b8352260SLeandro Dorileo * it on each ios seems to solve the problem. 1603b8352260SLeandro Dorileo */ 1604b8c86fc5SPierre Ossman if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1605b8352260SLeandro Dorileo sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1606b8352260SLeandro Dorileo 16071c6a0718SPierre Ossman mmiowb(); 16081c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 16091c6a0718SPierre Ossman } 16101c6a0718SPierre Ossman 161166fd8ad5SAdrian Hunter static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 161266fd8ad5SAdrian Hunter { 161366fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 161466fd8ad5SAdrian Hunter 161566fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 161666fd8ad5SAdrian Hunter sdhci_do_set_ios(host, ios); 161766fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 161866fd8ad5SAdrian Hunter } 161966fd8ad5SAdrian Hunter 162094144a46SKevin Liu static int sdhci_do_get_cd(struct sdhci_host *host) 162194144a46SKevin Liu { 162294144a46SKevin Liu int gpio_cd = mmc_gpio_get_cd(host->mmc); 162394144a46SKevin Liu 162494144a46SKevin Liu if (host->flags & SDHCI_DEVICE_DEAD) 162594144a46SKevin Liu return 0; 162694144a46SKevin Liu 162794144a46SKevin Liu /* If polling/nonremovable, assume that the card is always present. */ 162894144a46SKevin Liu if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 162994144a46SKevin Liu (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 163094144a46SKevin Liu return 1; 163194144a46SKevin Liu 163294144a46SKevin Liu /* Try slot gpio detect */ 163394144a46SKevin Liu if (!IS_ERR_VALUE(gpio_cd)) 163494144a46SKevin Liu return !!gpio_cd; 163594144a46SKevin Liu 163694144a46SKevin Liu /* Host native card detect */ 163794144a46SKevin Liu return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 163894144a46SKevin Liu } 163994144a46SKevin Liu 164094144a46SKevin Liu static int sdhci_get_cd(struct mmc_host *mmc) 164194144a46SKevin Liu { 164294144a46SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 164394144a46SKevin Liu int ret; 164494144a46SKevin Liu 164594144a46SKevin Liu sdhci_runtime_pm_get(host); 164694144a46SKevin Liu ret = sdhci_do_get_cd(host); 164794144a46SKevin Liu sdhci_runtime_pm_put(host); 164894144a46SKevin Liu return ret; 164994144a46SKevin Liu } 165094144a46SKevin Liu 165166fd8ad5SAdrian Hunter static int sdhci_check_ro(struct sdhci_host *host) 16521c6a0718SPierre Ossman { 16531c6a0718SPierre Ossman unsigned long flags; 16542dfb579cSWolfram Sang int is_readonly; 16551c6a0718SPierre Ossman 16561c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 16571c6a0718SPierre Ossman 16581e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 16592dfb579cSWolfram Sang is_readonly = 0; 16602dfb579cSWolfram Sang else if (host->ops->get_ro) 16612dfb579cSWolfram Sang is_readonly = host->ops->get_ro(host); 16621e72859eSPierre Ossman else 16632dfb579cSWolfram Sang is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 16642dfb579cSWolfram Sang & SDHCI_WRITE_PROTECT); 16651c6a0718SPierre Ossman 16661c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 16671c6a0718SPierre Ossman 16682dfb579cSWolfram Sang /* This quirk needs to be replaced by a callback-function later */ 16692dfb579cSWolfram Sang return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 16702dfb579cSWolfram Sang !is_readonly : is_readonly; 16711c6a0718SPierre Ossman } 16721c6a0718SPierre Ossman 167382b0e23aSTakashi Iwai #define SAMPLE_COUNT 5 167482b0e23aSTakashi Iwai 167566fd8ad5SAdrian Hunter static int sdhci_do_get_ro(struct sdhci_host *host) 167682b0e23aSTakashi Iwai { 167782b0e23aSTakashi Iwai int i, ro_count; 167882b0e23aSTakashi Iwai 167982b0e23aSTakashi Iwai if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 168066fd8ad5SAdrian Hunter return sdhci_check_ro(host); 168182b0e23aSTakashi Iwai 168282b0e23aSTakashi Iwai ro_count = 0; 168382b0e23aSTakashi Iwai for (i = 0; i < SAMPLE_COUNT; i++) { 168466fd8ad5SAdrian Hunter if (sdhci_check_ro(host)) { 168582b0e23aSTakashi Iwai if (++ro_count > SAMPLE_COUNT / 2) 168682b0e23aSTakashi Iwai return 1; 168782b0e23aSTakashi Iwai } 168882b0e23aSTakashi Iwai msleep(30); 168982b0e23aSTakashi Iwai } 169082b0e23aSTakashi Iwai return 0; 169182b0e23aSTakashi Iwai } 169282b0e23aSTakashi Iwai 169320758b66SAdrian Hunter static void sdhci_hw_reset(struct mmc_host *mmc) 169420758b66SAdrian Hunter { 169520758b66SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 169620758b66SAdrian Hunter 169720758b66SAdrian Hunter if (host->ops && host->ops->hw_reset) 169820758b66SAdrian Hunter host->ops->hw_reset(host); 169920758b66SAdrian Hunter } 170020758b66SAdrian Hunter 170166fd8ad5SAdrian Hunter static int sdhci_get_ro(struct mmc_host *mmc) 1702f75979b7SPierre Ossman { 170366fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 170466fd8ad5SAdrian Hunter int ret; 1705f75979b7SPierre Ossman 170666fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 170766fd8ad5SAdrian Hunter ret = sdhci_do_get_ro(host); 170866fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 170966fd8ad5SAdrian Hunter return ret; 171066fd8ad5SAdrian Hunter } 1711f75979b7SPierre Ossman 171266fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 171366fd8ad5SAdrian Hunter { 171466fd8ad5SAdrian Hunter /* SDIO IRQ will be enabled as appropriate in runtime resume */ 1715ef104333SRussell King if (!(host->flags & SDHCI_DEVICE_DEAD) || host->runtime_suspended) { 171666fd8ad5SAdrian Hunter if (enable) 17177260cf5eSAnton Vorontsov sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 17187260cf5eSAnton Vorontsov else 17197260cf5eSAnton Vorontsov sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 1720f75979b7SPierre Ossman mmiowb(); 172166fd8ad5SAdrian Hunter } 1722ef104333SRussell King } 1723f75979b7SPierre Ossman 172466fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 172566fd8ad5SAdrian Hunter { 172666fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 172766fd8ad5SAdrian Hunter unsigned long flags; 172866fd8ad5SAdrian Hunter 1729ef104333SRussell King sdhci_runtime_pm_get(host); 1730ef104333SRussell King 173166fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 1732ef104333SRussell King if (enable) 1733ef104333SRussell King host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1734ef104333SRussell King else 1735ef104333SRussell King host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1736ef104333SRussell King 173766fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, enable); 1738f75979b7SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 1739ef104333SRussell King 1740ef104333SRussell King sdhci_runtime_pm_put(host); 1741f75979b7SPierre Ossman } 1742f75979b7SPierre Ossman 174320b92a30SKevin Liu static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 174421f5998fSFabio Estevam struct mmc_ios *ios) 1745f2119df6SArindam Nath { 174620b92a30SKevin Liu u16 ctrl; 17476231f3deSPhilip Rakity int ret; 1748f2119df6SArindam Nath 174920b92a30SKevin Liu /* 175020b92a30SKevin Liu * Signal Voltage Switching is only applicable for Host Controllers 175120b92a30SKevin Liu * v3.00 and above. 175220b92a30SKevin Liu */ 175320b92a30SKevin Liu if (host->version < SDHCI_SPEC_300) 175420b92a30SKevin Liu return 0; 175520b92a30SKevin Liu 175620b92a30SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 175720b92a30SKevin Liu 175821f5998fSFabio Estevam switch (ios->signal_voltage) { 175920b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_330: 1760f2119df6SArindam Nath /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1761f2119df6SArindam Nath ctrl &= ~SDHCI_CTRL_VDD_180; 1762f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1763f2119df6SArindam Nath 17646231f3deSPhilip Rakity if (host->vqmmc) { 1765cec2e216SKevin Liu ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 17666231f3deSPhilip Rakity if (ret) { 17676231f3deSPhilip Rakity pr_warning("%s: Switching to 3.3V signalling voltage " 17686231f3deSPhilip Rakity " failed\n", mmc_hostname(host->mmc)); 17696231f3deSPhilip Rakity return -EIO; 17706231f3deSPhilip Rakity } 17716231f3deSPhilip Rakity } 1772f2119df6SArindam Nath /* Wait for 5ms */ 1773f2119df6SArindam Nath usleep_range(5000, 5500); 1774f2119df6SArindam Nath 1775f2119df6SArindam Nath /* 3.3V regulator output should be stable within 5 ms */ 1776f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1777f2119df6SArindam Nath if (!(ctrl & SDHCI_CTRL_VDD_180)) 1778f2119df6SArindam Nath return 0; 17796231f3deSPhilip Rakity 17806231f3deSPhilip Rakity pr_warning("%s: 3.3V regulator output did not became stable\n", 17816231f3deSPhilip Rakity mmc_hostname(host->mmc)); 17826231f3deSPhilip Rakity 178320b92a30SKevin Liu return -EAGAIN; 178420b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_180: 178520b92a30SKevin Liu if (host->vqmmc) { 178620b92a30SKevin Liu ret = regulator_set_voltage(host->vqmmc, 178720b92a30SKevin Liu 1700000, 1950000); 178820b92a30SKevin Liu if (ret) { 178920b92a30SKevin Liu pr_warning("%s: Switching to 1.8V signalling voltage " 179020b92a30SKevin Liu " failed\n", mmc_hostname(host->mmc)); 1791f2119df6SArindam Nath return -EIO; 1792f2119df6SArindam Nath } 179320b92a30SKevin Liu } 17946231f3deSPhilip Rakity 1795f2119df6SArindam Nath /* 1796f2119df6SArindam Nath * Enable 1.8V Signal Enable in the Host Control2 1797f2119df6SArindam Nath * register 1798f2119df6SArindam Nath */ 1799f2119df6SArindam Nath ctrl |= SDHCI_CTRL_VDD_180; 1800f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1801f2119df6SArindam Nath 1802f2119df6SArindam Nath /* Wait for 5ms */ 1803f2119df6SArindam Nath usleep_range(5000, 5500); 1804f2119df6SArindam Nath 180520b92a30SKevin Liu /* 1.8V regulator output should be stable within 5 ms */ 1806f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 180720b92a30SKevin Liu if (ctrl & SDHCI_CTRL_VDD_180) 1808f2119df6SArindam Nath return 0; 1809f2119df6SArindam Nath 181020b92a30SKevin Liu pr_warning("%s: 1.8V regulator output did not became stable\n", 181120b92a30SKevin Liu mmc_hostname(host->mmc)); 18126231f3deSPhilip Rakity 1813f2119df6SArindam Nath return -EAGAIN; 181420b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_120: 181520b92a30SKevin Liu if (host->vqmmc) { 181620b92a30SKevin Liu ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); 181720b92a30SKevin Liu if (ret) { 181820b92a30SKevin Liu pr_warning("%s: Switching to 1.2V signalling voltage " 181920b92a30SKevin Liu " failed\n", mmc_hostname(host->mmc)); 182020b92a30SKevin Liu return -EIO; 18216231f3deSPhilip Rakity } 182220b92a30SKevin Liu } 18236231f3deSPhilip Rakity return 0; 182420b92a30SKevin Liu default: 1825f2119df6SArindam Nath /* No signal voltage switch required */ 1826f2119df6SArindam Nath return 0; 1827f2119df6SArindam Nath } 182820b92a30SKevin Liu } 1829f2119df6SArindam Nath 183066fd8ad5SAdrian Hunter static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 183121f5998fSFabio Estevam struct mmc_ios *ios) 183266fd8ad5SAdrian Hunter { 183366fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 183466fd8ad5SAdrian Hunter int err; 183566fd8ad5SAdrian Hunter 183666fd8ad5SAdrian Hunter if (host->version < SDHCI_SPEC_300) 183766fd8ad5SAdrian Hunter return 0; 183866fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 183921f5998fSFabio Estevam err = sdhci_do_start_signal_voltage_switch(host, ios); 184066fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 184166fd8ad5SAdrian Hunter return err; 184266fd8ad5SAdrian Hunter } 184366fd8ad5SAdrian Hunter 184420b92a30SKevin Liu static int sdhci_card_busy(struct mmc_host *mmc) 184520b92a30SKevin Liu { 184620b92a30SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 184720b92a30SKevin Liu u32 present_state; 184820b92a30SKevin Liu 184920b92a30SKevin Liu sdhci_runtime_pm_get(host); 185020b92a30SKevin Liu /* Check whether DAT[3:0] is 0000 */ 185120b92a30SKevin Liu present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 185220b92a30SKevin Liu sdhci_runtime_pm_put(host); 185320b92a30SKevin Liu 185420b92a30SKevin Liu return !(present_state & SDHCI_DATA_LVL_MASK); 185520b92a30SKevin Liu } 185620b92a30SKevin Liu 1857069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1858b513ea25SArindam Nath { 1859b513ea25SArindam Nath struct sdhci_host *host; 1860b513ea25SArindam Nath u16 ctrl; 1861b513ea25SArindam Nath u32 ier; 1862b513ea25SArindam Nath int tuning_loop_counter = MAX_TUNING_LOOP; 1863b513ea25SArindam Nath unsigned long timeout; 1864b513ea25SArindam Nath int err = 0; 1865069c9f14SGirish K S bool requires_tuning_nonuhs = false; 18662b35bd83SAisheng Dong unsigned long flags; 1867b513ea25SArindam Nath 1868b513ea25SArindam Nath host = mmc_priv(mmc); 1869b513ea25SArindam Nath 187066fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 18712b35bd83SAisheng Dong spin_lock_irqsave(&host->lock, flags); 1872b513ea25SArindam Nath 1873b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1874b513ea25SArindam Nath 1875b513ea25SArindam Nath /* 1876069c9f14SGirish K S * The Host Controller needs tuning only in case of SDR104 mode 1877069c9f14SGirish K S * and for SDR50 mode when Use Tuning for SDR50 is set in the 1878b513ea25SArindam Nath * Capabilities register. 1879069c9f14SGirish K S * If the Host Controller supports the HS200 mode then the 1880069c9f14SGirish K S * tuning function has to be executed. 1881b513ea25SArindam Nath */ 1882069c9f14SGirish K S if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1883069c9f14SGirish K S (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1884156e14b1SGiuseppe CAVALLARO host->flags & SDHCI_SDR104_NEEDS_TUNING)) 1885069c9f14SGirish K S requires_tuning_nonuhs = true; 1886069c9f14SGirish K S 1887b513ea25SArindam Nath if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1888069c9f14SGirish K S requires_tuning_nonuhs) 1889b513ea25SArindam Nath ctrl |= SDHCI_CTRL_EXEC_TUNING; 1890b513ea25SArindam Nath else { 18912b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 189266fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 1893b513ea25SArindam Nath return 0; 1894b513ea25SArindam Nath } 1895b513ea25SArindam Nath 189645251812SDong Aisheng if (host->ops->platform_execute_tuning) { 18972b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 189845251812SDong Aisheng err = host->ops->platform_execute_tuning(host, opcode); 189945251812SDong Aisheng sdhci_runtime_pm_put(host); 190045251812SDong Aisheng return err; 190145251812SDong Aisheng } 190245251812SDong Aisheng 1903b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1904b513ea25SArindam Nath 1905b513ea25SArindam Nath /* 1906b513ea25SArindam Nath * As per the Host Controller spec v3.00, tuning command 1907b513ea25SArindam Nath * generates Buffer Read Ready interrupt, so enable that. 1908b513ea25SArindam Nath * 1909b513ea25SArindam Nath * Note: The spec clearly says that when tuning sequence 1910b513ea25SArindam Nath * is being performed, the controller does not generate 1911b513ea25SArindam Nath * interrupts other than Buffer Read Ready interrupt. But 1912b513ea25SArindam Nath * to make sure we don't hit a controller bug, we _only_ 1913b513ea25SArindam Nath * enable Buffer Read Ready interrupt here. 1914b513ea25SArindam Nath */ 1915b513ea25SArindam Nath ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1916b513ea25SArindam Nath sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1917b513ea25SArindam Nath 1918b513ea25SArindam Nath /* 1919b513ea25SArindam Nath * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1920b513ea25SArindam Nath * of loops reaches 40 times or a timeout of 150ms occurs. 1921b513ea25SArindam Nath */ 1922b513ea25SArindam Nath timeout = 150; 1923b513ea25SArindam Nath do { 1924b513ea25SArindam Nath struct mmc_command cmd = {0}; 192566fd8ad5SAdrian Hunter struct mmc_request mrq = {NULL}; 1926b513ea25SArindam Nath 1927b513ea25SArindam Nath if (!tuning_loop_counter && !timeout) 1928b513ea25SArindam Nath break; 1929b513ea25SArindam Nath 1930069c9f14SGirish K S cmd.opcode = opcode; 1931b513ea25SArindam Nath cmd.arg = 0; 1932b513ea25SArindam Nath cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1933b513ea25SArindam Nath cmd.retries = 0; 1934b513ea25SArindam Nath cmd.data = NULL; 1935b513ea25SArindam Nath cmd.error = 0; 1936b513ea25SArindam Nath 1937b513ea25SArindam Nath mrq.cmd = &cmd; 1938b513ea25SArindam Nath host->mrq = &mrq; 1939b513ea25SArindam Nath 1940b513ea25SArindam Nath /* 1941b513ea25SArindam Nath * In response to CMD19, the card sends 64 bytes of tuning 1942b513ea25SArindam Nath * block to the Host Controller. So we set the block size 1943b513ea25SArindam Nath * to 64 here. 1944b513ea25SArindam Nath */ 1945069c9f14SGirish K S if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1946069c9f14SGirish K S if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1947069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1948069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1949069c9f14SGirish K S else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1950069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1951069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1952069c9f14SGirish K S } else { 1953069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1954069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1955069c9f14SGirish K S } 1956b513ea25SArindam Nath 1957b513ea25SArindam Nath /* 1958b513ea25SArindam Nath * The tuning block is sent by the card to the host controller. 1959b513ea25SArindam Nath * So we set the TRNS_READ bit in the Transfer Mode register. 1960b513ea25SArindam Nath * This also takes care of setting DMA Enable and Multi Block 1961b513ea25SArindam Nath * Select in the same register to 0. 1962b513ea25SArindam Nath */ 1963b513ea25SArindam Nath sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1964b513ea25SArindam Nath 1965b513ea25SArindam Nath sdhci_send_command(host, &cmd); 1966b513ea25SArindam Nath 1967b513ea25SArindam Nath host->cmd = NULL; 1968b513ea25SArindam Nath host->mrq = NULL; 1969b513ea25SArindam Nath 19702b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 1971b513ea25SArindam Nath /* Wait for Buffer Read Ready interrupt */ 1972b513ea25SArindam Nath wait_event_interruptible_timeout(host->buf_ready_int, 1973b513ea25SArindam Nath (host->tuning_done == 1), 1974b513ea25SArindam Nath msecs_to_jiffies(50)); 19752b35bd83SAisheng Dong spin_lock_irqsave(&host->lock, flags); 1976b513ea25SArindam Nath 1977b513ea25SArindam Nath if (!host->tuning_done) { 1978a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Timeout waiting for " 1979b513ea25SArindam Nath "Buffer Read Ready interrupt during tuning " 1980b513ea25SArindam Nath "procedure, falling back to fixed sampling " 1981b513ea25SArindam Nath "clock\n"); 1982b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1983b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1984b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1985b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1986b513ea25SArindam Nath 1987b513ea25SArindam Nath err = -EIO; 1988b513ea25SArindam Nath goto out; 1989b513ea25SArindam Nath } 1990b513ea25SArindam Nath 1991b513ea25SArindam Nath host->tuning_done = 0; 1992b513ea25SArindam Nath 1993b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1994b513ea25SArindam Nath tuning_loop_counter--; 1995b513ea25SArindam Nath timeout--; 1996197160d5SNick Sanders 1997197160d5SNick Sanders /* eMMC spec does not require a delay between tuning cycles */ 1998197160d5SNick Sanders if (opcode == MMC_SEND_TUNING_BLOCK) 1999b513ea25SArindam Nath mdelay(1); 2000b513ea25SArindam Nath } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 2001b513ea25SArindam Nath 2002b513ea25SArindam Nath /* 2003b513ea25SArindam Nath * The Host Driver has exhausted the maximum number of loops allowed, 2004b513ea25SArindam Nath * so use fixed sampling frequency. 2005b513ea25SArindam Nath */ 2006b513ea25SArindam Nath if (!tuning_loop_counter || !timeout) { 2007b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2008b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2009114f2bf6SDong Aisheng err = -EIO; 2010b513ea25SArindam Nath } else { 2011b513ea25SArindam Nath if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 2012a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Tuning procedure" 2013b513ea25SArindam Nath " failed, falling back to fixed sampling" 2014b513ea25SArindam Nath " clock\n"); 2015b513ea25SArindam Nath err = -EIO; 2016b513ea25SArindam Nath } 2017b513ea25SArindam Nath } 2018b513ea25SArindam Nath 2019b513ea25SArindam Nath out: 2020cf2b5eeaSArindam Nath /* 2021cf2b5eeaSArindam Nath * If this is the very first time we are here, we start the retuning 2022cf2b5eeaSArindam Nath * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 2023cf2b5eeaSArindam Nath * flag won't be set, we check this condition before actually starting 2024cf2b5eeaSArindam Nath * the timer. 2025cf2b5eeaSArindam Nath */ 2026cf2b5eeaSArindam Nath if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 2027cf2b5eeaSArindam Nath (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 2028973905feSAaron Lu host->flags |= SDHCI_USING_RETUNING_TIMER; 2029cf2b5eeaSArindam Nath mod_timer(&host->tuning_timer, jiffies + 2030cf2b5eeaSArindam Nath host->tuning_count * HZ); 2031cf2b5eeaSArindam Nath /* Tuning mode 1 limits the maximum data length to 4MB */ 2032cf2b5eeaSArindam Nath mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 20332bc02485SArend van Spriel } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2034cf2b5eeaSArindam Nath host->flags &= ~SDHCI_NEEDS_RETUNING; 2035cf2b5eeaSArindam Nath /* Reload the new initial value for timer */ 2036cf2b5eeaSArindam Nath mod_timer(&host->tuning_timer, jiffies + 2037cf2b5eeaSArindam Nath host->tuning_count * HZ); 2038cf2b5eeaSArindam Nath } 2039cf2b5eeaSArindam Nath 2040cf2b5eeaSArindam Nath /* 2041cf2b5eeaSArindam Nath * In case tuning fails, host controllers which support re-tuning can 2042cf2b5eeaSArindam Nath * try tuning again at a later time, when the re-tuning timer expires. 2043cf2b5eeaSArindam Nath * So for these controllers, we return 0. Since there might be other 2044cf2b5eeaSArindam Nath * controllers who do not have this capability, we return error for 2045973905feSAaron Lu * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2046973905feSAaron Lu * a retuning timer to do the retuning for the card. 2047cf2b5eeaSArindam Nath */ 2048973905feSAaron Lu if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2049cf2b5eeaSArindam Nath err = 0; 2050cf2b5eeaSArindam Nath 2051b513ea25SArindam Nath sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 20522b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 205366fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 2054b513ea25SArindam Nath 2055b513ea25SArindam Nath return err; 2056b513ea25SArindam Nath } 2057b513ea25SArindam Nath 205852983382SKevin Liu 205952983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 20604d55c5a1SArindam Nath { 20614d55c5a1SArindam Nath u16 ctrl; 20624d55c5a1SArindam Nath 20634d55c5a1SArindam Nath /* Host Controller v3.00 defines preset value registers */ 20644d55c5a1SArindam Nath if (host->version < SDHCI_SPEC_300) 20654d55c5a1SArindam Nath return; 20664d55c5a1SArindam Nath 20674d55c5a1SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 20684d55c5a1SArindam Nath 20694d55c5a1SArindam Nath /* 20704d55c5a1SArindam Nath * We only enable or disable Preset Value if they are not already 20714d55c5a1SArindam Nath * enabled or disabled respectively. Otherwise, we bail out. 20724d55c5a1SArindam Nath */ 20734d55c5a1SArindam Nath if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 20744d55c5a1SArindam Nath ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 20754d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 207666fd8ad5SAdrian Hunter host->flags |= SDHCI_PV_ENABLED; 20774d55c5a1SArindam Nath } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 20784d55c5a1SArindam Nath ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 20794d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 208066fd8ad5SAdrian Hunter host->flags &= ~SDHCI_PV_ENABLED; 20814d55c5a1SArindam Nath } 208266fd8ad5SAdrian Hunter } 208366fd8ad5SAdrian Hunter 208471e69211SGuennadi Liakhovetski static void sdhci_card_event(struct mmc_host *mmc) 20851c6a0718SPierre Ossman { 208671e69211SGuennadi Liakhovetski struct sdhci_host *host = mmc_priv(mmc); 20871c6a0718SPierre Ossman unsigned long flags; 20881c6a0718SPierre Ossman 2089722e1280SChristian Daudt /* First check if client has provided their own card event */ 2090722e1280SChristian Daudt if (host->ops->card_event) 2091722e1280SChristian Daudt host->ops->card_event(host); 2092722e1280SChristian Daudt 20931c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 20941c6a0718SPierre Ossman 209566fd8ad5SAdrian Hunter /* Check host->mrq first in case we are runtime suspended */ 20969668d765SShawn Guo if (host->mrq && !sdhci_do_get_cd(host)) { 2097a3c76eb9SGirish K S pr_err("%s: Card removed during transfer!\n", 20981c6a0718SPierre Ossman mmc_hostname(host->mmc)); 2099a3c76eb9SGirish K S pr_err("%s: Resetting controller.\n", 21001c6a0718SPierre Ossman mmc_hostname(host->mmc)); 21011c6a0718SPierre Ossman 21021c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_CMD); 21031c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_DATA); 21041c6a0718SPierre Ossman 210517b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 21061c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 21071c6a0718SPierre Ossman } 21081c6a0718SPierre Ossman 21091c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 211071e69211SGuennadi Liakhovetski } 211171e69211SGuennadi Liakhovetski 211271e69211SGuennadi Liakhovetski static const struct mmc_host_ops sdhci_ops = { 211371e69211SGuennadi Liakhovetski .request = sdhci_request, 211471e69211SGuennadi Liakhovetski .set_ios = sdhci_set_ios, 211594144a46SKevin Liu .get_cd = sdhci_get_cd, 211671e69211SGuennadi Liakhovetski .get_ro = sdhci_get_ro, 211771e69211SGuennadi Liakhovetski .hw_reset = sdhci_hw_reset, 211871e69211SGuennadi Liakhovetski .enable_sdio_irq = sdhci_enable_sdio_irq, 211971e69211SGuennadi Liakhovetski .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 212071e69211SGuennadi Liakhovetski .execute_tuning = sdhci_execute_tuning, 212171e69211SGuennadi Liakhovetski .card_event = sdhci_card_event, 212220b92a30SKevin Liu .card_busy = sdhci_card_busy, 212371e69211SGuennadi Liakhovetski }; 212471e69211SGuennadi Liakhovetski 212571e69211SGuennadi Liakhovetski /*****************************************************************************\ 212671e69211SGuennadi Liakhovetski * * 212771e69211SGuennadi Liakhovetski * Tasklets * 212871e69211SGuennadi Liakhovetski * * 212971e69211SGuennadi Liakhovetski \*****************************************************************************/ 213071e69211SGuennadi Liakhovetski 213171e69211SGuennadi Liakhovetski static void sdhci_tasklet_card(unsigned long param) 213271e69211SGuennadi Liakhovetski { 213371e69211SGuennadi Liakhovetski struct sdhci_host *host = (struct sdhci_host*)param; 213471e69211SGuennadi Liakhovetski 213571e69211SGuennadi Liakhovetski sdhci_card_event(host->mmc); 21361c6a0718SPierre Ossman 213704cf585dSPierre Ossman mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 21381c6a0718SPierre Ossman } 21391c6a0718SPierre Ossman 21401c6a0718SPierre Ossman static void sdhci_tasklet_finish(unsigned long param) 21411c6a0718SPierre Ossman { 21421c6a0718SPierre Ossman struct sdhci_host *host; 21431c6a0718SPierre Ossman unsigned long flags; 21441c6a0718SPierre Ossman struct mmc_request *mrq; 21451c6a0718SPierre Ossman 21461c6a0718SPierre Ossman host = (struct sdhci_host*)param; 21471c6a0718SPierre Ossman 214866fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 214966fd8ad5SAdrian Hunter 21500c9c99a7SChris Ball /* 21510c9c99a7SChris Ball * If this tasklet gets rescheduled while running, it will 21520c9c99a7SChris Ball * be run again afterwards but without any active request. 21530c9c99a7SChris Ball */ 215466fd8ad5SAdrian Hunter if (!host->mrq) { 215566fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 21560c9c99a7SChris Ball return; 215766fd8ad5SAdrian Hunter } 21581c6a0718SPierre Ossman 21591c6a0718SPierre Ossman del_timer(&host->timer); 21601c6a0718SPierre Ossman 21611c6a0718SPierre Ossman mrq = host->mrq; 21621c6a0718SPierre Ossman 21631c6a0718SPierre Ossman /* 21641c6a0718SPierre Ossman * The controller needs a reset of internal state machines 21651c6a0718SPierre Ossman * upon error conditions. 21661c6a0718SPierre Ossman */ 21671e72859eSPierre Ossman if (!(host->flags & SDHCI_DEVICE_DEAD) && 2168b7b4d342SBen Dooks ((mrq->cmd && mrq->cmd->error) || 216917b0429dSPierre Ossman (mrq->data && (mrq->data->error || 217084c46a53SPierre Ossman (mrq->data->stop && mrq->data->stop->error))) || 21711e72859eSPierre Ossman (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 21721c6a0718SPierre Ossman 21731c6a0718SPierre Ossman /* Some controllers need this kick or reset won't work here */ 21748213af3bSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 21751c6a0718SPierre Ossman /* This is to force an update */ 21768213af3bSAndy Shevchenko sdhci_update_clock(host); 21771c6a0718SPierre Ossman 21781c6a0718SPierre Ossman /* Spec says we should do both at the same time, but Ricoh 21791c6a0718SPierre Ossman controllers do not like that. */ 21801c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_CMD); 21811c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_DATA); 21821c6a0718SPierre Ossman } 21831c6a0718SPierre Ossman 21841c6a0718SPierre Ossman host->mrq = NULL; 21851c6a0718SPierre Ossman host->cmd = NULL; 21861c6a0718SPierre Ossman host->data = NULL; 21871c6a0718SPierre Ossman 2188f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 21891c6a0718SPierre Ossman sdhci_deactivate_led(host); 21902f730fecSPierre Ossman #endif 21911c6a0718SPierre Ossman 21921c6a0718SPierre Ossman mmiowb(); 21931c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 21941c6a0718SPierre Ossman 21951c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 219666fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 21971c6a0718SPierre Ossman } 21981c6a0718SPierre Ossman 21991c6a0718SPierre Ossman static void sdhci_timeout_timer(unsigned long data) 22001c6a0718SPierre Ossman { 22011c6a0718SPierre Ossman struct sdhci_host *host; 22021c6a0718SPierre Ossman unsigned long flags; 22031c6a0718SPierre Ossman 22041c6a0718SPierre Ossman host = (struct sdhci_host*)data; 22051c6a0718SPierre Ossman 22061c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 22071c6a0718SPierre Ossman 22081c6a0718SPierre Ossman if (host->mrq) { 2209a3c76eb9SGirish K S pr_err("%s: Timeout waiting for hardware " 22101c6a0718SPierre Ossman "interrupt.\n", mmc_hostname(host->mmc)); 22111c6a0718SPierre Ossman sdhci_dumpregs(host); 22121c6a0718SPierre Ossman 22131c6a0718SPierre Ossman if (host->data) { 221417b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 22151c6a0718SPierre Ossman sdhci_finish_data(host); 22161c6a0718SPierre Ossman } else { 22171c6a0718SPierre Ossman if (host->cmd) 221817b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 22191c6a0718SPierre Ossman else 222017b0429dSPierre Ossman host->mrq->cmd->error = -ETIMEDOUT; 22211c6a0718SPierre Ossman 22221c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 22231c6a0718SPierre Ossman } 22241c6a0718SPierre Ossman } 22251c6a0718SPierre Ossman 22261c6a0718SPierre Ossman mmiowb(); 22271c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 22281c6a0718SPierre Ossman } 22291c6a0718SPierre Ossman 2230cf2b5eeaSArindam Nath static void sdhci_tuning_timer(unsigned long data) 2231cf2b5eeaSArindam Nath { 2232cf2b5eeaSArindam Nath struct sdhci_host *host; 2233cf2b5eeaSArindam Nath unsigned long flags; 2234cf2b5eeaSArindam Nath 2235cf2b5eeaSArindam Nath host = (struct sdhci_host *)data; 2236cf2b5eeaSArindam Nath 2237cf2b5eeaSArindam Nath spin_lock_irqsave(&host->lock, flags); 2238cf2b5eeaSArindam Nath 2239cf2b5eeaSArindam Nath host->flags |= SDHCI_NEEDS_RETUNING; 2240cf2b5eeaSArindam Nath 2241cf2b5eeaSArindam Nath spin_unlock_irqrestore(&host->lock, flags); 2242cf2b5eeaSArindam Nath } 2243cf2b5eeaSArindam Nath 22441c6a0718SPierre Ossman /*****************************************************************************\ 22451c6a0718SPierre Ossman * * 22461c6a0718SPierre Ossman * Interrupt handling * 22471c6a0718SPierre Ossman * * 22481c6a0718SPierre Ossman \*****************************************************************************/ 22491c6a0718SPierre Ossman 22501c6a0718SPierre Ossman static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 22511c6a0718SPierre Ossman { 22521c6a0718SPierre Ossman BUG_ON(intmask == 0); 22531c6a0718SPierre Ossman 22541c6a0718SPierre Ossman if (!host->cmd) { 2255a3c76eb9SGirish K S pr_err("%s: Got command interrupt 0x%08x even " 2256b67ac3f3SPierre Ossman "though no command operation was in progress.\n", 2257b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 22581c6a0718SPierre Ossman sdhci_dumpregs(host); 22591c6a0718SPierre Ossman return; 22601c6a0718SPierre Ossman } 22611c6a0718SPierre Ossman 22621c6a0718SPierre Ossman if (intmask & SDHCI_INT_TIMEOUT) 226317b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 226417b0429dSPierre Ossman else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 226517b0429dSPierre Ossman SDHCI_INT_INDEX)) 226617b0429dSPierre Ossman host->cmd->error = -EILSEQ; 22671c6a0718SPierre Ossman 2268e809517fSPierre Ossman if (host->cmd->error) { 22691c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 2270e809517fSPierre Ossman return; 2271e809517fSPierre Ossman } 2272e809517fSPierre Ossman 2273e809517fSPierre Ossman /* 2274e809517fSPierre Ossman * The host can send and interrupt when the busy state has 2275e809517fSPierre Ossman * ended, allowing us to wait without wasting CPU cycles. 2276e809517fSPierre Ossman * Unfortunately this is overloaded on the "data complete" 2277e809517fSPierre Ossman * interrupt, so we need to take some care when handling 2278e809517fSPierre Ossman * it. 2279e809517fSPierre Ossman * 2280e809517fSPierre Ossman * Note: The 1.0 specification is a bit ambiguous about this 2281e809517fSPierre Ossman * feature so there might be some problems with older 2282e809517fSPierre Ossman * controllers. 2283e809517fSPierre Ossman */ 2284e809517fSPierre Ossman if (host->cmd->flags & MMC_RSP_BUSY) { 2285e809517fSPierre Ossman if (host->cmd->data) 2286e809517fSPierre Ossman DBG("Cannot wait for busy signal when also " 2287e809517fSPierre Ossman "doing a data transfer"); 2288f945405cSBen Dooks else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2289e809517fSPierre Ossman return; 2290f945405cSBen Dooks 2291f945405cSBen Dooks /* The controller does not support the end-of-busy IRQ, 2292f945405cSBen Dooks * fall through and take the SDHCI_INT_RESPONSE */ 2293e809517fSPierre Ossman } 2294e809517fSPierre Ossman 2295e809517fSPierre Ossman if (intmask & SDHCI_INT_RESPONSE) 229643b58b36SPierre Ossman sdhci_finish_command(host); 22971c6a0718SPierre Ossman } 22981c6a0718SPierre Ossman 22990957c333SGeorge G. Davis #ifdef CONFIG_MMC_DEBUG 23006882a8c0SBen Dooks static void sdhci_show_adma_error(struct sdhci_host *host) 23016882a8c0SBen Dooks { 23026882a8c0SBen Dooks const char *name = mmc_hostname(host->mmc); 23036882a8c0SBen Dooks u8 *desc = host->adma_desc; 23046882a8c0SBen Dooks __le32 *dma; 23056882a8c0SBen Dooks __le16 *len; 23066882a8c0SBen Dooks u8 attr; 23076882a8c0SBen Dooks 23086882a8c0SBen Dooks sdhci_dumpregs(host); 23096882a8c0SBen Dooks 23106882a8c0SBen Dooks while (true) { 23116882a8c0SBen Dooks dma = (__le32 *)(desc + 4); 23126882a8c0SBen Dooks len = (__le16 *)(desc + 2); 23136882a8c0SBen Dooks attr = *desc; 23146882a8c0SBen Dooks 23156882a8c0SBen Dooks DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 23166882a8c0SBen Dooks name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 23176882a8c0SBen Dooks 23186882a8c0SBen Dooks desc += 8; 23196882a8c0SBen Dooks 23206882a8c0SBen Dooks if (attr & 2) 23216882a8c0SBen Dooks break; 23226882a8c0SBen Dooks } 23236882a8c0SBen Dooks } 23246882a8c0SBen Dooks #else 23256882a8c0SBen Dooks static void sdhci_show_adma_error(struct sdhci_host *host) { } 23266882a8c0SBen Dooks #endif 23276882a8c0SBen Dooks 23281c6a0718SPierre Ossman static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 23291c6a0718SPierre Ossman { 2330069c9f14SGirish K S u32 command; 23311c6a0718SPierre Ossman BUG_ON(intmask == 0); 23321c6a0718SPierre Ossman 2333b513ea25SArindam Nath /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2334b513ea25SArindam Nath if (intmask & SDHCI_INT_DATA_AVAIL) { 2335069c9f14SGirish K S command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2336069c9f14SGirish K S if (command == MMC_SEND_TUNING_BLOCK || 2337069c9f14SGirish K S command == MMC_SEND_TUNING_BLOCK_HS200) { 2338b513ea25SArindam Nath host->tuning_done = 1; 2339b513ea25SArindam Nath wake_up(&host->buf_ready_int); 2340b513ea25SArindam Nath return; 2341b513ea25SArindam Nath } 2342b513ea25SArindam Nath } 2343b513ea25SArindam Nath 23441c6a0718SPierre Ossman if (!host->data) { 23451c6a0718SPierre Ossman /* 2346e809517fSPierre Ossman * The "data complete" interrupt is also used to 2347e809517fSPierre Ossman * indicate that a busy state has ended. See comment 2348e809517fSPierre Ossman * above in sdhci_cmd_irq(). 23491c6a0718SPierre Ossman */ 2350e809517fSPierre Ossman if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2351e809517fSPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2352e809517fSPierre Ossman sdhci_finish_command(host); 23531c6a0718SPierre Ossman return; 2354e809517fSPierre Ossman } 2355e809517fSPierre Ossman } 23561c6a0718SPierre Ossman 2357a3c76eb9SGirish K S pr_err("%s: Got data interrupt 0x%08x even " 2358b67ac3f3SPierre Ossman "though no data operation was in progress.\n", 2359b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 23601c6a0718SPierre Ossman sdhci_dumpregs(host); 23611c6a0718SPierre Ossman 23621c6a0718SPierre Ossman return; 23631c6a0718SPierre Ossman } 23641c6a0718SPierre Ossman 23651c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_TIMEOUT) 236617b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 236722113efdSAries Lee else if (intmask & SDHCI_INT_DATA_END_BIT) 236822113efdSAries Lee host->data->error = -EILSEQ; 236922113efdSAries Lee else if ((intmask & SDHCI_INT_DATA_CRC) && 237022113efdSAries Lee SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 237122113efdSAries Lee != MMC_BUS_TEST_R) 237217b0429dSPierre Ossman host->data->error = -EILSEQ; 23736882a8c0SBen Dooks else if (intmask & SDHCI_INT_ADMA_ERROR) { 2374a3c76eb9SGirish K S pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 23756882a8c0SBen Dooks sdhci_show_adma_error(host); 23762134a922SPierre Ossman host->data->error = -EIO; 2377a4071fbbSHaijun Zhang if (host->ops->adma_workaround) 2378a4071fbbSHaijun Zhang host->ops->adma_workaround(host, intmask); 23796882a8c0SBen Dooks } 23801c6a0718SPierre Ossman 238117b0429dSPierre Ossman if (host->data->error) 23821c6a0718SPierre Ossman sdhci_finish_data(host); 23831c6a0718SPierre Ossman else { 23841c6a0718SPierre Ossman if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 23851c6a0718SPierre Ossman sdhci_transfer_pio(host); 23861c6a0718SPierre Ossman 23876ba736a1SPierre Ossman /* 23886ba736a1SPierre Ossman * We currently don't do anything fancy with DMA 23896ba736a1SPierre Ossman * boundaries, but as we can't disable the feature 23906ba736a1SPierre Ossman * we need to at least restart the transfer. 2391f6a03cbfSMikko Vinni * 2392f6a03cbfSMikko Vinni * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2393f6a03cbfSMikko Vinni * should return a valid address to continue from, but as 2394f6a03cbfSMikko Vinni * some controllers are faulty, don't trust them. 23956ba736a1SPierre Ossman */ 2396f6a03cbfSMikko Vinni if (intmask & SDHCI_INT_DMA_END) { 2397f6a03cbfSMikko Vinni u32 dmastart, dmanow; 2398f6a03cbfSMikko Vinni dmastart = sg_dma_address(host->data->sg); 2399f6a03cbfSMikko Vinni dmanow = dmastart + host->data->bytes_xfered; 2400f6a03cbfSMikko Vinni /* 2401f6a03cbfSMikko Vinni * Force update to the next DMA block boundary. 2402f6a03cbfSMikko Vinni */ 2403f6a03cbfSMikko Vinni dmanow = (dmanow & 2404f6a03cbfSMikko Vinni ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2405f6a03cbfSMikko Vinni SDHCI_DEFAULT_BOUNDARY_SIZE; 2406f6a03cbfSMikko Vinni host->data->bytes_xfered = dmanow - dmastart; 2407f6a03cbfSMikko Vinni DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2408f6a03cbfSMikko Vinni " next 0x%08x\n", 2409f6a03cbfSMikko Vinni mmc_hostname(host->mmc), dmastart, 2410f6a03cbfSMikko Vinni host->data->bytes_xfered, dmanow); 2411f6a03cbfSMikko Vinni sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2412f6a03cbfSMikko Vinni } 24136ba736a1SPierre Ossman 2414e538fbe8SPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2415e538fbe8SPierre Ossman if (host->cmd) { 2416e538fbe8SPierre Ossman /* 2417e538fbe8SPierre Ossman * Data managed to finish before the 2418e538fbe8SPierre Ossman * command completed. Make sure we do 2419e538fbe8SPierre Ossman * things in the proper order. 2420e538fbe8SPierre Ossman */ 2421e538fbe8SPierre Ossman host->data_early = 1; 2422e538fbe8SPierre Ossman } else { 24231c6a0718SPierre Ossman sdhci_finish_data(host); 24241c6a0718SPierre Ossman } 24251c6a0718SPierre Ossman } 2426e538fbe8SPierre Ossman } 2427e538fbe8SPierre Ossman } 24281c6a0718SPierre Ossman 24291c6a0718SPierre Ossman static irqreturn_t sdhci_irq(int irq, void *dev_id) 24301c6a0718SPierre Ossman { 24311c6a0718SPierre Ossman irqreturn_t result; 24321c6a0718SPierre Ossman struct sdhci_host *host = dev_id; 243341005003SRussell King u32 intmask, mask, unexpected = 0; 24346379b237SAlexander Stein int cardint = 0, max_loops = 16; 24351c6a0718SPierre Ossman 24361c6a0718SPierre Ossman spin_lock(&host->lock); 24371c6a0718SPierre Ossman 243866fd8ad5SAdrian Hunter if (host->runtime_suspended) { 243966fd8ad5SAdrian Hunter spin_unlock(&host->lock); 2440655bca76SAdrian Hunter return IRQ_NONE; 244166fd8ad5SAdrian Hunter } 244266fd8ad5SAdrian Hunter 24434e4141a5SAnton Vorontsov intmask = sdhci_readl(host, SDHCI_INT_STATUS); 24441c6a0718SPierre Ossman if (!intmask || intmask == 0xffffffff) { 24451c6a0718SPierre Ossman result = IRQ_NONE; 24461c6a0718SPierre Ossman goto out; 24471c6a0718SPierre Ossman } 24481c6a0718SPierre Ossman 244941005003SRussell King do { 245041005003SRussell King /* Clear selected interrupts. */ 245141005003SRussell King mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 245241005003SRussell King SDHCI_INT_BUS_POWER); 245341005003SRussell King sdhci_writel(host, mask, SDHCI_INT_STATUS); 245441005003SRussell King 2455b69c9058SPierre Ossman DBG("*** %s got interrupt: 0x%08x\n", 2456b69c9058SPierre Ossman mmc_hostname(host->mmc), intmask); 24571c6a0718SPierre Ossman 24581c6a0718SPierre Ossman if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2459d25928d1SShawn Guo u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2460d25928d1SShawn Guo SDHCI_CARD_PRESENT; 2461d25928d1SShawn Guo 2462d25928d1SShawn Guo /* 246341005003SRussell King * There is a observation on i.mx esdhc. INSERT 246441005003SRussell King * bit will be immediately set again when it gets 246541005003SRussell King * cleared, if a card is inserted. We have to mask 246641005003SRussell King * the irq to prevent interrupt storm which will 246741005003SRussell King * freeze the system. And the REMOVE gets the 246841005003SRussell King * same situation. 2469d25928d1SShawn Guo * 247041005003SRussell King * More testing are needed here to ensure it works 247141005003SRussell King * for other platforms though. 2472d25928d1SShawn Guo */ 2473d25928d1SShawn Guo sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : 2474d25928d1SShawn Guo SDHCI_INT_CARD_REMOVE); 2475d25928d1SShawn Guo sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : 2476d25928d1SShawn Guo SDHCI_INT_CARD_INSERT); 2477d25928d1SShawn Guo 24784e4141a5SAnton Vorontsov sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 24794e4141a5SAnton Vorontsov SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 24801c6a0718SPierre Ossman tasklet_schedule(&host->card_tasklet); 24811c6a0718SPierre Ossman } 24821c6a0718SPierre Ossman 248341005003SRussell King if (intmask & SDHCI_INT_CMD_MASK) 24841c6a0718SPierre Ossman sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 24851c6a0718SPierre Ossman 248641005003SRussell King if (intmask & SDHCI_INT_DATA_MASK) 24871c6a0718SPierre Ossman sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 24881c6a0718SPierre Ossman 248941005003SRussell King if (intmask & SDHCI_INT_BUS_POWER) 2490a3c76eb9SGirish K S pr_err("%s: Card is consuming too much power!\n", 24911c6a0718SPierre Ossman mmc_hostname(host->mmc)); 24921c6a0718SPierre Ossman 2493f75979b7SPierre Ossman if (intmask & SDHCI_INT_CARD_INT) 2494f75979b7SPierre Ossman cardint = 1; 2495f75979b7SPierre Ossman 249641005003SRussell King intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 249741005003SRussell King SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 249841005003SRussell King SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 249941005003SRussell King SDHCI_INT_CARD_INT); 2500f75979b7SPierre Ossman 25011c6a0718SPierre Ossman if (intmask) { 25026379b237SAlexander Stein unexpected |= intmask; 25034e4141a5SAnton Vorontsov sdhci_writel(host, intmask, SDHCI_INT_STATUS); 25041c6a0718SPierre Ossman } 25051c6a0718SPierre Ossman 25061c6a0718SPierre Ossman result = IRQ_HANDLED; 25071c6a0718SPierre Ossman 25086379b237SAlexander Stein intmask = sdhci_readl(host, SDHCI_INT_STATUS); 25090a8fd09cSAlexey Neyman 25100a8fd09cSAlexey Neyman /* 251141005003SRussell King * If we know we'll call the driver to signal SDIO IRQ, 251241005003SRussell King * disregard further indications of Card Interrupt in 251341005003SRussell King * the status to avoid a needless loop. 25140a8fd09cSAlexey Neyman */ 25150a8fd09cSAlexey Neyman if (cardint) 25160a8fd09cSAlexey Neyman intmask &= ~SDHCI_INT_CARD_INT; 251741005003SRussell King } while (intmask && --max_loops); 25181c6a0718SPierre Ossman out: 25191c6a0718SPierre Ossman spin_unlock(&host->lock); 25201c6a0718SPierre Ossman 25216379b237SAlexander Stein if (unexpected) { 25226379b237SAlexander Stein pr_err("%s: Unexpected interrupt 0x%08x.\n", 25236379b237SAlexander Stein mmc_hostname(host->mmc), unexpected); 25246379b237SAlexander Stein sdhci_dumpregs(host); 25256379b237SAlexander Stein } 2526f75979b7SPierre Ossman /* 2527f75979b7SPierre Ossman * We have to delay this as it calls back into the driver. 2528f75979b7SPierre Ossman */ 2529f75979b7SPierre Ossman if (cardint) 2530f75979b7SPierre Ossman mmc_signal_sdio_irq(host->mmc); 2531f75979b7SPierre Ossman 25321c6a0718SPierre Ossman return result; 25331c6a0718SPierre Ossman } 25341c6a0718SPierre Ossman 25351c6a0718SPierre Ossman /*****************************************************************************\ 25361c6a0718SPierre Ossman * * 25371c6a0718SPierre Ossman * Suspend/resume * 25381c6a0718SPierre Ossman * * 25391c6a0718SPierre Ossman \*****************************************************************************/ 25401c6a0718SPierre Ossman 25411c6a0718SPierre Ossman #ifdef CONFIG_PM 2542ad080d79SKevin Liu void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2543ad080d79SKevin Liu { 2544ad080d79SKevin Liu u8 val; 2545ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2546ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2547ad080d79SKevin Liu 2548ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2549ad080d79SKevin Liu val |= mask ; 2550ad080d79SKevin Liu /* Avoid fake wake up */ 2551ad080d79SKevin Liu if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2552ad080d79SKevin Liu val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2553ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2554ad080d79SKevin Liu } 2555ad080d79SKevin Liu EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2556ad080d79SKevin Liu 2557ad080d79SKevin Liu void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2558ad080d79SKevin Liu { 2559ad080d79SKevin Liu u8 val; 2560ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2561ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2562ad080d79SKevin Liu 2563ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2564ad080d79SKevin Liu val &= ~mask; 2565ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2566ad080d79SKevin Liu } 2567ad080d79SKevin Liu EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); 25681c6a0718SPierre Ossman 256929495aa0SManuel Lauss int sdhci_suspend_host(struct sdhci_host *host) 25701c6a0718SPierre Ossman { 2571a1b13b4eSChris Ball if (host->ops->platform_suspend) 2572a1b13b4eSChris Ball host->ops->platform_suspend(host); 2573a1b13b4eSChris Ball 25747260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 25757260cf5eSAnton Vorontsov 2576cf2b5eeaSArindam Nath /* Disable tuning since we are suspending */ 2577973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2578c6ced0dbSAaron Lu del_timer_sync(&host->tuning_timer); 2579cf2b5eeaSArindam Nath host->flags &= ~SDHCI_NEEDS_RETUNING; 2580cf2b5eeaSArindam Nath } 2581cf2b5eeaSArindam Nath 2582ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2583b0a8deceSKevin Liu sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2584b8c86fc5SPierre Ossman free_irq(host->irq, host); 2585ad080d79SKevin Liu } else { 2586ad080d79SKevin Liu sdhci_enable_irq_wakeups(host); 2587ad080d79SKevin Liu enable_irq_wake(host->irq); 2588ad080d79SKevin Liu } 25894ee14ec6SUlf Hansson return 0; 2590b8c86fc5SPierre Ossman } 2591b8c86fc5SPierre Ossman 2592b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2593b8c86fc5SPierre Ossman 2594b8c86fc5SPierre Ossman int sdhci_resume_host(struct sdhci_host *host) 2595b8c86fc5SPierre Ossman { 25964ee14ec6SUlf Hansson int ret = 0; 2597b8c86fc5SPierre Ossman 2598a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2599b8c86fc5SPierre Ossman if (host->ops->enable_dma) 2600b8c86fc5SPierre Ossman host->ops->enable_dma(host); 2601b8c86fc5SPierre Ossman } 2602b8c86fc5SPierre Ossman 2603ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2604b8c86fc5SPierre Ossman ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2605b8c86fc5SPierre Ossman mmc_hostname(host->mmc), host); 26061c6a0718SPierre Ossman if (ret) 26071c6a0718SPierre Ossman return ret; 2608ad080d79SKevin Liu } else { 2609ad080d79SKevin Liu sdhci_disable_irq_wakeups(host); 2610ad080d79SKevin Liu disable_irq_wake(host->irq); 2611ad080d79SKevin Liu } 2612b8c86fc5SPierre Ossman 26136308d290SAdrian Hunter if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 26146308d290SAdrian Hunter (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 26156308d290SAdrian Hunter /* Card keeps power but host controller does not */ 26166308d290SAdrian Hunter sdhci_init(host, 0); 26176308d290SAdrian Hunter host->pwr = 0; 26186308d290SAdrian Hunter host->clock = 0; 26196308d290SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 26206308d290SAdrian Hunter } else { 26212f4cbb3dSNicolas Pitre sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 26221c6a0718SPierre Ossman mmiowb(); 26236308d290SAdrian Hunter } 2624b8c86fc5SPierre Ossman 26257260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 26267260cf5eSAnton Vorontsov 2627a1b13b4eSChris Ball if (host->ops->platform_resume) 2628a1b13b4eSChris Ball host->ops->platform_resume(host); 2629a1b13b4eSChris Ball 2630cf2b5eeaSArindam Nath /* Set the re-tuning expiration flag */ 2631973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) 2632cf2b5eeaSArindam Nath host->flags |= SDHCI_NEEDS_RETUNING; 2633cf2b5eeaSArindam Nath 26342f4cbb3dSNicolas Pitre return ret; 26351c6a0718SPierre Ossman } 26361c6a0718SPierre Ossman 2637b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_resume_host); 26381c6a0718SPierre Ossman #endif /* CONFIG_PM */ 26391c6a0718SPierre Ossman 264066fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 264166fd8ad5SAdrian Hunter 264266fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host) 264366fd8ad5SAdrian Hunter { 264466fd8ad5SAdrian Hunter return pm_runtime_get_sync(host->mmc->parent); 264566fd8ad5SAdrian Hunter } 264666fd8ad5SAdrian Hunter 264766fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host) 264866fd8ad5SAdrian Hunter { 264966fd8ad5SAdrian Hunter pm_runtime_mark_last_busy(host->mmc->parent); 265066fd8ad5SAdrian Hunter return pm_runtime_put_autosuspend(host->mmc->parent); 265166fd8ad5SAdrian Hunter } 265266fd8ad5SAdrian Hunter 2653f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2654f0710a55SAdrian Hunter { 2655f0710a55SAdrian Hunter if (host->runtime_suspended || host->bus_on) 2656f0710a55SAdrian Hunter return; 2657f0710a55SAdrian Hunter host->bus_on = true; 2658f0710a55SAdrian Hunter pm_runtime_get_noresume(host->mmc->parent); 2659f0710a55SAdrian Hunter } 2660f0710a55SAdrian Hunter 2661f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2662f0710a55SAdrian Hunter { 2663f0710a55SAdrian Hunter if (host->runtime_suspended || !host->bus_on) 2664f0710a55SAdrian Hunter return; 2665f0710a55SAdrian Hunter host->bus_on = false; 2666f0710a55SAdrian Hunter pm_runtime_put_noidle(host->mmc->parent); 2667f0710a55SAdrian Hunter } 2668f0710a55SAdrian Hunter 266966fd8ad5SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host) 267066fd8ad5SAdrian Hunter { 267166fd8ad5SAdrian Hunter unsigned long flags; 267266fd8ad5SAdrian Hunter int ret = 0; 267366fd8ad5SAdrian Hunter 267466fd8ad5SAdrian Hunter /* Disable tuning since we are suspending */ 2675973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 267666fd8ad5SAdrian Hunter del_timer_sync(&host->tuning_timer); 267766fd8ad5SAdrian Hunter host->flags &= ~SDHCI_NEEDS_RETUNING; 267866fd8ad5SAdrian Hunter } 267966fd8ad5SAdrian Hunter 268066fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 268166fd8ad5SAdrian Hunter sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 268266fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 268366fd8ad5SAdrian Hunter 268466fd8ad5SAdrian Hunter synchronize_irq(host->irq); 268566fd8ad5SAdrian Hunter 268666fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 268766fd8ad5SAdrian Hunter host->runtime_suspended = true; 268866fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 268966fd8ad5SAdrian Hunter 269066fd8ad5SAdrian Hunter return ret; 269166fd8ad5SAdrian Hunter } 269266fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 269366fd8ad5SAdrian Hunter 269466fd8ad5SAdrian Hunter int sdhci_runtime_resume_host(struct sdhci_host *host) 269566fd8ad5SAdrian Hunter { 269666fd8ad5SAdrian Hunter unsigned long flags; 269766fd8ad5SAdrian Hunter int ret = 0, host_flags = host->flags; 269866fd8ad5SAdrian Hunter 269966fd8ad5SAdrian Hunter if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 270066fd8ad5SAdrian Hunter if (host->ops->enable_dma) 270166fd8ad5SAdrian Hunter host->ops->enable_dma(host); 270266fd8ad5SAdrian Hunter } 270366fd8ad5SAdrian Hunter 270466fd8ad5SAdrian Hunter sdhci_init(host, 0); 270566fd8ad5SAdrian Hunter 270666fd8ad5SAdrian Hunter /* Force clock and power re-program */ 270766fd8ad5SAdrian Hunter host->pwr = 0; 270866fd8ad5SAdrian Hunter host->clock = 0; 270966fd8ad5SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 271066fd8ad5SAdrian Hunter 271166fd8ad5SAdrian Hunter sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 271252983382SKevin Liu if ((host_flags & SDHCI_PV_ENABLED) && 271352983382SKevin Liu !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 271452983382SKevin Liu spin_lock_irqsave(&host->lock, flags); 271552983382SKevin Liu sdhci_enable_preset_value(host, true); 271652983382SKevin Liu spin_unlock_irqrestore(&host->lock, flags); 271752983382SKevin Liu } 271866fd8ad5SAdrian Hunter 271966fd8ad5SAdrian Hunter /* Set the re-tuning expiration flag */ 2720973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) 272166fd8ad5SAdrian Hunter host->flags |= SDHCI_NEEDS_RETUNING; 272266fd8ad5SAdrian Hunter 272366fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 272466fd8ad5SAdrian Hunter 272566fd8ad5SAdrian Hunter host->runtime_suspended = false; 272666fd8ad5SAdrian Hunter 272766fd8ad5SAdrian Hunter /* Enable SDIO IRQ */ 2728ef104333SRussell King if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 272966fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 273066fd8ad5SAdrian Hunter 273166fd8ad5SAdrian Hunter /* Enable Card Detection */ 273266fd8ad5SAdrian Hunter sdhci_enable_card_detection(host); 273366fd8ad5SAdrian Hunter 273466fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 273566fd8ad5SAdrian Hunter 273666fd8ad5SAdrian Hunter return ret; 273766fd8ad5SAdrian Hunter } 273866fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 273966fd8ad5SAdrian Hunter 274066fd8ad5SAdrian Hunter #endif 274166fd8ad5SAdrian Hunter 27421c6a0718SPierre Ossman /*****************************************************************************\ 27431c6a0718SPierre Ossman * * 2744b8c86fc5SPierre Ossman * Device allocation/registration * 27451c6a0718SPierre Ossman * * 27461c6a0718SPierre Ossman \*****************************************************************************/ 27471c6a0718SPierre Ossman 2748b8c86fc5SPierre Ossman struct sdhci_host *sdhci_alloc_host(struct device *dev, 2749b8c86fc5SPierre Ossman size_t priv_size) 27501c6a0718SPierre Ossman { 27511c6a0718SPierre Ossman struct mmc_host *mmc; 27521c6a0718SPierre Ossman struct sdhci_host *host; 27531c6a0718SPierre Ossman 2754b8c86fc5SPierre Ossman WARN_ON(dev == NULL); 27551c6a0718SPierre Ossman 2756b8c86fc5SPierre Ossman mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 27571c6a0718SPierre Ossman if (!mmc) 2758b8c86fc5SPierre Ossman return ERR_PTR(-ENOMEM); 27591c6a0718SPierre Ossman 27601c6a0718SPierre Ossman host = mmc_priv(mmc); 27611c6a0718SPierre Ossman host->mmc = mmc; 27621c6a0718SPierre Ossman 2763b8c86fc5SPierre Ossman return host; 27641c6a0718SPierre Ossman } 27651c6a0718SPierre Ossman 2766b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2767b8c86fc5SPierre Ossman 2768b8c86fc5SPierre Ossman int sdhci_add_host(struct sdhci_host *host) 2769b8c86fc5SPierre Ossman { 2770b8c86fc5SPierre Ossman struct mmc_host *mmc; 2771bd6a8c30SPhilip Rakity u32 caps[2] = {0, 0}; 2772f2119df6SArindam Nath u32 max_current_caps; 2773f2119df6SArindam Nath unsigned int ocr_avail; 2774b8c86fc5SPierre Ossman int ret; 2775b8c86fc5SPierre Ossman 2776b8c86fc5SPierre Ossman WARN_ON(host == NULL); 2777b8c86fc5SPierre Ossman if (host == NULL) 2778b8c86fc5SPierre Ossman return -EINVAL; 2779b8c86fc5SPierre Ossman 2780b8c86fc5SPierre Ossman mmc = host->mmc; 2781b8c86fc5SPierre Ossman 2782b8c86fc5SPierre Ossman if (debug_quirks) 2783b8c86fc5SPierre Ossman host->quirks = debug_quirks; 278466fd8ad5SAdrian Hunter if (debug_quirks2) 278566fd8ad5SAdrian Hunter host->quirks2 = debug_quirks2; 2786b8c86fc5SPierre Ossman 27871c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 27881c6a0718SPierre Ossman 27894e4141a5SAnton Vorontsov host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 27902134a922SPierre Ossman host->version = (host->version & SDHCI_SPEC_VER_MASK) 27912134a922SPierre Ossman >> SDHCI_SPEC_VER_SHIFT; 279285105c53SZhangfei Gao if (host->version > SDHCI_SPEC_300) { 2793a3c76eb9SGirish K S pr_err("%s: Unknown controller version (%d). " 2794b69c9058SPierre Ossman "You may experience problems.\n", mmc_hostname(mmc), 27952134a922SPierre Ossman host->version); 27961c6a0718SPierre Ossman } 27971c6a0718SPierre Ossman 2798f2119df6SArindam Nath caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2799ccc92c23SMaxim Levitsky sdhci_readl(host, SDHCI_CAPABILITIES); 28001c6a0718SPierre Ossman 2801bd6a8c30SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 2802bd6a8c30SPhilip Rakity caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2803bd6a8c30SPhilip Rakity host->caps1 : 2804bd6a8c30SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1); 2805f2119df6SArindam Nath 2806b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2807a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 2808f2119df6SArindam Nath else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2809a13abc7bSRichard Röjfors DBG("Controller doesn't have SDMA capability\n"); 28101c6a0718SPierre Ossman else 2811a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 28121c6a0718SPierre Ossman 2813b8c86fc5SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2814a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA)) { 2815cee687ceSRolf Eike Beer DBG("Disabling DMA as it is marked broken\n"); 2816a13abc7bSRichard Röjfors host->flags &= ~SDHCI_USE_SDMA; 28177c168e3dSFeng Tang } 28187c168e3dSFeng Tang 2819f2119df6SArindam Nath if ((host->version >= SDHCI_SPEC_200) && 2820f2119df6SArindam Nath (caps[0] & SDHCI_CAN_DO_ADMA2)) 28212134a922SPierre Ossman host->flags |= SDHCI_USE_ADMA; 28222134a922SPierre Ossman 28232134a922SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 28242134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) { 28252134a922SPierre Ossman DBG("Disabling ADMA as it is marked broken\n"); 28262134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 28272134a922SPierre Ossman } 28282134a922SPierre Ossman 2829a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2830b8c86fc5SPierre Ossman if (host->ops->enable_dma) { 2831b8c86fc5SPierre Ossman if (host->ops->enable_dma(host)) { 2832a3c76eb9SGirish K S pr_warning("%s: No suitable DMA " 2833b8c86fc5SPierre Ossman "available. Falling back to PIO.\n", 2834b8c86fc5SPierre Ossman mmc_hostname(mmc)); 2835a13abc7bSRichard Röjfors host->flags &= 2836a13abc7bSRichard Röjfors ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 28371c6a0718SPierre Ossman } 28381c6a0718SPierre Ossman } 2839b8c86fc5SPierre Ossman } 28401c6a0718SPierre Ossman 28412134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 28422134a922SPierre Ossman /* 28432134a922SPierre Ossman * We need to allocate descriptors for all sg entries 28442134a922SPierre Ossman * (128) and potentially one alignment transfer for 28452134a922SPierre Ossman * each of those entries. 28462134a922SPierre Ossman */ 28472134a922SPierre Ossman host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 28482134a922SPierre Ossman host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 28492134a922SPierre Ossman if (!host->adma_desc || !host->align_buffer) { 28502134a922SPierre Ossman kfree(host->adma_desc); 28512134a922SPierre Ossman kfree(host->align_buffer); 2852a3c76eb9SGirish K S pr_warning("%s: Unable to allocate ADMA " 28532134a922SPierre Ossman "buffers. Falling back to standard DMA.\n", 28542134a922SPierre Ossman mmc_hostname(mmc)); 28552134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 28562134a922SPierre Ossman } 28572134a922SPierre Ossman } 28582134a922SPierre Ossman 28597659150cSPierre Ossman /* 28607659150cSPierre Ossman * If we use DMA, then it's up to the caller to set the DMA 28617659150cSPierre Ossman * mask, but PIO does not need the hw shim so we set a new 28627659150cSPierre Ossman * mask here in that case. 28637659150cSPierre Ossman */ 2864a13abc7bSRichard Röjfors if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 28657659150cSPierre Ossman host->dma_mask = DMA_BIT_MASK(64); 28667659150cSPierre Ossman mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 28677659150cSPierre Ossman } 28681c6a0718SPierre Ossman 2869c4687d5fSZhangfei Gao if (host->version >= SDHCI_SPEC_300) 2870f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2871c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2872c4687d5fSZhangfei Gao else 2873f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2874c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2875c4687d5fSZhangfei Gao 28764240ff0aSBen Dooks host->max_clk *= 1000000; 2877f27f47efSAnton Vorontsov if (host->max_clk == 0 || host->quirks & 2878f27f47efSAnton Vorontsov SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 28794240ff0aSBen Dooks if (!host->ops->get_max_clock) { 2880a3c76eb9SGirish K S pr_err("%s: Hardware doesn't specify base clock " 2881b69c9058SPierre Ossman "frequency.\n", mmc_hostname(mmc)); 2882b8c86fc5SPierre Ossman return -ENODEV; 28831c6a0718SPierre Ossman } 28844240ff0aSBen Dooks host->max_clk = host->ops->get_max_clock(host); 28854240ff0aSBen Dooks } 28861c6a0718SPierre Ossman 28871c6a0718SPierre Ossman /* 2888c3ed3877SArindam Nath * In case of Host Controller v3.00, find out whether clock 2889c3ed3877SArindam Nath * multiplier is supported. 2890c3ed3877SArindam Nath */ 2891c3ed3877SArindam Nath host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2892c3ed3877SArindam Nath SDHCI_CLOCK_MUL_SHIFT; 2893c3ed3877SArindam Nath 2894c3ed3877SArindam Nath /* 2895c3ed3877SArindam Nath * In case the value in Clock Multiplier is 0, then programmable 2896c3ed3877SArindam Nath * clock mode is not supported, otherwise the actual clock 2897c3ed3877SArindam Nath * multiplier is one more than the value of Clock Multiplier 2898c3ed3877SArindam Nath * in the Capabilities Register. 2899c3ed3877SArindam Nath */ 2900c3ed3877SArindam Nath if (host->clk_mul) 2901c3ed3877SArindam Nath host->clk_mul += 1; 2902c3ed3877SArindam Nath 2903c3ed3877SArindam Nath /* 29041c6a0718SPierre Ossman * Set host parameters. 29051c6a0718SPierre Ossman */ 29061c6a0718SPierre Ossman mmc->ops = &sdhci_ops; 2907c3ed3877SArindam Nath mmc->f_max = host->max_clk; 2908ce5f036bSMarek Szyprowski if (host->ops->get_min_clock) 2909a9e58f25SAnton Vorontsov mmc->f_min = host->ops->get_min_clock(host); 2910c3ed3877SArindam Nath else if (host->version >= SDHCI_SPEC_300) { 2911c3ed3877SArindam Nath if (host->clk_mul) { 2912c3ed3877SArindam Nath mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2913c3ed3877SArindam Nath mmc->f_max = host->max_clk * host->clk_mul; 2914c3ed3877SArindam Nath } else 29150397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2916c3ed3877SArindam Nath } else 29170397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 291815ec4461SPhilip Rakity 2919272308caSAndy Shevchenko host->timeout_clk = 2920272308caSAndy Shevchenko (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2921272308caSAndy Shevchenko if (host->timeout_clk == 0) { 2922272308caSAndy Shevchenko if (host->ops->get_timeout_clock) { 2923272308caSAndy Shevchenko host->timeout_clk = host->ops->get_timeout_clock(host); 2924272308caSAndy Shevchenko } else if (!(host->quirks & 2925272308caSAndy Shevchenko SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2926a3c76eb9SGirish K S pr_err("%s: Hardware doesn't specify timeout clock " 2927272308caSAndy Shevchenko "frequency.\n", mmc_hostname(mmc)); 2928272308caSAndy Shevchenko return -ENODEV; 2929272308caSAndy Shevchenko } 2930272308caSAndy Shevchenko } 2931272308caSAndy Shevchenko if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2932272308caSAndy Shevchenko host->timeout_clk *= 1000; 2933272308caSAndy Shevchenko 2934272308caSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 293565be3fefSAndy Shevchenko host->timeout_clk = mmc->f_max / 1000; 2936272308caSAndy Shevchenko 293768eb80e0SUlf Hansson mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; 293858d1246dSAdrian Hunter 2939e89d456fSAndrei Warkentin mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2940e89d456fSAndrei Warkentin 2941e89d456fSAndrei Warkentin if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2942e89d456fSAndrei Warkentin host->flags |= SDHCI_AUTO_CMD12; 29435fe23c7fSAnton Vorontsov 29448edf6371SAndrei Warkentin /* Auto-CMD23 stuff only works in ADMA or PIO. */ 29454f3d3e9bSAndrei Warkentin if ((host->version >= SDHCI_SPEC_300) && 29468edf6371SAndrei Warkentin ((host->flags & SDHCI_USE_ADMA) || 29474f3d3e9bSAndrei Warkentin !(host->flags & SDHCI_USE_SDMA))) { 29488edf6371SAndrei Warkentin host->flags |= SDHCI_AUTO_CMD23; 29498edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 29508edf6371SAndrei Warkentin } else { 29518edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 29528edf6371SAndrei Warkentin } 29538edf6371SAndrei Warkentin 295415ec4461SPhilip Rakity /* 295515ec4461SPhilip Rakity * A controller may support 8-bit width, but the board itself 295615ec4461SPhilip Rakity * might not have the pins brought out. Boards that support 295715ec4461SPhilip Rakity * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 295815ec4461SPhilip Rakity * their platform code before calling sdhci_add_host(), and we 295915ec4461SPhilip Rakity * won't assume 8-bit width for hosts without that CAP. 296015ec4461SPhilip Rakity */ 29615fe23c7fSAnton Vorontsov if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 296215ec4461SPhilip Rakity mmc->caps |= MMC_CAP_4_BIT_DATA; 29631c6a0718SPierre Ossman 296463ef5d8cSJerry Huang if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 296563ef5d8cSJerry Huang mmc->caps &= ~MMC_CAP_CMD23; 296663ef5d8cSJerry Huang 2967f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_DO_HISPD) 2968a29e7e18SZhangfei Gao mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 29691c6a0718SPierre Ossman 2970176d1ed4SJaehoon Chung if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2971eb6d5ae1SDaniel Drake !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 297268d1fb7eSAnton Vorontsov mmc->caps |= MMC_CAP_NEEDS_POLL; 297368d1fb7eSAnton Vorontsov 29746231f3deSPhilip Rakity /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 2975462849aaSMark Brown host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc"); 2976657d5982SKevin Liu if (IS_ERR_OR_NULL(host->vqmmc)) { 2977657d5982SKevin Liu if (PTR_ERR(host->vqmmc) < 0) { 2978657d5982SKevin Liu pr_info("%s: no vqmmc regulator found\n", 2979657d5982SKevin Liu mmc_hostname(mmc)); 29806231f3deSPhilip Rakity host->vqmmc = NULL; 29816231f3deSPhilip Rakity } 29828363c374SKevin Liu } else { 2983a3361abaSChris Ball ret = regulator_enable(host->vqmmc); 2984cec2e216SKevin Liu if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2985cec2e216SKevin Liu 1950000)) 29868363c374SKevin Liu caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 29878363c374SKevin Liu SDHCI_SUPPORT_SDR50 | 29886231f3deSPhilip Rakity SDHCI_SUPPORT_DDR50); 2989a3361abaSChris Ball if (ret) { 2990a3361abaSChris Ball pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 2991a3361abaSChris Ball mmc_hostname(mmc), ret); 2992a3361abaSChris Ball host->vqmmc = NULL; 2993a3361abaSChris Ball } 29948363c374SKevin Liu } 29956231f3deSPhilip Rakity 29966a66180aSDaniel Drake if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 29976a66180aSDaniel Drake caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 29986a66180aSDaniel Drake SDHCI_SUPPORT_DDR50); 29996a66180aSDaniel Drake 30004188bba0SAl Cooper /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 30014188bba0SAl Cooper if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 30024188bba0SAl Cooper SDHCI_SUPPORT_DDR50)) 3003f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3004f2119df6SArindam Nath 3005f2119df6SArindam Nath /* SDR104 supports also implies SDR50 support */ 3006156e14b1SGiuseppe CAVALLARO if (caps[1] & SDHCI_SUPPORT_SDR104) { 3007f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3008156e14b1SGiuseppe CAVALLARO /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3009156e14b1SGiuseppe CAVALLARO * field can be promoted to support HS200. 3010156e14b1SGiuseppe CAVALLARO */ 301113868bf2SDavid Cohen if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3012156e14b1SGiuseppe CAVALLARO mmc->caps2 |= MMC_CAP2_HS200; 3013156e14b1SGiuseppe CAVALLARO } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3014f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR50; 3015f2119df6SArindam Nath 30169107ebbfSMicky Ching if ((caps[1] & SDHCI_SUPPORT_DDR50) && 30179107ebbfSMicky Ching !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3018f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_DDR50; 3019f2119df6SArindam Nath 3020069c9f14SGirish K S /* Does the host need tuning for SDR50? */ 3021b513ea25SArindam Nath if (caps[1] & SDHCI_USE_SDR50_TUNING) 3022b513ea25SArindam Nath host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3023b513ea25SArindam Nath 3024156e14b1SGiuseppe CAVALLARO /* Does the host need tuning for SDR104 / HS200? */ 3025069c9f14SGirish K S if (mmc->caps2 & MMC_CAP2_HS200) 3026156e14b1SGiuseppe CAVALLARO host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3027069c9f14SGirish K S 3028d6d50a15SArindam Nath /* Driver Type(s) (A, C, D) supported by the host */ 3029d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_A) 3030d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3031d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_C) 3032d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3033d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_D) 3034d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3035d6d50a15SArindam Nath 3036cf2b5eeaSArindam Nath /* Initial value for re-tuning timer count */ 3037cf2b5eeaSArindam Nath host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3038cf2b5eeaSArindam Nath SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3039cf2b5eeaSArindam Nath 3040cf2b5eeaSArindam Nath /* 3041cf2b5eeaSArindam Nath * In case Re-tuning Timer is not disabled, the actual value of 3042cf2b5eeaSArindam Nath * re-tuning timer will be 2 ^ (n - 1). 3043cf2b5eeaSArindam Nath */ 3044cf2b5eeaSArindam Nath if (host->tuning_count) 3045cf2b5eeaSArindam Nath host->tuning_count = 1 << (host->tuning_count - 1); 3046cf2b5eeaSArindam Nath 3047cf2b5eeaSArindam Nath /* Re-tuning mode supported by the Host Controller */ 3048cf2b5eeaSArindam Nath host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3049cf2b5eeaSArindam Nath SDHCI_RETUNING_MODE_SHIFT; 3050cf2b5eeaSArindam Nath 30518f230f45STakashi Iwai ocr_avail = 0; 3052bad37e1aSPhilip Rakity 3053462849aaSMark Brown host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc"); 3054657d5982SKevin Liu if (IS_ERR_OR_NULL(host->vmmc)) { 3055657d5982SKevin Liu if (PTR_ERR(host->vmmc) < 0) { 3056657d5982SKevin Liu pr_info("%s: no vmmc regulator found\n", 3057657d5982SKevin Liu mmc_hostname(mmc)); 3058bad37e1aSPhilip Rakity host->vmmc = NULL; 3059657d5982SKevin Liu } 30608363c374SKevin Liu } 3061bad37e1aSPhilip Rakity 306268737043SPhilip Rakity #ifdef CONFIG_REGULATOR 3063a4f8f257SMarek Szyprowski /* 3064a4f8f257SMarek Szyprowski * Voltage range check makes sense only if regulator reports 3065a4f8f257SMarek Szyprowski * any voltage value. 3066a4f8f257SMarek Szyprowski */ 3067a4f8f257SMarek Szyprowski if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { 3068cec2e216SKevin Liu ret = regulator_is_supported_voltage(host->vmmc, 2700000, 3069cec2e216SKevin Liu 3600000); 307068737043SPhilip Rakity if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 307168737043SPhilip Rakity caps[0] &= ~SDHCI_CAN_VDD_330; 307268737043SPhilip Rakity if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 307368737043SPhilip Rakity caps[0] &= ~SDHCI_CAN_VDD_300; 3074cec2e216SKevin Liu ret = regulator_is_supported_voltage(host->vmmc, 1700000, 3075cec2e216SKevin Liu 1950000); 307668737043SPhilip Rakity if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 307768737043SPhilip Rakity caps[0] &= ~SDHCI_CAN_VDD_180; 307868737043SPhilip Rakity } 307968737043SPhilip Rakity #endif /* CONFIG_REGULATOR */ 308068737043SPhilip Rakity 3081f2119df6SArindam Nath /* 3082f2119df6SArindam Nath * According to SD Host Controller spec v3.00, if the Host System 3083f2119df6SArindam Nath * can afford more than 150mA, Host Driver should set XPC to 1. Also 3084f2119df6SArindam Nath * the value is meaningful only if Voltage Support in the Capabilities 3085f2119df6SArindam Nath * register is set. The actual current value is 4 times the register 3086f2119df6SArindam Nath * value. 3087f2119df6SArindam Nath */ 3088f2119df6SArindam Nath max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3089bad37e1aSPhilip Rakity if (!max_current_caps && host->vmmc) { 3090bad37e1aSPhilip Rakity u32 curr = regulator_get_current_limit(host->vmmc); 3091bad37e1aSPhilip Rakity if (curr > 0) { 3092bad37e1aSPhilip Rakity 3093bad37e1aSPhilip Rakity /* convert to SDHCI_MAX_CURRENT format */ 3094bad37e1aSPhilip Rakity curr = curr/1000; /* convert to mA */ 3095bad37e1aSPhilip Rakity curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3096bad37e1aSPhilip Rakity 3097bad37e1aSPhilip Rakity curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3098bad37e1aSPhilip Rakity max_current_caps = 3099bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3100bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3101bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3102bad37e1aSPhilip Rakity } 3103bad37e1aSPhilip Rakity } 3104f2119df6SArindam Nath 3105f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_330) { 31068f230f45STakashi Iwai ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3107f2119df6SArindam Nath 310855c4665eSAaron Lu mmc->max_current_330 = ((max_current_caps & 3109f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_MASK) >> 3110f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_SHIFT) * 3111f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3112f2119df6SArindam Nath } 3113f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_300) { 31148f230f45STakashi Iwai ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3115f2119df6SArindam Nath 311655c4665eSAaron Lu mmc->max_current_300 = ((max_current_caps & 3117f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_MASK) >> 3118f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_SHIFT) * 3119f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3120f2119df6SArindam Nath } 3121f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_180) { 31228f230f45STakashi Iwai ocr_avail |= MMC_VDD_165_195; 31238f230f45STakashi Iwai 312455c4665eSAaron Lu mmc->max_current_180 = ((max_current_caps & 3125f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_MASK) >> 3126f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_SHIFT) * 3127f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3128f2119df6SArindam Nath } 3129f2119df6SArindam Nath 3130c0b887b6SHaijun Zhang if (host->ocr_mask) 3131c0b887b6SHaijun Zhang ocr_avail = host->ocr_mask; 3132c0b887b6SHaijun Zhang 31338f230f45STakashi Iwai mmc->ocr_avail = ocr_avail; 31348f230f45STakashi Iwai mmc->ocr_avail_sdio = ocr_avail; 31358f230f45STakashi Iwai if (host->ocr_avail_sdio) 31368f230f45STakashi Iwai mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 31378f230f45STakashi Iwai mmc->ocr_avail_sd = ocr_avail; 31388f230f45STakashi Iwai if (host->ocr_avail_sd) 31398f230f45STakashi Iwai mmc->ocr_avail_sd &= host->ocr_avail_sd; 31408f230f45STakashi Iwai else /* normal SD controllers don't support 1.8V */ 31418f230f45STakashi Iwai mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 31428f230f45STakashi Iwai mmc->ocr_avail_mmc = ocr_avail; 31438f230f45STakashi Iwai if (host->ocr_avail_mmc) 31448f230f45STakashi Iwai mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 31451c6a0718SPierre Ossman 31461c6a0718SPierre Ossman if (mmc->ocr_avail == 0) { 3147a3c76eb9SGirish K S pr_err("%s: Hardware doesn't report any " 3148b69c9058SPierre Ossman "support voltages.\n", mmc_hostname(mmc)); 3149b8c86fc5SPierre Ossman return -ENODEV; 31501c6a0718SPierre Ossman } 31511c6a0718SPierre Ossman 31521c6a0718SPierre Ossman spin_lock_init(&host->lock); 31531c6a0718SPierre Ossman 31541c6a0718SPierre Ossman /* 31552134a922SPierre Ossman * Maximum number of segments. Depends on if the hardware 31562134a922SPierre Ossman * can do scatter/gather or not. 31571c6a0718SPierre Ossman */ 31582134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 3159a36274e0SMartin K. Petersen mmc->max_segs = 128; 3160a13abc7bSRichard Röjfors else if (host->flags & SDHCI_USE_SDMA) 3161a36274e0SMartin K. Petersen mmc->max_segs = 1; 31622134a922SPierre Ossman else /* PIO */ 3163a36274e0SMartin K. Petersen mmc->max_segs = 128; 31641c6a0718SPierre Ossman 31651c6a0718SPierre Ossman /* 31661c6a0718SPierre Ossman * Maximum number of sectors in one transfer. Limited by DMA boundary 31671c6a0718SPierre Ossman * size (512KiB). 31681c6a0718SPierre Ossman */ 31691c6a0718SPierre Ossman mmc->max_req_size = 524288; 31701c6a0718SPierre Ossman 31711c6a0718SPierre Ossman /* 31721c6a0718SPierre Ossman * Maximum segment size. Could be one segment with the maximum number 31732134a922SPierre Ossman * of bytes. When doing hardware scatter/gather, each entry cannot 31742134a922SPierre Ossman * be larger than 64 KiB though. 31751c6a0718SPierre Ossman */ 317630652aa3SOlof Johansson if (host->flags & SDHCI_USE_ADMA) { 317730652aa3SOlof Johansson if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 317830652aa3SOlof Johansson mmc->max_seg_size = 65535; 31792134a922SPierre Ossman else 318030652aa3SOlof Johansson mmc->max_seg_size = 65536; 318130652aa3SOlof Johansson } else { 31821c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 318330652aa3SOlof Johansson } 31841c6a0718SPierre Ossman 31851c6a0718SPierre Ossman /* 31861c6a0718SPierre Ossman * Maximum block size. This varies from controller to controller and 31871c6a0718SPierre Ossman * is specified in the capabilities register. 31881c6a0718SPierre Ossman */ 31890633f654SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 31900633f654SAnton Vorontsov mmc->max_blk_size = 2; 31910633f654SAnton Vorontsov } else { 3192f2119df6SArindam Nath mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 31930633f654SAnton Vorontsov SDHCI_MAX_BLOCK_SHIFT; 31941c6a0718SPierre Ossman if (mmc->max_blk_size >= 3) { 3195a3c76eb9SGirish K S pr_warning("%s: Invalid maximum block size, " 3196b69c9058SPierre Ossman "assuming 512 bytes\n", mmc_hostname(mmc)); 31970633f654SAnton Vorontsov mmc->max_blk_size = 0; 31980633f654SAnton Vorontsov } 31990633f654SAnton Vorontsov } 32000633f654SAnton Vorontsov 32011c6a0718SPierre Ossman mmc->max_blk_size = 512 << mmc->max_blk_size; 32021c6a0718SPierre Ossman 32031c6a0718SPierre Ossman /* 32041c6a0718SPierre Ossman * Maximum block count. 32051c6a0718SPierre Ossman */ 32061388eefdSBen Dooks mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 32071c6a0718SPierre Ossman 32081c6a0718SPierre Ossman /* 32091c6a0718SPierre Ossman * Init tasklets. 32101c6a0718SPierre Ossman */ 32111c6a0718SPierre Ossman tasklet_init(&host->card_tasklet, 32121c6a0718SPierre Ossman sdhci_tasklet_card, (unsigned long)host); 32131c6a0718SPierre Ossman tasklet_init(&host->finish_tasklet, 32141c6a0718SPierre Ossman sdhci_tasklet_finish, (unsigned long)host); 32151c6a0718SPierre Ossman 32161c6a0718SPierre Ossman setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 32171c6a0718SPierre Ossman 3218cf2b5eeaSArindam Nath if (host->version >= SDHCI_SPEC_300) { 3219b513ea25SArindam Nath init_waitqueue_head(&host->buf_ready_int); 3220b513ea25SArindam Nath 3221cf2b5eeaSArindam Nath /* Initialize re-tuning timer */ 3222cf2b5eeaSArindam Nath init_timer(&host->tuning_timer); 3223cf2b5eeaSArindam Nath host->tuning_timer.data = (unsigned long)host; 3224cf2b5eeaSArindam Nath host->tuning_timer.function = sdhci_tuning_timer; 3225cf2b5eeaSArindam Nath } 3226cf2b5eeaSArindam Nath 32272af502caSShawn Guo sdhci_init(host, 0); 32282af502caSShawn Guo 32291c6a0718SPierre Ossman ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 3230b69c9058SPierre Ossman mmc_hostname(mmc), host); 32310fc81ee3SMark Brown if (ret) { 32320fc81ee3SMark Brown pr_err("%s: Failed to request IRQ %d: %d\n", 32330fc81ee3SMark Brown mmc_hostname(mmc), host->irq, ret); 32341c6a0718SPierre Ossman goto untasklet; 32350fc81ee3SMark Brown } 32361c6a0718SPierre Ossman 32371c6a0718SPierre Ossman #ifdef CONFIG_MMC_DEBUG 32381c6a0718SPierre Ossman sdhci_dumpregs(host); 32391c6a0718SPierre Ossman #endif 32401c6a0718SPierre Ossman 3241f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 32425dbace0cSHelmut Schaa snprintf(host->led_name, sizeof(host->led_name), 32435dbace0cSHelmut Schaa "%s::", mmc_hostname(mmc)); 32445dbace0cSHelmut Schaa host->led.name = host->led_name; 32452f730fecSPierre Ossman host->led.brightness = LED_OFF; 32462f730fecSPierre Ossman host->led.default_trigger = mmc_hostname(mmc); 32472f730fecSPierre Ossman host->led.brightness_set = sdhci_led_control; 32482f730fecSPierre Ossman 3249b8c86fc5SPierre Ossman ret = led_classdev_register(mmc_dev(mmc), &host->led); 32500fc81ee3SMark Brown if (ret) { 32510fc81ee3SMark Brown pr_err("%s: Failed to register LED device: %d\n", 32520fc81ee3SMark Brown mmc_hostname(mmc), ret); 32532f730fecSPierre Ossman goto reset; 32540fc81ee3SMark Brown } 32552f730fecSPierre Ossman #endif 32562f730fecSPierre Ossman 32571c6a0718SPierre Ossman mmiowb(); 32581c6a0718SPierre Ossman 32591c6a0718SPierre Ossman mmc_add_host(mmc); 32601c6a0718SPierre Ossman 3261a3c76eb9SGirish K S pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3262d1b26863SKay Sievers mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3263a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3264a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 32651c6a0718SPierre Ossman 32667260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 32677260cf5eSAnton Vorontsov 32681c6a0718SPierre Ossman return 0; 32691c6a0718SPierre Ossman 3270f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 32712f730fecSPierre Ossman reset: 32722f730fecSPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 3273b0a8deceSKevin Liu sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 32742f730fecSPierre Ossman free_irq(host->irq, host); 32752f730fecSPierre Ossman #endif 32761c6a0718SPierre Ossman untasklet: 32771c6a0718SPierre Ossman tasklet_kill(&host->card_tasklet); 32781c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 32791c6a0718SPierre Ossman 32801c6a0718SPierre Ossman return ret; 32811c6a0718SPierre Ossman } 32821c6a0718SPierre Ossman 3283b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_add_host); 3284b8c86fc5SPierre Ossman 32851e72859eSPierre Ossman void sdhci_remove_host(struct sdhci_host *host, int dead) 32861c6a0718SPierre Ossman { 32871e72859eSPierre Ossman unsigned long flags; 32881e72859eSPierre Ossman 32891e72859eSPierre Ossman if (dead) { 32901e72859eSPierre Ossman spin_lock_irqsave(&host->lock, flags); 32911e72859eSPierre Ossman 32921e72859eSPierre Ossman host->flags |= SDHCI_DEVICE_DEAD; 32931e72859eSPierre Ossman 32941e72859eSPierre Ossman if (host->mrq) { 3295a3c76eb9SGirish K S pr_err("%s: Controller removed during " 32961e72859eSPierre Ossman " transfer!\n", mmc_hostname(host->mmc)); 32971e72859eSPierre Ossman 32981e72859eSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 32991e72859eSPierre Ossman tasklet_schedule(&host->finish_tasklet); 33001e72859eSPierre Ossman } 33011e72859eSPierre Ossman 33021e72859eSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 33031e72859eSPierre Ossman } 33041e72859eSPierre Ossman 33057260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 33067260cf5eSAnton Vorontsov 3307b8c86fc5SPierre Ossman mmc_remove_host(host->mmc); 33081c6a0718SPierre Ossman 3309f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 33102f730fecSPierre Ossman led_classdev_unregister(&host->led); 33112f730fecSPierre Ossman #endif 33122f730fecSPierre Ossman 33131e72859eSPierre Ossman if (!dead) 33141c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 33151c6a0718SPierre Ossman 3316b0a8deceSKevin Liu sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 33171c6a0718SPierre Ossman free_irq(host->irq, host); 33181c6a0718SPierre Ossman 33191c6a0718SPierre Ossman del_timer_sync(&host->timer); 33201c6a0718SPierre Ossman 33211c6a0718SPierre Ossman tasklet_kill(&host->card_tasklet); 33221c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 33232134a922SPierre Ossman 332477dcb3f4SPhilip Rakity if (host->vmmc) { 332577dcb3f4SPhilip Rakity regulator_disable(host->vmmc); 33269bea3c85SMarek Szyprowski regulator_put(host->vmmc); 332777dcb3f4SPhilip Rakity } 33289bea3c85SMarek Szyprowski 33296231f3deSPhilip Rakity if (host->vqmmc) { 33306231f3deSPhilip Rakity regulator_disable(host->vqmmc); 33316231f3deSPhilip Rakity regulator_put(host->vqmmc); 33326231f3deSPhilip Rakity } 33336231f3deSPhilip Rakity 33342134a922SPierre Ossman kfree(host->adma_desc); 33352134a922SPierre Ossman kfree(host->align_buffer); 33362134a922SPierre Ossman 33372134a922SPierre Ossman host->adma_desc = NULL; 33382134a922SPierre Ossman host->align_buffer = NULL; 33391c6a0718SPierre Ossman } 33401c6a0718SPierre Ossman 3341b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_remove_host); 3342b8c86fc5SPierre Ossman 3343b8c86fc5SPierre Ossman void sdhci_free_host(struct sdhci_host *host) 33441c6a0718SPierre Ossman { 3345b8c86fc5SPierre Ossman mmc_free_host(host->mmc); 33461c6a0718SPierre Ossman } 33471c6a0718SPierre Ossman 3348b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_free_host); 33491c6a0718SPierre Ossman 33501c6a0718SPierre Ossman /*****************************************************************************\ 33511c6a0718SPierre Ossman * * 33521c6a0718SPierre Ossman * Driver init/exit * 33531c6a0718SPierre Ossman * * 33541c6a0718SPierre Ossman \*****************************************************************************/ 33551c6a0718SPierre Ossman 33561c6a0718SPierre Ossman static int __init sdhci_drv_init(void) 33571c6a0718SPierre Ossman { 3358a3c76eb9SGirish K S pr_info(DRIVER_NAME 33591c6a0718SPierre Ossman ": Secure Digital Host Controller Interface driver\n"); 3360a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 33611c6a0718SPierre Ossman 3362b8c86fc5SPierre Ossman return 0; 33631c6a0718SPierre Ossman } 33641c6a0718SPierre Ossman 33651c6a0718SPierre Ossman static void __exit sdhci_drv_exit(void) 33661c6a0718SPierre Ossman { 33671c6a0718SPierre Ossman } 33681c6a0718SPierre Ossman 33691c6a0718SPierre Ossman module_init(sdhci_drv_init); 33701c6a0718SPierre Ossman module_exit(sdhci_drv_exit); 33711c6a0718SPierre Ossman 33721c6a0718SPierre Ossman module_param(debug_quirks, uint, 0444); 337366fd8ad5SAdrian Hunter module_param(debug_quirks2, uint, 0444); 33741c6a0718SPierre Ossman 337532710e8fSPierre Ossman MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3376b8c86fc5SPierre Ossman MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 33771c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 33781c6a0718SPierre Ossman 33791c6a0718SPierre Ossman MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 338066fd8ad5SAdrian Hunter MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3381