11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 4b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 81c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 91c6a0718SPierre Ossman * your option) any later version. 1084c46a53SPierre Ossman * 1184c46a53SPierre Ossman * Thanks to the following companies for their support: 1284c46a53SPierre Ossman * 1384c46a53SPierre Ossman * - JMicron (hardware and technical support) 141c6a0718SPierre Ossman */ 151c6a0718SPierre Ossman 161c6a0718SPierre Ossman #include <linux/delay.h> 171c6a0718SPierre Ossman #include <linux/highmem.h> 18b8c86fc5SPierre Ossman #include <linux/io.h> 1988b47679SPaul Gortmaker #include <linux/module.h> 201c6a0718SPierre Ossman #include <linux/dma-mapping.h> 215a0e3ad6STejun Heo #include <linux/slab.h> 2211763609SRalf Baechle #include <linux/scatterlist.h> 239bea3c85SMarek Szyprowski #include <linux/regulator/consumer.h> 2466fd8ad5SAdrian Hunter #include <linux/pm_runtime.h> 251c6a0718SPierre Ossman 262f730fecSPierre Ossman #include <linux/leds.h> 272f730fecSPierre Ossman 2822113efdSAries Lee #include <linux/mmc/mmc.h> 291c6a0718SPierre Ossman #include <linux/mmc/host.h> 30473b095aSAaron Lu #include <linux/mmc/card.h> 31bec9d4e5SGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #include "sdhci.h" 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define DRIVER_NAME "sdhci" 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define DBG(f, x...) \ 381c6a0718SPierre Ossman pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 391c6a0718SPierre Ossman 40f9134319SPierre Ossman #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41f9134319SPierre Ossman defined(CONFIG_MMC_SDHCI_MODULE)) 42f9134319SPierre Ossman #define SDHCI_USE_LEDS_CLASS 43f9134319SPierre Ossman #endif 44f9134319SPierre Ossman 45b513ea25SArindam Nath #define MAX_TUNING_LOOP 40 46b513ea25SArindam Nath 471c6a0718SPierre Ossman static unsigned int debug_quirks = 0; 4866fd8ad5SAdrian Hunter static unsigned int debug_quirks2; 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *); 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); 531c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *); 54069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 55cf2b5eeaSArindam Nath static void sdhci_tuning_timer(unsigned long data); 5652983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 571c6a0718SPierre Ossman 5866fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 5966fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host); 6066fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host); 6166fd8ad5SAdrian Hunter #else 6266fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 6366fd8ad5SAdrian Hunter { 6466fd8ad5SAdrian Hunter return 0; 6566fd8ad5SAdrian Hunter } 6666fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 6766fd8ad5SAdrian Hunter { 6866fd8ad5SAdrian Hunter return 0; 6966fd8ad5SAdrian Hunter } 7066fd8ad5SAdrian Hunter #endif 7166fd8ad5SAdrian Hunter 721c6a0718SPierre Ossman static void sdhci_dumpregs(struct sdhci_host *host) 731c6a0718SPierre Ossman { 74a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 75412ab659SPhilip Rakity mmc_hostname(host->mmc)); 761c6a0718SPierre Ossman 77a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 784e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_DMA_ADDRESS), 794e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_HOST_VERSION)); 80a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 814e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_SIZE), 824e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_COUNT)); 83a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 844e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_ARGUMENT), 854e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_TRANSFER_MODE)); 86a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 874e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_PRESENT_STATE), 884e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_HOST_CONTROL)); 89a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 904e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_POWER_CONTROL), 914e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 92a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 934e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 944e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 95a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 964e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 974e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_STATUS)); 98a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 994e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_ENABLE), 1004e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 101a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 1024e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_ACMD12_ERR), 1034e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 104a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 1054e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_CAPABILITIES), 106e8120ad1SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1)); 107a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 108e8120ad1SPhilip Rakity sdhci_readw(host, SDHCI_COMMAND), 1094e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_MAX_CURRENT)); 110a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 111f2119df6SArindam Nath sdhci_readw(host, SDHCI_HOST_CONTROL2)); 1121c6a0718SPierre Ossman 113be3f4ae0SBen Dooks if (host->flags & SDHCI_USE_ADMA) 114a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 115be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ERROR), 116be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 117be3f4ae0SBen Dooks 118a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ===========================================\n"); 1191c6a0718SPierre Ossman } 1201c6a0718SPierre Ossman 1211c6a0718SPierre Ossman /*****************************************************************************\ 1221c6a0718SPierre Ossman * * 1231c6a0718SPierre Ossman * Low level functions * 1241c6a0718SPierre Ossman * * 1251c6a0718SPierre Ossman \*****************************************************************************/ 1261c6a0718SPierre Ossman 1277260cf5eSAnton Vorontsov static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 1287260cf5eSAnton Vorontsov { 1297260cf5eSAnton Vorontsov u32 ier; 1307260cf5eSAnton Vorontsov 1317260cf5eSAnton Vorontsov ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1327260cf5eSAnton Vorontsov ier &= ~clear; 1337260cf5eSAnton Vorontsov ier |= set; 1347260cf5eSAnton Vorontsov sdhci_writel(host, ier, SDHCI_INT_ENABLE); 1357260cf5eSAnton Vorontsov sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 1367260cf5eSAnton Vorontsov } 1377260cf5eSAnton Vorontsov 1387260cf5eSAnton Vorontsov static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 1397260cf5eSAnton Vorontsov { 1407260cf5eSAnton Vorontsov sdhci_clear_set_irqs(host, 0, irqs); 1417260cf5eSAnton Vorontsov } 1427260cf5eSAnton Vorontsov 1437260cf5eSAnton Vorontsov static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 1447260cf5eSAnton Vorontsov { 1457260cf5eSAnton Vorontsov sdhci_clear_set_irqs(host, irqs, 0); 1467260cf5eSAnton Vorontsov } 1477260cf5eSAnton Vorontsov 1487260cf5eSAnton Vorontsov static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 1497260cf5eSAnton Vorontsov { 150d25928d1SShawn Guo u32 present, irqs; 1517260cf5eSAnton Vorontsov 152c79396c1SAdrian Hunter if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 15387b87a3fSDaniel Drake (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 15466fd8ad5SAdrian Hunter return; 15566fd8ad5SAdrian Hunter 156d25928d1SShawn Guo present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 157d25928d1SShawn Guo SDHCI_CARD_PRESENT; 158d25928d1SShawn Guo irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; 159d25928d1SShawn Guo 1607260cf5eSAnton Vorontsov if (enable) 1617260cf5eSAnton Vorontsov sdhci_unmask_irqs(host, irqs); 1627260cf5eSAnton Vorontsov else 1637260cf5eSAnton Vorontsov sdhci_mask_irqs(host, irqs); 1647260cf5eSAnton Vorontsov } 1657260cf5eSAnton Vorontsov 1667260cf5eSAnton Vorontsov static void sdhci_enable_card_detection(struct sdhci_host *host) 1677260cf5eSAnton Vorontsov { 1687260cf5eSAnton Vorontsov sdhci_set_card_detection(host, true); 1697260cf5eSAnton Vorontsov } 1707260cf5eSAnton Vorontsov 1717260cf5eSAnton Vorontsov static void sdhci_disable_card_detection(struct sdhci_host *host) 1727260cf5eSAnton Vorontsov { 1737260cf5eSAnton Vorontsov sdhci_set_card_detection(host, false); 1747260cf5eSAnton Vorontsov } 1757260cf5eSAnton Vorontsov 1761c6a0718SPierre Ossman static void sdhci_reset(struct sdhci_host *host, u8 mask) 1771c6a0718SPierre Ossman { 1781c6a0718SPierre Ossman unsigned long timeout; 179063a9dbbSAnton Vorontsov u32 uninitialized_var(ier); 1801c6a0718SPierre Ossman 181b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 1824e4141a5SAnton Vorontsov if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 1831c6a0718SPierre Ossman SDHCI_CARD_PRESENT)) 1841c6a0718SPierre Ossman return; 1851c6a0718SPierre Ossman } 1861c6a0718SPierre Ossman 187063a9dbbSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 188063a9dbbSAnton Vorontsov ier = sdhci_readl(host, SDHCI_INT_ENABLE); 189063a9dbbSAnton Vorontsov 190393c1a34SPhilip Rakity if (host->ops->platform_reset_enter) 191393c1a34SPhilip Rakity host->ops->platform_reset_enter(host, mask); 192393c1a34SPhilip Rakity 1934e4141a5SAnton Vorontsov sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1941c6a0718SPierre Ossman 1951c6a0718SPierre Ossman if (mask & SDHCI_RESET_ALL) 1961c6a0718SPierre Ossman host->clock = 0; 1971c6a0718SPierre Ossman 1981c6a0718SPierre Ossman /* Wait max 100 ms */ 1991c6a0718SPierre Ossman timeout = 100; 2001c6a0718SPierre Ossman 2011c6a0718SPierre Ossman /* hw clears the bit when it's done */ 2024e4141a5SAnton Vorontsov while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 2031c6a0718SPierre Ossman if (timeout == 0) { 204a3c76eb9SGirish K S pr_err("%s: Reset 0x%x never completed.\n", 2051c6a0718SPierre Ossman mmc_hostname(host->mmc), (int)mask); 2061c6a0718SPierre Ossman sdhci_dumpregs(host); 2071c6a0718SPierre Ossman return; 2081c6a0718SPierre Ossman } 2091c6a0718SPierre Ossman timeout--; 2101c6a0718SPierre Ossman mdelay(1); 2111c6a0718SPierre Ossman } 212063a9dbbSAnton Vorontsov 213393c1a34SPhilip Rakity if (host->ops->platform_reset_exit) 214393c1a34SPhilip Rakity host->ops->platform_reset_exit(host, mask); 215393c1a34SPhilip Rakity 216063a9dbbSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 217063a9dbbSAnton Vorontsov sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 2183abc1e80SShaohui Xie 2193abc1e80SShaohui Xie if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2203abc1e80SShaohui Xie if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) 2213abc1e80SShaohui Xie host->ops->enable_dma(host); 2223abc1e80SShaohui Xie } 2231c6a0718SPierre Ossman } 2241c6a0718SPierre Ossman 2252f4cbb3dSNicolas Pitre static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 2262f4cbb3dSNicolas Pitre 2272f4cbb3dSNicolas Pitre static void sdhci_init(struct sdhci_host *host, int soft) 2281c6a0718SPierre Ossman { 2292f4cbb3dSNicolas Pitre if (soft) 2302f4cbb3dSNicolas Pitre sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 2312f4cbb3dSNicolas Pitre else 2321c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 2331c6a0718SPierre Ossman 2347260cf5eSAnton Vorontsov sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 2357260cf5eSAnton Vorontsov SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 2361c6a0718SPierre Ossman SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 2371c6a0718SPierre Ossman SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 2386aa943abSAnton Vorontsov SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 2392f4cbb3dSNicolas Pitre 2402f4cbb3dSNicolas Pitre if (soft) { 2412f4cbb3dSNicolas Pitre /* force clock reconfiguration */ 2422f4cbb3dSNicolas Pitre host->clock = 0; 2432f4cbb3dSNicolas Pitre sdhci_set_ios(host->mmc, &host->mmc->ios); 2442f4cbb3dSNicolas Pitre } 2457260cf5eSAnton Vorontsov } 2461c6a0718SPierre Ossman 2477260cf5eSAnton Vorontsov static void sdhci_reinit(struct sdhci_host *host) 2487260cf5eSAnton Vorontsov { 2492f4cbb3dSNicolas Pitre sdhci_init(host, 0); 250b67c6b41SAaron Lu /* 251b67c6b41SAaron Lu * Retuning stuffs are affected by different cards inserted and only 252b67c6b41SAaron Lu * applicable to UHS-I cards. So reset these fields to their initial 253b67c6b41SAaron Lu * value when card is removed. 254b67c6b41SAaron Lu */ 255973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 256973905feSAaron Lu host->flags &= ~SDHCI_USING_RETUNING_TIMER; 257973905feSAaron Lu 258b67c6b41SAaron Lu del_timer_sync(&host->tuning_timer); 259b67c6b41SAaron Lu host->flags &= ~SDHCI_NEEDS_RETUNING; 260b67c6b41SAaron Lu host->mmc->max_blk_count = 261b67c6b41SAaron Lu (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 262b67c6b41SAaron Lu } 2637260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 2641c6a0718SPierre Ossman } 2651c6a0718SPierre Ossman 2661c6a0718SPierre Ossman static void sdhci_activate_led(struct sdhci_host *host) 2671c6a0718SPierre Ossman { 2681c6a0718SPierre Ossman u8 ctrl; 2691c6a0718SPierre Ossman 2704e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2711c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_LED; 2724e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2731c6a0718SPierre Ossman } 2741c6a0718SPierre Ossman 2751c6a0718SPierre Ossman static void sdhci_deactivate_led(struct sdhci_host *host) 2761c6a0718SPierre Ossman { 2771c6a0718SPierre Ossman u8 ctrl; 2781c6a0718SPierre Ossman 2794e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2801c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_LED; 2814e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2821c6a0718SPierre Ossman } 2831c6a0718SPierre Ossman 284f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 2852f730fecSPierre Ossman static void sdhci_led_control(struct led_classdev *led, 2862f730fecSPierre Ossman enum led_brightness brightness) 2872f730fecSPierre Ossman { 2882f730fecSPierre Ossman struct sdhci_host *host = container_of(led, struct sdhci_host, led); 2892f730fecSPierre Ossman unsigned long flags; 2902f730fecSPierre Ossman 2912f730fecSPierre Ossman spin_lock_irqsave(&host->lock, flags); 2922f730fecSPierre Ossman 29366fd8ad5SAdrian Hunter if (host->runtime_suspended) 29466fd8ad5SAdrian Hunter goto out; 29566fd8ad5SAdrian Hunter 2962f730fecSPierre Ossman if (brightness == LED_OFF) 2972f730fecSPierre Ossman sdhci_deactivate_led(host); 2982f730fecSPierre Ossman else 2992f730fecSPierre Ossman sdhci_activate_led(host); 30066fd8ad5SAdrian Hunter out: 3012f730fecSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 3022f730fecSPierre Ossman } 3032f730fecSPierre Ossman #endif 3042f730fecSPierre Ossman 3051c6a0718SPierre Ossman /*****************************************************************************\ 3061c6a0718SPierre Ossman * * 3071c6a0718SPierre Ossman * Core functions * 3081c6a0718SPierre Ossman * * 3091c6a0718SPierre Ossman \*****************************************************************************/ 3101c6a0718SPierre Ossman 3111c6a0718SPierre Ossman static void sdhci_read_block_pio(struct sdhci_host *host) 3121c6a0718SPierre Ossman { 3137659150cSPierre Ossman unsigned long flags; 3147659150cSPierre Ossman size_t blksize, len, chunk; 3157244b85bSSteven Noonan u32 uninitialized_var(scratch); 3167659150cSPierre Ossman u8 *buf; 3171c6a0718SPierre Ossman 3181c6a0718SPierre Ossman DBG("PIO reading\n"); 3191c6a0718SPierre Ossman 3201c6a0718SPierre Ossman blksize = host->data->blksz; 3217659150cSPierre Ossman chunk = 0; 3221c6a0718SPierre Ossman 3237659150cSPierre Ossman local_irq_save(flags); 3241c6a0718SPierre Ossman 3251c6a0718SPierre Ossman while (blksize) { 3267659150cSPierre Ossman if (!sg_miter_next(&host->sg_miter)) 3277659150cSPierre Ossman BUG(); 3287659150cSPierre Ossman 3297659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3307659150cSPierre Ossman 3317659150cSPierre Ossman blksize -= len; 3327659150cSPierre Ossman host->sg_miter.consumed = len; 3337659150cSPierre Ossman 3347659150cSPierre Ossman buf = host->sg_miter.addr; 3357659150cSPierre Ossman 3367659150cSPierre Ossman while (len) { 3377659150cSPierre Ossman if (chunk == 0) { 3384e4141a5SAnton Vorontsov scratch = sdhci_readl(host, SDHCI_BUFFER); 3397659150cSPierre Ossman chunk = 4; 3401c6a0718SPierre Ossman } 3411c6a0718SPierre Ossman 3427659150cSPierre Ossman *buf = scratch & 0xFF; 3431c6a0718SPierre Ossman 3447659150cSPierre Ossman buf++; 3457659150cSPierre Ossman scratch >>= 8; 3467659150cSPierre Ossman chunk--; 3477659150cSPierre Ossman len--; 3487659150cSPierre Ossman } 3491c6a0718SPierre Ossman } 3501c6a0718SPierre Ossman 3517659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3527659150cSPierre Ossman 3537659150cSPierre Ossman local_irq_restore(flags); 3541c6a0718SPierre Ossman } 3551c6a0718SPierre Ossman 3561c6a0718SPierre Ossman static void sdhci_write_block_pio(struct sdhci_host *host) 3571c6a0718SPierre Ossman { 3587659150cSPierre Ossman unsigned long flags; 3597659150cSPierre Ossman size_t blksize, len, chunk; 3607659150cSPierre Ossman u32 scratch; 3617659150cSPierre Ossman u8 *buf; 3621c6a0718SPierre Ossman 3631c6a0718SPierre Ossman DBG("PIO writing\n"); 3641c6a0718SPierre Ossman 3651c6a0718SPierre Ossman blksize = host->data->blksz; 3667659150cSPierre Ossman chunk = 0; 3677659150cSPierre Ossman scratch = 0; 3681c6a0718SPierre Ossman 3697659150cSPierre Ossman local_irq_save(flags); 3701c6a0718SPierre Ossman 3711c6a0718SPierre Ossman while (blksize) { 3727659150cSPierre Ossman if (!sg_miter_next(&host->sg_miter)) 3737659150cSPierre Ossman BUG(); 3741c6a0718SPierre Ossman 3757659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3761c6a0718SPierre Ossman 3777659150cSPierre Ossman blksize -= len; 3787659150cSPierre Ossman host->sg_miter.consumed = len; 3797659150cSPierre Ossman 3807659150cSPierre Ossman buf = host->sg_miter.addr; 3817659150cSPierre Ossman 3827659150cSPierre Ossman while (len) { 3837659150cSPierre Ossman scratch |= (u32)*buf << (chunk * 8); 3847659150cSPierre Ossman 3857659150cSPierre Ossman buf++; 3867659150cSPierre Ossman chunk++; 3877659150cSPierre Ossman len--; 3887659150cSPierre Ossman 3897659150cSPierre Ossman if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 3904e4141a5SAnton Vorontsov sdhci_writel(host, scratch, SDHCI_BUFFER); 3917659150cSPierre Ossman chunk = 0; 3927659150cSPierre Ossman scratch = 0; 3937659150cSPierre Ossman } 3947659150cSPierre Ossman } 3951c6a0718SPierre Ossman } 3961c6a0718SPierre Ossman 3977659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3981c6a0718SPierre Ossman 3997659150cSPierre Ossman local_irq_restore(flags); 4001c6a0718SPierre Ossman } 4011c6a0718SPierre Ossman 4021c6a0718SPierre Ossman static void sdhci_transfer_pio(struct sdhci_host *host) 4031c6a0718SPierre Ossman { 4041c6a0718SPierre Ossman u32 mask; 4051c6a0718SPierre Ossman 4061c6a0718SPierre Ossman BUG_ON(!host->data); 4071c6a0718SPierre Ossman 4087659150cSPierre Ossman if (host->blocks == 0) 4091c6a0718SPierre Ossman return; 4101c6a0718SPierre Ossman 4111c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4121c6a0718SPierre Ossman mask = SDHCI_DATA_AVAILABLE; 4131c6a0718SPierre Ossman else 4141c6a0718SPierre Ossman mask = SDHCI_SPACE_AVAILABLE; 4151c6a0718SPierre Ossman 4164a3cba32SPierre Ossman /* 4174a3cba32SPierre Ossman * Some controllers (JMicron JMB38x) mess up the buffer bits 4184a3cba32SPierre Ossman * for transfers < 4 bytes. As long as it is just one block, 4194a3cba32SPierre Ossman * we can ignore the bits. 4204a3cba32SPierre Ossman */ 4214a3cba32SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 4224a3cba32SPierre Ossman (host->data->blocks == 1)) 4234a3cba32SPierre Ossman mask = ~0; 4244a3cba32SPierre Ossman 4254e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 4263e3bf207SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 4273e3bf207SAnton Vorontsov udelay(100); 4283e3bf207SAnton Vorontsov 4291c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4301c6a0718SPierre Ossman sdhci_read_block_pio(host); 4311c6a0718SPierre Ossman else 4321c6a0718SPierre Ossman sdhci_write_block_pio(host); 4331c6a0718SPierre Ossman 4347659150cSPierre Ossman host->blocks--; 4357659150cSPierre Ossman if (host->blocks == 0) 4361c6a0718SPierre Ossman break; 4371c6a0718SPierre Ossman } 4381c6a0718SPierre Ossman 4391c6a0718SPierre Ossman DBG("PIO transfer complete.\n"); 4401c6a0718SPierre Ossman } 4411c6a0718SPierre Ossman 4422134a922SPierre Ossman static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 4432134a922SPierre Ossman { 4442134a922SPierre Ossman local_irq_save(*flags); 445482fce99SCong Wang return kmap_atomic(sg_page(sg)) + sg->offset; 4462134a922SPierre Ossman } 4472134a922SPierre Ossman 4482134a922SPierre Ossman static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 4492134a922SPierre Ossman { 450482fce99SCong Wang kunmap_atomic(buffer); 4512134a922SPierre Ossman local_irq_restore(*flags); 4522134a922SPierre Ossman } 4532134a922SPierre Ossman 454118cd17dSBen Dooks static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 455118cd17dSBen Dooks { 4569e506f35SBen Dooks __le32 *dataddr = (__le32 __force *)(desc + 4); 4579e506f35SBen Dooks __le16 *cmdlen = (__le16 __force *)desc; 458118cd17dSBen Dooks 4599e506f35SBen Dooks /* SDHCI specification says ADMA descriptors should be 4 byte 4609e506f35SBen Dooks * aligned, so using 16 or 32bit operations should be safe. */ 461118cd17dSBen Dooks 4629e506f35SBen Dooks cmdlen[0] = cpu_to_le16(cmd); 4639e506f35SBen Dooks cmdlen[1] = cpu_to_le16(len); 4649e506f35SBen Dooks 4659e506f35SBen Dooks dataddr[0] = cpu_to_le32(addr); 466118cd17dSBen Dooks } 467118cd17dSBen Dooks 4688f1934ceSPierre Ossman static int sdhci_adma_table_pre(struct sdhci_host *host, 4692134a922SPierre Ossman struct mmc_data *data) 4702134a922SPierre Ossman { 4712134a922SPierre Ossman int direction; 4722134a922SPierre Ossman 4732134a922SPierre Ossman u8 *desc; 4742134a922SPierre Ossman u8 *align; 4752134a922SPierre Ossman dma_addr_t addr; 4762134a922SPierre Ossman dma_addr_t align_addr; 4772134a922SPierre Ossman int len, offset; 4782134a922SPierre Ossman 4792134a922SPierre Ossman struct scatterlist *sg; 4802134a922SPierre Ossman int i; 4812134a922SPierre Ossman char *buffer; 4822134a922SPierre Ossman unsigned long flags; 4832134a922SPierre Ossman 4842134a922SPierre Ossman /* 4852134a922SPierre Ossman * The spec does not specify endianness of descriptor table. 4862134a922SPierre Ossman * We currently guess that it is LE. 4872134a922SPierre Ossman */ 4882134a922SPierre Ossman 4892134a922SPierre Ossman if (data->flags & MMC_DATA_READ) 4902134a922SPierre Ossman direction = DMA_FROM_DEVICE; 4912134a922SPierre Ossman else 4922134a922SPierre Ossman direction = DMA_TO_DEVICE; 4932134a922SPierre Ossman 4942134a922SPierre Ossman /* 4952134a922SPierre Ossman * The ADMA descriptor table is mapped further down as we 4962134a922SPierre Ossman * need to fill it with data first. 4972134a922SPierre Ossman */ 4982134a922SPierre Ossman 4992134a922SPierre Ossman host->align_addr = dma_map_single(mmc_dev(host->mmc), 5002134a922SPierre Ossman host->align_buffer, 128 * 4, direction); 5018d8bb39bSFUJITA Tomonori if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 5028f1934ceSPierre Ossman goto fail; 5032134a922SPierre Ossman BUG_ON(host->align_addr & 0x3); 5042134a922SPierre Ossman 5052134a922SPierre Ossman host->sg_count = dma_map_sg(mmc_dev(host->mmc), 5062134a922SPierre Ossman data->sg, data->sg_len, direction); 5078f1934ceSPierre Ossman if (host->sg_count == 0) 5088f1934ceSPierre Ossman goto unmap_align; 5092134a922SPierre Ossman 5102134a922SPierre Ossman desc = host->adma_desc; 5112134a922SPierre Ossman align = host->align_buffer; 5122134a922SPierre Ossman 5132134a922SPierre Ossman align_addr = host->align_addr; 5142134a922SPierre Ossman 5152134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 5162134a922SPierre Ossman addr = sg_dma_address(sg); 5172134a922SPierre Ossman len = sg_dma_len(sg); 5182134a922SPierre Ossman 5192134a922SPierre Ossman /* 5202134a922SPierre Ossman * The SDHCI specification states that ADMA 5212134a922SPierre Ossman * addresses must be 32-bit aligned. If they 5222134a922SPierre Ossman * aren't, then we use a bounce buffer for 5232134a922SPierre Ossman * the (up to three) bytes that screw up the 5242134a922SPierre Ossman * alignment. 5252134a922SPierre Ossman */ 5262134a922SPierre Ossman offset = (4 - (addr & 0x3)) & 0x3; 5272134a922SPierre Ossman if (offset) { 5282134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5292134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 5306cefd05fSPierre Ossman WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 5312134a922SPierre Ossman memcpy(align, buffer, offset); 5322134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 5332134a922SPierre Ossman } 5342134a922SPierre Ossman 535118cd17dSBen Dooks /* tran, valid */ 536118cd17dSBen Dooks sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 5372134a922SPierre Ossman 5382134a922SPierre Ossman BUG_ON(offset > 65536); 5392134a922SPierre Ossman 5402134a922SPierre Ossman align += 4; 5412134a922SPierre Ossman align_addr += 4; 5422134a922SPierre Ossman 5432134a922SPierre Ossman desc += 8; 5442134a922SPierre Ossman 5452134a922SPierre Ossman addr += offset; 5462134a922SPierre Ossman len -= offset; 5472134a922SPierre Ossman } 5482134a922SPierre Ossman 5492134a922SPierre Ossman BUG_ON(len > 65536); 5502134a922SPierre Ossman 551118cd17dSBen Dooks /* tran, valid */ 552118cd17dSBen Dooks sdhci_set_adma_desc(desc, addr, len, 0x21); 5532134a922SPierre Ossman desc += 8; 5542134a922SPierre Ossman 5552134a922SPierre Ossman /* 5562134a922SPierre Ossman * If this triggers then we have a calculation bug 5572134a922SPierre Ossman * somewhere. :/ 5582134a922SPierre Ossman */ 5592134a922SPierre Ossman WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 5602134a922SPierre Ossman } 5612134a922SPierre Ossman 56270764a90SThomas Abraham if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 56370764a90SThomas Abraham /* 56470764a90SThomas Abraham * Mark the last descriptor as the terminating descriptor 56570764a90SThomas Abraham */ 56670764a90SThomas Abraham if (desc != host->adma_desc) { 56770764a90SThomas Abraham desc -= 8; 56870764a90SThomas Abraham desc[0] |= 0x2; /* end */ 56970764a90SThomas Abraham } 57070764a90SThomas Abraham } else { 5712134a922SPierre Ossman /* 5722134a922SPierre Ossman * Add a terminating entry. 5732134a922SPierre Ossman */ 5742134a922SPierre Ossman 575118cd17dSBen Dooks /* nop, end, valid */ 576118cd17dSBen Dooks sdhci_set_adma_desc(desc, 0, 0, 0x3); 57770764a90SThomas Abraham } 5782134a922SPierre Ossman 5792134a922SPierre Ossman /* 5802134a922SPierre Ossman * Resync align buffer as we might have changed it. 5812134a922SPierre Ossman */ 5822134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5832134a922SPierre Ossman dma_sync_single_for_device(mmc_dev(host->mmc), 5842134a922SPierre Ossman host->align_addr, 128 * 4, direction); 5852134a922SPierre Ossman } 5862134a922SPierre Ossman 5872134a922SPierre Ossman host->adma_addr = dma_map_single(mmc_dev(host->mmc), 5882134a922SPierre Ossman host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 589980167b7SPierre Ossman if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 5908f1934ceSPierre Ossman goto unmap_entries; 5912134a922SPierre Ossman BUG_ON(host->adma_addr & 0x3); 5928f1934ceSPierre Ossman 5938f1934ceSPierre Ossman return 0; 5948f1934ceSPierre Ossman 5958f1934ceSPierre Ossman unmap_entries: 5968f1934ceSPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 5978f1934ceSPierre Ossman data->sg_len, direction); 5988f1934ceSPierre Ossman unmap_align: 5998f1934ceSPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 6008f1934ceSPierre Ossman 128 * 4, direction); 6018f1934ceSPierre Ossman fail: 6028f1934ceSPierre Ossman return -EINVAL; 6032134a922SPierre Ossman } 6042134a922SPierre Ossman 6052134a922SPierre Ossman static void sdhci_adma_table_post(struct sdhci_host *host, 6062134a922SPierre Ossman struct mmc_data *data) 6072134a922SPierre Ossman { 6082134a922SPierre Ossman int direction; 6092134a922SPierre Ossman 6102134a922SPierre Ossman struct scatterlist *sg; 6112134a922SPierre Ossman int i, size; 6122134a922SPierre Ossman u8 *align; 6132134a922SPierre Ossman char *buffer; 6142134a922SPierre Ossman unsigned long flags; 6152134a922SPierre Ossman 6162134a922SPierre Ossman if (data->flags & MMC_DATA_READ) 6172134a922SPierre Ossman direction = DMA_FROM_DEVICE; 6182134a922SPierre Ossman else 6192134a922SPierre Ossman direction = DMA_TO_DEVICE; 6202134a922SPierre Ossman 6212134a922SPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 6222134a922SPierre Ossman (128 * 2 + 1) * 4, DMA_TO_DEVICE); 6232134a922SPierre Ossman 6242134a922SPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 6252134a922SPierre Ossman 128 * 4, direction); 6262134a922SPierre Ossman 6272134a922SPierre Ossman if (data->flags & MMC_DATA_READ) { 6282134a922SPierre Ossman dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 6292134a922SPierre Ossman data->sg_len, direction); 6302134a922SPierre Ossman 6312134a922SPierre Ossman align = host->align_buffer; 6322134a922SPierre Ossman 6332134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 6342134a922SPierre Ossman if (sg_dma_address(sg) & 0x3) { 6352134a922SPierre Ossman size = 4 - (sg_dma_address(sg) & 0x3); 6362134a922SPierre Ossman 6372134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 6386cefd05fSPierre Ossman WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 6392134a922SPierre Ossman memcpy(buffer, align, size); 6402134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 6412134a922SPierre Ossman 6422134a922SPierre Ossman align += 4; 6432134a922SPierre Ossman } 6442134a922SPierre Ossman } 6452134a922SPierre Ossman } 6462134a922SPierre Ossman 6472134a922SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 6482134a922SPierre Ossman data->sg_len, direction); 6492134a922SPierre Ossman } 6502134a922SPierre Ossman 651a3c7778fSAndrei Warkentin static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 6521c6a0718SPierre Ossman { 6531c6a0718SPierre Ossman u8 count; 654a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 6551c6a0718SPierre Ossman unsigned target_timeout, current_timeout; 6561c6a0718SPierre Ossman 657ee53ab5dSPierre Ossman /* 658ee53ab5dSPierre Ossman * If the host controller provides us with an incorrect timeout 659ee53ab5dSPierre Ossman * value, just skip the check and use 0xE. The hardware may take 660ee53ab5dSPierre Ossman * longer to time out, but that's much better than having a too-short 661ee53ab5dSPierre Ossman * timeout value. 662ee53ab5dSPierre Ossman */ 66311a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 664ee53ab5dSPierre Ossman return 0xE; 665e538fbe8SPierre Ossman 666a3c7778fSAndrei Warkentin /* Unspecified timeout, assume max */ 667a3c7778fSAndrei Warkentin if (!data && !cmd->cmd_timeout_ms) 668a3c7778fSAndrei Warkentin return 0xE; 669a3c7778fSAndrei Warkentin 6701c6a0718SPierre Ossman /* timeout in us */ 671a3c7778fSAndrei Warkentin if (!data) 672a3c7778fSAndrei Warkentin target_timeout = cmd->cmd_timeout_ms * 1000; 67378a2ca27SAndy Shevchenko else { 67478a2ca27SAndy Shevchenko target_timeout = data->timeout_ns / 1000; 67578a2ca27SAndy Shevchenko if (host->clock) 67678a2ca27SAndy Shevchenko target_timeout += data->timeout_clks / host->clock; 67778a2ca27SAndy Shevchenko } 6781c6a0718SPierre Ossman 6791c6a0718SPierre Ossman /* 6801c6a0718SPierre Ossman * Figure out needed cycles. 6811c6a0718SPierre Ossman * We do this in steps in order to fit inside a 32 bit int. 6821c6a0718SPierre Ossman * The first step is the minimum timeout, which will have a 6831c6a0718SPierre Ossman * minimum resolution of 6 bits: 6841c6a0718SPierre Ossman * (1) 2^13*1000 > 2^22, 6851c6a0718SPierre Ossman * (2) host->timeout_clk < 2^16 6861c6a0718SPierre Ossman * => 6871c6a0718SPierre Ossman * (1) / (2) > 2^6 6881c6a0718SPierre Ossman */ 6891c6a0718SPierre Ossman count = 0; 6901c6a0718SPierre Ossman current_timeout = (1 << 13) * 1000 / host->timeout_clk; 6911c6a0718SPierre Ossman while (current_timeout < target_timeout) { 6921c6a0718SPierre Ossman count++; 6931c6a0718SPierre Ossman current_timeout <<= 1; 6941c6a0718SPierre Ossman if (count >= 0xF) 6951c6a0718SPierre Ossman break; 6961c6a0718SPierre Ossman } 6971c6a0718SPierre Ossman 6981c6a0718SPierre Ossman if (count >= 0xF) { 69909eeff52SChris Ball DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 70002145977SMark Brown mmc_hostname(host->mmc), count, cmd->opcode); 7011c6a0718SPierre Ossman count = 0xE; 7021c6a0718SPierre Ossman } 7031c6a0718SPierre Ossman 704ee53ab5dSPierre Ossman return count; 705ee53ab5dSPierre Ossman } 706ee53ab5dSPierre Ossman 7076aa943abSAnton Vorontsov static void sdhci_set_transfer_irqs(struct sdhci_host *host) 7086aa943abSAnton Vorontsov { 7096aa943abSAnton Vorontsov u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 7106aa943abSAnton Vorontsov u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 7116aa943abSAnton Vorontsov 7126aa943abSAnton Vorontsov if (host->flags & SDHCI_REQ_USE_DMA) 7136aa943abSAnton Vorontsov sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 7146aa943abSAnton Vorontsov else 7156aa943abSAnton Vorontsov sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 7166aa943abSAnton Vorontsov } 7176aa943abSAnton Vorontsov 718a3c7778fSAndrei Warkentin static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 719ee53ab5dSPierre Ossman { 720ee53ab5dSPierre Ossman u8 count; 7212134a922SPierre Ossman u8 ctrl; 722a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 7238f1934ceSPierre Ossman int ret; 724ee53ab5dSPierre Ossman 725ee53ab5dSPierre Ossman WARN_ON(host->data); 726ee53ab5dSPierre Ossman 727a3c7778fSAndrei Warkentin if (data || (cmd->flags & MMC_RSP_BUSY)) { 728a3c7778fSAndrei Warkentin count = sdhci_calc_timeout(host, cmd); 729a3c7778fSAndrei Warkentin sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 730a3c7778fSAndrei Warkentin } 731a3c7778fSAndrei Warkentin 732a3c7778fSAndrei Warkentin if (!data) 733ee53ab5dSPierre Ossman return; 734ee53ab5dSPierre Ossman 735ee53ab5dSPierre Ossman /* Sanity checks */ 736ee53ab5dSPierre Ossman BUG_ON(data->blksz * data->blocks > 524288); 737ee53ab5dSPierre Ossman BUG_ON(data->blksz > host->mmc->max_blk_size); 738ee53ab5dSPierre Ossman BUG_ON(data->blocks > 65535); 739ee53ab5dSPierre Ossman 740ee53ab5dSPierre Ossman host->data = data; 741ee53ab5dSPierre Ossman host->data_early = 0; 742f6a03cbfSMikko Vinni host->data->bytes_xfered = 0; 743ee53ab5dSPierre Ossman 744a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 745c9fddbc4SPierre Ossman host->flags |= SDHCI_REQ_USE_DMA; 746c9fddbc4SPierre Ossman 7472134a922SPierre Ossman /* 7482134a922SPierre Ossman * FIXME: This doesn't account for merging when mapping the 7492134a922SPierre Ossman * scatterlist. 7502134a922SPierre Ossman */ 7512134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7522134a922SPierre Ossman int broken, i; 7532134a922SPierre Ossman struct scatterlist *sg; 7542134a922SPierre Ossman 7552134a922SPierre Ossman broken = 0; 7562134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7572134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7582134a922SPierre Ossman broken = 1; 7592134a922SPierre Ossman } else { 7602134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 7612134a922SPierre Ossman broken = 1; 7622134a922SPierre Ossman } 7632134a922SPierre Ossman 7642134a922SPierre Ossman if (unlikely(broken)) { 7652134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 7662134a922SPierre Ossman if (sg->length & 0x3) { 7672134a922SPierre Ossman DBG("Reverting to PIO because of " 7682134a922SPierre Ossman "transfer size (%d)\n", 7692134a922SPierre Ossman sg->length); 770c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 7712134a922SPierre Ossman break; 7722134a922SPierre Ossman } 7732134a922SPierre Ossman } 7742134a922SPierre Ossman } 775c9fddbc4SPierre Ossman } 776c9fddbc4SPierre Ossman 777c9fddbc4SPierre Ossman /* 778c9fddbc4SPierre Ossman * The assumption here being that alignment is the same after 779c9fddbc4SPierre Ossman * translation to device address space. 780c9fddbc4SPierre Ossman */ 7812134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7822134a922SPierre Ossman int broken, i; 7832134a922SPierre Ossman struct scatterlist *sg; 7842134a922SPierre Ossman 7852134a922SPierre Ossman broken = 0; 7862134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7872134a922SPierre Ossman /* 7882134a922SPierre Ossman * As we use 3 byte chunks to work around 7892134a922SPierre Ossman * alignment problems, we need to check this 7902134a922SPierre Ossman * quirk. 7912134a922SPierre Ossman */ 7922134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7932134a922SPierre Ossman broken = 1; 7942134a922SPierre Ossman } else { 7952134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 7962134a922SPierre Ossman broken = 1; 7972134a922SPierre Ossman } 7982134a922SPierre Ossman 7992134a922SPierre Ossman if (unlikely(broken)) { 8002134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 8012134a922SPierre Ossman if (sg->offset & 0x3) { 8022134a922SPierre Ossman DBG("Reverting to PIO because of " 8032134a922SPierre Ossman "bad alignment\n"); 804c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8052134a922SPierre Ossman break; 8062134a922SPierre Ossman } 8072134a922SPierre Ossman } 8082134a922SPierre Ossman } 8092134a922SPierre Ossman } 8102134a922SPierre Ossman 8118f1934ceSPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 8128f1934ceSPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 8138f1934ceSPierre Ossman ret = sdhci_adma_table_pre(host, data); 8148f1934ceSPierre Ossman if (ret) { 8158f1934ceSPierre Ossman /* 8168f1934ceSPierre Ossman * This only happens when someone fed 8178f1934ceSPierre Ossman * us an invalid request. 8188f1934ceSPierre Ossman */ 8198f1934ceSPierre Ossman WARN_ON(1); 820ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8218f1934ceSPierre Ossman } else { 8224e4141a5SAnton Vorontsov sdhci_writel(host, host->adma_addr, 8234e4141a5SAnton Vorontsov SDHCI_ADMA_ADDRESS); 8248f1934ceSPierre Ossman } 8258f1934ceSPierre Ossman } else { 826c8b3e02eSTomas Winkler int sg_cnt; 8278f1934ceSPierre Ossman 828c8b3e02eSTomas Winkler sg_cnt = dma_map_sg(mmc_dev(host->mmc), 8298f1934ceSPierre Ossman data->sg, data->sg_len, 8308f1934ceSPierre Ossman (data->flags & MMC_DATA_READ) ? 8318f1934ceSPierre Ossman DMA_FROM_DEVICE : 8328f1934ceSPierre Ossman DMA_TO_DEVICE); 833c8b3e02eSTomas Winkler if (sg_cnt == 0) { 8348f1934ceSPierre Ossman /* 8358f1934ceSPierre Ossman * This only happens when someone fed 8368f1934ceSPierre Ossman * us an invalid request. 8378f1934ceSPierre Ossman */ 8388f1934ceSPierre Ossman WARN_ON(1); 839ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8408f1934ceSPierre Ossman } else { 841719a61b4SPierre Ossman WARN_ON(sg_cnt != 1); 8424e4141a5SAnton Vorontsov sdhci_writel(host, sg_dma_address(data->sg), 8434e4141a5SAnton Vorontsov SDHCI_DMA_ADDRESS); 8448f1934ceSPierre Ossman } 8458f1934ceSPierre Ossman } 8468f1934ceSPierre Ossman } 8478f1934ceSPierre Ossman 8482134a922SPierre Ossman /* 8492134a922SPierre Ossman * Always adjust the DMA selection as some controllers 8502134a922SPierre Ossman * (e.g. JMicron) can't do PIO properly when the selection 8512134a922SPierre Ossman * is ADMA. 8522134a922SPierre Ossman */ 8532134a922SPierre Ossman if (host->version >= SDHCI_SPEC_200) { 8544e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 8552134a922SPierre Ossman ctrl &= ~SDHCI_CTRL_DMA_MASK; 8562134a922SPierre Ossman if ((host->flags & SDHCI_REQ_USE_DMA) && 8572134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) 8582134a922SPierre Ossman ctrl |= SDHCI_CTRL_ADMA32; 8592134a922SPierre Ossman else 8602134a922SPierre Ossman ctrl |= SDHCI_CTRL_SDMA; 8614e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 862c9fddbc4SPierre Ossman } 863c9fddbc4SPierre Ossman 8648f1934ceSPierre Ossman if (!(host->flags & SDHCI_REQ_USE_DMA)) { 865da60a91dSSebastian Andrzej Siewior int flags; 866da60a91dSSebastian Andrzej Siewior 867da60a91dSSebastian Andrzej Siewior flags = SG_MITER_ATOMIC; 868da60a91dSSebastian Andrzej Siewior if (host->data->flags & MMC_DATA_READ) 869da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_TO_SG; 870da60a91dSSebastian Andrzej Siewior else 871da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_FROM_SG; 872da60a91dSSebastian Andrzej Siewior sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 8737659150cSPierre Ossman host->blocks = data->blocks; 8741c6a0718SPierre Ossman } 8751c6a0718SPierre Ossman 8766aa943abSAnton Vorontsov sdhci_set_transfer_irqs(host); 8776aa943abSAnton Vorontsov 878f6a03cbfSMikko Vinni /* Set the DMA boundary value and block size */ 879f6a03cbfSMikko Vinni sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 880f6a03cbfSMikko Vinni data->blksz), SDHCI_BLOCK_SIZE); 8814e4141a5SAnton Vorontsov sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 8821c6a0718SPierre Ossman } 8831c6a0718SPierre Ossman 8841c6a0718SPierre Ossman static void sdhci_set_transfer_mode(struct sdhci_host *host, 885e89d456fSAndrei Warkentin struct mmc_command *cmd) 8861c6a0718SPierre Ossman { 8871c6a0718SPierre Ossman u16 mode; 888e89d456fSAndrei Warkentin struct mmc_data *data = cmd->data; 8891c6a0718SPierre Ossman 8901c6a0718SPierre Ossman if (data == NULL) 8911c6a0718SPierre Ossman return; 8921c6a0718SPierre Ossman 893e538fbe8SPierre Ossman WARN_ON(!host->data); 894e538fbe8SPierre Ossman 8951c6a0718SPierre Ossman mode = SDHCI_TRNS_BLK_CNT_EN; 896e89d456fSAndrei Warkentin if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 8971c6a0718SPierre Ossman mode |= SDHCI_TRNS_MULTI; 898e89d456fSAndrei Warkentin /* 899e89d456fSAndrei Warkentin * If we are sending CMD23, CMD12 never gets sent 900e89d456fSAndrei Warkentin * on successful completion (so no Auto-CMD12). 901e89d456fSAndrei Warkentin */ 902e89d456fSAndrei Warkentin if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 903e89d456fSAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD12; 9048edf6371SAndrei Warkentin else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 9058edf6371SAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD23; 9068edf6371SAndrei Warkentin sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 907c4512f79SJerry Huang } 9088edf6371SAndrei Warkentin } 9098edf6371SAndrei Warkentin 9101c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 9111c6a0718SPierre Ossman mode |= SDHCI_TRNS_READ; 912c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) 9131c6a0718SPierre Ossman mode |= SDHCI_TRNS_DMA; 9141c6a0718SPierre Ossman 9154e4141a5SAnton Vorontsov sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 9161c6a0718SPierre Ossman } 9171c6a0718SPierre Ossman 9181c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *host) 9191c6a0718SPierre Ossman { 9201c6a0718SPierre Ossman struct mmc_data *data; 9211c6a0718SPierre Ossman 9221c6a0718SPierre Ossman BUG_ON(!host->data); 9231c6a0718SPierre Ossman 9241c6a0718SPierre Ossman data = host->data; 9251c6a0718SPierre Ossman host->data = NULL; 9261c6a0718SPierre Ossman 927c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 9282134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 9292134a922SPierre Ossman sdhci_adma_table_post(host, data); 9302134a922SPierre Ossman else { 9312134a922SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 9322134a922SPierre Ossman data->sg_len, (data->flags & MMC_DATA_READ) ? 933b8c86fc5SPierre Ossman DMA_FROM_DEVICE : DMA_TO_DEVICE); 9341c6a0718SPierre Ossman } 9352134a922SPierre Ossman } 9361c6a0718SPierre Ossman 9371c6a0718SPierre Ossman /* 938c9b74c5bSPierre Ossman * The specification states that the block count register must 939c9b74c5bSPierre Ossman * be updated, but it does not specify at what point in the 940c9b74c5bSPierre Ossman * data flow. That makes the register entirely useless to read 941c9b74c5bSPierre Ossman * back so we have to assume that nothing made it to the card 942c9b74c5bSPierre Ossman * in the event of an error. 9431c6a0718SPierre Ossman */ 944c9b74c5bSPierre Ossman if (data->error) 945c9b74c5bSPierre Ossman data->bytes_xfered = 0; 9461c6a0718SPierre Ossman else 947c9b74c5bSPierre Ossman data->bytes_xfered = data->blksz * data->blocks; 9481c6a0718SPierre Ossman 949e89d456fSAndrei Warkentin /* 950e89d456fSAndrei Warkentin * Need to send CMD12 if - 951e89d456fSAndrei Warkentin * a) open-ended multiblock transfer (no CMD23) 952e89d456fSAndrei Warkentin * b) error in multiblock transfer 953e89d456fSAndrei Warkentin */ 954e89d456fSAndrei Warkentin if (data->stop && 955e89d456fSAndrei Warkentin (data->error || 956e89d456fSAndrei Warkentin !host->mrq->sbc)) { 957e89d456fSAndrei Warkentin 9581c6a0718SPierre Ossman /* 9591c6a0718SPierre Ossman * The controller needs a reset of internal state machines 9601c6a0718SPierre Ossman * upon error conditions. 9611c6a0718SPierre Ossman */ 96217b0429dSPierre Ossman if (data->error) { 9631c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_CMD); 9641c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_DATA); 9651c6a0718SPierre Ossman } 9661c6a0718SPierre Ossman 9671c6a0718SPierre Ossman sdhci_send_command(host, data->stop); 9681c6a0718SPierre Ossman } else 9691c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 9701c6a0718SPierre Ossman } 9711c6a0718SPierre Ossman 9721c6a0718SPierre Ossman static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 9731c6a0718SPierre Ossman { 9741c6a0718SPierre Ossman int flags; 9751c6a0718SPierre Ossman u32 mask; 9761c6a0718SPierre Ossman unsigned long timeout; 9771c6a0718SPierre Ossman 9781c6a0718SPierre Ossman WARN_ON(host->cmd); 9791c6a0718SPierre Ossman 9801c6a0718SPierre Ossman /* Wait max 10 ms */ 9811c6a0718SPierre Ossman timeout = 10; 9821c6a0718SPierre Ossman 9831c6a0718SPierre Ossman mask = SDHCI_CMD_INHIBIT; 9841c6a0718SPierre Ossman if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 9851c6a0718SPierre Ossman mask |= SDHCI_DATA_INHIBIT; 9861c6a0718SPierre Ossman 9871c6a0718SPierre Ossman /* We shouldn't wait for data inihibit for stop commands, even 9881c6a0718SPierre Ossman though they might use busy signaling */ 9891c6a0718SPierre Ossman if (host->mrq->data && (cmd == host->mrq->data->stop)) 9901c6a0718SPierre Ossman mask &= ~SDHCI_DATA_INHIBIT; 9911c6a0718SPierre Ossman 9924e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 9931c6a0718SPierre Ossman if (timeout == 0) { 994a3c76eb9SGirish K S pr_err("%s: Controller never released " 9951c6a0718SPierre Ossman "inhibit bit(s).\n", mmc_hostname(host->mmc)); 9961c6a0718SPierre Ossman sdhci_dumpregs(host); 99717b0429dSPierre Ossman cmd->error = -EIO; 9981c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 9991c6a0718SPierre Ossman return; 10001c6a0718SPierre Ossman } 10011c6a0718SPierre Ossman timeout--; 10021c6a0718SPierre Ossman mdelay(1); 10031c6a0718SPierre Ossman } 10041c6a0718SPierre Ossman 10051c6a0718SPierre Ossman mod_timer(&host->timer, jiffies + 10 * HZ); 10061c6a0718SPierre Ossman 10071c6a0718SPierre Ossman host->cmd = cmd; 10081c6a0718SPierre Ossman 1009a3c7778fSAndrei Warkentin sdhci_prepare_data(host, cmd); 10101c6a0718SPierre Ossman 10114e4141a5SAnton Vorontsov sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 10121c6a0718SPierre Ossman 1013e89d456fSAndrei Warkentin sdhci_set_transfer_mode(host, cmd); 10141c6a0718SPierre Ossman 10151c6a0718SPierre Ossman if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1016a3c76eb9SGirish K S pr_err("%s: Unsupported response type!\n", 10171c6a0718SPierre Ossman mmc_hostname(host->mmc)); 101817b0429dSPierre Ossman cmd->error = -EINVAL; 10191c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10201c6a0718SPierre Ossman return; 10211c6a0718SPierre Ossman } 10221c6a0718SPierre Ossman 10231c6a0718SPierre Ossman if (!(cmd->flags & MMC_RSP_PRESENT)) 10241c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_NONE; 10251c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_136) 10261c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_LONG; 10271c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_BUSY) 10281c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT_BUSY; 10291c6a0718SPierre Ossman else 10301c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT; 10311c6a0718SPierre Ossman 10321c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_CRC) 10331c6a0718SPierre Ossman flags |= SDHCI_CMD_CRC; 10341c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_OPCODE) 10351c6a0718SPierre Ossman flags |= SDHCI_CMD_INDEX; 1036b513ea25SArindam Nath 1037b513ea25SArindam Nath /* CMD19 is special in that the Data Present Select should be set */ 1038069c9f14SGirish K S if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1039069c9f14SGirish K S cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 10401c6a0718SPierre Ossman flags |= SDHCI_CMD_DATA; 10411c6a0718SPierre Ossman 10424e4141a5SAnton Vorontsov sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 10431c6a0718SPierre Ossman } 10441c6a0718SPierre Ossman 10451c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *host) 10461c6a0718SPierre Ossman { 10471c6a0718SPierre Ossman int i; 10481c6a0718SPierre Ossman 10491c6a0718SPierre Ossman BUG_ON(host->cmd == NULL); 10501c6a0718SPierre Ossman 10511c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_PRESENT) { 10521c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_136) { 10531c6a0718SPierre Ossman /* CRC is stripped so we need to do some shifting. */ 10541c6a0718SPierre Ossman for (i = 0;i < 4;i++) { 10554e4141a5SAnton Vorontsov host->cmd->resp[i] = sdhci_readl(host, 10561c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4) << 8; 10571c6a0718SPierre Ossman if (i != 3) 10581c6a0718SPierre Ossman host->cmd->resp[i] |= 10594e4141a5SAnton Vorontsov sdhci_readb(host, 10601c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4-1); 10611c6a0718SPierre Ossman } 10621c6a0718SPierre Ossman } else { 10634e4141a5SAnton Vorontsov host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 10641c6a0718SPierre Ossman } 10651c6a0718SPierre Ossman } 10661c6a0718SPierre Ossman 106717b0429dSPierre Ossman host->cmd->error = 0; 10681c6a0718SPierre Ossman 1069e89d456fSAndrei Warkentin /* Finished CMD23, now send actual command. */ 1070e89d456fSAndrei Warkentin if (host->cmd == host->mrq->sbc) { 1071e89d456fSAndrei Warkentin host->cmd = NULL; 1072e89d456fSAndrei Warkentin sdhci_send_command(host, host->mrq->cmd); 1073e89d456fSAndrei Warkentin } else { 1074e89d456fSAndrei Warkentin 1075e89d456fSAndrei Warkentin /* Processed actual command. */ 1076e538fbe8SPierre Ossman if (host->data && host->data_early) 1077e538fbe8SPierre Ossman sdhci_finish_data(host); 1078e538fbe8SPierre Ossman 1079e538fbe8SPierre Ossman if (!host->cmd->data) 10801c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10811c6a0718SPierre Ossman 10821c6a0718SPierre Ossman host->cmd = NULL; 10831c6a0718SPierre Ossman } 1084e89d456fSAndrei Warkentin } 10851c6a0718SPierre Ossman 108652983382SKevin Liu static u16 sdhci_get_preset_value(struct sdhci_host *host) 108752983382SKevin Liu { 108852983382SKevin Liu u16 ctrl, preset = 0; 108952983382SKevin Liu 109052983382SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 109152983382SKevin Liu 109252983382SKevin Liu switch (ctrl & SDHCI_CTRL_UHS_MASK) { 109352983382SKevin Liu case SDHCI_CTRL_UHS_SDR12: 109452983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 109552983382SKevin Liu break; 109652983382SKevin Liu case SDHCI_CTRL_UHS_SDR25: 109752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 109852983382SKevin Liu break; 109952983382SKevin Liu case SDHCI_CTRL_UHS_SDR50: 110052983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 110152983382SKevin Liu break; 110252983382SKevin Liu case SDHCI_CTRL_UHS_SDR104: 110352983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 110452983382SKevin Liu break; 110552983382SKevin Liu case SDHCI_CTRL_UHS_DDR50: 110652983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 110752983382SKevin Liu break; 110852983382SKevin Liu default: 110952983382SKevin Liu pr_warn("%s: Invalid UHS-I mode selected\n", 111052983382SKevin Liu mmc_hostname(host->mmc)); 111152983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 111252983382SKevin Liu break; 111352983382SKevin Liu } 111452983382SKevin Liu return preset; 111552983382SKevin Liu } 111652983382SKevin Liu 11171c6a0718SPierre Ossman static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 11181c6a0718SPierre Ossman { 1119c3ed3877SArindam Nath int div = 0; /* Initialized for compiler warning */ 1120df16219fSGiuseppe CAVALLARO int real_div = div, clk_mul = 1; 1121c3ed3877SArindam Nath u16 clk = 0; 11221c6a0718SPierre Ossman unsigned long timeout; 11231c6a0718SPierre Ossman 112430832ab5STodd Poynor if (clock && clock == host->clock) 11251c6a0718SPierre Ossman return; 11261c6a0718SPierre Ossman 1127df16219fSGiuseppe CAVALLARO host->mmc->actual_clock = 0; 1128df16219fSGiuseppe CAVALLARO 11298114634cSAnton Vorontsov if (host->ops->set_clock) { 11308114634cSAnton Vorontsov host->ops->set_clock(host, clock); 11318114634cSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 11328114634cSAnton Vorontsov return; 11338114634cSAnton Vorontsov } 11348114634cSAnton Vorontsov 11354e4141a5SAnton Vorontsov sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 11361c6a0718SPierre Ossman 11371c6a0718SPierre Ossman if (clock == 0) 11381c6a0718SPierre Ossman goto out; 11391c6a0718SPierre Ossman 114085105c53SZhangfei Gao if (host->version >= SDHCI_SPEC_300) { 114152983382SKevin Liu if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & 114252983382SKevin Liu SDHCI_CTRL_PRESET_VAL_ENABLE) { 114352983382SKevin Liu u16 pre_val; 114452983382SKevin Liu 114552983382SKevin Liu clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 114652983382SKevin Liu pre_val = sdhci_get_preset_value(host); 114752983382SKevin Liu div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 114852983382SKevin Liu >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 114952983382SKevin Liu if (host->clk_mul && 115052983382SKevin Liu (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 115152983382SKevin Liu clk = SDHCI_PROG_CLOCK_MODE; 115252983382SKevin Liu real_div = div + 1; 115352983382SKevin Liu clk_mul = host->clk_mul; 115452983382SKevin Liu } else { 115552983382SKevin Liu real_div = max_t(int, 1, div << 1); 115652983382SKevin Liu } 115752983382SKevin Liu goto clock_set; 115852983382SKevin Liu } 115952983382SKevin Liu 1160c3ed3877SArindam Nath /* 1161c3ed3877SArindam Nath * Check if the Host Controller supports Programmable Clock 1162c3ed3877SArindam Nath * Mode. 1163c3ed3877SArindam Nath */ 1164c3ed3877SArindam Nath if (host->clk_mul) { 1165c3ed3877SArindam Nath for (div = 1; div <= 1024; div++) { 116652983382SKevin Liu if ((host->max_clk * host->clk_mul / div) 116752983382SKevin Liu <= clock) 1168c3ed3877SArindam Nath break; 1169c3ed3877SArindam Nath } 1170c3ed3877SArindam Nath /* 1171c3ed3877SArindam Nath * Set Programmable Clock Mode in the Clock 1172c3ed3877SArindam Nath * Control register. 1173c3ed3877SArindam Nath */ 1174c3ed3877SArindam Nath clk = SDHCI_PROG_CLOCK_MODE; 1175df16219fSGiuseppe CAVALLARO real_div = div; 1176df16219fSGiuseppe CAVALLARO clk_mul = host->clk_mul; 1177c3ed3877SArindam Nath div--; 1178c3ed3877SArindam Nath } else { 117985105c53SZhangfei Gao /* Version 3.00 divisors must be a multiple of 2. */ 118085105c53SZhangfei Gao if (host->max_clk <= clock) 118185105c53SZhangfei Gao div = 1; 118285105c53SZhangfei Gao else { 1183c3ed3877SArindam Nath for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1184c3ed3877SArindam Nath div += 2) { 118585105c53SZhangfei Gao if ((host->max_clk / div) <= clock) 118685105c53SZhangfei Gao break; 118785105c53SZhangfei Gao } 118885105c53SZhangfei Gao } 1189df16219fSGiuseppe CAVALLARO real_div = div; 1190c3ed3877SArindam Nath div >>= 1; 1191c3ed3877SArindam Nath } 119285105c53SZhangfei Gao } else { 119385105c53SZhangfei Gao /* Version 2.00 divisors must be a power of 2. */ 11940397526dSZhangfei Gao for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 11951c6a0718SPierre Ossman if ((host->max_clk / div) <= clock) 11961c6a0718SPierre Ossman break; 11971c6a0718SPierre Ossman } 1198df16219fSGiuseppe CAVALLARO real_div = div; 11991c6a0718SPierre Ossman div >>= 1; 1200c3ed3877SArindam Nath } 12011c6a0718SPierre Ossman 120252983382SKevin Liu clock_set: 1203df16219fSGiuseppe CAVALLARO if (real_div) 1204df16219fSGiuseppe CAVALLARO host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1205df16219fSGiuseppe CAVALLARO 1206c3ed3877SArindam Nath clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 120785105c53SZhangfei Gao clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 120885105c53SZhangfei Gao << SDHCI_DIVIDER_HI_SHIFT; 12091c6a0718SPierre Ossman clk |= SDHCI_CLOCK_INT_EN; 12104e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12111c6a0718SPierre Ossman 121227f6cb16SChris Ball /* Wait max 20 ms */ 121327f6cb16SChris Ball timeout = 20; 12144e4141a5SAnton Vorontsov while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 12151c6a0718SPierre Ossman & SDHCI_CLOCK_INT_STABLE)) { 12161c6a0718SPierre Ossman if (timeout == 0) { 1217a3c76eb9SGirish K S pr_err("%s: Internal clock never " 12181c6a0718SPierre Ossman "stabilised.\n", mmc_hostname(host->mmc)); 12191c6a0718SPierre Ossman sdhci_dumpregs(host); 12201c6a0718SPierre Ossman return; 12211c6a0718SPierre Ossman } 12221c6a0718SPierre Ossman timeout--; 12231c6a0718SPierre Ossman mdelay(1); 12241c6a0718SPierre Ossman } 12251c6a0718SPierre Ossman 12261c6a0718SPierre Ossman clk |= SDHCI_CLOCK_CARD_EN; 12274e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12281c6a0718SPierre Ossman 12291c6a0718SPierre Ossman out: 12301c6a0718SPierre Ossman host->clock = clock; 12311c6a0718SPierre Ossman } 12321c6a0718SPierre Ossman 12338213af3bSAndy Shevchenko static inline void sdhci_update_clock(struct sdhci_host *host) 12348213af3bSAndy Shevchenko { 12358213af3bSAndy Shevchenko unsigned int clock; 12368213af3bSAndy Shevchenko 12378213af3bSAndy Shevchenko clock = host->clock; 12388213af3bSAndy Shevchenko host->clock = 0; 12398213af3bSAndy Shevchenko sdhci_set_clock(host, clock); 12408213af3bSAndy Shevchenko } 12418213af3bSAndy Shevchenko 1242ceb6143bSAdrian Hunter static int sdhci_set_power(struct sdhci_host *host, unsigned short power) 12431c6a0718SPierre Ossman { 12448364248aSGiuseppe Cavallaro u8 pwr = 0; 12451c6a0718SPierre Ossman 12468364248aSGiuseppe Cavallaro if (power != (unsigned short)-1) { 1247ae628903SPierre Ossman switch (1 << power) { 1248ae628903SPierre Ossman case MMC_VDD_165_195: 1249ae628903SPierre Ossman pwr = SDHCI_POWER_180; 1250ae628903SPierre Ossman break; 1251ae628903SPierre Ossman case MMC_VDD_29_30: 1252ae628903SPierre Ossman case MMC_VDD_30_31: 1253ae628903SPierre Ossman pwr = SDHCI_POWER_300; 1254ae628903SPierre Ossman break; 1255ae628903SPierre Ossman case MMC_VDD_32_33: 1256ae628903SPierre Ossman case MMC_VDD_33_34: 1257ae628903SPierre Ossman pwr = SDHCI_POWER_330; 1258ae628903SPierre Ossman break; 1259ae628903SPierre Ossman default: 1260ae628903SPierre Ossman BUG(); 1261ae628903SPierre Ossman } 1262ae628903SPierre Ossman } 1263ae628903SPierre Ossman 1264ae628903SPierre Ossman if (host->pwr == pwr) 1265ceb6143bSAdrian Hunter return -1; 12661c6a0718SPierre Ossman 1267ae628903SPierre Ossman host->pwr = pwr; 1268ae628903SPierre Ossman 1269ae628903SPierre Ossman if (pwr == 0) { 12704e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1271ceb6143bSAdrian Hunter return 0; 12721c6a0718SPierre Ossman } 12731c6a0718SPierre Ossman 12741c6a0718SPierre Ossman /* 12751c6a0718SPierre Ossman * Spec says that we should clear the power reg before setting 12761c6a0718SPierre Ossman * a new value. Some controllers don't seem to like this though. 12771c6a0718SPierre Ossman */ 1278b8c86fc5SPierre Ossman if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 12794e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 12801c6a0718SPierre Ossman 1281e08c1694SAndres Salomon /* 1282c71f6512SAndres Salomon * At least the Marvell CaFe chip gets confused if we set the voltage 1283e08c1694SAndres Salomon * and set turn on power at the same time, so set the voltage first. 1284e08c1694SAndres Salomon */ 128511a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 12864e4141a5SAnton Vorontsov sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 12871c6a0718SPierre Ossman 1288ae628903SPierre Ossman pwr |= SDHCI_POWER_ON; 1289ae628903SPierre Ossman 1290ae628903SPierre Ossman sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1291557b0697SHarald Welte 1292557b0697SHarald Welte /* 1293557b0697SHarald Welte * Some controllers need an extra 10ms delay of 10ms before they 1294557b0697SHarald Welte * can apply clock after applying power 1295557b0697SHarald Welte */ 129611a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1297557b0697SHarald Welte mdelay(10); 1298ceb6143bSAdrian Hunter 1299ceb6143bSAdrian Hunter return power; 13001c6a0718SPierre Ossman } 13011c6a0718SPierre Ossman 13021c6a0718SPierre Ossman /*****************************************************************************\ 13031c6a0718SPierre Ossman * * 13041c6a0718SPierre Ossman * MMC callbacks * 13051c6a0718SPierre Ossman * * 13061c6a0718SPierre Ossman \*****************************************************************************/ 13071c6a0718SPierre Ossman 13081c6a0718SPierre Ossman static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13091c6a0718SPierre Ossman { 13101c6a0718SPierre Ossman struct sdhci_host *host; 1311505a8680SShawn Guo int present; 13121c6a0718SPierre Ossman unsigned long flags; 1313473b095aSAaron Lu u32 tuning_opcode; 13141c6a0718SPierre Ossman 13151c6a0718SPierre Ossman host = mmc_priv(mmc); 13161c6a0718SPierre Ossman 131766fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 131866fd8ad5SAdrian Hunter 13191c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 13201c6a0718SPierre Ossman 13211c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13221c6a0718SPierre Ossman 1323f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 13241c6a0718SPierre Ossman sdhci_activate_led(host); 13252f730fecSPierre Ossman #endif 1326e89d456fSAndrei Warkentin 1327e89d456fSAndrei Warkentin /* 1328e89d456fSAndrei Warkentin * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1329e89d456fSAndrei Warkentin * requests if Auto-CMD12 is enabled. 1330e89d456fSAndrei Warkentin */ 1331e89d456fSAndrei Warkentin if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1332c4512f79SJerry Huang if (mrq->stop) { 1333c4512f79SJerry Huang mrq->data->stop = NULL; 1334c4512f79SJerry Huang mrq->stop = NULL; 1335c4512f79SJerry Huang } 1336c4512f79SJerry Huang } 13371c6a0718SPierre Ossman 13381c6a0718SPierre Ossman host->mrq = mrq; 13391c6a0718SPierre Ossman 1340505a8680SShawn Guo /* 1341505a8680SShawn Guo * Firstly check card presence from cd-gpio. The return could 1342505a8680SShawn Guo * be one of the following possibilities: 1343505a8680SShawn Guo * negative: cd-gpio is not available 1344505a8680SShawn Guo * zero: cd-gpio is used, and card is removed 1345505a8680SShawn Guo * one: cd-gpio is used, and card is present 1346505a8680SShawn Guo */ 1347505a8680SShawn Guo present = mmc_gpio_get_cd(host->mmc); 1348505a8680SShawn Guo if (present < 0) { 134968d1fb7eSAnton Vorontsov /* If polling, assume that the card is always present. */ 135068d1fb7eSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1351505a8680SShawn Guo present = 1; 135268d1fb7eSAnton Vorontsov else 135368d1fb7eSAnton Vorontsov present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 135468d1fb7eSAnton Vorontsov SDHCI_CARD_PRESENT; 1355bec9d4e5SGuennadi Liakhovetski } 1356bec9d4e5SGuennadi Liakhovetski 135768d1fb7eSAnton Vorontsov if (!present || host->flags & SDHCI_DEVICE_DEAD) { 135817b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 13591c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 1360cf2b5eeaSArindam Nath } else { 1361cf2b5eeaSArindam Nath u32 present_state; 1362cf2b5eeaSArindam Nath 1363cf2b5eeaSArindam Nath present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1364cf2b5eeaSArindam Nath /* 1365cf2b5eeaSArindam Nath * Check if the re-tuning timer has already expired and there 1366cf2b5eeaSArindam Nath * is no on-going data transfer. If so, we need to execute 1367cf2b5eeaSArindam Nath * tuning procedure before sending command. 1368cf2b5eeaSArindam Nath */ 1369cf2b5eeaSArindam Nath if ((host->flags & SDHCI_NEEDS_RETUNING) && 1370cf2b5eeaSArindam Nath !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 137114efd957SChris Ball if (mmc->card) { 137214efd957SChris Ball /* eMMC uses cmd21 but sd and sdio use cmd19 */ 137314efd957SChris Ball tuning_opcode = 137414efd957SChris Ball mmc->card->type == MMC_TYPE_MMC ? 1375473b095aSAaron Lu MMC_SEND_TUNING_BLOCK_HS200 : 1376473b095aSAaron Lu MMC_SEND_TUNING_BLOCK; 1377cf2b5eeaSArindam Nath spin_unlock_irqrestore(&host->lock, flags); 1378473b095aSAaron Lu sdhci_execute_tuning(mmc, tuning_opcode); 1379cf2b5eeaSArindam Nath spin_lock_irqsave(&host->lock, flags); 1380cf2b5eeaSArindam Nath 1381cf2b5eeaSArindam Nath /* Restore original mmc_request structure */ 1382cf2b5eeaSArindam Nath host->mrq = mrq; 1383cf2b5eeaSArindam Nath } 138414efd957SChris Ball } 1385cf2b5eeaSArindam Nath 13868edf6371SAndrei Warkentin if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1387e89d456fSAndrei Warkentin sdhci_send_command(host, mrq->sbc); 1388e89d456fSAndrei Warkentin else 13891c6a0718SPierre Ossman sdhci_send_command(host, mrq->cmd); 1390cf2b5eeaSArindam Nath } 13911c6a0718SPierre Ossman 13921c6a0718SPierre Ossman mmiowb(); 13931c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 13941c6a0718SPierre Ossman } 13951c6a0718SPierre Ossman 139666fd8ad5SAdrian Hunter static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 13971c6a0718SPierre Ossman { 13981c6a0718SPierre Ossman unsigned long flags; 1399ceb6143bSAdrian Hunter int vdd_bit = -1; 14001c6a0718SPierre Ossman u8 ctrl; 14011c6a0718SPierre Ossman 14021c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 14031c6a0718SPierre Ossman 1404ceb6143bSAdrian Hunter if (host->flags & SDHCI_DEVICE_DEAD) { 1405ceb6143bSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 1406ceb6143bSAdrian Hunter if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1407ceb6143bSAdrian Hunter mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1408ceb6143bSAdrian Hunter return; 1409ceb6143bSAdrian Hunter } 14101e72859eSPierre Ossman 14111c6a0718SPierre Ossman /* 14121c6a0718SPierre Ossman * Reset the chip on each power off. 14131c6a0718SPierre Ossman * Should clear out any weird states. 14141c6a0718SPierre Ossman */ 14151c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) { 14164e4141a5SAnton Vorontsov sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 14177260cf5eSAnton Vorontsov sdhci_reinit(host); 14181c6a0718SPierre Ossman } 14191c6a0718SPierre Ossman 142052983382SKevin Liu if (host->version >= SDHCI_SPEC_300 && 142152983382SKevin Liu (ios->power_mode == MMC_POWER_UP)) 142252983382SKevin Liu sdhci_enable_preset_value(host, false); 142352983382SKevin Liu 14241c6a0718SPierre Ossman sdhci_set_clock(host, ios->clock); 14251c6a0718SPierre Ossman 14261c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) 1427ceb6143bSAdrian Hunter vdd_bit = sdhci_set_power(host, -1); 14281c6a0718SPierre Ossman else 1429ceb6143bSAdrian Hunter vdd_bit = sdhci_set_power(host, ios->vdd); 1430ceb6143bSAdrian Hunter 1431ceb6143bSAdrian Hunter if (host->vmmc && vdd_bit != -1) { 1432ceb6143bSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 1433ceb6143bSAdrian Hunter mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); 1434ceb6143bSAdrian Hunter spin_lock_irqsave(&host->lock, flags); 1435ceb6143bSAdrian Hunter } 14361c6a0718SPierre Ossman 1437643a81ffSPhilip Rakity if (host->ops->platform_send_init_74_clocks) 1438643a81ffSPhilip Rakity host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1439643a81ffSPhilip Rakity 144015ec4461SPhilip Rakity /* 144115ec4461SPhilip Rakity * If your platform has 8-bit width support but is not a v3 controller, 144215ec4461SPhilip Rakity * or if it requires special setup code, you should implement that in 14437bc088d3SSascha Hauer * platform_bus_width(). 144415ec4461SPhilip Rakity */ 14457bc088d3SSascha Hauer if (host->ops->platform_bus_width) { 14467bc088d3SSascha Hauer host->ops->platform_bus_width(host, ios->bus_width); 14477bc088d3SSascha Hauer } else { 14484e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 144915ec4461SPhilip Rakity if (ios->bus_width == MMC_BUS_WIDTH_8) { 145015ec4461SPhilip Rakity ctrl &= ~SDHCI_CTRL_4BITBUS; 145115ec4461SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 1452ae6d6c92SKyungmin Park ctrl |= SDHCI_CTRL_8BITBUS; 145315ec4461SPhilip Rakity } else { 145415ec4461SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 1455ae6d6c92SKyungmin Park ctrl &= ~SDHCI_CTRL_8BITBUS; 14561c6a0718SPierre Ossman if (ios->bus_width == MMC_BUS_WIDTH_4) 14571c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_4BITBUS; 14581c6a0718SPierre Ossman else 14591c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_4BITBUS; 146015ec4461SPhilip Rakity } 146115ec4461SPhilip Rakity sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 146215ec4461SPhilip Rakity } 146315ec4461SPhilip Rakity 146415ec4461SPhilip Rakity ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 14651c6a0718SPierre Ossman 14663ab9c8daSPhilip Rakity if ((ios->timing == MMC_TIMING_SD_HS || 14673ab9c8daSPhilip Rakity ios->timing == MMC_TIMING_MMC_HS) 14683ab9c8daSPhilip Rakity && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 14691c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_HISPD; 14701c6a0718SPierre Ossman else 14711c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_HISPD; 14721c6a0718SPierre Ossman 1473d6d50a15SArindam Nath if (host->version >= SDHCI_SPEC_300) { 147449c468fcSArindam Nath u16 clk, ctrl_2; 147549c468fcSArindam Nath 147649c468fcSArindam Nath /* In case of UHS-I modes, set High Speed Enable */ 1477069c9f14SGirish K S if ((ios->timing == MMC_TIMING_MMC_HS200) || 1478069c9f14SGirish K S (ios->timing == MMC_TIMING_UHS_SDR50) || 147949c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_SDR104) || 148049c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_DDR50) || 1481dd8df17fSAlexander Elbs (ios->timing == MMC_TIMING_UHS_SDR25)) 148249c468fcSArindam Nath ctrl |= SDHCI_CTRL_HISPD; 1483d6d50a15SArindam Nath 1484d6d50a15SArindam Nath ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1485d6d50a15SArindam Nath if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1486758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1487d6d50a15SArindam Nath /* 1488d6d50a15SArindam Nath * We only need to set Driver Strength if the 1489d6d50a15SArindam Nath * preset value enable is not set. 1490d6d50a15SArindam Nath */ 1491d6d50a15SArindam Nath ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1492d6d50a15SArindam Nath if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1493d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1494d6d50a15SArindam Nath else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1495d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1496d6d50a15SArindam Nath 1497d6d50a15SArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1498758535c4SArindam Nath } else { 1499758535c4SArindam Nath /* 1500758535c4SArindam Nath * According to SDHC Spec v3.00, if the Preset Value 1501758535c4SArindam Nath * Enable in the Host Control 2 register is set, we 1502758535c4SArindam Nath * need to reset SD Clock Enable before changing High 1503758535c4SArindam Nath * Speed Enable to avoid generating clock gliches. 1504758535c4SArindam Nath */ 1505758535c4SArindam Nath 1506758535c4SArindam Nath /* Reset SD Clock Enable */ 1507758535c4SArindam Nath clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1508758535c4SArindam Nath clk &= ~SDHCI_CLOCK_CARD_EN; 1509758535c4SArindam Nath sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1510758535c4SArindam Nath 1511758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1512758535c4SArindam Nath 1513758535c4SArindam Nath /* Re-enable SD Clock */ 15148213af3bSAndy Shevchenko sdhci_update_clock(host); 1515d6d50a15SArindam Nath } 151649c468fcSArindam Nath 151749c468fcSArindam Nath 15186322cdd0SPhilip Rakity /* Reset SD Clock Enable */ 15196322cdd0SPhilip Rakity clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 15206322cdd0SPhilip Rakity clk &= ~SDHCI_CLOCK_CARD_EN; 15216322cdd0SPhilip Rakity sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 15226322cdd0SPhilip Rakity 15236322cdd0SPhilip Rakity if (host->ops->set_uhs_signaling) 15246322cdd0SPhilip Rakity host->ops->set_uhs_signaling(host, ios->timing); 15256322cdd0SPhilip Rakity else { 15266322cdd0SPhilip Rakity ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 152749c468fcSArindam Nath /* Select Bus Speed Mode for host */ 152849c468fcSArindam Nath ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1529069c9f14SGirish K S if (ios->timing == MMC_TIMING_MMC_HS200) 1530069c9f14SGirish K S ctrl_2 |= SDHCI_CTRL_HS_SDR200; 1531069c9f14SGirish K S else if (ios->timing == MMC_TIMING_UHS_SDR12) 153249c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 153349c468fcSArindam Nath else if (ios->timing == MMC_TIMING_UHS_SDR25) 153449c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 153549c468fcSArindam Nath else if (ios->timing == MMC_TIMING_UHS_SDR50) 153649c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 153749c468fcSArindam Nath else if (ios->timing == MMC_TIMING_UHS_SDR104) 153849c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 153949c468fcSArindam Nath else if (ios->timing == MMC_TIMING_UHS_DDR50) 154049c468fcSArindam Nath ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 154149c468fcSArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 15426322cdd0SPhilip Rakity } 154349c468fcSArindam Nath 154452983382SKevin Liu if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 154552983382SKevin Liu ((ios->timing == MMC_TIMING_UHS_SDR12) || 154652983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR25) || 154752983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR50) || 154852983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR104) || 154952983382SKevin Liu (ios->timing == MMC_TIMING_UHS_DDR50))) { 155052983382SKevin Liu u16 preset; 155152983382SKevin Liu 155252983382SKevin Liu sdhci_enable_preset_value(host, true); 155352983382SKevin Liu preset = sdhci_get_preset_value(host); 155452983382SKevin Liu ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 155552983382SKevin Liu >> SDHCI_PRESET_DRV_SHIFT; 155652983382SKevin Liu } 155752983382SKevin Liu 155849c468fcSArindam Nath /* Re-enable SD Clock */ 15598213af3bSAndy Shevchenko sdhci_update_clock(host); 1560758535c4SArindam Nath } else 1561758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1562d6d50a15SArindam Nath 1563b8352260SLeandro Dorileo /* 1564b8352260SLeandro Dorileo * Some (ENE) controllers go apeshit on some ios operation, 1565b8352260SLeandro Dorileo * signalling timeout and CRC errors even on CMD0. Resetting 1566b8352260SLeandro Dorileo * it on each ios seems to solve the problem. 1567b8352260SLeandro Dorileo */ 1568b8c86fc5SPierre Ossman if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1569b8352260SLeandro Dorileo sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1570b8352260SLeandro Dorileo 15711c6a0718SPierre Ossman mmiowb(); 15721c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 15731c6a0718SPierre Ossman } 15741c6a0718SPierre Ossman 157566fd8ad5SAdrian Hunter static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 157666fd8ad5SAdrian Hunter { 157766fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 157866fd8ad5SAdrian Hunter 157966fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 158066fd8ad5SAdrian Hunter sdhci_do_set_ios(host, ios); 158166fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 158266fd8ad5SAdrian Hunter } 158366fd8ad5SAdrian Hunter 158494144a46SKevin Liu static int sdhci_do_get_cd(struct sdhci_host *host) 158594144a46SKevin Liu { 158694144a46SKevin Liu int gpio_cd = mmc_gpio_get_cd(host->mmc); 158794144a46SKevin Liu 158894144a46SKevin Liu if (host->flags & SDHCI_DEVICE_DEAD) 158994144a46SKevin Liu return 0; 159094144a46SKevin Liu 159194144a46SKevin Liu /* If polling/nonremovable, assume that the card is always present. */ 159294144a46SKevin Liu if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 159394144a46SKevin Liu (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 159494144a46SKevin Liu return 1; 159594144a46SKevin Liu 159694144a46SKevin Liu /* Try slot gpio detect */ 159794144a46SKevin Liu if (!IS_ERR_VALUE(gpio_cd)) 159894144a46SKevin Liu return !!gpio_cd; 159994144a46SKevin Liu 160094144a46SKevin Liu /* Host native card detect */ 160194144a46SKevin Liu return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 160294144a46SKevin Liu } 160394144a46SKevin Liu 160494144a46SKevin Liu static int sdhci_get_cd(struct mmc_host *mmc) 160594144a46SKevin Liu { 160694144a46SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 160794144a46SKevin Liu int ret; 160894144a46SKevin Liu 160994144a46SKevin Liu sdhci_runtime_pm_get(host); 161094144a46SKevin Liu ret = sdhci_do_get_cd(host); 161194144a46SKevin Liu sdhci_runtime_pm_put(host); 161294144a46SKevin Liu return ret; 161394144a46SKevin Liu } 161494144a46SKevin Liu 161566fd8ad5SAdrian Hunter static int sdhci_check_ro(struct sdhci_host *host) 16161c6a0718SPierre Ossman { 16171c6a0718SPierre Ossman unsigned long flags; 16182dfb579cSWolfram Sang int is_readonly; 16191c6a0718SPierre Ossman 16201c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 16211c6a0718SPierre Ossman 16221e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 16232dfb579cSWolfram Sang is_readonly = 0; 16242dfb579cSWolfram Sang else if (host->ops->get_ro) 16252dfb579cSWolfram Sang is_readonly = host->ops->get_ro(host); 16261e72859eSPierre Ossman else 16272dfb579cSWolfram Sang is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 16282dfb579cSWolfram Sang & SDHCI_WRITE_PROTECT); 16291c6a0718SPierre Ossman 16301c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 16311c6a0718SPierre Ossman 16322dfb579cSWolfram Sang /* This quirk needs to be replaced by a callback-function later */ 16332dfb579cSWolfram Sang return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 16342dfb579cSWolfram Sang !is_readonly : is_readonly; 16351c6a0718SPierre Ossman } 16361c6a0718SPierre Ossman 163782b0e23aSTakashi Iwai #define SAMPLE_COUNT 5 163882b0e23aSTakashi Iwai 163966fd8ad5SAdrian Hunter static int sdhci_do_get_ro(struct sdhci_host *host) 164082b0e23aSTakashi Iwai { 164182b0e23aSTakashi Iwai int i, ro_count; 164282b0e23aSTakashi Iwai 164382b0e23aSTakashi Iwai if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 164466fd8ad5SAdrian Hunter return sdhci_check_ro(host); 164582b0e23aSTakashi Iwai 164682b0e23aSTakashi Iwai ro_count = 0; 164782b0e23aSTakashi Iwai for (i = 0; i < SAMPLE_COUNT; i++) { 164866fd8ad5SAdrian Hunter if (sdhci_check_ro(host)) { 164982b0e23aSTakashi Iwai if (++ro_count > SAMPLE_COUNT / 2) 165082b0e23aSTakashi Iwai return 1; 165182b0e23aSTakashi Iwai } 165282b0e23aSTakashi Iwai msleep(30); 165382b0e23aSTakashi Iwai } 165482b0e23aSTakashi Iwai return 0; 165582b0e23aSTakashi Iwai } 165682b0e23aSTakashi Iwai 165720758b66SAdrian Hunter static void sdhci_hw_reset(struct mmc_host *mmc) 165820758b66SAdrian Hunter { 165920758b66SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 166020758b66SAdrian Hunter 166120758b66SAdrian Hunter if (host->ops && host->ops->hw_reset) 166220758b66SAdrian Hunter host->ops->hw_reset(host); 166320758b66SAdrian Hunter } 166420758b66SAdrian Hunter 166566fd8ad5SAdrian Hunter static int sdhci_get_ro(struct mmc_host *mmc) 1666f75979b7SPierre Ossman { 166766fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 166866fd8ad5SAdrian Hunter int ret; 1669f75979b7SPierre Ossman 167066fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 167166fd8ad5SAdrian Hunter ret = sdhci_do_get_ro(host); 167266fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 167366fd8ad5SAdrian Hunter return ret; 167466fd8ad5SAdrian Hunter } 1675f75979b7SPierre Ossman 167666fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 167766fd8ad5SAdrian Hunter { 16781e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 16791e72859eSPierre Ossman goto out; 16801e72859eSPierre Ossman 1681f75979b7SPierre Ossman if (enable) 168266fd8ad5SAdrian Hunter host->flags |= SDHCI_SDIO_IRQ_ENABLED; 168366fd8ad5SAdrian Hunter else 168466fd8ad5SAdrian Hunter host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 168566fd8ad5SAdrian Hunter 168666fd8ad5SAdrian Hunter /* SDIO IRQ will be enabled as appropriate in runtime resume */ 168766fd8ad5SAdrian Hunter if (host->runtime_suspended) 168866fd8ad5SAdrian Hunter goto out; 168966fd8ad5SAdrian Hunter 169066fd8ad5SAdrian Hunter if (enable) 16917260cf5eSAnton Vorontsov sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 16927260cf5eSAnton Vorontsov else 16937260cf5eSAnton Vorontsov sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 16941e72859eSPierre Ossman out: 1695f75979b7SPierre Ossman mmiowb(); 169666fd8ad5SAdrian Hunter } 1697f75979b7SPierre Ossman 169866fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 169966fd8ad5SAdrian Hunter { 170066fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 170166fd8ad5SAdrian Hunter unsigned long flags; 170266fd8ad5SAdrian Hunter 170366fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 170466fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, enable); 1705f75979b7SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 1706f75979b7SPierre Ossman } 1707f75979b7SPierre Ossman 170820b92a30SKevin Liu static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 170921f5998fSFabio Estevam struct mmc_ios *ios) 1710f2119df6SArindam Nath { 171120b92a30SKevin Liu u16 ctrl; 17126231f3deSPhilip Rakity int ret; 1713f2119df6SArindam Nath 171420b92a30SKevin Liu /* 171520b92a30SKevin Liu * Signal Voltage Switching is only applicable for Host Controllers 171620b92a30SKevin Liu * v3.00 and above. 171720b92a30SKevin Liu */ 171820b92a30SKevin Liu if (host->version < SDHCI_SPEC_300) 171920b92a30SKevin Liu return 0; 172020b92a30SKevin Liu 172120b92a30SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 172220b92a30SKevin Liu 172321f5998fSFabio Estevam switch (ios->signal_voltage) { 172420b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_330: 1725f2119df6SArindam Nath /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1726f2119df6SArindam Nath ctrl &= ~SDHCI_CTRL_VDD_180; 1727f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1728f2119df6SArindam Nath 17296231f3deSPhilip Rakity if (host->vqmmc) { 1730cec2e216SKevin Liu ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 17316231f3deSPhilip Rakity if (ret) { 17326231f3deSPhilip Rakity pr_warning("%s: Switching to 3.3V signalling voltage " 17336231f3deSPhilip Rakity " failed\n", mmc_hostname(host->mmc)); 17346231f3deSPhilip Rakity return -EIO; 17356231f3deSPhilip Rakity } 17366231f3deSPhilip Rakity } 1737f2119df6SArindam Nath /* Wait for 5ms */ 1738f2119df6SArindam Nath usleep_range(5000, 5500); 1739f2119df6SArindam Nath 1740f2119df6SArindam Nath /* 3.3V regulator output should be stable within 5 ms */ 1741f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1742f2119df6SArindam Nath if (!(ctrl & SDHCI_CTRL_VDD_180)) 1743f2119df6SArindam Nath return 0; 17446231f3deSPhilip Rakity 17456231f3deSPhilip Rakity pr_warning("%s: 3.3V regulator output did not became stable\n", 17466231f3deSPhilip Rakity mmc_hostname(host->mmc)); 17476231f3deSPhilip Rakity 174820b92a30SKevin Liu return -EAGAIN; 174920b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_180: 175020b92a30SKevin Liu if (host->vqmmc) { 175120b92a30SKevin Liu ret = regulator_set_voltage(host->vqmmc, 175220b92a30SKevin Liu 1700000, 1950000); 175320b92a30SKevin Liu if (ret) { 175420b92a30SKevin Liu pr_warning("%s: Switching to 1.8V signalling voltage " 175520b92a30SKevin Liu " failed\n", mmc_hostname(host->mmc)); 1756f2119df6SArindam Nath return -EIO; 1757f2119df6SArindam Nath } 175820b92a30SKevin Liu } 17596231f3deSPhilip Rakity 1760f2119df6SArindam Nath /* 1761f2119df6SArindam Nath * Enable 1.8V Signal Enable in the Host Control2 1762f2119df6SArindam Nath * register 1763f2119df6SArindam Nath */ 1764f2119df6SArindam Nath ctrl |= SDHCI_CTRL_VDD_180; 1765f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1766f2119df6SArindam Nath 1767f2119df6SArindam Nath /* Wait for 5ms */ 1768f2119df6SArindam Nath usleep_range(5000, 5500); 1769f2119df6SArindam Nath 177020b92a30SKevin Liu /* 1.8V regulator output should be stable within 5 ms */ 1771f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 177220b92a30SKevin Liu if (ctrl & SDHCI_CTRL_VDD_180) 1773f2119df6SArindam Nath return 0; 1774f2119df6SArindam Nath 177520b92a30SKevin Liu pr_warning("%s: 1.8V regulator output did not became stable\n", 177620b92a30SKevin Liu mmc_hostname(host->mmc)); 17776231f3deSPhilip Rakity 1778f2119df6SArindam Nath return -EAGAIN; 177920b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_120: 178020b92a30SKevin Liu if (host->vqmmc) { 178120b92a30SKevin Liu ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); 178220b92a30SKevin Liu if (ret) { 178320b92a30SKevin Liu pr_warning("%s: Switching to 1.2V signalling voltage " 178420b92a30SKevin Liu " failed\n", mmc_hostname(host->mmc)); 178520b92a30SKevin Liu return -EIO; 17866231f3deSPhilip Rakity } 178720b92a30SKevin Liu } 17886231f3deSPhilip Rakity return 0; 178920b92a30SKevin Liu default: 1790f2119df6SArindam Nath /* No signal voltage switch required */ 1791f2119df6SArindam Nath return 0; 1792f2119df6SArindam Nath } 179320b92a30SKevin Liu } 1794f2119df6SArindam Nath 179566fd8ad5SAdrian Hunter static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 179621f5998fSFabio Estevam struct mmc_ios *ios) 179766fd8ad5SAdrian Hunter { 179866fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 179966fd8ad5SAdrian Hunter int err; 180066fd8ad5SAdrian Hunter 180166fd8ad5SAdrian Hunter if (host->version < SDHCI_SPEC_300) 180266fd8ad5SAdrian Hunter return 0; 180366fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 180421f5998fSFabio Estevam err = sdhci_do_start_signal_voltage_switch(host, ios); 180566fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 180666fd8ad5SAdrian Hunter return err; 180766fd8ad5SAdrian Hunter } 180866fd8ad5SAdrian Hunter 180920b92a30SKevin Liu static int sdhci_card_busy(struct mmc_host *mmc) 181020b92a30SKevin Liu { 181120b92a30SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 181220b92a30SKevin Liu u32 present_state; 181320b92a30SKevin Liu 181420b92a30SKevin Liu sdhci_runtime_pm_get(host); 181520b92a30SKevin Liu /* Check whether DAT[3:0] is 0000 */ 181620b92a30SKevin Liu present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 181720b92a30SKevin Liu sdhci_runtime_pm_put(host); 181820b92a30SKevin Liu 181920b92a30SKevin Liu return !(present_state & SDHCI_DATA_LVL_MASK); 182020b92a30SKevin Liu } 182120b92a30SKevin Liu 1822069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1823b513ea25SArindam Nath { 1824b513ea25SArindam Nath struct sdhci_host *host; 1825b513ea25SArindam Nath u16 ctrl; 1826b513ea25SArindam Nath u32 ier; 1827b513ea25SArindam Nath int tuning_loop_counter = MAX_TUNING_LOOP; 1828b513ea25SArindam Nath unsigned long timeout; 1829b513ea25SArindam Nath int err = 0; 1830069c9f14SGirish K S bool requires_tuning_nonuhs = false; 1831b513ea25SArindam Nath 1832b513ea25SArindam Nath host = mmc_priv(mmc); 1833b513ea25SArindam Nath 183466fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 1835b513ea25SArindam Nath disable_irq(host->irq); 1836b513ea25SArindam Nath spin_lock(&host->lock); 1837b513ea25SArindam Nath 1838b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1839b513ea25SArindam Nath 1840b513ea25SArindam Nath /* 1841069c9f14SGirish K S * The Host Controller needs tuning only in case of SDR104 mode 1842069c9f14SGirish K S * and for SDR50 mode when Use Tuning for SDR50 is set in the 1843b513ea25SArindam Nath * Capabilities register. 1844069c9f14SGirish K S * If the Host Controller supports the HS200 mode then the 1845069c9f14SGirish K S * tuning function has to be executed. 1846b513ea25SArindam Nath */ 1847069c9f14SGirish K S if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1848069c9f14SGirish K S (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1849069c9f14SGirish K S host->flags & SDHCI_HS200_NEEDS_TUNING)) 1850069c9f14SGirish K S requires_tuning_nonuhs = true; 1851069c9f14SGirish K S 1852b513ea25SArindam Nath if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1853069c9f14SGirish K S requires_tuning_nonuhs) 1854b513ea25SArindam Nath ctrl |= SDHCI_CTRL_EXEC_TUNING; 1855b513ea25SArindam Nath else { 1856b513ea25SArindam Nath spin_unlock(&host->lock); 1857b513ea25SArindam Nath enable_irq(host->irq); 185866fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 1859b513ea25SArindam Nath return 0; 1860b513ea25SArindam Nath } 1861b513ea25SArindam Nath 1862b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1863b513ea25SArindam Nath 1864b513ea25SArindam Nath /* 1865b513ea25SArindam Nath * As per the Host Controller spec v3.00, tuning command 1866b513ea25SArindam Nath * generates Buffer Read Ready interrupt, so enable that. 1867b513ea25SArindam Nath * 1868b513ea25SArindam Nath * Note: The spec clearly says that when tuning sequence 1869b513ea25SArindam Nath * is being performed, the controller does not generate 1870b513ea25SArindam Nath * interrupts other than Buffer Read Ready interrupt. But 1871b513ea25SArindam Nath * to make sure we don't hit a controller bug, we _only_ 1872b513ea25SArindam Nath * enable Buffer Read Ready interrupt here. 1873b513ea25SArindam Nath */ 1874b513ea25SArindam Nath ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1875b513ea25SArindam Nath sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1876b513ea25SArindam Nath 1877b513ea25SArindam Nath /* 1878b513ea25SArindam Nath * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1879b513ea25SArindam Nath * of loops reaches 40 times or a timeout of 150ms occurs. 1880b513ea25SArindam Nath */ 1881b513ea25SArindam Nath timeout = 150; 1882b513ea25SArindam Nath do { 1883b513ea25SArindam Nath struct mmc_command cmd = {0}; 188466fd8ad5SAdrian Hunter struct mmc_request mrq = {NULL}; 1885b513ea25SArindam Nath 1886b513ea25SArindam Nath if (!tuning_loop_counter && !timeout) 1887b513ea25SArindam Nath break; 1888b513ea25SArindam Nath 1889069c9f14SGirish K S cmd.opcode = opcode; 1890b513ea25SArindam Nath cmd.arg = 0; 1891b513ea25SArindam Nath cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1892b513ea25SArindam Nath cmd.retries = 0; 1893b513ea25SArindam Nath cmd.data = NULL; 1894b513ea25SArindam Nath cmd.error = 0; 1895b513ea25SArindam Nath 1896b513ea25SArindam Nath mrq.cmd = &cmd; 1897b513ea25SArindam Nath host->mrq = &mrq; 1898b513ea25SArindam Nath 1899b513ea25SArindam Nath /* 1900b513ea25SArindam Nath * In response to CMD19, the card sends 64 bytes of tuning 1901b513ea25SArindam Nath * block to the Host Controller. So we set the block size 1902b513ea25SArindam Nath * to 64 here. 1903b513ea25SArindam Nath */ 1904069c9f14SGirish K S if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1905069c9f14SGirish K S if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1906069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1907069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1908069c9f14SGirish K S else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1909069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1910069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1911069c9f14SGirish K S } else { 1912069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1913069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1914069c9f14SGirish K S } 1915b513ea25SArindam Nath 1916b513ea25SArindam Nath /* 1917b513ea25SArindam Nath * The tuning block is sent by the card to the host controller. 1918b513ea25SArindam Nath * So we set the TRNS_READ bit in the Transfer Mode register. 1919b513ea25SArindam Nath * This also takes care of setting DMA Enable and Multi Block 1920b513ea25SArindam Nath * Select in the same register to 0. 1921b513ea25SArindam Nath */ 1922b513ea25SArindam Nath sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1923b513ea25SArindam Nath 1924b513ea25SArindam Nath sdhci_send_command(host, &cmd); 1925b513ea25SArindam Nath 1926b513ea25SArindam Nath host->cmd = NULL; 1927b513ea25SArindam Nath host->mrq = NULL; 1928b513ea25SArindam Nath 1929b513ea25SArindam Nath spin_unlock(&host->lock); 1930b513ea25SArindam Nath enable_irq(host->irq); 1931b513ea25SArindam Nath 1932b513ea25SArindam Nath /* Wait for Buffer Read Ready interrupt */ 1933b513ea25SArindam Nath wait_event_interruptible_timeout(host->buf_ready_int, 1934b513ea25SArindam Nath (host->tuning_done == 1), 1935b513ea25SArindam Nath msecs_to_jiffies(50)); 1936b513ea25SArindam Nath disable_irq(host->irq); 1937b513ea25SArindam Nath spin_lock(&host->lock); 1938b513ea25SArindam Nath 1939b513ea25SArindam Nath if (!host->tuning_done) { 1940a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Timeout waiting for " 1941b513ea25SArindam Nath "Buffer Read Ready interrupt during tuning " 1942b513ea25SArindam Nath "procedure, falling back to fixed sampling " 1943b513ea25SArindam Nath "clock\n"); 1944b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1945b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1946b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1947b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1948b513ea25SArindam Nath 1949b513ea25SArindam Nath err = -EIO; 1950b513ea25SArindam Nath goto out; 1951b513ea25SArindam Nath } 1952b513ea25SArindam Nath 1953b513ea25SArindam Nath host->tuning_done = 0; 1954b513ea25SArindam Nath 1955b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1956b513ea25SArindam Nath tuning_loop_counter--; 1957b513ea25SArindam Nath timeout--; 1958b513ea25SArindam Nath mdelay(1); 1959b513ea25SArindam Nath } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1960b513ea25SArindam Nath 1961b513ea25SArindam Nath /* 1962b513ea25SArindam Nath * The Host Driver has exhausted the maximum number of loops allowed, 1963b513ea25SArindam Nath * so use fixed sampling frequency. 1964b513ea25SArindam Nath */ 1965b513ea25SArindam Nath if (!tuning_loop_counter || !timeout) { 1966b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1967b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1968b513ea25SArindam Nath } else { 1969b513ea25SArindam Nath if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1970a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Tuning procedure" 1971b513ea25SArindam Nath " failed, falling back to fixed sampling" 1972b513ea25SArindam Nath " clock\n"); 1973b513ea25SArindam Nath err = -EIO; 1974b513ea25SArindam Nath } 1975b513ea25SArindam Nath } 1976b513ea25SArindam Nath 1977b513ea25SArindam Nath out: 1978cf2b5eeaSArindam Nath /* 1979cf2b5eeaSArindam Nath * If this is the very first time we are here, we start the retuning 1980cf2b5eeaSArindam Nath * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1981cf2b5eeaSArindam Nath * flag won't be set, we check this condition before actually starting 1982cf2b5eeaSArindam Nath * the timer. 1983cf2b5eeaSArindam Nath */ 1984cf2b5eeaSArindam Nath if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1985cf2b5eeaSArindam Nath (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1986973905feSAaron Lu host->flags |= SDHCI_USING_RETUNING_TIMER; 1987cf2b5eeaSArindam Nath mod_timer(&host->tuning_timer, jiffies + 1988cf2b5eeaSArindam Nath host->tuning_count * HZ); 1989cf2b5eeaSArindam Nath /* Tuning mode 1 limits the maximum data length to 4MB */ 1990cf2b5eeaSArindam Nath mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1991cf2b5eeaSArindam Nath } else { 1992cf2b5eeaSArindam Nath host->flags &= ~SDHCI_NEEDS_RETUNING; 1993cf2b5eeaSArindam Nath /* Reload the new initial value for timer */ 1994cf2b5eeaSArindam Nath if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1995cf2b5eeaSArindam Nath mod_timer(&host->tuning_timer, jiffies + 1996cf2b5eeaSArindam Nath host->tuning_count * HZ); 1997cf2b5eeaSArindam Nath } 1998cf2b5eeaSArindam Nath 1999cf2b5eeaSArindam Nath /* 2000cf2b5eeaSArindam Nath * In case tuning fails, host controllers which support re-tuning can 2001cf2b5eeaSArindam Nath * try tuning again at a later time, when the re-tuning timer expires. 2002cf2b5eeaSArindam Nath * So for these controllers, we return 0. Since there might be other 2003cf2b5eeaSArindam Nath * controllers who do not have this capability, we return error for 2004973905feSAaron Lu * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2005973905feSAaron Lu * a retuning timer to do the retuning for the card. 2006cf2b5eeaSArindam Nath */ 2007973905feSAaron Lu if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2008cf2b5eeaSArindam Nath err = 0; 2009cf2b5eeaSArindam Nath 2010b513ea25SArindam Nath sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 2011b513ea25SArindam Nath spin_unlock(&host->lock); 2012b513ea25SArindam Nath enable_irq(host->irq); 201366fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 2014b513ea25SArindam Nath 2015b513ea25SArindam Nath return err; 2016b513ea25SArindam Nath } 2017b513ea25SArindam Nath 201852983382SKevin Liu 201952983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 20204d55c5a1SArindam Nath { 20214d55c5a1SArindam Nath u16 ctrl; 20224d55c5a1SArindam Nath 20234d55c5a1SArindam Nath /* Host Controller v3.00 defines preset value registers */ 20244d55c5a1SArindam Nath if (host->version < SDHCI_SPEC_300) 20254d55c5a1SArindam Nath return; 20264d55c5a1SArindam Nath 20274d55c5a1SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 20284d55c5a1SArindam Nath 20294d55c5a1SArindam Nath /* 20304d55c5a1SArindam Nath * We only enable or disable Preset Value if they are not already 20314d55c5a1SArindam Nath * enabled or disabled respectively. Otherwise, we bail out. 20324d55c5a1SArindam Nath */ 20334d55c5a1SArindam Nath if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 20344d55c5a1SArindam Nath ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 20354d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 203666fd8ad5SAdrian Hunter host->flags |= SDHCI_PV_ENABLED; 20374d55c5a1SArindam Nath } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 20384d55c5a1SArindam Nath ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 20394d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 204066fd8ad5SAdrian Hunter host->flags &= ~SDHCI_PV_ENABLED; 20414d55c5a1SArindam Nath } 204266fd8ad5SAdrian Hunter } 204366fd8ad5SAdrian Hunter 204471e69211SGuennadi Liakhovetski static void sdhci_card_event(struct mmc_host *mmc) 20451c6a0718SPierre Ossman { 204671e69211SGuennadi Liakhovetski struct sdhci_host *host = mmc_priv(mmc); 20471c6a0718SPierre Ossman unsigned long flags; 20481c6a0718SPierre Ossman 20491c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 20501c6a0718SPierre Ossman 205166fd8ad5SAdrian Hunter /* Check host->mrq first in case we are runtime suspended */ 205266fd8ad5SAdrian Hunter if (host->mrq && 205366fd8ad5SAdrian Hunter !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 2054a3c76eb9SGirish K S pr_err("%s: Card removed during transfer!\n", 20551c6a0718SPierre Ossman mmc_hostname(host->mmc)); 2056a3c76eb9SGirish K S pr_err("%s: Resetting controller.\n", 20571c6a0718SPierre Ossman mmc_hostname(host->mmc)); 20581c6a0718SPierre Ossman 20591c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_CMD); 20601c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_DATA); 20611c6a0718SPierre Ossman 206217b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 20631c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 20641c6a0718SPierre Ossman } 20651c6a0718SPierre Ossman 20661c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 206771e69211SGuennadi Liakhovetski } 206871e69211SGuennadi Liakhovetski 206971e69211SGuennadi Liakhovetski static const struct mmc_host_ops sdhci_ops = { 207071e69211SGuennadi Liakhovetski .request = sdhci_request, 207171e69211SGuennadi Liakhovetski .set_ios = sdhci_set_ios, 207294144a46SKevin Liu .get_cd = sdhci_get_cd, 207371e69211SGuennadi Liakhovetski .get_ro = sdhci_get_ro, 207471e69211SGuennadi Liakhovetski .hw_reset = sdhci_hw_reset, 207571e69211SGuennadi Liakhovetski .enable_sdio_irq = sdhci_enable_sdio_irq, 207671e69211SGuennadi Liakhovetski .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 207771e69211SGuennadi Liakhovetski .execute_tuning = sdhci_execute_tuning, 207871e69211SGuennadi Liakhovetski .card_event = sdhci_card_event, 207920b92a30SKevin Liu .card_busy = sdhci_card_busy, 208071e69211SGuennadi Liakhovetski }; 208171e69211SGuennadi Liakhovetski 208271e69211SGuennadi Liakhovetski /*****************************************************************************\ 208371e69211SGuennadi Liakhovetski * * 208471e69211SGuennadi Liakhovetski * Tasklets * 208571e69211SGuennadi Liakhovetski * * 208671e69211SGuennadi Liakhovetski \*****************************************************************************/ 208771e69211SGuennadi Liakhovetski 208871e69211SGuennadi Liakhovetski static void sdhci_tasklet_card(unsigned long param) 208971e69211SGuennadi Liakhovetski { 209071e69211SGuennadi Liakhovetski struct sdhci_host *host = (struct sdhci_host*)param; 209171e69211SGuennadi Liakhovetski 209271e69211SGuennadi Liakhovetski sdhci_card_event(host->mmc); 20931c6a0718SPierre Ossman 209404cf585dSPierre Ossman mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 20951c6a0718SPierre Ossman } 20961c6a0718SPierre Ossman 20971c6a0718SPierre Ossman static void sdhci_tasklet_finish(unsigned long param) 20981c6a0718SPierre Ossman { 20991c6a0718SPierre Ossman struct sdhci_host *host; 21001c6a0718SPierre Ossman unsigned long flags; 21011c6a0718SPierre Ossman struct mmc_request *mrq; 21021c6a0718SPierre Ossman 21031c6a0718SPierre Ossman host = (struct sdhci_host*)param; 21041c6a0718SPierre Ossman 210566fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 210666fd8ad5SAdrian Hunter 21070c9c99a7SChris Ball /* 21080c9c99a7SChris Ball * If this tasklet gets rescheduled while running, it will 21090c9c99a7SChris Ball * be run again afterwards but without any active request. 21100c9c99a7SChris Ball */ 211166fd8ad5SAdrian Hunter if (!host->mrq) { 211266fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 21130c9c99a7SChris Ball return; 211466fd8ad5SAdrian Hunter } 21151c6a0718SPierre Ossman 21161c6a0718SPierre Ossman del_timer(&host->timer); 21171c6a0718SPierre Ossman 21181c6a0718SPierre Ossman mrq = host->mrq; 21191c6a0718SPierre Ossman 21201c6a0718SPierre Ossman /* 21211c6a0718SPierre Ossman * The controller needs a reset of internal state machines 21221c6a0718SPierre Ossman * upon error conditions. 21231c6a0718SPierre Ossman */ 21241e72859eSPierre Ossman if (!(host->flags & SDHCI_DEVICE_DEAD) && 2125b7b4d342SBen Dooks ((mrq->cmd && mrq->cmd->error) || 212617b0429dSPierre Ossman (mrq->data && (mrq->data->error || 212784c46a53SPierre Ossman (mrq->data->stop && mrq->data->stop->error))) || 21281e72859eSPierre Ossman (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 21291c6a0718SPierre Ossman 21301c6a0718SPierre Ossman /* Some controllers need this kick or reset won't work here */ 21318213af3bSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 21321c6a0718SPierre Ossman /* This is to force an update */ 21338213af3bSAndy Shevchenko sdhci_update_clock(host); 21341c6a0718SPierre Ossman 21351c6a0718SPierre Ossman /* Spec says we should do both at the same time, but Ricoh 21361c6a0718SPierre Ossman controllers do not like that. */ 21371c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_CMD); 21381c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_DATA); 21391c6a0718SPierre Ossman } 21401c6a0718SPierre Ossman 21411c6a0718SPierre Ossman host->mrq = NULL; 21421c6a0718SPierre Ossman host->cmd = NULL; 21431c6a0718SPierre Ossman host->data = NULL; 21441c6a0718SPierre Ossman 2145f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 21461c6a0718SPierre Ossman sdhci_deactivate_led(host); 21472f730fecSPierre Ossman #endif 21481c6a0718SPierre Ossman 21491c6a0718SPierre Ossman mmiowb(); 21501c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 21511c6a0718SPierre Ossman 21521c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 215366fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 21541c6a0718SPierre Ossman } 21551c6a0718SPierre Ossman 21561c6a0718SPierre Ossman static void sdhci_timeout_timer(unsigned long data) 21571c6a0718SPierre Ossman { 21581c6a0718SPierre Ossman struct sdhci_host *host; 21591c6a0718SPierre Ossman unsigned long flags; 21601c6a0718SPierre Ossman 21611c6a0718SPierre Ossman host = (struct sdhci_host*)data; 21621c6a0718SPierre Ossman 21631c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 21641c6a0718SPierre Ossman 21651c6a0718SPierre Ossman if (host->mrq) { 2166a3c76eb9SGirish K S pr_err("%s: Timeout waiting for hardware " 21671c6a0718SPierre Ossman "interrupt.\n", mmc_hostname(host->mmc)); 21681c6a0718SPierre Ossman sdhci_dumpregs(host); 21691c6a0718SPierre Ossman 21701c6a0718SPierre Ossman if (host->data) { 217117b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 21721c6a0718SPierre Ossman sdhci_finish_data(host); 21731c6a0718SPierre Ossman } else { 21741c6a0718SPierre Ossman if (host->cmd) 217517b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 21761c6a0718SPierre Ossman else 217717b0429dSPierre Ossman host->mrq->cmd->error = -ETIMEDOUT; 21781c6a0718SPierre Ossman 21791c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 21801c6a0718SPierre Ossman } 21811c6a0718SPierre Ossman } 21821c6a0718SPierre Ossman 21831c6a0718SPierre Ossman mmiowb(); 21841c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 21851c6a0718SPierre Ossman } 21861c6a0718SPierre Ossman 2187cf2b5eeaSArindam Nath static void sdhci_tuning_timer(unsigned long data) 2188cf2b5eeaSArindam Nath { 2189cf2b5eeaSArindam Nath struct sdhci_host *host; 2190cf2b5eeaSArindam Nath unsigned long flags; 2191cf2b5eeaSArindam Nath 2192cf2b5eeaSArindam Nath host = (struct sdhci_host *)data; 2193cf2b5eeaSArindam Nath 2194cf2b5eeaSArindam Nath spin_lock_irqsave(&host->lock, flags); 2195cf2b5eeaSArindam Nath 2196cf2b5eeaSArindam Nath host->flags |= SDHCI_NEEDS_RETUNING; 2197cf2b5eeaSArindam Nath 2198cf2b5eeaSArindam Nath spin_unlock_irqrestore(&host->lock, flags); 2199cf2b5eeaSArindam Nath } 2200cf2b5eeaSArindam Nath 22011c6a0718SPierre Ossman /*****************************************************************************\ 22021c6a0718SPierre Ossman * * 22031c6a0718SPierre Ossman * Interrupt handling * 22041c6a0718SPierre Ossman * * 22051c6a0718SPierre Ossman \*****************************************************************************/ 22061c6a0718SPierre Ossman 22071c6a0718SPierre Ossman static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 22081c6a0718SPierre Ossman { 22091c6a0718SPierre Ossman BUG_ON(intmask == 0); 22101c6a0718SPierre Ossman 22111c6a0718SPierre Ossman if (!host->cmd) { 2212a3c76eb9SGirish K S pr_err("%s: Got command interrupt 0x%08x even " 2213b67ac3f3SPierre Ossman "though no command operation was in progress.\n", 2214b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 22151c6a0718SPierre Ossman sdhci_dumpregs(host); 22161c6a0718SPierre Ossman return; 22171c6a0718SPierre Ossman } 22181c6a0718SPierre Ossman 22191c6a0718SPierre Ossman if (intmask & SDHCI_INT_TIMEOUT) 222017b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 222117b0429dSPierre Ossman else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 222217b0429dSPierre Ossman SDHCI_INT_INDEX)) 222317b0429dSPierre Ossman host->cmd->error = -EILSEQ; 22241c6a0718SPierre Ossman 2225e809517fSPierre Ossman if (host->cmd->error) { 22261c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 2227e809517fSPierre Ossman return; 2228e809517fSPierre Ossman } 2229e809517fSPierre Ossman 2230e809517fSPierre Ossman /* 2231e809517fSPierre Ossman * The host can send and interrupt when the busy state has 2232e809517fSPierre Ossman * ended, allowing us to wait without wasting CPU cycles. 2233e809517fSPierre Ossman * Unfortunately this is overloaded on the "data complete" 2234e809517fSPierre Ossman * interrupt, so we need to take some care when handling 2235e809517fSPierre Ossman * it. 2236e809517fSPierre Ossman * 2237e809517fSPierre Ossman * Note: The 1.0 specification is a bit ambiguous about this 2238e809517fSPierre Ossman * feature so there might be some problems with older 2239e809517fSPierre Ossman * controllers. 2240e809517fSPierre Ossman */ 2241e809517fSPierre Ossman if (host->cmd->flags & MMC_RSP_BUSY) { 2242e809517fSPierre Ossman if (host->cmd->data) 2243e809517fSPierre Ossman DBG("Cannot wait for busy signal when also " 2244e809517fSPierre Ossman "doing a data transfer"); 2245f945405cSBen Dooks else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2246e809517fSPierre Ossman return; 2247f945405cSBen Dooks 2248f945405cSBen Dooks /* The controller does not support the end-of-busy IRQ, 2249f945405cSBen Dooks * fall through and take the SDHCI_INT_RESPONSE */ 2250e809517fSPierre Ossman } 2251e809517fSPierre Ossman 2252e809517fSPierre Ossman if (intmask & SDHCI_INT_RESPONSE) 225343b58b36SPierre Ossman sdhci_finish_command(host); 22541c6a0718SPierre Ossman } 22551c6a0718SPierre Ossman 22560957c333SGeorge G. Davis #ifdef CONFIG_MMC_DEBUG 22576882a8c0SBen Dooks static void sdhci_show_adma_error(struct sdhci_host *host) 22586882a8c0SBen Dooks { 22596882a8c0SBen Dooks const char *name = mmc_hostname(host->mmc); 22606882a8c0SBen Dooks u8 *desc = host->adma_desc; 22616882a8c0SBen Dooks __le32 *dma; 22626882a8c0SBen Dooks __le16 *len; 22636882a8c0SBen Dooks u8 attr; 22646882a8c0SBen Dooks 22656882a8c0SBen Dooks sdhci_dumpregs(host); 22666882a8c0SBen Dooks 22676882a8c0SBen Dooks while (true) { 22686882a8c0SBen Dooks dma = (__le32 *)(desc + 4); 22696882a8c0SBen Dooks len = (__le16 *)(desc + 2); 22706882a8c0SBen Dooks attr = *desc; 22716882a8c0SBen Dooks 22726882a8c0SBen Dooks DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 22736882a8c0SBen Dooks name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 22746882a8c0SBen Dooks 22756882a8c0SBen Dooks desc += 8; 22766882a8c0SBen Dooks 22776882a8c0SBen Dooks if (attr & 2) 22786882a8c0SBen Dooks break; 22796882a8c0SBen Dooks } 22806882a8c0SBen Dooks } 22816882a8c0SBen Dooks #else 22826882a8c0SBen Dooks static void sdhci_show_adma_error(struct sdhci_host *host) { } 22836882a8c0SBen Dooks #endif 22846882a8c0SBen Dooks 22851c6a0718SPierre Ossman static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 22861c6a0718SPierre Ossman { 2287069c9f14SGirish K S u32 command; 22881c6a0718SPierre Ossman BUG_ON(intmask == 0); 22891c6a0718SPierre Ossman 2290b513ea25SArindam Nath /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2291b513ea25SArindam Nath if (intmask & SDHCI_INT_DATA_AVAIL) { 2292069c9f14SGirish K S command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2293069c9f14SGirish K S if (command == MMC_SEND_TUNING_BLOCK || 2294069c9f14SGirish K S command == MMC_SEND_TUNING_BLOCK_HS200) { 2295b513ea25SArindam Nath host->tuning_done = 1; 2296b513ea25SArindam Nath wake_up(&host->buf_ready_int); 2297b513ea25SArindam Nath return; 2298b513ea25SArindam Nath } 2299b513ea25SArindam Nath } 2300b513ea25SArindam Nath 23011c6a0718SPierre Ossman if (!host->data) { 23021c6a0718SPierre Ossman /* 2303e809517fSPierre Ossman * The "data complete" interrupt is also used to 2304e809517fSPierre Ossman * indicate that a busy state has ended. See comment 2305e809517fSPierre Ossman * above in sdhci_cmd_irq(). 23061c6a0718SPierre Ossman */ 2307e809517fSPierre Ossman if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2308e809517fSPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2309e809517fSPierre Ossman sdhci_finish_command(host); 23101c6a0718SPierre Ossman return; 2311e809517fSPierre Ossman } 2312e809517fSPierre Ossman } 23131c6a0718SPierre Ossman 2314a3c76eb9SGirish K S pr_err("%s: Got data interrupt 0x%08x even " 2315b67ac3f3SPierre Ossman "though no data operation was in progress.\n", 2316b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 23171c6a0718SPierre Ossman sdhci_dumpregs(host); 23181c6a0718SPierre Ossman 23191c6a0718SPierre Ossman return; 23201c6a0718SPierre Ossman } 23211c6a0718SPierre Ossman 23221c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_TIMEOUT) 232317b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 232422113efdSAries Lee else if (intmask & SDHCI_INT_DATA_END_BIT) 232522113efdSAries Lee host->data->error = -EILSEQ; 232622113efdSAries Lee else if ((intmask & SDHCI_INT_DATA_CRC) && 232722113efdSAries Lee SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 232822113efdSAries Lee != MMC_BUS_TEST_R) 232917b0429dSPierre Ossman host->data->error = -EILSEQ; 23306882a8c0SBen Dooks else if (intmask & SDHCI_INT_ADMA_ERROR) { 2331a3c76eb9SGirish K S pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 23326882a8c0SBen Dooks sdhci_show_adma_error(host); 23332134a922SPierre Ossman host->data->error = -EIO; 2334a4071fbbSHaijun Zhang if (host->ops->adma_workaround) 2335a4071fbbSHaijun Zhang host->ops->adma_workaround(host, intmask); 23366882a8c0SBen Dooks } 23371c6a0718SPierre Ossman 233817b0429dSPierre Ossman if (host->data->error) 23391c6a0718SPierre Ossman sdhci_finish_data(host); 23401c6a0718SPierre Ossman else { 23411c6a0718SPierre Ossman if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 23421c6a0718SPierre Ossman sdhci_transfer_pio(host); 23431c6a0718SPierre Ossman 23446ba736a1SPierre Ossman /* 23456ba736a1SPierre Ossman * We currently don't do anything fancy with DMA 23466ba736a1SPierre Ossman * boundaries, but as we can't disable the feature 23476ba736a1SPierre Ossman * we need to at least restart the transfer. 2348f6a03cbfSMikko Vinni * 2349f6a03cbfSMikko Vinni * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2350f6a03cbfSMikko Vinni * should return a valid address to continue from, but as 2351f6a03cbfSMikko Vinni * some controllers are faulty, don't trust them. 23526ba736a1SPierre Ossman */ 2353f6a03cbfSMikko Vinni if (intmask & SDHCI_INT_DMA_END) { 2354f6a03cbfSMikko Vinni u32 dmastart, dmanow; 2355f6a03cbfSMikko Vinni dmastart = sg_dma_address(host->data->sg); 2356f6a03cbfSMikko Vinni dmanow = dmastart + host->data->bytes_xfered; 2357f6a03cbfSMikko Vinni /* 2358f6a03cbfSMikko Vinni * Force update to the next DMA block boundary. 2359f6a03cbfSMikko Vinni */ 2360f6a03cbfSMikko Vinni dmanow = (dmanow & 2361f6a03cbfSMikko Vinni ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2362f6a03cbfSMikko Vinni SDHCI_DEFAULT_BOUNDARY_SIZE; 2363f6a03cbfSMikko Vinni host->data->bytes_xfered = dmanow - dmastart; 2364f6a03cbfSMikko Vinni DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2365f6a03cbfSMikko Vinni " next 0x%08x\n", 2366f6a03cbfSMikko Vinni mmc_hostname(host->mmc), dmastart, 2367f6a03cbfSMikko Vinni host->data->bytes_xfered, dmanow); 2368f6a03cbfSMikko Vinni sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2369f6a03cbfSMikko Vinni } 23706ba736a1SPierre Ossman 2371e538fbe8SPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2372e538fbe8SPierre Ossman if (host->cmd) { 2373e538fbe8SPierre Ossman /* 2374e538fbe8SPierre Ossman * Data managed to finish before the 2375e538fbe8SPierre Ossman * command completed. Make sure we do 2376e538fbe8SPierre Ossman * things in the proper order. 2377e538fbe8SPierre Ossman */ 2378e538fbe8SPierre Ossman host->data_early = 1; 2379e538fbe8SPierre Ossman } else { 23801c6a0718SPierre Ossman sdhci_finish_data(host); 23811c6a0718SPierre Ossman } 23821c6a0718SPierre Ossman } 2383e538fbe8SPierre Ossman } 2384e538fbe8SPierre Ossman } 23851c6a0718SPierre Ossman 23861c6a0718SPierre Ossman static irqreturn_t sdhci_irq(int irq, void *dev_id) 23871c6a0718SPierre Ossman { 23881c6a0718SPierre Ossman irqreturn_t result; 23891c6a0718SPierre Ossman struct sdhci_host *host = dev_id; 23906379b237SAlexander Stein u32 intmask, unexpected = 0; 23916379b237SAlexander Stein int cardint = 0, max_loops = 16; 23921c6a0718SPierre Ossman 23931c6a0718SPierre Ossman spin_lock(&host->lock); 23941c6a0718SPierre Ossman 239566fd8ad5SAdrian Hunter if (host->runtime_suspended) { 239666fd8ad5SAdrian Hunter spin_unlock(&host->lock); 2397a3c76eb9SGirish K S pr_warning("%s: got irq while runtime suspended\n", 239866fd8ad5SAdrian Hunter mmc_hostname(host->mmc)); 239966fd8ad5SAdrian Hunter return IRQ_HANDLED; 240066fd8ad5SAdrian Hunter } 240166fd8ad5SAdrian Hunter 24024e4141a5SAnton Vorontsov intmask = sdhci_readl(host, SDHCI_INT_STATUS); 24031c6a0718SPierre Ossman 24041c6a0718SPierre Ossman if (!intmask || intmask == 0xffffffff) { 24051c6a0718SPierre Ossman result = IRQ_NONE; 24061c6a0718SPierre Ossman goto out; 24071c6a0718SPierre Ossman } 24081c6a0718SPierre Ossman 24096379b237SAlexander Stein again: 2410b69c9058SPierre Ossman DBG("*** %s got interrupt: 0x%08x\n", 2411b69c9058SPierre Ossman mmc_hostname(host->mmc), intmask); 24121c6a0718SPierre Ossman 24131c6a0718SPierre Ossman if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2414d25928d1SShawn Guo u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2415d25928d1SShawn Guo SDHCI_CARD_PRESENT; 2416d25928d1SShawn Guo 2417d25928d1SShawn Guo /* 2418d25928d1SShawn Guo * There is a observation on i.mx esdhc. INSERT bit will be 2419d25928d1SShawn Guo * immediately set again when it gets cleared, if a card is 2420d25928d1SShawn Guo * inserted. We have to mask the irq to prevent interrupt 2421d25928d1SShawn Guo * storm which will freeze the system. And the REMOVE gets 2422d25928d1SShawn Guo * the same situation. 2423d25928d1SShawn Guo * 2424d25928d1SShawn Guo * More testing are needed here to ensure it works for other 2425d25928d1SShawn Guo * platforms though. 2426d25928d1SShawn Guo */ 2427d25928d1SShawn Guo sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : 2428d25928d1SShawn Guo SDHCI_INT_CARD_REMOVE); 2429d25928d1SShawn Guo sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : 2430d25928d1SShawn Guo SDHCI_INT_CARD_INSERT); 2431d25928d1SShawn Guo 24324e4141a5SAnton Vorontsov sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 24334e4141a5SAnton Vorontsov SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2434d25928d1SShawn Guo intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 24351c6a0718SPierre Ossman tasklet_schedule(&host->card_tasklet); 24361c6a0718SPierre Ossman } 24371c6a0718SPierre Ossman 24381c6a0718SPierre Ossman if (intmask & SDHCI_INT_CMD_MASK) { 24394e4141a5SAnton Vorontsov sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, 24404e4141a5SAnton Vorontsov SDHCI_INT_STATUS); 24411c6a0718SPierre Ossman sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 24421c6a0718SPierre Ossman } 24431c6a0718SPierre Ossman 24441c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_MASK) { 24454e4141a5SAnton Vorontsov sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, 24464e4141a5SAnton Vorontsov SDHCI_INT_STATUS); 24471c6a0718SPierre Ossman sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 24481c6a0718SPierre Ossman } 24491c6a0718SPierre Ossman 24501c6a0718SPierre Ossman intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 24511c6a0718SPierre Ossman 2452964f9ce2SPierre Ossman intmask &= ~SDHCI_INT_ERROR; 2453964f9ce2SPierre Ossman 24541c6a0718SPierre Ossman if (intmask & SDHCI_INT_BUS_POWER) { 2455a3c76eb9SGirish K S pr_err("%s: Card is consuming too much power!\n", 24561c6a0718SPierre Ossman mmc_hostname(host->mmc)); 24574e4141a5SAnton Vorontsov sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); 24581c6a0718SPierre Ossman } 24591c6a0718SPierre Ossman 24609d26a5d3SRolf Eike Beer intmask &= ~SDHCI_INT_BUS_POWER; 24611c6a0718SPierre Ossman 2462f75979b7SPierre Ossman if (intmask & SDHCI_INT_CARD_INT) 2463f75979b7SPierre Ossman cardint = 1; 2464f75979b7SPierre Ossman 2465f75979b7SPierre Ossman intmask &= ~SDHCI_INT_CARD_INT; 2466f75979b7SPierre Ossman 24671c6a0718SPierre Ossman if (intmask) { 24686379b237SAlexander Stein unexpected |= intmask; 24694e4141a5SAnton Vorontsov sdhci_writel(host, intmask, SDHCI_INT_STATUS); 24701c6a0718SPierre Ossman } 24711c6a0718SPierre Ossman 24721c6a0718SPierre Ossman result = IRQ_HANDLED; 24731c6a0718SPierre Ossman 24746379b237SAlexander Stein intmask = sdhci_readl(host, SDHCI_INT_STATUS); 24756379b237SAlexander Stein if (intmask && --max_loops) 24766379b237SAlexander Stein goto again; 24771c6a0718SPierre Ossman out: 24781c6a0718SPierre Ossman spin_unlock(&host->lock); 24791c6a0718SPierre Ossman 24806379b237SAlexander Stein if (unexpected) { 24816379b237SAlexander Stein pr_err("%s: Unexpected interrupt 0x%08x.\n", 24826379b237SAlexander Stein mmc_hostname(host->mmc), unexpected); 24836379b237SAlexander Stein sdhci_dumpregs(host); 24846379b237SAlexander Stein } 2485f75979b7SPierre Ossman /* 2486f75979b7SPierre Ossman * We have to delay this as it calls back into the driver. 2487f75979b7SPierre Ossman */ 2488f75979b7SPierre Ossman if (cardint) 2489f75979b7SPierre Ossman mmc_signal_sdio_irq(host->mmc); 2490f75979b7SPierre Ossman 24911c6a0718SPierre Ossman return result; 24921c6a0718SPierre Ossman } 24931c6a0718SPierre Ossman 24941c6a0718SPierre Ossman /*****************************************************************************\ 24951c6a0718SPierre Ossman * * 24961c6a0718SPierre Ossman * Suspend/resume * 24971c6a0718SPierre Ossman * * 24981c6a0718SPierre Ossman \*****************************************************************************/ 24991c6a0718SPierre Ossman 25001c6a0718SPierre Ossman #ifdef CONFIG_PM 2501ad080d79SKevin Liu void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2502ad080d79SKevin Liu { 2503ad080d79SKevin Liu u8 val; 2504ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2505ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2506ad080d79SKevin Liu 2507ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2508ad080d79SKevin Liu val |= mask ; 2509ad080d79SKevin Liu /* Avoid fake wake up */ 2510ad080d79SKevin Liu if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2511ad080d79SKevin Liu val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2512ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2513ad080d79SKevin Liu } 2514ad080d79SKevin Liu EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2515ad080d79SKevin Liu 2516ad080d79SKevin Liu void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2517ad080d79SKevin Liu { 2518ad080d79SKevin Liu u8 val; 2519ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2520ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2521ad080d79SKevin Liu 2522ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2523ad080d79SKevin Liu val &= ~mask; 2524ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2525ad080d79SKevin Liu } 2526ad080d79SKevin Liu EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); 25271c6a0718SPierre Ossman 252829495aa0SManuel Lauss int sdhci_suspend_host(struct sdhci_host *host) 25291c6a0718SPierre Ossman { 2530b8c86fc5SPierre Ossman int ret; 25311c6a0718SPierre Ossman 2532a1b13b4eSChris Ball if (host->ops->platform_suspend) 2533a1b13b4eSChris Ball host->ops->platform_suspend(host); 2534a1b13b4eSChris Ball 25357260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 25367260cf5eSAnton Vorontsov 2537cf2b5eeaSArindam Nath /* Disable tuning since we are suspending */ 2538973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2539c6ced0dbSAaron Lu del_timer_sync(&host->tuning_timer); 2540cf2b5eeaSArindam Nath host->flags &= ~SDHCI_NEEDS_RETUNING; 2541cf2b5eeaSArindam Nath } 2542cf2b5eeaSArindam Nath 25431a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 254438a60ea2SAaron Lu if (ret) { 2545973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 254638a60ea2SAaron Lu host->flags |= SDHCI_NEEDS_RETUNING; 254738a60ea2SAaron Lu mod_timer(&host->tuning_timer, jiffies + 254838a60ea2SAaron Lu host->tuning_count * HZ); 254938a60ea2SAaron Lu } 255038a60ea2SAaron Lu 255138a60ea2SAaron Lu sdhci_enable_card_detection(host); 255238a60ea2SAaron Lu 25531c6a0718SPierre Ossman return ret; 255438a60ea2SAaron Lu } 25551c6a0718SPierre Ossman 2556ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2557b0a8deceSKevin Liu sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2558b8c86fc5SPierre Ossman free_irq(host->irq, host); 2559ad080d79SKevin Liu } else { 2560ad080d79SKevin Liu sdhci_enable_irq_wakeups(host); 2561ad080d79SKevin Liu enable_irq_wake(host->irq); 2562ad080d79SKevin Liu } 25639bea3c85SMarek Szyprowski return ret; 2564b8c86fc5SPierre Ossman } 2565b8c86fc5SPierre Ossman 2566b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2567b8c86fc5SPierre Ossman 2568b8c86fc5SPierre Ossman int sdhci_resume_host(struct sdhci_host *host) 2569b8c86fc5SPierre Ossman { 2570b8c86fc5SPierre Ossman int ret; 2571b8c86fc5SPierre Ossman 2572a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2573b8c86fc5SPierre Ossman if (host->ops->enable_dma) 2574b8c86fc5SPierre Ossman host->ops->enable_dma(host); 2575b8c86fc5SPierre Ossman } 2576b8c86fc5SPierre Ossman 2577ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2578b8c86fc5SPierre Ossman ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2579b8c86fc5SPierre Ossman mmc_hostname(host->mmc), host); 25801c6a0718SPierre Ossman if (ret) 25811c6a0718SPierre Ossman return ret; 2582ad080d79SKevin Liu } else { 2583ad080d79SKevin Liu sdhci_disable_irq_wakeups(host); 2584ad080d79SKevin Liu disable_irq_wake(host->irq); 2585ad080d79SKevin Liu } 2586b8c86fc5SPierre Ossman 25876308d290SAdrian Hunter if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 25886308d290SAdrian Hunter (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 25896308d290SAdrian Hunter /* Card keeps power but host controller does not */ 25906308d290SAdrian Hunter sdhci_init(host, 0); 25916308d290SAdrian Hunter host->pwr = 0; 25926308d290SAdrian Hunter host->clock = 0; 25936308d290SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 25946308d290SAdrian Hunter } else { 25952f4cbb3dSNicolas Pitre sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 25961c6a0718SPierre Ossman mmiowb(); 25976308d290SAdrian Hunter } 2598b8c86fc5SPierre Ossman 2599b8c86fc5SPierre Ossman ret = mmc_resume_host(host->mmc); 26007260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 26017260cf5eSAnton Vorontsov 2602a1b13b4eSChris Ball if (host->ops->platform_resume) 2603a1b13b4eSChris Ball host->ops->platform_resume(host); 2604a1b13b4eSChris Ball 2605cf2b5eeaSArindam Nath /* Set the re-tuning expiration flag */ 2606973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) 2607cf2b5eeaSArindam Nath host->flags |= SDHCI_NEEDS_RETUNING; 2608cf2b5eeaSArindam Nath 26092f4cbb3dSNicolas Pitre return ret; 26101c6a0718SPierre Ossman } 26111c6a0718SPierre Ossman 2612b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_resume_host); 26131c6a0718SPierre Ossman #endif /* CONFIG_PM */ 26141c6a0718SPierre Ossman 261566fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 261666fd8ad5SAdrian Hunter 261766fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host) 261866fd8ad5SAdrian Hunter { 261966fd8ad5SAdrian Hunter return pm_runtime_get_sync(host->mmc->parent); 262066fd8ad5SAdrian Hunter } 262166fd8ad5SAdrian Hunter 262266fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host) 262366fd8ad5SAdrian Hunter { 262466fd8ad5SAdrian Hunter pm_runtime_mark_last_busy(host->mmc->parent); 262566fd8ad5SAdrian Hunter return pm_runtime_put_autosuspend(host->mmc->parent); 262666fd8ad5SAdrian Hunter } 262766fd8ad5SAdrian Hunter 262866fd8ad5SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host) 262966fd8ad5SAdrian Hunter { 263066fd8ad5SAdrian Hunter unsigned long flags; 263166fd8ad5SAdrian Hunter int ret = 0; 263266fd8ad5SAdrian Hunter 263366fd8ad5SAdrian Hunter /* Disable tuning since we are suspending */ 2634973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 263566fd8ad5SAdrian Hunter del_timer_sync(&host->tuning_timer); 263666fd8ad5SAdrian Hunter host->flags &= ~SDHCI_NEEDS_RETUNING; 263766fd8ad5SAdrian Hunter } 263866fd8ad5SAdrian Hunter 263966fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 264066fd8ad5SAdrian Hunter sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 264166fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 264266fd8ad5SAdrian Hunter 264366fd8ad5SAdrian Hunter synchronize_irq(host->irq); 264466fd8ad5SAdrian Hunter 264566fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 264666fd8ad5SAdrian Hunter host->runtime_suspended = true; 264766fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 264866fd8ad5SAdrian Hunter 264966fd8ad5SAdrian Hunter return ret; 265066fd8ad5SAdrian Hunter } 265166fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 265266fd8ad5SAdrian Hunter 265366fd8ad5SAdrian Hunter int sdhci_runtime_resume_host(struct sdhci_host *host) 265466fd8ad5SAdrian Hunter { 265566fd8ad5SAdrian Hunter unsigned long flags; 265666fd8ad5SAdrian Hunter int ret = 0, host_flags = host->flags; 265766fd8ad5SAdrian Hunter 265866fd8ad5SAdrian Hunter if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 265966fd8ad5SAdrian Hunter if (host->ops->enable_dma) 266066fd8ad5SAdrian Hunter host->ops->enable_dma(host); 266166fd8ad5SAdrian Hunter } 266266fd8ad5SAdrian Hunter 266366fd8ad5SAdrian Hunter sdhci_init(host, 0); 266466fd8ad5SAdrian Hunter 266566fd8ad5SAdrian Hunter /* Force clock and power re-program */ 266666fd8ad5SAdrian Hunter host->pwr = 0; 266766fd8ad5SAdrian Hunter host->clock = 0; 266866fd8ad5SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 266966fd8ad5SAdrian Hunter 267066fd8ad5SAdrian Hunter sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 267152983382SKevin Liu if ((host_flags & SDHCI_PV_ENABLED) && 267252983382SKevin Liu !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 267352983382SKevin Liu spin_lock_irqsave(&host->lock, flags); 267452983382SKevin Liu sdhci_enable_preset_value(host, true); 267552983382SKevin Liu spin_unlock_irqrestore(&host->lock, flags); 267652983382SKevin Liu } 267766fd8ad5SAdrian Hunter 267866fd8ad5SAdrian Hunter /* Set the re-tuning expiration flag */ 2679973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) 268066fd8ad5SAdrian Hunter host->flags |= SDHCI_NEEDS_RETUNING; 268166fd8ad5SAdrian Hunter 268266fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 268366fd8ad5SAdrian Hunter 268466fd8ad5SAdrian Hunter host->runtime_suspended = false; 268566fd8ad5SAdrian Hunter 268666fd8ad5SAdrian Hunter /* Enable SDIO IRQ */ 268766fd8ad5SAdrian Hunter if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) 268866fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 268966fd8ad5SAdrian Hunter 269066fd8ad5SAdrian Hunter /* Enable Card Detection */ 269166fd8ad5SAdrian Hunter sdhci_enable_card_detection(host); 269266fd8ad5SAdrian Hunter 269366fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 269466fd8ad5SAdrian Hunter 269566fd8ad5SAdrian Hunter return ret; 269666fd8ad5SAdrian Hunter } 269766fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 269866fd8ad5SAdrian Hunter 269966fd8ad5SAdrian Hunter #endif 270066fd8ad5SAdrian Hunter 27011c6a0718SPierre Ossman /*****************************************************************************\ 27021c6a0718SPierre Ossman * * 2703b8c86fc5SPierre Ossman * Device allocation/registration * 27041c6a0718SPierre Ossman * * 27051c6a0718SPierre Ossman \*****************************************************************************/ 27061c6a0718SPierre Ossman 2707b8c86fc5SPierre Ossman struct sdhci_host *sdhci_alloc_host(struct device *dev, 2708b8c86fc5SPierre Ossman size_t priv_size) 27091c6a0718SPierre Ossman { 27101c6a0718SPierre Ossman struct mmc_host *mmc; 27111c6a0718SPierre Ossman struct sdhci_host *host; 27121c6a0718SPierre Ossman 2713b8c86fc5SPierre Ossman WARN_ON(dev == NULL); 27141c6a0718SPierre Ossman 2715b8c86fc5SPierre Ossman mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 27161c6a0718SPierre Ossman if (!mmc) 2717b8c86fc5SPierre Ossman return ERR_PTR(-ENOMEM); 27181c6a0718SPierre Ossman 27191c6a0718SPierre Ossman host = mmc_priv(mmc); 27201c6a0718SPierre Ossman host->mmc = mmc; 27211c6a0718SPierre Ossman 2722b8c86fc5SPierre Ossman return host; 27231c6a0718SPierre Ossman } 27241c6a0718SPierre Ossman 2725b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2726b8c86fc5SPierre Ossman 2727b8c86fc5SPierre Ossman int sdhci_add_host(struct sdhci_host *host) 2728b8c86fc5SPierre Ossman { 2729b8c86fc5SPierre Ossman struct mmc_host *mmc; 2730bd6a8c30SPhilip Rakity u32 caps[2] = {0, 0}; 2731f2119df6SArindam Nath u32 max_current_caps; 2732f2119df6SArindam Nath unsigned int ocr_avail; 2733b8c86fc5SPierre Ossman int ret; 2734b8c86fc5SPierre Ossman 2735b8c86fc5SPierre Ossman WARN_ON(host == NULL); 2736b8c86fc5SPierre Ossman if (host == NULL) 2737b8c86fc5SPierre Ossman return -EINVAL; 2738b8c86fc5SPierre Ossman 2739b8c86fc5SPierre Ossman mmc = host->mmc; 2740b8c86fc5SPierre Ossman 2741b8c86fc5SPierre Ossman if (debug_quirks) 2742b8c86fc5SPierre Ossman host->quirks = debug_quirks; 274366fd8ad5SAdrian Hunter if (debug_quirks2) 274466fd8ad5SAdrian Hunter host->quirks2 = debug_quirks2; 2745b8c86fc5SPierre Ossman 27461c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 27471c6a0718SPierre Ossman 27484e4141a5SAnton Vorontsov host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 27492134a922SPierre Ossman host->version = (host->version & SDHCI_SPEC_VER_MASK) 27502134a922SPierre Ossman >> SDHCI_SPEC_VER_SHIFT; 275185105c53SZhangfei Gao if (host->version > SDHCI_SPEC_300) { 2752a3c76eb9SGirish K S pr_err("%s: Unknown controller version (%d). " 2753b69c9058SPierre Ossman "You may experience problems.\n", mmc_hostname(mmc), 27542134a922SPierre Ossman host->version); 27551c6a0718SPierre Ossman } 27561c6a0718SPierre Ossman 2757f2119df6SArindam Nath caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2758ccc92c23SMaxim Levitsky sdhci_readl(host, SDHCI_CAPABILITIES); 27591c6a0718SPierre Ossman 2760bd6a8c30SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 2761bd6a8c30SPhilip Rakity caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2762bd6a8c30SPhilip Rakity host->caps1 : 2763bd6a8c30SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1); 2764f2119df6SArindam Nath 2765b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2766a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 2767f2119df6SArindam Nath else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2768a13abc7bSRichard Röjfors DBG("Controller doesn't have SDMA capability\n"); 27691c6a0718SPierre Ossman else 2770a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 27711c6a0718SPierre Ossman 2772b8c86fc5SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2773a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA)) { 2774cee687ceSRolf Eike Beer DBG("Disabling DMA as it is marked broken\n"); 2775a13abc7bSRichard Röjfors host->flags &= ~SDHCI_USE_SDMA; 27767c168e3dSFeng Tang } 27777c168e3dSFeng Tang 2778f2119df6SArindam Nath if ((host->version >= SDHCI_SPEC_200) && 2779f2119df6SArindam Nath (caps[0] & SDHCI_CAN_DO_ADMA2)) 27802134a922SPierre Ossman host->flags |= SDHCI_USE_ADMA; 27812134a922SPierre Ossman 27822134a922SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 27832134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) { 27842134a922SPierre Ossman DBG("Disabling ADMA as it is marked broken\n"); 27852134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 27862134a922SPierre Ossman } 27872134a922SPierre Ossman 2788a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2789b8c86fc5SPierre Ossman if (host->ops->enable_dma) { 2790b8c86fc5SPierre Ossman if (host->ops->enable_dma(host)) { 2791a3c76eb9SGirish K S pr_warning("%s: No suitable DMA " 2792b8c86fc5SPierre Ossman "available. Falling back to PIO.\n", 2793b8c86fc5SPierre Ossman mmc_hostname(mmc)); 2794a13abc7bSRichard Röjfors host->flags &= 2795a13abc7bSRichard Röjfors ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 27961c6a0718SPierre Ossman } 27971c6a0718SPierre Ossman } 2798b8c86fc5SPierre Ossman } 27991c6a0718SPierre Ossman 28002134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 28012134a922SPierre Ossman /* 28022134a922SPierre Ossman * We need to allocate descriptors for all sg entries 28032134a922SPierre Ossman * (128) and potentially one alignment transfer for 28042134a922SPierre Ossman * each of those entries. 28052134a922SPierre Ossman */ 28062134a922SPierre Ossman host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 28072134a922SPierre Ossman host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 28082134a922SPierre Ossman if (!host->adma_desc || !host->align_buffer) { 28092134a922SPierre Ossman kfree(host->adma_desc); 28102134a922SPierre Ossman kfree(host->align_buffer); 2811a3c76eb9SGirish K S pr_warning("%s: Unable to allocate ADMA " 28122134a922SPierre Ossman "buffers. Falling back to standard DMA.\n", 28132134a922SPierre Ossman mmc_hostname(mmc)); 28142134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 28152134a922SPierre Ossman } 28162134a922SPierre Ossman } 28172134a922SPierre Ossman 28187659150cSPierre Ossman /* 28197659150cSPierre Ossman * If we use DMA, then it's up to the caller to set the DMA 28207659150cSPierre Ossman * mask, but PIO does not need the hw shim so we set a new 28217659150cSPierre Ossman * mask here in that case. 28227659150cSPierre Ossman */ 2823a13abc7bSRichard Röjfors if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 28247659150cSPierre Ossman host->dma_mask = DMA_BIT_MASK(64); 28257659150cSPierre Ossman mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 28267659150cSPierre Ossman } 28271c6a0718SPierre Ossman 2828c4687d5fSZhangfei Gao if (host->version >= SDHCI_SPEC_300) 2829f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2830c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2831c4687d5fSZhangfei Gao else 2832f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2833c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2834c4687d5fSZhangfei Gao 28354240ff0aSBen Dooks host->max_clk *= 1000000; 2836f27f47efSAnton Vorontsov if (host->max_clk == 0 || host->quirks & 2837f27f47efSAnton Vorontsov SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 28384240ff0aSBen Dooks if (!host->ops->get_max_clock) { 2839a3c76eb9SGirish K S pr_err("%s: Hardware doesn't specify base clock " 2840b69c9058SPierre Ossman "frequency.\n", mmc_hostname(mmc)); 2841b8c86fc5SPierre Ossman return -ENODEV; 28421c6a0718SPierre Ossman } 28434240ff0aSBen Dooks host->max_clk = host->ops->get_max_clock(host); 28444240ff0aSBen Dooks } 28451c6a0718SPierre Ossman 28461c6a0718SPierre Ossman /* 2847c3ed3877SArindam Nath * In case of Host Controller v3.00, find out whether clock 2848c3ed3877SArindam Nath * multiplier is supported. 2849c3ed3877SArindam Nath */ 2850c3ed3877SArindam Nath host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2851c3ed3877SArindam Nath SDHCI_CLOCK_MUL_SHIFT; 2852c3ed3877SArindam Nath 2853c3ed3877SArindam Nath /* 2854c3ed3877SArindam Nath * In case the value in Clock Multiplier is 0, then programmable 2855c3ed3877SArindam Nath * clock mode is not supported, otherwise the actual clock 2856c3ed3877SArindam Nath * multiplier is one more than the value of Clock Multiplier 2857c3ed3877SArindam Nath * in the Capabilities Register. 2858c3ed3877SArindam Nath */ 2859c3ed3877SArindam Nath if (host->clk_mul) 2860c3ed3877SArindam Nath host->clk_mul += 1; 2861c3ed3877SArindam Nath 2862c3ed3877SArindam Nath /* 28631c6a0718SPierre Ossman * Set host parameters. 28641c6a0718SPierre Ossman */ 28651c6a0718SPierre Ossman mmc->ops = &sdhci_ops; 2866c3ed3877SArindam Nath mmc->f_max = host->max_clk; 2867ce5f036bSMarek Szyprowski if (host->ops->get_min_clock) 2868a9e58f25SAnton Vorontsov mmc->f_min = host->ops->get_min_clock(host); 2869c3ed3877SArindam Nath else if (host->version >= SDHCI_SPEC_300) { 2870c3ed3877SArindam Nath if (host->clk_mul) { 2871c3ed3877SArindam Nath mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2872c3ed3877SArindam Nath mmc->f_max = host->max_clk * host->clk_mul; 2873c3ed3877SArindam Nath } else 28740397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2875c3ed3877SArindam Nath } else 28760397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 287715ec4461SPhilip Rakity 2878272308caSAndy Shevchenko host->timeout_clk = 2879272308caSAndy Shevchenko (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2880272308caSAndy Shevchenko if (host->timeout_clk == 0) { 2881272308caSAndy Shevchenko if (host->ops->get_timeout_clock) { 2882272308caSAndy Shevchenko host->timeout_clk = host->ops->get_timeout_clock(host); 2883272308caSAndy Shevchenko } else if (!(host->quirks & 2884272308caSAndy Shevchenko SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2885a3c76eb9SGirish K S pr_err("%s: Hardware doesn't specify timeout clock " 2886272308caSAndy Shevchenko "frequency.\n", mmc_hostname(mmc)); 2887272308caSAndy Shevchenko return -ENODEV; 2888272308caSAndy Shevchenko } 2889272308caSAndy Shevchenko } 2890272308caSAndy Shevchenko if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2891272308caSAndy Shevchenko host->timeout_clk *= 1000; 2892272308caSAndy Shevchenko 2893272308caSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 289465be3fefSAndy Shevchenko host->timeout_clk = mmc->f_max / 1000; 2895272308caSAndy Shevchenko 289658d1246dSAdrian Hunter mmc->max_discard_to = (1 << 27) / host->timeout_clk; 289758d1246dSAdrian Hunter 2898e89d456fSAndrei Warkentin mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2899e89d456fSAndrei Warkentin 2900e89d456fSAndrei Warkentin if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2901e89d456fSAndrei Warkentin host->flags |= SDHCI_AUTO_CMD12; 29025fe23c7fSAnton Vorontsov 29038edf6371SAndrei Warkentin /* Auto-CMD23 stuff only works in ADMA or PIO. */ 29044f3d3e9bSAndrei Warkentin if ((host->version >= SDHCI_SPEC_300) && 29058edf6371SAndrei Warkentin ((host->flags & SDHCI_USE_ADMA) || 29064f3d3e9bSAndrei Warkentin !(host->flags & SDHCI_USE_SDMA))) { 29078edf6371SAndrei Warkentin host->flags |= SDHCI_AUTO_CMD23; 29088edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 29098edf6371SAndrei Warkentin } else { 29108edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 29118edf6371SAndrei Warkentin } 29128edf6371SAndrei Warkentin 291315ec4461SPhilip Rakity /* 291415ec4461SPhilip Rakity * A controller may support 8-bit width, but the board itself 291515ec4461SPhilip Rakity * might not have the pins brought out. Boards that support 291615ec4461SPhilip Rakity * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 291715ec4461SPhilip Rakity * their platform code before calling sdhci_add_host(), and we 291815ec4461SPhilip Rakity * won't assume 8-bit width for hosts without that CAP. 291915ec4461SPhilip Rakity */ 29205fe23c7fSAnton Vorontsov if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 292115ec4461SPhilip Rakity mmc->caps |= MMC_CAP_4_BIT_DATA; 29221c6a0718SPierre Ossman 292363ef5d8cSJerry Huang if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 292463ef5d8cSJerry Huang mmc->caps &= ~MMC_CAP_CMD23; 292563ef5d8cSJerry Huang 2926f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_DO_HISPD) 2927a29e7e18SZhangfei Gao mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 29281c6a0718SPierre Ossman 2929176d1ed4SJaehoon Chung if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2930eb6d5ae1SDaniel Drake !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 293168d1fb7eSAnton Vorontsov mmc->caps |= MMC_CAP_NEEDS_POLL; 293268d1fb7eSAnton Vorontsov 29336231f3deSPhilip Rakity /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 29346231f3deSPhilip Rakity host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc"); 2935657d5982SKevin Liu if (IS_ERR_OR_NULL(host->vqmmc)) { 2936657d5982SKevin Liu if (PTR_ERR(host->vqmmc) < 0) { 2937657d5982SKevin Liu pr_info("%s: no vqmmc regulator found\n", 2938657d5982SKevin Liu mmc_hostname(mmc)); 29396231f3deSPhilip Rakity host->vqmmc = NULL; 29406231f3deSPhilip Rakity } 29418363c374SKevin Liu } else { 29426231f3deSPhilip Rakity regulator_enable(host->vqmmc); 2943cec2e216SKevin Liu if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2944cec2e216SKevin Liu 1950000)) 29458363c374SKevin Liu caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 29468363c374SKevin Liu SDHCI_SUPPORT_SDR50 | 29476231f3deSPhilip Rakity SDHCI_SUPPORT_DDR50); 29488363c374SKevin Liu } 29496231f3deSPhilip Rakity 29506a66180aSDaniel Drake if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 29516a66180aSDaniel Drake caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 29526a66180aSDaniel Drake SDHCI_SUPPORT_DDR50); 29536a66180aSDaniel Drake 29544188bba0SAl Cooper /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 29554188bba0SAl Cooper if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 29564188bba0SAl Cooper SDHCI_SUPPORT_DDR50)) 2957f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 2958f2119df6SArindam Nath 2959f2119df6SArindam Nath /* SDR104 supports also implies SDR50 support */ 2960f2119df6SArindam Nath if (caps[1] & SDHCI_SUPPORT_SDR104) 2961f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 2962f2119df6SArindam Nath else if (caps[1] & SDHCI_SUPPORT_SDR50) 2963f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR50; 2964f2119df6SArindam Nath 2965f2119df6SArindam Nath if (caps[1] & SDHCI_SUPPORT_DDR50) 2966f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_DDR50; 2967f2119df6SArindam Nath 2968069c9f14SGirish K S /* Does the host need tuning for SDR50? */ 2969b513ea25SArindam Nath if (caps[1] & SDHCI_USE_SDR50_TUNING) 2970b513ea25SArindam Nath host->flags |= SDHCI_SDR50_NEEDS_TUNING; 2971b513ea25SArindam Nath 2972069c9f14SGirish K S /* Does the host need tuning for HS200? */ 2973069c9f14SGirish K S if (mmc->caps2 & MMC_CAP2_HS200) 2974069c9f14SGirish K S host->flags |= SDHCI_HS200_NEEDS_TUNING; 2975069c9f14SGirish K S 2976d6d50a15SArindam Nath /* Driver Type(s) (A, C, D) supported by the host */ 2977d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_A) 2978d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 2979d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_C) 2980d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 2981d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_D) 2982d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 2983d6d50a15SArindam Nath 2984cf2b5eeaSArindam Nath /* Initial value for re-tuning timer count */ 2985cf2b5eeaSArindam Nath host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 2986cf2b5eeaSArindam Nath SDHCI_RETUNING_TIMER_COUNT_SHIFT; 2987cf2b5eeaSArindam Nath 2988cf2b5eeaSArindam Nath /* 2989cf2b5eeaSArindam Nath * In case Re-tuning Timer is not disabled, the actual value of 2990cf2b5eeaSArindam Nath * re-tuning timer will be 2 ^ (n - 1). 2991cf2b5eeaSArindam Nath */ 2992cf2b5eeaSArindam Nath if (host->tuning_count) 2993cf2b5eeaSArindam Nath host->tuning_count = 1 << (host->tuning_count - 1); 2994cf2b5eeaSArindam Nath 2995cf2b5eeaSArindam Nath /* Re-tuning mode supported by the Host Controller */ 2996cf2b5eeaSArindam Nath host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 2997cf2b5eeaSArindam Nath SDHCI_RETUNING_MODE_SHIFT; 2998cf2b5eeaSArindam Nath 29998f230f45STakashi Iwai ocr_avail = 0; 3000bad37e1aSPhilip Rakity 3001bad37e1aSPhilip Rakity host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 3002657d5982SKevin Liu if (IS_ERR_OR_NULL(host->vmmc)) { 3003657d5982SKevin Liu if (PTR_ERR(host->vmmc) < 0) { 3004657d5982SKevin Liu pr_info("%s: no vmmc regulator found\n", 3005657d5982SKevin Liu mmc_hostname(mmc)); 3006bad37e1aSPhilip Rakity host->vmmc = NULL; 3007657d5982SKevin Liu } 30088363c374SKevin Liu } 3009bad37e1aSPhilip Rakity 301068737043SPhilip Rakity #ifdef CONFIG_REGULATOR 3011a4f8f257SMarek Szyprowski /* 3012a4f8f257SMarek Szyprowski * Voltage range check makes sense only if regulator reports 3013a4f8f257SMarek Szyprowski * any voltage value. 3014a4f8f257SMarek Szyprowski */ 3015a4f8f257SMarek Szyprowski if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { 3016cec2e216SKevin Liu ret = regulator_is_supported_voltage(host->vmmc, 2700000, 3017cec2e216SKevin Liu 3600000); 301868737043SPhilip Rakity if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 301968737043SPhilip Rakity caps[0] &= ~SDHCI_CAN_VDD_330; 302068737043SPhilip Rakity if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 302168737043SPhilip Rakity caps[0] &= ~SDHCI_CAN_VDD_300; 3022cec2e216SKevin Liu ret = regulator_is_supported_voltage(host->vmmc, 1700000, 3023cec2e216SKevin Liu 1950000); 302468737043SPhilip Rakity if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 302568737043SPhilip Rakity caps[0] &= ~SDHCI_CAN_VDD_180; 302668737043SPhilip Rakity } 302768737043SPhilip Rakity #endif /* CONFIG_REGULATOR */ 302868737043SPhilip Rakity 3029f2119df6SArindam Nath /* 3030f2119df6SArindam Nath * According to SD Host Controller spec v3.00, if the Host System 3031f2119df6SArindam Nath * can afford more than 150mA, Host Driver should set XPC to 1. Also 3032f2119df6SArindam Nath * the value is meaningful only if Voltage Support in the Capabilities 3033f2119df6SArindam Nath * register is set. The actual current value is 4 times the register 3034f2119df6SArindam Nath * value. 3035f2119df6SArindam Nath */ 3036f2119df6SArindam Nath max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3037bad37e1aSPhilip Rakity if (!max_current_caps && host->vmmc) { 3038bad37e1aSPhilip Rakity u32 curr = regulator_get_current_limit(host->vmmc); 3039bad37e1aSPhilip Rakity if (curr > 0) { 3040bad37e1aSPhilip Rakity 3041bad37e1aSPhilip Rakity /* convert to SDHCI_MAX_CURRENT format */ 3042bad37e1aSPhilip Rakity curr = curr/1000; /* convert to mA */ 3043bad37e1aSPhilip Rakity curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3044bad37e1aSPhilip Rakity 3045bad37e1aSPhilip Rakity curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3046bad37e1aSPhilip Rakity max_current_caps = 3047bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3048bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3049bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3050bad37e1aSPhilip Rakity } 3051bad37e1aSPhilip Rakity } 3052f2119df6SArindam Nath 3053f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_330) { 30548f230f45STakashi Iwai ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3055f2119df6SArindam Nath 305655c4665eSAaron Lu mmc->max_current_330 = ((max_current_caps & 3057f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_MASK) >> 3058f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_SHIFT) * 3059f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3060f2119df6SArindam Nath } 3061f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_300) { 30628f230f45STakashi Iwai ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3063f2119df6SArindam Nath 306455c4665eSAaron Lu mmc->max_current_300 = ((max_current_caps & 3065f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_MASK) >> 3066f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_SHIFT) * 3067f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3068f2119df6SArindam Nath } 3069f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_180) { 30708f230f45STakashi Iwai ocr_avail |= MMC_VDD_165_195; 30718f230f45STakashi Iwai 307255c4665eSAaron Lu mmc->max_current_180 = ((max_current_caps & 3073f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_MASK) >> 3074f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_SHIFT) * 3075f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3076f2119df6SArindam Nath } 3077f2119df6SArindam Nath 30788f230f45STakashi Iwai mmc->ocr_avail = ocr_avail; 30798f230f45STakashi Iwai mmc->ocr_avail_sdio = ocr_avail; 30808f230f45STakashi Iwai if (host->ocr_avail_sdio) 30818f230f45STakashi Iwai mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 30828f230f45STakashi Iwai mmc->ocr_avail_sd = ocr_avail; 30838f230f45STakashi Iwai if (host->ocr_avail_sd) 30848f230f45STakashi Iwai mmc->ocr_avail_sd &= host->ocr_avail_sd; 30858f230f45STakashi Iwai else /* normal SD controllers don't support 1.8V */ 30868f230f45STakashi Iwai mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 30878f230f45STakashi Iwai mmc->ocr_avail_mmc = ocr_avail; 30888f230f45STakashi Iwai if (host->ocr_avail_mmc) 30898f230f45STakashi Iwai mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 30901c6a0718SPierre Ossman 30911c6a0718SPierre Ossman if (mmc->ocr_avail == 0) { 3092a3c76eb9SGirish K S pr_err("%s: Hardware doesn't report any " 3093b69c9058SPierre Ossman "support voltages.\n", mmc_hostname(mmc)); 3094b8c86fc5SPierre Ossman return -ENODEV; 30951c6a0718SPierre Ossman } 30961c6a0718SPierre Ossman 30971c6a0718SPierre Ossman spin_lock_init(&host->lock); 30981c6a0718SPierre Ossman 30991c6a0718SPierre Ossman /* 31002134a922SPierre Ossman * Maximum number of segments. Depends on if the hardware 31012134a922SPierre Ossman * can do scatter/gather or not. 31021c6a0718SPierre Ossman */ 31032134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 3104a36274e0SMartin K. Petersen mmc->max_segs = 128; 3105a13abc7bSRichard Röjfors else if (host->flags & SDHCI_USE_SDMA) 3106a36274e0SMartin K. Petersen mmc->max_segs = 1; 31072134a922SPierre Ossman else /* PIO */ 3108a36274e0SMartin K. Petersen mmc->max_segs = 128; 31091c6a0718SPierre Ossman 31101c6a0718SPierre Ossman /* 31111c6a0718SPierre Ossman * Maximum number of sectors in one transfer. Limited by DMA boundary 31121c6a0718SPierre Ossman * size (512KiB). 31131c6a0718SPierre Ossman */ 31141c6a0718SPierre Ossman mmc->max_req_size = 524288; 31151c6a0718SPierre Ossman 31161c6a0718SPierre Ossman /* 31171c6a0718SPierre Ossman * Maximum segment size. Could be one segment with the maximum number 31182134a922SPierre Ossman * of bytes. When doing hardware scatter/gather, each entry cannot 31192134a922SPierre Ossman * be larger than 64 KiB though. 31201c6a0718SPierre Ossman */ 312130652aa3SOlof Johansson if (host->flags & SDHCI_USE_ADMA) { 312230652aa3SOlof Johansson if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 312330652aa3SOlof Johansson mmc->max_seg_size = 65535; 31242134a922SPierre Ossman else 312530652aa3SOlof Johansson mmc->max_seg_size = 65536; 312630652aa3SOlof Johansson } else { 31271c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 312830652aa3SOlof Johansson } 31291c6a0718SPierre Ossman 31301c6a0718SPierre Ossman /* 31311c6a0718SPierre Ossman * Maximum block size. This varies from controller to controller and 31321c6a0718SPierre Ossman * is specified in the capabilities register. 31331c6a0718SPierre Ossman */ 31340633f654SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 31350633f654SAnton Vorontsov mmc->max_blk_size = 2; 31360633f654SAnton Vorontsov } else { 3137f2119df6SArindam Nath mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 31380633f654SAnton Vorontsov SDHCI_MAX_BLOCK_SHIFT; 31391c6a0718SPierre Ossman if (mmc->max_blk_size >= 3) { 3140a3c76eb9SGirish K S pr_warning("%s: Invalid maximum block size, " 3141b69c9058SPierre Ossman "assuming 512 bytes\n", mmc_hostname(mmc)); 31420633f654SAnton Vorontsov mmc->max_blk_size = 0; 31430633f654SAnton Vorontsov } 31440633f654SAnton Vorontsov } 31450633f654SAnton Vorontsov 31461c6a0718SPierre Ossman mmc->max_blk_size = 512 << mmc->max_blk_size; 31471c6a0718SPierre Ossman 31481c6a0718SPierre Ossman /* 31491c6a0718SPierre Ossman * Maximum block count. 31501c6a0718SPierre Ossman */ 31511388eefdSBen Dooks mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 31521c6a0718SPierre Ossman 31531c6a0718SPierre Ossman /* 31541c6a0718SPierre Ossman * Init tasklets. 31551c6a0718SPierre Ossman */ 31561c6a0718SPierre Ossman tasklet_init(&host->card_tasklet, 31571c6a0718SPierre Ossman sdhci_tasklet_card, (unsigned long)host); 31581c6a0718SPierre Ossman tasklet_init(&host->finish_tasklet, 31591c6a0718SPierre Ossman sdhci_tasklet_finish, (unsigned long)host); 31601c6a0718SPierre Ossman 31611c6a0718SPierre Ossman setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 31621c6a0718SPierre Ossman 3163cf2b5eeaSArindam Nath if (host->version >= SDHCI_SPEC_300) { 3164b513ea25SArindam Nath init_waitqueue_head(&host->buf_ready_int); 3165b513ea25SArindam Nath 3166cf2b5eeaSArindam Nath /* Initialize re-tuning timer */ 3167cf2b5eeaSArindam Nath init_timer(&host->tuning_timer); 3168cf2b5eeaSArindam Nath host->tuning_timer.data = (unsigned long)host; 3169cf2b5eeaSArindam Nath host->tuning_timer.function = sdhci_tuning_timer; 3170cf2b5eeaSArindam Nath } 3171cf2b5eeaSArindam Nath 31721c6a0718SPierre Ossman ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 3173b69c9058SPierre Ossman mmc_hostname(mmc), host); 31740fc81ee3SMark Brown if (ret) { 31750fc81ee3SMark Brown pr_err("%s: Failed to request IRQ %d: %d\n", 31760fc81ee3SMark Brown mmc_hostname(mmc), host->irq, ret); 31771c6a0718SPierre Ossman goto untasklet; 31780fc81ee3SMark Brown } 31791c6a0718SPierre Ossman 31802f4cbb3dSNicolas Pitre sdhci_init(host, 0); 31811c6a0718SPierre Ossman 31821c6a0718SPierre Ossman #ifdef CONFIG_MMC_DEBUG 31831c6a0718SPierre Ossman sdhci_dumpregs(host); 31841c6a0718SPierre Ossman #endif 31851c6a0718SPierre Ossman 3186f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 31875dbace0cSHelmut Schaa snprintf(host->led_name, sizeof(host->led_name), 31885dbace0cSHelmut Schaa "%s::", mmc_hostname(mmc)); 31895dbace0cSHelmut Schaa host->led.name = host->led_name; 31902f730fecSPierre Ossman host->led.brightness = LED_OFF; 31912f730fecSPierre Ossman host->led.default_trigger = mmc_hostname(mmc); 31922f730fecSPierre Ossman host->led.brightness_set = sdhci_led_control; 31932f730fecSPierre Ossman 3194b8c86fc5SPierre Ossman ret = led_classdev_register(mmc_dev(mmc), &host->led); 31950fc81ee3SMark Brown if (ret) { 31960fc81ee3SMark Brown pr_err("%s: Failed to register LED device: %d\n", 31970fc81ee3SMark Brown mmc_hostname(mmc), ret); 31982f730fecSPierre Ossman goto reset; 31990fc81ee3SMark Brown } 32002f730fecSPierre Ossman #endif 32012f730fecSPierre Ossman 32021c6a0718SPierre Ossman mmiowb(); 32031c6a0718SPierre Ossman 32041c6a0718SPierre Ossman mmc_add_host(mmc); 32051c6a0718SPierre Ossman 3206a3c76eb9SGirish K S pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3207d1b26863SKay Sievers mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3208a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3209a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 32101c6a0718SPierre Ossman 32117260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 32127260cf5eSAnton Vorontsov 32131c6a0718SPierre Ossman return 0; 32141c6a0718SPierre Ossman 3215f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 32162f730fecSPierre Ossman reset: 32172f730fecSPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 3218b0a8deceSKevin Liu sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 32192f730fecSPierre Ossman free_irq(host->irq, host); 32202f730fecSPierre Ossman #endif 32211c6a0718SPierre Ossman untasklet: 32221c6a0718SPierre Ossman tasklet_kill(&host->card_tasklet); 32231c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 32241c6a0718SPierre Ossman 32251c6a0718SPierre Ossman return ret; 32261c6a0718SPierre Ossman } 32271c6a0718SPierre Ossman 3228b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_add_host); 3229b8c86fc5SPierre Ossman 32301e72859eSPierre Ossman void sdhci_remove_host(struct sdhci_host *host, int dead) 32311c6a0718SPierre Ossman { 32321e72859eSPierre Ossman unsigned long flags; 32331e72859eSPierre Ossman 32341e72859eSPierre Ossman if (dead) { 32351e72859eSPierre Ossman spin_lock_irqsave(&host->lock, flags); 32361e72859eSPierre Ossman 32371e72859eSPierre Ossman host->flags |= SDHCI_DEVICE_DEAD; 32381e72859eSPierre Ossman 32391e72859eSPierre Ossman if (host->mrq) { 3240a3c76eb9SGirish K S pr_err("%s: Controller removed during " 32411e72859eSPierre Ossman " transfer!\n", mmc_hostname(host->mmc)); 32421e72859eSPierre Ossman 32431e72859eSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 32441e72859eSPierre Ossman tasklet_schedule(&host->finish_tasklet); 32451e72859eSPierre Ossman } 32461e72859eSPierre Ossman 32471e72859eSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 32481e72859eSPierre Ossman } 32491e72859eSPierre Ossman 32507260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 32517260cf5eSAnton Vorontsov 3252b8c86fc5SPierre Ossman mmc_remove_host(host->mmc); 32531c6a0718SPierre Ossman 3254f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 32552f730fecSPierre Ossman led_classdev_unregister(&host->led); 32562f730fecSPierre Ossman #endif 32572f730fecSPierre Ossman 32581e72859eSPierre Ossman if (!dead) 32591c6a0718SPierre Ossman sdhci_reset(host, SDHCI_RESET_ALL); 32601c6a0718SPierre Ossman 3261b0a8deceSKevin Liu sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 32621c6a0718SPierre Ossman free_irq(host->irq, host); 32631c6a0718SPierre Ossman 32641c6a0718SPierre Ossman del_timer_sync(&host->timer); 32651c6a0718SPierre Ossman 32661c6a0718SPierre Ossman tasklet_kill(&host->card_tasklet); 32671c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 32682134a922SPierre Ossman 326977dcb3f4SPhilip Rakity if (host->vmmc) { 327077dcb3f4SPhilip Rakity regulator_disable(host->vmmc); 32719bea3c85SMarek Szyprowski regulator_put(host->vmmc); 327277dcb3f4SPhilip Rakity } 32739bea3c85SMarek Szyprowski 32746231f3deSPhilip Rakity if (host->vqmmc) { 32756231f3deSPhilip Rakity regulator_disable(host->vqmmc); 32766231f3deSPhilip Rakity regulator_put(host->vqmmc); 32776231f3deSPhilip Rakity } 32786231f3deSPhilip Rakity 32792134a922SPierre Ossman kfree(host->adma_desc); 32802134a922SPierre Ossman kfree(host->align_buffer); 32812134a922SPierre Ossman 32822134a922SPierre Ossman host->adma_desc = NULL; 32832134a922SPierre Ossman host->align_buffer = NULL; 32841c6a0718SPierre Ossman } 32851c6a0718SPierre Ossman 3286b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_remove_host); 3287b8c86fc5SPierre Ossman 3288b8c86fc5SPierre Ossman void sdhci_free_host(struct sdhci_host *host) 32891c6a0718SPierre Ossman { 3290b8c86fc5SPierre Ossman mmc_free_host(host->mmc); 32911c6a0718SPierre Ossman } 32921c6a0718SPierre Ossman 3293b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_free_host); 32941c6a0718SPierre Ossman 32951c6a0718SPierre Ossman /*****************************************************************************\ 32961c6a0718SPierre Ossman * * 32971c6a0718SPierre Ossman * Driver init/exit * 32981c6a0718SPierre Ossman * * 32991c6a0718SPierre Ossman \*****************************************************************************/ 33001c6a0718SPierre Ossman 33011c6a0718SPierre Ossman static int __init sdhci_drv_init(void) 33021c6a0718SPierre Ossman { 3303a3c76eb9SGirish K S pr_info(DRIVER_NAME 33041c6a0718SPierre Ossman ": Secure Digital Host Controller Interface driver\n"); 3305a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 33061c6a0718SPierre Ossman 3307b8c86fc5SPierre Ossman return 0; 33081c6a0718SPierre Ossman } 33091c6a0718SPierre Ossman 33101c6a0718SPierre Ossman static void __exit sdhci_drv_exit(void) 33111c6a0718SPierre Ossman { 33121c6a0718SPierre Ossman } 33131c6a0718SPierre Ossman 33141c6a0718SPierre Ossman module_init(sdhci_drv_init); 33151c6a0718SPierre Ossman module_exit(sdhci_drv_exit); 33161c6a0718SPierre Ossman 33171c6a0718SPierre Ossman module_param(debug_quirks, uint, 0444); 331866fd8ad5SAdrian Hunter module_param(debug_quirks2, uint, 0444); 33191c6a0718SPierre Ossman 332032710e8fSPierre Ossman MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3321b8c86fc5SPierre Ossman MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 33221c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 33231c6a0718SPierre Ossman 33241c6a0718SPierre Ossman MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 332566fd8ad5SAdrian Hunter MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3326