11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 4b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 81c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 91c6a0718SPierre Ossman * your option) any later version. 1084c46a53SPierre Ossman * 1184c46a53SPierre Ossman * Thanks to the following companies for their support: 1284c46a53SPierre Ossman * 1384c46a53SPierre Ossman * - JMicron (hardware and technical support) 141c6a0718SPierre Ossman */ 151c6a0718SPierre Ossman 161c6a0718SPierre Ossman #include <linux/delay.h> 171c6a0718SPierre Ossman #include <linux/highmem.h> 18b8c86fc5SPierre Ossman #include <linux/io.h> 1988b47679SPaul Gortmaker #include <linux/module.h> 201c6a0718SPierre Ossman #include <linux/dma-mapping.h> 215a0e3ad6STejun Heo #include <linux/slab.h> 2211763609SRalf Baechle #include <linux/scatterlist.h> 239bea3c85SMarek Szyprowski #include <linux/regulator/consumer.h> 2466fd8ad5SAdrian Hunter #include <linux/pm_runtime.h> 251c6a0718SPierre Ossman 262f730fecSPierre Ossman #include <linux/leds.h> 272f730fecSPierre Ossman 2822113efdSAries Lee #include <linux/mmc/mmc.h> 291c6a0718SPierre Ossman #include <linux/mmc/host.h> 30473b095aSAaron Lu #include <linux/mmc/card.h> 3185cc1c33SCorneliu Doban #include <linux/mmc/sdio.h> 32bec9d4e5SGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #include "sdhci.h" 351c6a0718SPierre Ossman 361c6a0718SPierre Ossman #define DRIVER_NAME "sdhci" 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman #define DBG(f, x...) \ 391c6a0718SPierre Ossman pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 401c6a0718SPierre Ossman 41f9134319SPierre Ossman #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 42f9134319SPierre Ossman defined(CONFIG_MMC_SDHCI_MODULE)) 43f9134319SPierre Ossman #define SDHCI_USE_LEDS_CLASS 44f9134319SPierre Ossman #endif 45f9134319SPierre Ossman 46b513ea25SArindam Nath #define MAX_TUNING_LOOP 40 47b513ea25SArindam Nath 481c6a0718SPierre Ossman static unsigned int debug_quirks = 0; 4966fd8ad5SAdrian Hunter static unsigned int debug_quirks2; 501c6a0718SPierre Ossman 511c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *); 521c6a0718SPierre Ossman 531c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *); 54069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 5552983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 5604e079cfSScott Branden static int sdhci_do_get_cd(struct sdhci_host *host); 571c6a0718SPierre Ossman 58162d6f98SRafael J. Wysocki #ifdef CONFIG_PM 5966fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host); 6066fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host); 61f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 62f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 6366fd8ad5SAdrian Hunter #else 6466fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 6566fd8ad5SAdrian Hunter { 6666fd8ad5SAdrian Hunter return 0; 6766fd8ad5SAdrian Hunter } 6866fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 6966fd8ad5SAdrian Hunter { 7066fd8ad5SAdrian Hunter return 0; 7166fd8ad5SAdrian Hunter } 72f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 73f0710a55SAdrian Hunter { 74f0710a55SAdrian Hunter } 75f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 76f0710a55SAdrian Hunter { 77f0710a55SAdrian Hunter } 7866fd8ad5SAdrian Hunter #endif 7966fd8ad5SAdrian Hunter 801c6a0718SPierre Ossman static void sdhci_dumpregs(struct sdhci_host *host) 811c6a0718SPierre Ossman { 82a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 83412ab659SPhilip Rakity mmc_hostname(host->mmc)); 841c6a0718SPierre Ossman 85a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 864e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_DMA_ADDRESS), 874e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_HOST_VERSION)); 88a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 894e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_SIZE), 904e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_COUNT)); 91a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 924e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_ARGUMENT), 934e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_TRANSFER_MODE)); 94a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 954e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_PRESENT_STATE), 964e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_HOST_CONTROL)); 97a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 984e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_POWER_CONTROL), 994e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 100a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 1014e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 1024e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 103a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 1044e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 1054e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_STATUS)); 106a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 1074e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_ENABLE), 1084e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 109a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 1104e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_ACMD12_ERR), 1114e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 112a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 1134e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_CAPABILITIES), 114e8120ad1SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1)); 115a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 116e8120ad1SPhilip Rakity sdhci_readw(host, SDHCI_COMMAND), 1174e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_MAX_CURRENT)); 118a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 119f2119df6SArindam Nath sdhci_readw(host, SDHCI_HOST_CONTROL2)); 1201c6a0718SPierre Ossman 121e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_ADMA) { 122e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 123e57a5f61SAdrian Hunter pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 124e57a5f61SAdrian Hunter readl(host->ioaddr + SDHCI_ADMA_ERROR), 125e57a5f61SAdrian Hunter readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 126e57a5f61SAdrian Hunter readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 127e57a5f61SAdrian Hunter else 128a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 129be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ERROR), 130be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 131e57a5f61SAdrian Hunter } 132be3f4ae0SBen Dooks 133a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ===========================================\n"); 1341c6a0718SPierre Ossman } 1351c6a0718SPierre Ossman 1361c6a0718SPierre Ossman /*****************************************************************************\ 1371c6a0718SPierre Ossman * * 1381c6a0718SPierre Ossman * Low level functions * 1391c6a0718SPierre Ossman * * 1401c6a0718SPierre Ossman \*****************************************************************************/ 1411c6a0718SPierre Ossman 1427260cf5eSAnton Vorontsov static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 1437260cf5eSAnton Vorontsov { 1445b4f1f6cSRussell King u32 present; 1457260cf5eSAnton Vorontsov 146c79396c1SAdrian Hunter if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 14787b87a3fSDaniel Drake (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 14866fd8ad5SAdrian Hunter return; 14966fd8ad5SAdrian Hunter 1505b4f1f6cSRussell King if (enable) { 151d25928d1SShawn Guo present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 152d25928d1SShawn Guo SDHCI_CARD_PRESENT; 153d25928d1SShawn Guo 1545b4f1f6cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 1555b4f1f6cSRussell King SDHCI_INT_CARD_INSERT; 1565b4f1f6cSRussell King } else { 1575b4f1f6cSRussell King host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 1585b4f1f6cSRussell King } 159b537f94cSRussell King 160b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 161b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1627260cf5eSAnton Vorontsov } 1637260cf5eSAnton Vorontsov 1647260cf5eSAnton Vorontsov static void sdhci_enable_card_detection(struct sdhci_host *host) 1657260cf5eSAnton Vorontsov { 1667260cf5eSAnton Vorontsov sdhci_set_card_detection(host, true); 1677260cf5eSAnton Vorontsov } 1687260cf5eSAnton Vorontsov 1697260cf5eSAnton Vorontsov static void sdhci_disable_card_detection(struct sdhci_host *host) 1707260cf5eSAnton Vorontsov { 1717260cf5eSAnton Vorontsov sdhci_set_card_detection(host, false); 1727260cf5eSAnton Vorontsov } 1737260cf5eSAnton Vorontsov 17403231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask) 1751c6a0718SPierre Ossman { 1761c6a0718SPierre Ossman unsigned long timeout; 177393c1a34SPhilip Rakity 1784e4141a5SAnton Vorontsov sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1791c6a0718SPierre Ossman 180f0710a55SAdrian Hunter if (mask & SDHCI_RESET_ALL) { 1811c6a0718SPierre Ossman host->clock = 0; 182f0710a55SAdrian Hunter /* Reset-all turns off SD Bus Power */ 183f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 184f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 185f0710a55SAdrian Hunter } 1861c6a0718SPierre Ossman 1871c6a0718SPierre Ossman /* Wait max 100 ms */ 1881c6a0718SPierre Ossman timeout = 100; 1891c6a0718SPierre Ossman 1901c6a0718SPierre Ossman /* hw clears the bit when it's done */ 1914e4141a5SAnton Vorontsov while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 1921c6a0718SPierre Ossman if (timeout == 0) { 193a3c76eb9SGirish K S pr_err("%s: Reset 0x%x never completed.\n", 1941c6a0718SPierre Ossman mmc_hostname(host->mmc), (int)mask); 1951c6a0718SPierre Ossman sdhci_dumpregs(host); 1961c6a0718SPierre Ossman return; 1971c6a0718SPierre Ossman } 1981c6a0718SPierre Ossman timeout--; 1991c6a0718SPierre Ossman mdelay(1); 2001c6a0718SPierre Ossman } 20103231f9bSRussell King } 20203231f9bSRussell King EXPORT_SYMBOL_GPL(sdhci_reset); 203063a9dbbSAnton Vorontsov 20403231f9bSRussell King static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 20503231f9bSRussell King { 20603231f9bSRussell King if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 207135b0a28SIvan T. Ivanov if (!sdhci_do_get_cd(host)) 20803231f9bSRussell King return; 20903231f9bSRussell King } 21003231f9bSRussell King 21103231f9bSRussell King host->ops->reset(host, mask); 212393c1a34SPhilip Rakity 213da91a8f9SRussell King if (mask & SDHCI_RESET_ALL) { 2143abc1e80SShaohui Xie if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 215da91a8f9SRussell King if (host->ops->enable_dma) 2163abc1e80SShaohui Xie host->ops->enable_dma(host); 2173abc1e80SShaohui Xie } 218da91a8f9SRussell King 219da91a8f9SRussell King /* Resetting the controller clears many */ 220da91a8f9SRussell King host->preset_enabled = false; 221da91a8f9SRussell King } 2221c6a0718SPierre Ossman } 2231c6a0718SPierre Ossman 2242f4cbb3dSNicolas Pitre static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 2252f4cbb3dSNicolas Pitre 2262f4cbb3dSNicolas Pitre static void sdhci_init(struct sdhci_host *host, int soft) 2271c6a0718SPierre Ossman { 2282f4cbb3dSNicolas Pitre if (soft) 22903231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 2302f4cbb3dSNicolas Pitre else 23103231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 2321c6a0718SPierre Ossman 233b537f94cSRussell King host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 234b537f94cSRussell King SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 235b537f94cSRussell King SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 236b537f94cSRussell King SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 237b537f94cSRussell King SDHCI_INT_RESPONSE; 238b537f94cSRussell King 239b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 240b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2412f4cbb3dSNicolas Pitre 2422f4cbb3dSNicolas Pitre if (soft) { 2432f4cbb3dSNicolas Pitre /* force clock reconfiguration */ 2442f4cbb3dSNicolas Pitre host->clock = 0; 2452f4cbb3dSNicolas Pitre sdhci_set_ios(host->mmc, &host->mmc->ios); 2462f4cbb3dSNicolas Pitre } 2477260cf5eSAnton Vorontsov } 2481c6a0718SPierre Ossman 2497260cf5eSAnton Vorontsov static void sdhci_reinit(struct sdhci_host *host) 2507260cf5eSAnton Vorontsov { 2512f4cbb3dSNicolas Pitre sdhci_init(host, 0); 2527260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 2531c6a0718SPierre Ossman } 2541c6a0718SPierre Ossman 2551c6a0718SPierre Ossman static void sdhci_activate_led(struct sdhci_host *host) 2561c6a0718SPierre Ossman { 2571c6a0718SPierre Ossman u8 ctrl; 2581c6a0718SPierre Ossman 2594e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2601c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_LED; 2614e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2621c6a0718SPierre Ossman } 2631c6a0718SPierre Ossman 2641c6a0718SPierre Ossman static void sdhci_deactivate_led(struct sdhci_host *host) 2651c6a0718SPierre Ossman { 2661c6a0718SPierre Ossman u8 ctrl; 2671c6a0718SPierre Ossman 2684e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2691c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_LED; 2704e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2711c6a0718SPierre Ossman } 2721c6a0718SPierre Ossman 273f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 2742f730fecSPierre Ossman static void sdhci_led_control(struct led_classdev *led, 2752f730fecSPierre Ossman enum led_brightness brightness) 2762f730fecSPierre Ossman { 2772f730fecSPierre Ossman struct sdhci_host *host = container_of(led, struct sdhci_host, led); 2782f730fecSPierre Ossman unsigned long flags; 2792f730fecSPierre Ossman 2802f730fecSPierre Ossman spin_lock_irqsave(&host->lock, flags); 2812f730fecSPierre Ossman 28266fd8ad5SAdrian Hunter if (host->runtime_suspended) 28366fd8ad5SAdrian Hunter goto out; 28466fd8ad5SAdrian Hunter 2852f730fecSPierre Ossman if (brightness == LED_OFF) 2862f730fecSPierre Ossman sdhci_deactivate_led(host); 2872f730fecSPierre Ossman else 2882f730fecSPierre Ossman sdhci_activate_led(host); 28966fd8ad5SAdrian Hunter out: 2902f730fecSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 2912f730fecSPierre Ossman } 2922f730fecSPierre Ossman #endif 2932f730fecSPierre Ossman 2941c6a0718SPierre Ossman /*****************************************************************************\ 2951c6a0718SPierre Ossman * * 2961c6a0718SPierre Ossman * Core functions * 2971c6a0718SPierre Ossman * * 2981c6a0718SPierre Ossman \*****************************************************************************/ 2991c6a0718SPierre Ossman 3001c6a0718SPierre Ossman static void sdhci_read_block_pio(struct sdhci_host *host) 3011c6a0718SPierre Ossman { 3027659150cSPierre Ossman unsigned long flags; 3037659150cSPierre Ossman size_t blksize, len, chunk; 3047244b85bSSteven Noonan u32 uninitialized_var(scratch); 3057659150cSPierre Ossman u8 *buf; 3061c6a0718SPierre Ossman 3071c6a0718SPierre Ossman DBG("PIO reading\n"); 3081c6a0718SPierre Ossman 3091c6a0718SPierre Ossman blksize = host->data->blksz; 3107659150cSPierre Ossman chunk = 0; 3111c6a0718SPierre Ossman 3127659150cSPierre Ossman local_irq_save(flags); 3131c6a0718SPierre Ossman 3141c6a0718SPierre Ossman while (blksize) { 315bf3a35acSFabio Estevam BUG_ON(!sg_miter_next(&host->sg_miter)); 3167659150cSPierre Ossman 3177659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3187659150cSPierre Ossman 3197659150cSPierre Ossman blksize -= len; 3207659150cSPierre Ossman host->sg_miter.consumed = len; 3217659150cSPierre Ossman 3227659150cSPierre Ossman buf = host->sg_miter.addr; 3237659150cSPierre Ossman 3247659150cSPierre Ossman while (len) { 3257659150cSPierre Ossman if (chunk == 0) { 3264e4141a5SAnton Vorontsov scratch = sdhci_readl(host, SDHCI_BUFFER); 3277659150cSPierre Ossman chunk = 4; 3281c6a0718SPierre Ossman } 3291c6a0718SPierre Ossman 3307659150cSPierre Ossman *buf = scratch & 0xFF; 3311c6a0718SPierre Ossman 3327659150cSPierre Ossman buf++; 3337659150cSPierre Ossman scratch >>= 8; 3347659150cSPierre Ossman chunk--; 3357659150cSPierre Ossman len--; 3367659150cSPierre Ossman } 3371c6a0718SPierre Ossman } 3381c6a0718SPierre Ossman 3397659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3407659150cSPierre Ossman 3417659150cSPierre Ossman local_irq_restore(flags); 3421c6a0718SPierre Ossman } 3431c6a0718SPierre Ossman 3441c6a0718SPierre Ossman static void sdhci_write_block_pio(struct sdhci_host *host) 3451c6a0718SPierre Ossman { 3467659150cSPierre Ossman unsigned long flags; 3477659150cSPierre Ossman size_t blksize, len, chunk; 3487659150cSPierre Ossman u32 scratch; 3497659150cSPierre Ossman u8 *buf; 3501c6a0718SPierre Ossman 3511c6a0718SPierre Ossman DBG("PIO writing\n"); 3521c6a0718SPierre Ossman 3531c6a0718SPierre Ossman blksize = host->data->blksz; 3547659150cSPierre Ossman chunk = 0; 3557659150cSPierre Ossman scratch = 0; 3561c6a0718SPierre Ossman 3577659150cSPierre Ossman local_irq_save(flags); 3581c6a0718SPierre Ossman 3591c6a0718SPierre Ossman while (blksize) { 360bf3a35acSFabio Estevam BUG_ON(!sg_miter_next(&host->sg_miter)); 3611c6a0718SPierre Ossman 3627659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3631c6a0718SPierre Ossman 3647659150cSPierre Ossman blksize -= len; 3657659150cSPierre Ossman host->sg_miter.consumed = len; 3667659150cSPierre Ossman 3677659150cSPierre Ossman buf = host->sg_miter.addr; 3687659150cSPierre Ossman 3697659150cSPierre Ossman while (len) { 3707659150cSPierre Ossman scratch |= (u32)*buf << (chunk * 8); 3717659150cSPierre Ossman 3727659150cSPierre Ossman buf++; 3737659150cSPierre Ossman chunk++; 3747659150cSPierre Ossman len--; 3757659150cSPierre Ossman 3767659150cSPierre Ossman if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 3774e4141a5SAnton Vorontsov sdhci_writel(host, scratch, SDHCI_BUFFER); 3787659150cSPierre Ossman chunk = 0; 3797659150cSPierre Ossman scratch = 0; 3807659150cSPierre Ossman } 3817659150cSPierre Ossman } 3821c6a0718SPierre Ossman } 3831c6a0718SPierre Ossman 3847659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3851c6a0718SPierre Ossman 3867659150cSPierre Ossman local_irq_restore(flags); 3871c6a0718SPierre Ossman } 3881c6a0718SPierre Ossman 3891c6a0718SPierre Ossman static void sdhci_transfer_pio(struct sdhci_host *host) 3901c6a0718SPierre Ossman { 3911c6a0718SPierre Ossman u32 mask; 3921c6a0718SPierre Ossman 3931c6a0718SPierre Ossman BUG_ON(!host->data); 3941c6a0718SPierre Ossman 3957659150cSPierre Ossman if (host->blocks == 0) 3961c6a0718SPierre Ossman return; 3971c6a0718SPierre Ossman 3981c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 3991c6a0718SPierre Ossman mask = SDHCI_DATA_AVAILABLE; 4001c6a0718SPierre Ossman else 4011c6a0718SPierre Ossman mask = SDHCI_SPACE_AVAILABLE; 4021c6a0718SPierre Ossman 4034a3cba32SPierre Ossman /* 4044a3cba32SPierre Ossman * Some controllers (JMicron JMB38x) mess up the buffer bits 4054a3cba32SPierre Ossman * for transfers < 4 bytes. As long as it is just one block, 4064a3cba32SPierre Ossman * we can ignore the bits. 4074a3cba32SPierre Ossman */ 4084a3cba32SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 4094a3cba32SPierre Ossman (host->data->blocks == 1)) 4104a3cba32SPierre Ossman mask = ~0; 4114a3cba32SPierre Ossman 4124e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 4133e3bf207SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 4143e3bf207SAnton Vorontsov udelay(100); 4153e3bf207SAnton Vorontsov 4161c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4171c6a0718SPierre Ossman sdhci_read_block_pio(host); 4181c6a0718SPierre Ossman else 4191c6a0718SPierre Ossman sdhci_write_block_pio(host); 4201c6a0718SPierre Ossman 4217659150cSPierre Ossman host->blocks--; 4227659150cSPierre Ossman if (host->blocks == 0) 4231c6a0718SPierre Ossman break; 4241c6a0718SPierre Ossman } 4251c6a0718SPierre Ossman 4261c6a0718SPierre Ossman DBG("PIO transfer complete.\n"); 4271c6a0718SPierre Ossman } 4281c6a0718SPierre Ossman 42948857d9bSRussell King static int sdhci_pre_dma_transfer(struct sdhci_host *host, 43048857d9bSRussell King struct mmc_data *data) 43148857d9bSRussell King { 43248857d9bSRussell King int sg_count; 43348857d9bSRussell King 43448857d9bSRussell King if (data->host_cookie == COOKIE_MAPPED) { 43548857d9bSRussell King data->host_cookie = COOKIE_GIVEN; 43648857d9bSRussell King return data->sg_count; 43748857d9bSRussell King } 43848857d9bSRussell King 43948857d9bSRussell King WARN_ON(data->host_cookie == COOKIE_GIVEN); 44048857d9bSRussell King 44148857d9bSRussell King sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 44248857d9bSRussell King data->flags & MMC_DATA_WRITE ? 44348857d9bSRussell King DMA_TO_DEVICE : DMA_FROM_DEVICE); 44448857d9bSRussell King 44548857d9bSRussell King if (sg_count == 0) 44648857d9bSRussell King return -ENOSPC; 44748857d9bSRussell King 44848857d9bSRussell King data->sg_count = sg_count; 44948857d9bSRussell King data->host_cookie = COOKIE_MAPPED; 45048857d9bSRussell King 45148857d9bSRussell King return sg_count; 45248857d9bSRussell King } 45348857d9bSRussell King 4542134a922SPierre Ossman static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 4552134a922SPierre Ossman { 4562134a922SPierre Ossman local_irq_save(*flags); 457482fce99SCong Wang return kmap_atomic(sg_page(sg)) + sg->offset; 4582134a922SPierre Ossman } 4592134a922SPierre Ossman 4602134a922SPierre Ossman static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 4612134a922SPierre Ossman { 462482fce99SCong Wang kunmap_atomic(buffer); 4632134a922SPierre Ossman local_irq_restore(*flags); 4642134a922SPierre Ossman } 4652134a922SPierre Ossman 466e57a5f61SAdrian Hunter static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 467e57a5f61SAdrian Hunter dma_addr_t addr, int len, unsigned cmd) 468118cd17dSBen Dooks { 469e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 470118cd17dSBen Dooks 471e57a5f61SAdrian Hunter /* 32-bit and 64-bit descriptors have these members in same position */ 4720545230fSAdrian Hunter dma_desc->cmd = cpu_to_le16(cmd); 4730545230fSAdrian Hunter dma_desc->len = cpu_to_le16(len); 474e57a5f61SAdrian Hunter dma_desc->addr_lo = cpu_to_le32((u32)addr); 475e57a5f61SAdrian Hunter 476e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 477e57a5f61SAdrian Hunter dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 478118cd17dSBen Dooks } 479118cd17dSBen Dooks 480b5ffa674SAdrian Hunter static void sdhci_adma_mark_end(void *desc) 481b5ffa674SAdrian Hunter { 482e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 483b5ffa674SAdrian Hunter 484e57a5f61SAdrian Hunter /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 4850545230fSAdrian Hunter dma_desc->cmd |= cpu_to_le16(ADMA2_END); 486b5ffa674SAdrian Hunter } 487b5ffa674SAdrian Hunter 4888f1934ceSPierre Ossman static int sdhci_adma_table_pre(struct sdhci_host *host, 4892134a922SPierre Ossman struct mmc_data *data) 4902134a922SPierre Ossman { 4912134a922SPierre Ossman struct scatterlist *sg; 4922134a922SPierre Ossman unsigned long flags; 493acc3ad13SRussell King dma_addr_t addr, align_addr; 494acc3ad13SRussell King void *desc, *align; 495acc3ad13SRussell King char *buffer; 496acc3ad13SRussell King int len, offset, i; 4972134a922SPierre Ossman 4982134a922SPierre Ossman /* 4992134a922SPierre Ossman * The spec does not specify endianness of descriptor table. 5002134a922SPierre Ossman * We currently guess that it is LE. 5012134a922SPierre Ossman */ 5022134a922SPierre Ossman 503d31911b9SHaibo Chen host->sg_count = sdhci_pre_dma_transfer(host, data); 504348487cbSHaibo Chen if (host->sg_count < 0) 505edd63fccSRussell King return -EINVAL; 5062134a922SPierre Ossman 5074efaa6fbSAdrian Hunter desc = host->adma_table; 5082134a922SPierre Ossman align = host->align_buffer; 5092134a922SPierre Ossman 5102134a922SPierre Ossman align_addr = host->align_addr; 5112134a922SPierre Ossman 5122134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 5132134a922SPierre Ossman addr = sg_dma_address(sg); 5142134a922SPierre Ossman len = sg_dma_len(sg); 5152134a922SPierre Ossman 5162134a922SPierre Ossman /* 517acc3ad13SRussell King * The SDHCI specification states that ADMA addresses must 518acc3ad13SRussell King * be 32-bit aligned. If they aren't, then we use a bounce 519acc3ad13SRussell King * buffer for the (up to three) bytes that screw up the 5202134a922SPierre Ossman * alignment. 5212134a922SPierre Ossman */ 52204a5ae6fSAdrian Hunter offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 52304a5ae6fSAdrian Hunter SDHCI_ADMA2_MASK; 5242134a922SPierre Ossman if (offset) { 5252134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5262134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 5272134a922SPierre Ossman memcpy(align, buffer, offset); 5282134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 5292134a922SPierre Ossman } 5302134a922SPierre Ossman 531118cd17dSBen Dooks /* tran, valid */ 532e57a5f61SAdrian Hunter sdhci_adma_write_desc(host, desc, align_addr, offset, 533739d46dcSAdrian Hunter ADMA2_TRAN_VALID); 5342134a922SPierre Ossman 5352134a922SPierre Ossman BUG_ON(offset > 65536); 5362134a922SPierre Ossman 53704a5ae6fSAdrian Hunter align += SDHCI_ADMA2_ALIGN; 53804a5ae6fSAdrian Hunter align_addr += SDHCI_ADMA2_ALIGN; 5392134a922SPierre Ossman 54076fe379aSAdrian Hunter desc += host->desc_sz; 5412134a922SPierre Ossman 5422134a922SPierre Ossman addr += offset; 5432134a922SPierre Ossman len -= offset; 5442134a922SPierre Ossman } 5452134a922SPierre Ossman 5462134a922SPierre Ossman BUG_ON(len > 65536); 5472134a922SPierre Ossman 548347ea32dSAdrian Hunter if (len) { 549118cd17dSBen Dooks /* tran, valid */ 550347ea32dSAdrian Hunter sdhci_adma_write_desc(host, desc, addr, len, 551347ea32dSAdrian Hunter ADMA2_TRAN_VALID); 55276fe379aSAdrian Hunter desc += host->desc_sz; 553347ea32dSAdrian Hunter } 5542134a922SPierre Ossman 5552134a922SPierre Ossman /* 5562134a922SPierre Ossman * If this triggers then we have a calculation bug 5572134a922SPierre Ossman * somewhere. :/ 5582134a922SPierre Ossman */ 55976fe379aSAdrian Hunter WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 5602134a922SPierre Ossman } 5612134a922SPierre Ossman 56270764a90SThomas Abraham if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 563acc3ad13SRussell King /* Mark the last descriptor as the terminating descriptor */ 5644efaa6fbSAdrian Hunter if (desc != host->adma_table) { 56576fe379aSAdrian Hunter desc -= host->desc_sz; 566b5ffa674SAdrian Hunter sdhci_adma_mark_end(desc); 56770764a90SThomas Abraham } 56870764a90SThomas Abraham } else { 569acc3ad13SRussell King /* Add a terminating entry - nop, end, valid */ 570e57a5f61SAdrian Hunter sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 57170764a90SThomas Abraham } 5728f1934ceSPierre Ossman return 0; 5732134a922SPierre Ossman } 5742134a922SPierre Ossman 5752134a922SPierre Ossman static void sdhci_adma_table_post(struct sdhci_host *host, 5762134a922SPierre Ossman struct mmc_data *data) 5772134a922SPierre Ossman { 5782134a922SPierre Ossman struct scatterlist *sg; 5792134a922SPierre Ossman int i, size; 5801c3d5f6dSAdrian Hunter void *align; 5812134a922SPierre Ossman char *buffer; 5822134a922SPierre Ossman unsigned long flags; 5832134a922SPierre Ossman 58447fa9613SRussell King if (data->flags & MMC_DATA_READ) { 58547fa9613SRussell King bool has_unaligned = false; 58647fa9613SRussell King 587de0b65a7SRussell King /* Do a quick scan of the SG list for any unaligned mappings */ 588de0b65a7SRussell King for_each_sg(data->sg, sg, host->sg_count, i) 58904a5ae6fSAdrian Hunter if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 590de0b65a7SRussell King has_unaligned = true; 591de0b65a7SRussell King break; 592de0b65a7SRussell King } 593de0b65a7SRussell King 59447fa9613SRussell King if (has_unaligned) { 5952134a922SPierre Ossman dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 596f55c98f7SRussell King data->sg_len, DMA_FROM_DEVICE); 5972134a922SPierre Ossman 5982134a922SPierre Ossman align = host->align_buffer; 5992134a922SPierre Ossman 6002134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 60104a5ae6fSAdrian Hunter if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 60204a5ae6fSAdrian Hunter size = SDHCI_ADMA2_ALIGN - 60304a5ae6fSAdrian Hunter (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 6042134a922SPierre Ossman 6052134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 6062134a922SPierre Ossman memcpy(buffer, align, size); 6072134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 6082134a922SPierre Ossman 60904a5ae6fSAdrian Hunter align += SDHCI_ADMA2_ALIGN; 6102134a922SPierre Ossman } 6112134a922SPierre Ossman } 6122134a922SPierre Ossman } 61347fa9613SRussell King } 6142134a922SPierre Ossman } 6152134a922SPierre Ossman 616a3c7778fSAndrei Warkentin static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 6171c6a0718SPierre Ossman { 6181c6a0718SPierre Ossman u8 count; 619a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 6201c6a0718SPierre Ossman unsigned target_timeout, current_timeout; 6211c6a0718SPierre Ossman 622ee53ab5dSPierre Ossman /* 623ee53ab5dSPierre Ossman * If the host controller provides us with an incorrect timeout 624ee53ab5dSPierre Ossman * value, just skip the check and use 0xE. The hardware may take 625ee53ab5dSPierre Ossman * longer to time out, but that's much better than having a too-short 626ee53ab5dSPierre Ossman * timeout value. 627ee53ab5dSPierre Ossman */ 62811a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 629ee53ab5dSPierre Ossman return 0xE; 630e538fbe8SPierre Ossman 631a3c7778fSAndrei Warkentin /* Unspecified timeout, assume max */ 6321d4d7744SUlf Hansson if (!data && !cmd->busy_timeout) 633a3c7778fSAndrei Warkentin return 0xE; 634a3c7778fSAndrei Warkentin 6351c6a0718SPierre Ossman /* timeout in us */ 636a3c7778fSAndrei Warkentin if (!data) 6371d4d7744SUlf Hansson target_timeout = cmd->busy_timeout * 1000; 63878a2ca27SAndy Shevchenko else { 639fafcfda9SRussell King target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 6407f05538aSRussell King if (host->clock && data->timeout_clks) { 6417f05538aSRussell King unsigned long long val; 6427f05538aSRussell King 6437f05538aSRussell King /* 6447f05538aSRussell King * data->timeout_clks is in units of clock cycles. 6457f05538aSRussell King * host->clock is in Hz. target_timeout is in us. 6467f05538aSRussell King * Hence, us = 1000000 * cycles / Hz. Round up. 6477f05538aSRussell King */ 6487f05538aSRussell King val = 1000000 * data->timeout_clks; 6497f05538aSRussell King if (do_div(val, host->clock)) 6507f05538aSRussell King target_timeout++; 6517f05538aSRussell King target_timeout += val; 6527f05538aSRussell King } 65378a2ca27SAndy Shevchenko } 6541c6a0718SPierre Ossman 6551c6a0718SPierre Ossman /* 6561c6a0718SPierre Ossman * Figure out needed cycles. 6571c6a0718SPierre Ossman * We do this in steps in order to fit inside a 32 bit int. 6581c6a0718SPierre Ossman * The first step is the minimum timeout, which will have a 6591c6a0718SPierre Ossman * minimum resolution of 6 bits: 6601c6a0718SPierre Ossman * (1) 2^13*1000 > 2^22, 6611c6a0718SPierre Ossman * (2) host->timeout_clk < 2^16 6621c6a0718SPierre Ossman * => 6631c6a0718SPierre Ossman * (1) / (2) > 2^6 6641c6a0718SPierre Ossman */ 6651c6a0718SPierre Ossman count = 0; 6661c6a0718SPierre Ossman current_timeout = (1 << 13) * 1000 / host->timeout_clk; 6671c6a0718SPierre Ossman while (current_timeout < target_timeout) { 6681c6a0718SPierre Ossman count++; 6691c6a0718SPierre Ossman current_timeout <<= 1; 6701c6a0718SPierre Ossman if (count >= 0xF) 6711c6a0718SPierre Ossman break; 6721c6a0718SPierre Ossman } 6731c6a0718SPierre Ossman 6741c6a0718SPierre Ossman if (count >= 0xF) { 67509eeff52SChris Ball DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 67602145977SMark Brown mmc_hostname(host->mmc), count, cmd->opcode); 6771c6a0718SPierre Ossman count = 0xE; 6781c6a0718SPierre Ossman } 6791c6a0718SPierre Ossman 680ee53ab5dSPierre Ossman return count; 681ee53ab5dSPierre Ossman } 682ee53ab5dSPierre Ossman 6836aa943abSAnton Vorontsov static void sdhci_set_transfer_irqs(struct sdhci_host *host) 6846aa943abSAnton Vorontsov { 6856aa943abSAnton Vorontsov u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 6866aa943abSAnton Vorontsov u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 6876aa943abSAnton Vorontsov 6886aa943abSAnton Vorontsov if (host->flags & SDHCI_REQ_USE_DMA) 689b537f94cSRussell King host->ier = (host->ier & ~pio_irqs) | dma_irqs; 6906aa943abSAnton Vorontsov else 691b537f94cSRussell King host->ier = (host->ier & ~dma_irqs) | pio_irqs; 692b537f94cSRussell King 693b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 694b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 6956aa943abSAnton Vorontsov } 6966aa943abSAnton Vorontsov 697b45e668aSAisheng Dong static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 698ee53ab5dSPierre Ossman { 699ee53ab5dSPierre Ossman u8 count; 700b45e668aSAisheng Dong 701b45e668aSAisheng Dong if (host->ops->set_timeout) { 702b45e668aSAisheng Dong host->ops->set_timeout(host, cmd); 703b45e668aSAisheng Dong } else { 704b45e668aSAisheng Dong count = sdhci_calc_timeout(host, cmd); 705b45e668aSAisheng Dong sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 706b45e668aSAisheng Dong } 707b45e668aSAisheng Dong } 708b45e668aSAisheng Dong 709b45e668aSAisheng Dong static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 710b45e668aSAisheng Dong { 7112134a922SPierre Ossman u8 ctrl; 712a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 7138f1934ceSPierre Ossman int ret; 714ee53ab5dSPierre Ossman 715ee53ab5dSPierre Ossman WARN_ON(host->data); 716ee53ab5dSPierre Ossman 717b45e668aSAisheng Dong if (data || (cmd->flags & MMC_RSP_BUSY)) 718b45e668aSAisheng Dong sdhci_set_timeout(host, cmd); 719a3c7778fSAndrei Warkentin 720a3c7778fSAndrei Warkentin if (!data) 721ee53ab5dSPierre Ossman return; 722ee53ab5dSPierre Ossman 723ee53ab5dSPierre Ossman /* Sanity checks */ 724ee53ab5dSPierre Ossman BUG_ON(data->blksz * data->blocks > 524288); 725ee53ab5dSPierre Ossman BUG_ON(data->blksz > host->mmc->max_blk_size); 726ee53ab5dSPierre Ossman BUG_ON(data->blocks > 65535); 727ee53ab5dSPierre Ossman 728ee53ab5dSPierre Ossman host->data = data; 729ee53ab5dSPierre Ossman host->data_early = 0; 730f6a03cbfSMikko Vinni host->data->bytes_xfered = 0; 731ee53ab5dSPierre Ossman 732a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 733c9fddbc4SPierre Ossman host->flags |= SDHCI_REQ_USE_DMA; 734c9fddbc4SPierre Ossman 7352134a922SPierre Ossman /* 7362134a922SPierre Ossman * FIXME: This doesn't account for merging when mapping the 7372134a922SPierre Ossman * scatterlist. 7382134a922SPierre Ossman */ 7392134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7402134a922SPierre Ossman int broken, i; 7412134a922SPierre Ossman struct scatterlist *sg; 7422134a922SPierre Ossman 7432134a922SPierre Ossman broken = 0; 7442134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7452134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7462134a922SPierre Ossman broken = 1; 7472134a922SPierre Ossman } else { 7482134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 7492134a922SPierre Ossman broken = 1; 7502134a922SPierre Ossman } 7512134a922SPierre Ossman 7522134a922SPierre Ossman if (unlikely(broken)) { 7532134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 7542134a922SPierre Ossman if (sg->length & 0x3) { 7552e4456f0SMarek Vasut DBG("Reverting to PIO because of transfer size (%d)\n", 7562134a922SPierre Ossman sg->length); 757c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 7582134a922SPierre Ossman break; 7592134a922SPierre Ossman } 7602134a922SPierre Ossman } 7612134a922SPierre Ossman } 762c9fddbc4SPierre Ossman } 763c9fddbc4SPierre Ossman 764c9fddbc4SPierre Ossman /* 765c9fddbc4SPierre Ossman * The assumption here being that alignment is the same after 766c9fddbc4SPierre Ossman * translation to device address space. 767c9fddbc4SPierre Ossman */ 7682134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7692134a922SPierre Ossman int broken, i; 7702134a922SPierre Ossman struct scatterlist *sg; 7712134a922SPierre Ossman 7722134a922SPierre Ossman broken = 0; 7732134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7742134a922SPierre Ossman /* 7752134a922SPierre Ossman * As we use 3 byte chunks to work around 7762134a922SPierre Ossman * alignment problems, we need to check this 7772134a922SPierre Ossman * quirk. 7782134a922SPierre Ossman */ 7792134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7802134a922SPierre Ossman broken = 1; 7812134a922SPierre Ossman } else { 7822134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 7832134a922SPierre Ossman broken = 1; 7842134a922SPierre Ossman } 7852134a922SPierre Ossman 7862134a922SPierre Ossman if (unlikely(broken)) { 7872134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 7882134a922SPierre Ossman if (sg->offset & 0x3) { 7892e4456f0SMarek Vasut DBG("Reverting to PIO because of bad alignment\n"); 790c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 7912134a922SPierre Ossman break; 7922134a922SPierre Ossman } 7932134a922SPierre Ossman } 7942134a922SPierre Ossman } 7952134a922SPierre Ossman } 7962134a922SPierre Ossman 7978f1934ceSPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7988f1934ceSPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7998f1934ceSPierre Ossman ret = sdhci_adma_table_pre(host, data); 8008f1934ceSPierre Ossman if (ret) { 8018f1934ceSPierre Ossman /* 8028f1934ceSPierre Ossman * This only happens when someone fed 8038f1934ceSPierre Ossman * us an invalid request. 8048f1934ceSPierre Ossman */ 8058f1934ceSPierre Ossman WARN_ON(1); 806ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8078f1934ceSPierre Ossman } else { 8084e4141a5SAnton Vorontsov sdhci_writel(host, host->adma_addr, 8094e4141a5SAnton Vorontsov SDHCI_ADMA_ADDRESS); 810e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 811e57a5f61SAdrian Hunter sdhci_writel(host, 812e57a5f61SAdrian Hunter (u64)host->adma_addr >> 32, 813e57a5f61SAdrian Hunter SDHCI_ADMA_ADDRESS_HI); 8148f1934ceSPierre Ossman } 8158f1934ceSPierre Ossman } else { 816c8b3e02eSTomas Winkler int sg_cnt; 8178f1934ceSPierre Ossman 818d31911b9SHaibo Chen sg_cnt = sdhci_pre_dma_transfer(host, data); 81962a7f368SJiri Slaby if (sg_cnt <= 0) { 8208f1934ceSPierre Ossman /* 8218f1934ceSPierre Ossman * This only happens when someone fed 8228f1934ceSPierre Ossman * us an invalid request. 8238f1934ceSPierre Ossman */ 8248f1934ceSPierre Ossman WARN_ON(1); 825ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8268f1934ceSPierre Ossman } else { 827719a61b4SPierre Ossman WARN_ON(sg_cnt != 1); 8284e4141a5SAnton Vorontsov sdhci_writel(host, sg_dma_address(data->sg), 8294e4141a5SAnton Vorontsov SDHCI_DMA_ADDRESS); 8308f1934ceSPierre Ossman } 8318f1934ceSPierre Ossman } 8328f1934ceSPierre Ossman } 8338f1934ceSPierre Ossman 8342134a922SPierre Ossman /* 8352134a922SPierre Ossman * Always adjust the DMA selection as some controllers 8362134a922SPierre Ossman * (e.g. JMicron) can't do PIO properly when the selection 8372134a922SPierre Ossman * is ADMA. 8382134a922SPierre Ossman */ 8392134a922SPierre Ossman if (host->version >= SDHCI_SPEC_200) { 8404e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 8412134a922SPierre Ossman ctrl &= ~SDHCI_CTRL_DMA_MASK; 8422134a922SPierre Ossman if ((host->flags & SDHCI_REQ_USE_DMA) && 843e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_ADMA)) { 844e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 845e57a5f61SAdrian Hunter ctrl |= SDHCI_CTRL_ADMA64; 8462134a922SPierre Ossman else 847e57a5f61SAdrian Hunter ctrl |= SDHCI_CTRL_ADMA32; 848e57a5f61SAdrian Hunter } else { 8492134a922SPierre Ossman ctrl |= SDHCI_CTRL_SDMA; 850e57a5f61SAdrian Hunter } 8514e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 852c9fddbc4SPierre Ossman } 853c9fddbc4SPierre Ossman 8548f1934ceSPierre Ossman if (!(host->flags & SDHCI_REQ_USE_DMA)) { 855da60a91dSSebastian Andrzej Siewior int flags; 856da60a91dSSebastian Andrzej Siewior 857da60a91dSSebastian Andrzej Siewior flags = SG_MITER_ATOMIC; 858da60a91dSSebastian Andrzej Siewior if (host->data->flags & MMC_DATA_READ) 859da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_TO_SG; 860da60a91dSSebastian Andrzej Siewior else 861da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_FROM_SG; 862da60a91dSSebastian Andrzej Siewior sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 8637659150cSPierre Ossman host->blocks = data->blocks; 8641c6a0718SPierre Ossman } 8651c6a0718SPierre Ossman 8666aa943abSAnton Vorontsov sdhci_set_transfer_irqs(host); 8676aa943abSAnton Vorontsov 868f6a03cbfSMikko Vinni /* Set the DMA boundary value and block size */ 869f6a03cbfSMikko Vinni sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 870f6a03cbfSMikko Vinni data->blksz), SDHCI_BLOCK_SIZE); 8714e4141a5SAnton Vorontsov sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 8721c6a0718SPierre Ossman } 8731c6a0718SPierre Ossman 8741c6a0718SPierre Ossman static void sdhci_set_transfer_mode(struct sdhci_host *host, 875e89d456fSAndrei Warkentin struct mmc_command *cmd) 8761c6a0718SPierre Ossman { 877d3fc5d71SVincent Yang u16 mode = 0; 878e89d456fSAndrei Warkentin struct mmc_data *data = cmd->data; 8791c6a0718SPierre Ossman 8802b558c13SDong Aisheng if (data == NULL) { 8819b8ffea6SVincent Wan if (host->quirks2 & 8829b8ffea6SVincent Wan SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 8839b8ffea6SVincent Wan sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 8849b8ffea6SVincent Wan } else { 8852b558c13SDong Aisheng /* clear Auto CMD settings for no data CMDs */ 8862b558c13SDong Aisheng mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 8872b558c13SDong Aisheng sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 8882b558c13SDong Aisheng SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 8899b8ffea6SVincent Wan } 8901c6a0718SPierre Ossman return; 8912b558c13SDong Aisheng } 8921c6a0718SPierre Ossman 893e538fbe8SPierre Ossman WARN_ON(!host->data); 894e538fbe8SPierre Ossman 895d3fc5d71SVincent Yang if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 8961c6a0718SPierre Ossman mode = SDHCI_TRNS_BLK_CNT_EN; 897d3fc5d71SVincent Yang 898e89d456fSAndrei Warkentin if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 899d3fc5d71SVincent Yang mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 900e89d456fSAndrei Warkentin /* 901e89d456fSAndrei Warkentin * If we are sending CMD23, CMD12 never gets sent 902e89d456fSAndrei Warkentin * on successful completion (so no Auto-CMD12). 903e89d456fSAndrei Warkentin */ 90485cc1c33SCorneliu Doban if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 90585cc1c33SCorneliu Doban (cmd->opcode != SD_IO_RW_EXTENDED)) 906e89d456fSAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD12; 9078edf6371SAndrei Warkentin else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 9088edf6371SAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD23; 9098edf6371SAndrei Warkentin sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 910c4512f79SJerry Huang } 9118edf6371SAndrei Warkentin } 9128edf6371SAndrei Warkentin 9131c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 9141c6a0718SPierre Ossman mode |= SDHCI_TRNS_READ; 915c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) 9161c6a0718SPierre Ossman mode |= SDHCI_TRNS_DMA; 9171c6a0718SPierre Ossman 9184e4141a5SAnton Vorontsov sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 9191c6a0718SPierre Ossman } 9201c6a0718SPierre Ossman 9211c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *host) 9221c6a0718SPierre Ossman { 9231c6a0718SPierre Ossman struct mmc_data *data; 9241c6a0718SPierre Ossman 9251c6a0718SPierre Ossman BUG_ON(!host->data); 9261c6a0718SPierre Ossman 9271c6a0718SPierre Ossman data = host->data; 9281c6a0718SPierre Ossman host->data = NULL; 9291c6a0718SPierre Ossman 930c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 9312134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 9322134a922SPierre Ossman sdhci_adma_table_post(host, data); 933f55c98f7SRussell King 934d31911b9SHaibo Chen if (data->host_cookie == COOKIE_MAPPED) { 935f55c98f7SRussell King dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 936348487cbSHaibo Chen (data->flags & MMC_DATA_READ) ? 937b8c86fc5SPierre Ossman DMA_FROM_DEVICE : DMA_TO_DEVICE); 938d31911b9SHaibo Chen data->host_cookie = COOKIE_UNMAPPED; 939d31911b9SHaibo Chen } 9401c6a0718SPierre Ossman } 9411c6a0718SPierre Ossman 9421c6a0718SPierre Ossman /* 943c9b74c5bSPierre Ossman * The specification states that the block count register must 944c9b74c5bSPierre Ossman * be updated, but it does not specify at what point in the 945c9b74c5bSPierre Ossman * data flow. That makes the register entirely useless to read 946c9b74c5bSPierre Ossman * back so we have to assume that nothing made it to the card 947c9b74c5bSPierre Ossman * in the event of an error. 9481c6a0718SPierre Ossman */ 949c9b74c5bSPierre Ossman if (data->error) 950c9b74c5bSPierre Ossman data->bytes_xfered = 0; 9511c6a0718SPierre Ossman else 952c9b74c5bSPierre Ossman data->bytes_xfered = data->blksz * data->blocks; 9531c6a0718SPierre Ossman 954e89d456fSAndrei Warkentin /* 955e89d456fSAndrei Warkentin * Need to send CMD12 if - 956e89d456fSAndrei Warkentin * a) open-ended multiblock transfer (no CMD23) 957e89d456fSAndrei Warkentin * b) error in multiblock transfer 958e89d456fSAndrei Warkentin */ 959e89d456fSAndrei Warkentin if (data->stop && 960e89d456fSAndrei Warkentin (data->error || 961e89d456fSAndrei Warkentin !host->mrq->sbc)) { 962e89d456fSAndrei Warkentin 9631c6a0718SPierre Ossman /* 9641c6a0718SPierre Ossman * The controller needs a reset of internal state machines 9651c6a0718SPierre Ossman * upon error conditions. 9661c6a0718SPierre Ossman */ 96717b0429dSPierre Ossman if (data->error) { 96803231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 96903231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 9701c6a0718SPierre Ossman } 9711c6a0718SPierre Ossman 9721c6a0718SPierre Ossman sdhci_send_command(host, data->stop); 9731c6a0718SPierre Ossman } else 9741c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 9751c6a0718SPierre Ossman } 9761c6a0718SPierre Ossman 977c0e55129SDong Aisheng void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 9781c6a0718SPierre Ossman { 9791c6a0718SPierre Ossman int flags; 9801c6a0718SPierre Ossman u32 mask; 9811c6a0718SPierre Ossman unsigned long timeout; 9821c6a0718SPierre Ossman 9831c6a0718SPierre Ossman WARN_ON(host->cmd); 9841c6a0718SPierre Ossman 98596776200SRussell King /* Initially, a command has no error */ 98696776200SRussell King cmd->error = 0; 98796776200SRussell King 9881c6a0718SPierre Ossman /* Wait max 10 ms */ 9891c6a0718SPierre Ossman timeout = 10; 9901c6a0718SPierre Ossman 9911c6a0718SPierre Ossman mask = SDHCI_CMD_INHIBIT; 9921c6a0718SPierre Ossman if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 9931c6a0718SPierre Ossman mask |= SDHCI_DATA_INHIBIT; 9941c6a0718SPierre Ossman 9951c6a0718SPierre Ossman /* We shouldn't wait for data inihibit for stop commands, even 9961c6a0718SPierre Ossman though they might use busy signaling */ 9971c6a0718SPierre Ossman if (host->mrq->data && (cmd == host->mrq->data->stop)) 9981c6a0718SPierre Ossman mask &= ~SDHCI_DATA_INHIBIT; 9991c6a0718SPierre Ossman 10004e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 10011c6a0718SPierre Ossman if (timeout == 0) { 10022e4456f0SMarek Vasut pr_err("%s: Controller never released inhibit bit(s).\n", 10032e4456f0SMarek Vasut mmc_hostname(host->mmc)); 10041c6a0718SPierre Ossman sdhci_dumpregs(host); 100517b0429dSPierre Ossman cmd->error = -EIO; 10061c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10071c6a0718SPierre Ossman return; 10081c6a0718SPierre Ossman } 10091c6a0718SPierre Ossman timeout--; 10101c6a0718SPierre Ossman mdelay(1); 10111c6a0718SPierre Ossman } 10121c6a0718SPierre Ossman 10133e1a6892SAdrian Hunter timeout = jiffies; 10141d4d7744SUlf Hansson if (!cmd->data && cmd->busy_timeout > 9000) 10151d4d7744SUlf Hansson timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 10163e1a6892SAdrian Hunter else 10173e1a6892SAdrian Hunter timeout += 10 * HZ; 10183e1a6892SAdrian Hunter mod_timer(&host->timer, timeout); 10191c6a0718SPierre Ossman 10201c6a0718SPierre Ossman host->cmd = cmd; 1021e99783a4SChanho Min host->busy_handle = 0; 10221c6a0718SPierre Ossman 1023a3c7778fSAndrei Warkentin sdhci_prepare_data(host, cmd); 10241c6a0718SPierre Ossman 10254e4141a5SAnton Vorontsov sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 10261c6a0718SPierre Ossman 1027e89d456fSAndrei Warkentin sdhci_set_transfer_mode(host, cmd); 10281c6a0718SPierre Ossman 10291c6a0718SPierre Ossman if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1030a3c76eb9SGirish K S pr_err("%s: Unsupported response type!\n", 10311c6a0718SPierre Ossman mmc_hostname(host->mmc)); 103217b0429dSPierre Ossman cmd->error = -EINVAL; 10331c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10341c6a0718SPierre Ossman return; 10351c6a0718SPierre Ossman } 10361c6a0718SPierre Ossman 10371c6a0718SPierre Ossman if (!(cmd->flags & MMC_RSP_PRESENT)) 10381c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_NONE; 10391c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_136) 10401c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_LONG; 10411c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_BUSY) 10421c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT_BUSY; 10431c6a0718SPierre Ossman else 10441c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT; 10451c6a0718SPierre Ossman 10461c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_CRC) 10471c6a0718SPierre Ossman flags |= SDHCI_CMD_CRC; 10481c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_OPCODE) 10491c6a0718SPierre Ossman flags |= SDHCI_CMD_INDEX; 1050b513ea25SArindam Nath 1051b513ea25SArindam Nath /* CMD19 is special in that the Data Present Select should be set */ 1052069c9f14SGirish K S if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1053069c9f14SGirish K S cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 10541c6a0718SPierre Ossman flags |= SDHCI_CMD_DATA; 10551c6a0718SPierre Ossman 10564e4141a5SAnton Vorontsov sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 10571c6a0718SPierre Ossman } 1058c0e55129SDong Aisheng EXPORT_SYMBOL_GPL(sdhci_send_command); 10591c6a0718SPierre Ossman 10601c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *host) 10611c6a0718SPierre Ossman { 10621c6a0718SPierre Ossman int i; 10631c6a0718SPierre Ossman 10641c6a0718SPierre Ossman BUG_ON(host->cmd == NULL); 10651c6a0718SPierre Ossman 10661c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_PRESENT) { 10671c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_136) { 10681c6a0718SPierre Ossman /* CRC is stripped so we need to do some shifting. */ 10691c6a0718SPierre Ossman for (i = 0;i < 4;i++) { 10704e4141a5SAnton Vorontsov host->cmd->resp[i] = sdhci_readl(host, 10711c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4) << 8; 10721c6a0718SPierre Ossman if (i != 3) 10731c6a0718SPierre Ossman host->cmd->resp[i] |= 10744e4141a5SAnton Vorontsov sdhci_readb(host, 10751c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4-1); 10761c6a0718SPierre Ossman } 10771c6a0718SPierre Ossman } else { 10784e4141a5SAnton Vorontsov host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 10791c6a0718SPierre Ossman } 10801c6a0718SPierre Ossman } 10811c6a0718SPierre Ossman 1082e89d456fSAndrei Warkentin /* Finished CMD23, now send actual command. */ 1083e89d456fSAndrei Warkentin if (host->cmd == host->mrq->sbc) { 1084e89d456fSAndrei Warkentin host->cmd = NULL; 1085e89d456fSAndrei Warkentin sdhci_send_command(host, host->mrq->cmd); 1086e89d456fSAndrei Warkentin } else { 1087e89d456fSAndrei Warkentin 1088e89d456fSAndrei Warkentin /* Processed actual command. */ 1089e538fbe8SPierre Ossman if (host->data && host->data_early) 1090e538fbe8SPierre Ossman sdhci_finish_data(host); 1091e538fbe8SPierre Ossman 1092e538fbe8SPierre Ossman if (!host->cmd->data) 10931c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10941c6a0718SPierre Ossman 10951c6a0718SPierre Ossman host->cmd = NULL; 10961c6a0718SPierre Ossman } 1097e89d456fSAndrei Warkentin } 10981c6a0718SPierre Ossman 109952983382SKevin Liu static u16 sdhci_get_preset_value(struct sdhci_host *host) 110052983382SKevin Liu { 1101d975f121SRussell King u16 preset = 0; 110252983382SKevin Liu 1103d975f121SRussell King switch (host->timing) { 1104d975f121SRussell King case MMC_TIMING_UHS_SDR12: 110552983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 110652983382SKevin Liu break; 1107d975f121SRussell King case MMC_TIMING_UHS_SDR25: 110852983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 110952983382SKevin Liu break; 1110d975f121SRussell King case MMC_TIMING_UHS_SDR50: 111152983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 111252983382SKevin Liu break; 1113d975f121SRussell King case MMC_TIMING_UHS_SDR104: 1114d975f121SRussell King case MMC_TIMING_MMC_HS200: 111552983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 111652983382SKevin Liu break; 1117d975f121SRussell King case MMC_TIMING_UHS_DDR50: 11180dafa60eSJisheng Zhang case MMC_TIMING_MMC_DDR52: 111952983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 112052983382SKevin Liu break; 1121e9fb05d5SAdrian Hunter case MMC_TIMING_MMC_HS400: 1122e9fb05d5SAdrian Hunter preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1123e9fb05d5SAdrian Hunter break; 112452983382SKevin Liu default: 112552983382SKevin Liu pr_warn("%s: Invalid UHS-I mode selected\n", 112652983382SKevin Liu mmc_hostname(host->mmc)); 112752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 112852983382SKevin Liu break; 112952983382SKevin Liu } 113052983382SKevin Liu return preset; 113152983382SKevin Liu } 113252983382SKevin Liu 11331771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 11341c6a0718SPierre Ossman { 1135c3ed3877SArindam Nath int div = 0; /* Initialized for compiler warning */ 1136df16219fSGiuseppe CAVALLARO int real_div = div, clk_mul = 1; 1137c3ed3877SArindam Nath u16 clk = 0; 11381c6a0718SPierre Ossman unsigned long timeout; 11395497159cSludovic.desroches@atmel.com bool switch_base_clk = false; 11401c6a0718SPierre Ossman 11411650d0c7SRussell King host->mmc->actual_clock = 0; 11421650d0c7SRussell King 11434e4141a5SAnton Vorontsov sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1144af951761Sludovic.desroches@atmel.com if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST) 1145af951761Sludovic.desroches@atmel.com mdelay(1); 11461c6a0718SPierre Ossman 11471c6a0718SPierre Ossman if (clock == 0) 1148373073efSRussell King return; 11491c6a0718SPierre Ossman 115085105c53SZhangfei Gao if (host->version >= SDHCI_SPEC_300) { 1151da91a8f9SRussell King if (host->preset_enabled) { 115252983382SKevin Liu u16 pre_val; 115352983382SKevin Liu 115452983382SKevin Liu clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 115552983382SKevin Liu pre_val = sdhci_get_preset_value(host); 115652983382SKevin Liu div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 115752983382SKevin Liu >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 115852983382SKevin Liu if (host->clk_mul && 115952983382SKevin Liu (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 116052983382SKevin Liu clk = SDHCI_PROG_CLOCK_MODE; 116152983382SKevin Liu real_div = div + 1; 116252983382SKevin Liu clk_mul = host->clk_mul; 116352983382SKevin Liu } else { 116452983382SKevin Liu real_div = max_t(int, 1, div << 1); 116552983382SKevin Liu } 116652983382SKevin Liu goto clock_set; 116752983382SKevin Liu } 116852983382SKevin Liu 1169c3ed3877SArindam Nath /* 1170c3ed3877SArindam Nath * Check if the Host Controller supports Programmable Clock 1171c3ed3877SArindam Nath * Mode. 1172c3ed3877SArindam Nath */ 1173c3ed3877SArindam Nath if (host->clk_mul) { 1174c3ed3877SArindam Nath for (div = 1; div <= 1024; div++) { 117552983382SKevin Liu if ((host->max_clk * host->clk_mul / div) 117652983382SKevin Liu <= clock) 1177c3ed3877SArindam Nath break; 1178c3ed3877SArindam Nath } 11795497159cSludovic.desroches@atmel.com if ((host->max_clk * host->clk_mul / div) <= clock) { 1180c3ed3877SArindam Nath /* 1181c3ed3877SArindam Nath * Set Programmable Clock Mode in the Clock 1182c3ed3877SArindam Nath * Control register. 1183c3ed3877SArindam Nath */ 1184c3ed3877SArindam Nath clk = SDHCI_PROG_CLOCK_MODE; 1185df16219fSGiuseppe CAVALLARO real_div = div; 1186df16219fSGiuseppe CAVALLARO clk_mul = host->clk_mul; 1187c3ed3877SArindam Nath div--; 1188c3ed3877SArindam Nath } else { 11895497159cSludovic.desroches@atmel.com /* 11905497159cSludovic.desroches@atmel.com * Divisor can be too small to reach clock 11915497159cSludovic.desroches@atmel.com * speed requirement. Then use the base clock. 11925497159cSludovic.desroches@atmel.com */ 11935497159cSludovic.desroches@atmel.com switch_base_clk = true; 11945497159cSludovic.desroches@atmel.com } 11955497159cSludovic.desroches@atmel.com } 11965497159cSludovic.desroches@atmel.com 11975497159cSludovic.desroches@atmel.com if (!host->clk_mul || switch_base_clk) { 119885105c53SZhangfei Gao /* Version 3.00 divisors must be a multiple of 2. */ 119985105c53SZhangfei Gao if (host->max_clk <= clock) 120085105c53SZhangfei Gao div = 1; 120185105c53SZhangfei Gao else { 1202c3ed3877SArindam Nath for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1203c3ed3877SArindam Nath div += 2) { 120485105c53SZhangfei Gao if ((host->max_clk / div) <= clock) 120585105c53SZhangfei Gao break; 120685105c53SZhangfei Gao } 120785105c53SZhangfei Gao } 1208df16219fSGiuseppe CAVALLARO real_div = div; 1209c3ed3877SArindam Nath div >>= 1; 1210d1955c3aSSuneel Garapati if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1211d1955c3aSSuneel Garapati && !div && host->max_clk <= 25000000) 1212d1955c3aSSuneel Garapati div = 1; 1213c3ed3877SArindam Nath } 121485105c53SZhangfei Gao } else { 121585105c53SZhangfei Gao /* Version 2.00 divisors must be a power of 2. */ 12160397526dSZhangfei Gao for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 12171c6a0718SPierre Ossman if ((host->max_clk / div) <= clock) 12181c6a0718SPierre Ossman break; 12191c6a0718SPierre Ossman } 1220df16219fSGiuseppe CAVALLARO real_div = div; 12211c6a0718SPierre Ossman div >>= 1; 1222c3ed3877SArindam Nath } 12231c6a0718SPierre Ossman 122452983382SKevin Liu clock_set: 122503d6f5ffSAisheng Dong if (real_div) 1226df16219fSGiuseppe CAVALLARO host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1227c3ed3877SArindam Nath clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 122885105c53SZhangfei Gao clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 122985105c53SZhangfei Gao << SDHCI_DIVIDER_HI_SHIFT; 12301c6a0718SPierre Ossman clk |= SDHCI_CLOCK_INT_EN; 12314e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12321c6a0718SPierre Ossman 123327f6cb16SChris Ball /* Wait max 20 ms */ 123427f6cb16SChris Ball timeout = 20; 12354e4141a5SAnton Vorontsov while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 12361c6a0718SPierre Ossman & SDHCI_CLOCK_INT_STABLE)) { 12371c6a0718SPierre Ossman if (timeout == 0) { 12382e4456f0SMarek Vasut pr_err("%s: Internal clock never stabilised.\n", 12392e4456f0SMarek Vasut mmc_hostname(host->mmc)); 12401c6a0718SPierre Ossman sdhci_dumpregs(host); 12411c6a0718SPierre Ossman return; 12421c6a0718SPierre Ossman } 12431c6a0718SPierre Ossman timeout--; 12441c6a0718SPierre Ossman mdelay(1); 12451c6a0718SPierre Ossman } 12461c6a0718SPierre Ossman 12471c6a0718SPierre Ossman clk |= SDHCI_CLOCK_CARD_EN; 12484e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12491c6a0718SPierre Ossman } 12501771059cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_clock); 12511c6a0718SPierre Ossman 125224fbb3caSRussell King static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 125324fbb3caSRussell King unsigned short vdd) 12541c6a0718SPierre Ossman { 12553a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 12568364248aSGiuseppe Cavallaro u8 pwr = 0; 12571c6a0718SPierre Ossman 125824fbb3caSRussell King if (mode != MMC_POWER_OFF) { 125924fbb3caSRussell King switch (1 << vdd) { 1260ae628903SPierre Ossman case MMC_VDD_165_195: 1261ae628903SPierre Ossman pwr = SDHCI_POWER_180; 1262ae628903SPierre Ossman break; 1263ae628903SPierre Ossman case MMC_VDD_29_30: 1264ae628903SPierre Ossman case MMC_VDD_30_31: 1265ae628903SPierre Ossman pwr = SDHCI_POWER_300; 1266ae628903SPierre Ossman break; 1267ae628903SPierre Ossman case MMC_VDD_32_33: 1268ae628903SPierre Ossman case MMC_VDD_33_34: 1269ae628903SPierre Ossman pwr = SDHCI_POWER_330; 1270ae628903SPierre Ossman break; 1271ae628903SPierre Ossman default: 12729d5de93fSAdrian Hunter WARN(1, "%s: Invalid vdd %#x\n", 12739d5de93fSAdrian Hunter mmc_hostname(host->mmc), vdd); 12749d5de93fSAdrian Hunter break; 1275ae628903SPierre Ossman } 1276ae628903SPierre Ossman } 1277ae628903SPierre Ossman 1278ae628903SPierre Ossman if (host->pwr == pwr) 1279e921a8b6SRussell King return; 12801c6a0718SPierre Ossman 1281ae628903SPierre Ossman host->pwr = pwr; 1282ae628903SPierre Ossman 1283ae628903SPierre Ossman if (pwr == 0) { 12844e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1285f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1286f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 128724fbb3caSRussell King vdd = 0; 1288e921a8b6SRussell King } else { 12891c6a0718SPierre Ossman /* 12901c6a0718SPierre Ossman * Spec says that we should clear the power reg before setting 12911c6a0718SPierre Ossman * a new value. Some controllers don't seem to like this though. 12921c6a0718SPierre Ossman */ 1293b8c86fc5SPierre Ossman if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 12944e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 12951c6a0718SPierre Ossman 1296e08c1694SAndres Salomon /* 1297e921a8b6SRussell King * At least the Marvell CaFe chip gets confused if we set the 1298e921a8b6SRussell King * voltage and set turn on power at the same time, so set the 1299e921a8b6SRussell King * voltage first. 1300e08c1694SAndres Salomon */ 130111a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 13024e4141a5SAnton Vorontsov sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 13031c6a0718SPierre Ossman 1304ae628903SPierre Ossman pwr |= SDHCI_POWER_ON; 1305ae628903SPierre Ossman 1306ae628903SPierre Ossman sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1307557b0697SHarald Welte 1308f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1309f0710a55SAdrian Hunter sdhci_runtime_pm_bus_on(host); 1310f0710a55SAdrian Hunter 1311557b0697SHarald Welte /* 1312e921a8b6SRussell King * Some controllers need an extra 10ms delay of 10ms before 1313e921a8b6SRussell King * they can apply clock after applying power 1314557b0697SHarald Welte */ 131511a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1316557b0697SHarald Welte mdelay(10); 1317e921a8b6SRussell King } 1318918f4cbdSJisheng Zhang 1319918f4cbdSJisheng Zhang if (!IS_ERR(mmc->supply.vmmc)) { 1320918f4cbdSJisheng Zhang spin_unlock_irq(&host->lock); 1321918f4cbdSJisheng Zhang mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1322918f4cbdSJisheng Zhang spin_lock_irq(&host->lock); 1323918f4cbdSJisheng Zhang } 13241c6a0718SPierre Ossman } 13251c6a0718SPierre Ossman 13261c6a0718SPierre Ossman /*****************************************************************************\ 13271c6a0718SPierre Ossman * * 13281c6a0718SPierre Ossman * MMC callbacks * 13291c6a0718SPierre Ossman * * 13301c6a0718SPierre Ossman \*****************************************************************************/ 13311c6a0718SPierre Ossman 13321c6a0718SPierre Ossman static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13331c6a0718SPierre Ossman { 13341c6a0718SPierre Ossman struct sdhci_host *host; 1335505a8680SShawn Guo int present; 13361c6a0718SPierre Ossman unsigned long flags; 13371c6a0718SPierre Ossman 13381c6a0718SPierre Ossman host = mmc_priv(mmc); 13391c6a0718SPierre Ossman 134066fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 134166fd8ad5SAdrian Hunter 134204e079cfSScott Branden /* Firstly check card presence */ 13438d28b7a7SAdrian Hunter present = mmc->ops->get_cd(mmc); 13442836766aSKrzysztof Kozlowski 13451c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 13461c6a0718SPierre Ossman 13471c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13481c6a0718SPierre Ossman 1349f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 13501c6a0718SPierre Ossman sdhci_activate_led(host); 13512f730fecSPierre Ossman #endif 1352e89d456fSAndrei Warkentin 1353e89d456fSAndrei Warkentin /* 1354e89d456fSAndrei Warkentin * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1355e89d456fSAndrei Warkentin * requests if Auto-CMD12 is enabled. 1356e89d456fSAndrei Warkentin */ 1357e89d456fSAndrei Warkentin if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1358c4512f79SJerry Huang if (mrq->stop) { 1359c4512f79SJerry Huang mrq->data->stop = NULL; 1360c4512f79SJerry Huang mrq->stop = NULL; 1361c4512f79SJerry Huang } 1362c4512f79SJerry Huang } 13631c6a0718SPierre Ossman 13641c6a0718SPierre Ossman host->mrq = mrq; 13651c6a0718SPierre Ossman 136668d1fb7eSAnton Vorontsov if (!present || host->flags & SDHCI_DEVICE_DEAD) { 136717b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 13681c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 1369cf2b5eeaSArindam Nath } else { 13708edf6371SAndrei Warkentin if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1371e89d456fSAndrei Warkentin sdhci_send_command(host, mrq->sbc); 1372e89d456fSAndrei Warkentin else 13731c6a0718SPierre Ossman sdhci_send_command(host, mrq->cmd); 1374cf2b5eeaSArindam Nath } 13751c6a0718SPierre Ossman 13761c6a0718SPierre Ossman mmiowb(); 13771c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 13781c6a0718SPierre Ossman } 13791c6a0718SPierre Ossman 13802317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width) 13812317f56cSRussell King { 13822317f56cSRussell King u8 ctrl; 13832317f56cSRussell King 13842317f56cSRussell King ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 13852317f56cSRussell King if (width == MMC_BUS_WIDTH_8) { 13862317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 13872317f56cSRussell King if (host->version >= SDHCI_SPEC_300) 13882317f56cSRussell King ctrl |= SDHCI_CTRL_8BITBUS; 13892317f56cSRussell King } else { 13902317f56cSRussell King if (host->version >= SDHCI_SPEC_300) 13912317f56cSRussell King ctrl &= ~SDHCI_CTRL_8BITBUS; 13922317f56cSRussell King if (width == MMC_BUS_WIDTH_4) 13932317f56cSRussell King ctrl |= SDHCI_CTRL_4BITBUS; 13942317f56cSRussell King else 13952317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 13962317f56cSRussell King } 13972317f56cSRussell King sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 13982317f56cSRussell King } 13992317f56cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 14002317f56cSRussell King 140196d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 140296d7b78cSRussell King { 140396d7b78cSRussell King u16 ctrl_2; 140496d7b78cSRussell King 140596d7b78cSRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 140696d7b78cSRussell King /* Select Bus Speed Mode for host */ 140796d7b78cSRussell King ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 140896d7b78cSRussell King if ((timing == MMC_TIMING_MMC_HS200) || 140996d7b78cSRussell King (timing == MMC_TIMING_UHS_SDR104)) 141096d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 141196d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR12) 141296d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 141396d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR25) 141496d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 141596d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR50) 141696d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 141796d7b78cSRussell King else if ((timing == MMC_TIMING_UHS_DDR50) || 141896d7b78cSRussell King (timing == MMC_TIMING_MMC_DDR52)) 141996d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1420e9fb05d5SAdrian Hunter else if (timing == MMC_TIMING_MMC_HS400) 1421e9fb05d5SAdrian Hunter ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 142296d7b78cSRussell King sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 142396d7b78cSRussell King } 142496d7b78cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 142596d7b78cSRussell King 142666fd8ad5SAdrian Hunter static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 14271c6a0718SPierre Ossman { 14281c6a0718SPierre Ossman unsigned long flags; 14291c6a0718SPierre Ossman u8 ctrl; 14303a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 14311c6a0718SPierre Ossman 14321c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 14331c6a0718SPierre Ossman 1434ceb6143bSAdrian Hunter if (host->flags & SDHCI_DEVICE_DEAD) { 1435ceb6143bSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 14363a48edc4STim Kryger if (!IS_ERR(mmc->supply.vmmc) && 14373a48edc4STim Kryger ios->power_mode == MMC_POWER_OFF) 14384e743f1fSMarkus Mayer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1439ceb6143bSAdrian Hunter return; 1440ceb6143bSAdrian Hunter } 14411e72859eSPierre Ossman 14421c6a0718SPierre Ossman /* 14431c6a0718SPierre Ossman * Reset the chip on each power off. 14441c6a0718SPierre Ossman * Should clear out any weird states. 14451c6a0718SPierre Ossman */ 14461c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) { 14474e4141a5SAnton Vorontsov sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 14487260cf5eSAnton Vorontsov sdhci_reinit(host); 14491c6a0718SPierre Ossman } 14501c6a0718SPierre Ossman 145152983382SKevin Liu if (host->version >= SDHCI_SPEC_300 && 1452372c4634SDong Aisheng (ios->power_mode == MMC_POWER_UP) && 1453372c4634SDong Aisheng !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 145452983382SKevin Liu sdhci_enable_preset_value(host, false); 145552983382SKevin Liu 1456373073efSRussell King if (!ios->clock || ios->clock != host->clock) { 14571771059cSRussell King host->ops->set_clock(host, ios->clock); 1458373073efSRussell King host->clock = ios->clock; 145903d6f5ffSAisheng Dong 146003d6f5ffSAisheng Dong if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 146103d6f5ffSAisheng Dong host->clock) { 146203d6f5ffSAisheng Dong host->timeout_clk = host->mmc->actual_clock ? 146303d6f5ffSAisheng Dong host->mmc->actual_clock / 1000 : 146403d6f5ffSAisheng Dong host->clock / 1000; 146503d6f5ffSAisheng Dong host->mmc->max_busy_timeout = 146603d6f5ffSAisheng Dong host->ops->get_max_timeout_count ? 146703d6f5ffSAisheng Dong host->ops->get_max_timeout_count(host) : 146803d6f5ffSAisheng Dong 1 << 27; 146903d6f5ffSAisheng Dong host->mmc->max_busy_timeout /= host->timeout_clk; 147003d6f5ffSAisheng Dong } 1471373073efSRussell King } 14721c6a0718SPierre Ossman 147324fbb3caSRussell King sdhci_set_power(host, ios->power_mode, ios->vdd); 14741c6a0718SPierre Ossman 1475643a81ffSPhilip Rakity if (host->ops->platform_send_init_74_clocks) 1476643a81ffSPhilip Rakity host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1477643a81ffSPhilip Rakity 14782317f56cSRussell King host->ops->set_bus_width(host, ios->bus_width); 147915ec4461SPhilip Rakity 148015ec4461SPhilip Rakity ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 14811c6a0718SPierre Ossman 14823ab9c8daSPhilip Rakity if ((ios->timing == MMC_TIMING_SD_HS || 14833ab9c8daSPhilip Rakity ios->timing == MMC_TIMING_MMC_HS) 14843ab9c8daSPhilip Rakity && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 14851c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_HISPD; 14861c6a0718SPierre Ossman else 14871c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_HISPD; 14881c6a0718SPierre Ossman 1489d6d50a15SArindam Nath if (host->version >= SDHCI_SPEC_300) { 149049c468fcSArindam Nath u16 clk, ctrl_2; 149149c468fcSArindam Nath 149249c468fcSArindam Nath /* In case of UHS-I modes, set High Speed Enable */ 1493e9fb05d5SAdrian Hunter if ((ios->timing == MMC_TIMING_MMC_HS400) || 1494e9fb05d5SAdrian Hunter (ios->timing == MMC_TIMING_MMC_HS200) || 1495bb8175a8SSeungwon Jeon (ios->timing == MMC_TIMING_MMC_DDR52) || 1496069c9f14SGirish K S (ios->timing == MMC_TIMING_UHS_SDR50) || 149749c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_SDR104) || 149849c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_DDR50) || 1499dd8df17fSAlexander Elbs (ios->timing == MMC_TIMING_UHS_SDR25)) 150049c468fcSArindam Nath ctrl |= SDHCI_CTRL_HISPD; 1501d6d50a15SArindam Nath 1502da91a8f9SRussell King if (!host->preset_enabled) { 1503758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1504d6d50a15SArindam Nath /* 1505d6d50a15SArindam Nath * We only need to set Driver Strength if the 1506d6d50a15SArindam Nath * preset value enable is not set. 1507d6d50a15SArindam Nath */ 1508da91a8f9SRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1509d6d50a15SArindam Nath ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1510d6d50a15SArindam Nath if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1511d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 151243e943a0SPetri Gynther else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 151343e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1514d6d50a15SArindam Nath else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1515d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 151643e943a0SPetri Gynther else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 151743e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 151843e943a0SPetri Gynther else { 15192e4456f0SMarek Vasut pr_warn("%s: invalid driver type, default to driver type B\n", 15202e4456f0SMarek Vasut mmc_hostname(mmc)); 152143e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 152243e943a0SPetri Gynther } 1523d6d50a15SArindam Nath 1524d6d50a15SArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1525758535c4SArindam Nath } else { 1526758535c4SArindam Nath /* 1527758535c4SArindam Nath * According to SDHC Spec v3.00, if the Preset Value 1528758535c4SArindam Nath * Enable in the Host Control 2 register is set, we 1529758535c4SArindam Nath * need to reset SD Clock Enable before changing High 1530758535c4SArindam Nath * Speed Enable to avoid generating clock gliches. 1531758535c4SArindam Nath */ 1532758535c4SArindam Nath 1533758535c4SArindam Nath /* Reset SD Clock Enable */ 1534758535c4SArindam Nath clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1535758535c4SArindam Nath clk &= ~SDHCI_CLOCK_CARD_EN; 1536758535c4SArindam Nath sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1537758535c4SArindam Nath 1538758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1539758535c4SArindam Nath 1540758535c4SArindam Nath /* Re-enable SD Clock */ 15411771059cSRussell King host->ops->set_clock(host, host->clock); 1542d6d50a15SArindam Nath } 154349c468fcSArindam Nath 15446322cdd0SPhilip Rakity /* Reset SD Clock Enable */ 15456322cdd0SPhilip Rakity clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 15466322cdd0SPhilip Rakity clk &= ~SDHCI_CLOCK_CARD_EN; 15476322cdd0SPhilip Rakity sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 15486322cdd0SPhilip Rakity 15496322cdd0SPhilip Rakity host->ops->set_uhs_signaling(host, ios->timing); 1550d975f121SRussell King host->timing = ios->timing; 155149c468fcSArindam Nath 155252983382SKevin Liu if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 155352983382SKevin Liu ((ios->timing == MMC_TIMING_UHS_SDR12) || 155452983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR25) || 155552983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR50) || 155652983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR104) || 15570dafa60eSJisheng Zhang (ios->timing == MMC_TIMING_UHS_DDR50) || 15580dafa60eSJisheng Zhang (ios->timing == MMC_TIMING_MMC_DDR52))) { 155952983382SKevin Liu u16 preset; 156052983382SKevin Liu 156152983382SKevin Liu sdhci_enable_preset_value(host, true); 156252983382SKevin Liu preset = sdhci_get_preset_value(host); 156352983382SKevin Liu ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 156452983382SKevin Liu >> SDHCI_PRESET_DRV_SHIFT; 156552983382SKevin Liu } 156652983382SKevin Liu 156749c468fcSArindam Nath /* Re-enable SD Clock */ 15681771059cSRussell King host->ops->set_clock(host, host->clock); 1569758535c4SArindam Nath } else 1570758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1571d6d50a15SArindam Nath 1572b8352260SLeandro Dorileo /* 1573b8352260SLeandro Dorileo * Some (ENE) controllers go apeshit on some ios operation, 1574b8352260SLeandro Dorileo * signalling timeout and CRC errors even on CMD0. Resetting 1575b8352260SLeandro Dorileo * it on each ios seems to solve the problem. 1576b8352260SLeandro Dorileo */ 1577b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 157803231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1579b8352260SLeandro Dorileo 15801c6a0718SPierre Ossman mmiowb(); 15811c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 15821c6a0718SPierre Ossman } 15831c6a0718SPierre Ossman 158466fd8ad5SAdrian Hunter static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 158566fd8ad5SAdrian Hunter { 158666fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 158766fd8ad5SAdrian Hunter 158866fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 158966fd8ad5SAdrian Hunter sdhci_do_set_ios(host, ios); 159066fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 159166fd8ad5SAdrian Hunter } 159266fd8ad5SAdrian Hunter 159394144a46SKevin Liu static int sdhci_do_get_cd(struct sdhci_host *host) 159494144a46SKevin Liu { 159594144a46SKevin Liu int gpio_cd = mmc_gpio_get_cd(host->mmc); 159694144a46SKevin Liu 159794144a46SKevin Liu if (host->flags & SDHCI_DEVICE_DEAD) 159894144a46SKevin Liu return 0; 159994144a46SKevin Liu 160088af5655SIvan T. Ivanov /* If nonremovable, assume that the card is always present. */ 160188af5655SIvan T. Ivanov if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 160294144a46SKevin Liu return 1; 160394144a46SKevin Liu 160488af5655SIvan T. Ivanov /* 160588af5655SIvan T. Ivanov * Try slot gpio detect, if defined it take precedence 160688af5655SIvan T. Ivanov * over build in controller functionality 160788af5655SIvan T. Ivanov */ 160894144a46SKevin Liu if (!IS_ERR_VALUE(gpio_cd)) 160994144a46SKevin Liu return !!gpio_cd; 161094144a46SKevin Liu 161188af5655SIvan T. Ivanov /* If polling, assume that the card is always present. */ 161288af5655SIvan T. Ivanov if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 161388af5655SIvan T. Ivanov return 1; 161488af5655SIvan T. Ivanov 161594144a46SKevin Liu /* Host native card detect */ 161694144a46SKevin Liu return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 161794144a46SKevin Liu } 161894144a46SKevin Liu 161994144a46SKevin Liu static int sdhci_get_cd(struct mmc_host *mmc) 162094144a46SKevin Liu { 162194144a46SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 162294144a46SKevin Liu int ret; 162394144a46SKevin Liu 162494144a46SKevin Liu sdhci_runtime_pm_get(host); 162594144a46SKevin Liu ret = sdhci_do_get_cd(host); 162694144a46SKevin Liu sdhci_runtime_pm_put(host); 162794144a46SKevin Liu return ret; 162894144a46SKevin Liu } 162994144a46SKevin Liu 163066fd8ad5SAdrian Hunter static int sdhci_check_ro(struct sdhci_host *host) 16311c6a0718SPierre Ossman { 16321c6a0718SPierre Ossman unsigned long flags; 16332dfb579cSWolfram Sang int is_readonly; 16341c6a0718SPierre Ossman 16351c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 16361c6a0718SPierre Ossman 16371e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 16382dfb579cSWolfram Sang is_readonly = 0; 16392dfb579cSWolfram Sang else if (host->ops->get_ro) 16402dfb579cSWolfram Sang is_readonly = host->ops->get_ro(host); 16411e72859eSPierre Ossman else 16422dfb579cSWolfram Sang is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 16432dfb579cSWolfram Sang & SDHCI_WRITE_PROTECT); 16441c6a0718SPierre Ossman 16451c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 16461c6a0718SPierre Ossman 16472dfb579cSWolfram Sang /* This quirk needs to be replaced by a callback-function later */ 16482dfb579cSWolfram Sang return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 16492dfb579cSWolfram Sang !is_readonly : is_readonly; 16501c6a0718SPierre Ossman } 16511c6a0718SPierre Ossman 165282b0e23aSTakashi Iwai #define SAMPLE_COUNT 5 165382b0e23aSTakashi Iwai 165466fd8ad5SAdrian Hunter static int sdhci_do_get_ro(struct sdhci_host *host) 165582b0e23aSTakashi Iwai { 165682b0e23aSTakashi Iwai int i, ro_count; 165782b0e23aSTakashi Iwai 165882b0e23aSTakashi Iwai if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 165966fd8ad5SAdrian Hunter return sdhci_check_ro(host); 166082b0e23aSTakashi Iwai 166182b0e23aSTakashi Iwai ro_count = 0; 166282b0e23aSTakashi Iwai for (i = 0; i < SAMPLE_COUNT; i++) { 166366fd8ad5SAdrian Hunter if (sdhci_check_ro(host)) { 166482b0e23aSTakashi Iwai if (++ro_count > SAMPLE_COUNT / 2) 166582b0e23aSTakashi Iwai return 1; 166682b0e23aSTakashi Iwai } 166782b0e23aSTakashi Iwai msleep(30); 166882b0e23aSTakashi Iwai } 166982b0e23aSTakashi Iwai return 0; 167082b0e23aSTakashi Iwai } 167182b0e23aSTakashi Iwai 167220758b66SAdrian Hunter static void sdhci_hw_reset(struct mmc_host *mmc) 167320758b66SAdrian Hunter { 167420758b66SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 167520758b66SAdrian Hunter 167620758b66SAdrian Hunter if (host->ops && host->ops->hw_reset) 167720758b66SAdrian Hunter host->ops->hw_reset(host); 167820758b66SAdrian Hunter } 167920758b66SAdrian Hunter 168066fd8ad5SAdrian Hunter static int sdhci_get_ro(struct mmc_host *mmc) 1681f75979b7SPierre Ossman { 168266fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 168366fd8ad5SAdrian Hunter int ret; 1684f75979b7SPierre Ossman 168566fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 168666fd8ad5SAdrian Hunter ret = sdhci_do_get_ro(host); 168766fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 168866fd8ad5SAdrian Hunter return ret; 168966fd8ad5SAdrian Hunter } 1690f75979b7SPierre Ossman 169166fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 169266fd8ad5SAdrian Hunter { 1693be138554SRussell King if (!(host->flags & SDHCI_DEVICE_DEAD)) { 169466fd8ad5SAdrian Hunter if (enable) 1695b537f94cSRussell King host->ier |= SDHCI_INT_CARD_INT; 16967260cf5eSAnton Vorontsov else 1697b537f94cSRussell King host->ier &= ~SDHCI_INT_CARD_INT; 1698b537f94cSRussell King 1699b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1700b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1701f75979b7SPierre Ossman mmiowb(); 170266fd8ad5SAdrian Hunter } 1703ef104333SRussell King } 1704f75979b7SPierre Ossman 170566fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 170666fd8ad5SAdrian Hunter { 170766fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 170866fd8ad5SAdrian Hunter unsigned long flags; 170966fd8ad5SAdrian Hunter 1710ef104333SRussell King sdhci_runtime_pm_get(host); 1711ef104333SRussell King 171266fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 1713ef104333SRussell King if (enable) 1714ef104333SRussell King host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1715ef104333SRussell King else 1716ef104333SRussell King host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1717ef104333SRussell King 171866fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, enable); 1719f75979b7SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 1720ef104333SRussell King 1721ef104333SRussell King sdhci_runtime_pm_put(host); 1722f75979b7SPierre Ossman } 1723f75979b7SPierre Ossman 172420b92a30SKevin Liu static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 172521f5998fSFabio Estevam struct mmc_ios *ios) 1726f2119df6SArindam Nath { 17273a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 172820b92a30SKevin Liu u16 ctrl; 17296231f3deSPhilip Rakity int ret; 1730f2119df6SArindam Nath 173120b92a30SKevin Liu /* 173220b92a30SKevin Liu * Signal Voltage Switching is only applicable for Host Controllers 173320b92a30SKevin Liu * v3.00 and above. 173420b92a30SKevin Liu */ 173520b92a30SKevin Liu if (host->version < SDHCI_SPEC_300) 173620b92a30SKevin Liu return 0; 173720b92a30SKevin Liu 173820b92a30SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 173920b92a30SKevin Liu 174021f5998fSFabio Estevam switch (ios->signal_voltage) { 174120b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_330: 1742f2119df6SArindam Nath /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1743f2119df6SArindam Nath ctrl &= ~SDHCI_CTRL_VDD_180; 1744f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1745f2119df6SArindam Nath 17463a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 17473a48edc4STim Kryger ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, 17483a48edc4STim Kryger 3600000); 17496231f3deSPhilip Rakity if (ret) { 17506606110dSJoe Perches pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 17516606110dSJoe Perches mmc_hostname(mmc)); 17526231f3deSPhilip Rakity return -EIO; 17536231f3deSPhilip Rakity } 17546231f3deSPhilip Rakity } 1755f2119df6SArindam Nath /* Wait for 5ms */ 1756f2119df6SArindam Nath usleep_range(5000, 5500); 1757f2119df6SArindam Nath 1758f2119df6SArindam Nath /* 3.3V regulator output should be stable within 5 ms */ 1759f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1760f2119df6SArindam Nath if (!(ctrl & SDHCI_CTRL_VDD_180)) 1761f2119df6SArindam Nath return 0; 17626231f3deSPhilip Rakity 17636606110dSJoe Perches pr_warn("%s: 3.3V regulator output did not became stable\n", 17644e743f1fSMarkus Mayer mmc_hostname(mmc)); 17656231f3deSPhilip Rakity 176620b92a30SKevin Liu return -EAGAIN; 176720b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_180: 17683a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 17693a48edc4STim Kryger ret = regulator_set_voltage(mmc->supply.vqmmc, 177020b92a30SKevin Liu 1700000, 1950000); 177120b92a30SKevin Liu if (ret) { 17726606110dSJoe Perches pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 17736606110dSJoe Perches mmc_hostname(mmc)); 1774f2119df6SArindam Nath return -EIO; 1775f2119df6SArindam Nath } 177620b92a30SKevin Liu } 17776231f3deSPhilip Rakity 1778f2119df6SArindam Nath /* 1779f2119df6SArindam Nath * Enable 1.8V Signal Enable in the Host Control2 1780f2119df6SArindam Nath * register 1781f2119df6SArindam Nath */ 1782f2119df6SArindam Nath ctrl |= SDHCI_CTRL_VDD_180; 1783f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1784f2119df6SArindam Nath 17859d967a61SVincent Yang /* Some controller need to do more when switching */ 17869d967a61SVincent Yang if (host->ops->voltage_switch) 17879d967a61SVincent Yang host->ops->voltage_switch(host); 17889d967a61SVincent Yang 178920b92a30SKevin Liu /* 1.8V regulator output should be stable within 5 ms */ 1790f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 179120b92a30SKevin Liu if (ctrl & SDHCI_CTRL_VDD_180) 1792f2119df6SArindam Nath return 0; 1793f2119df6SArindam Nath 17946606110dSJoe Perches pr_warn("%s: 1.8V regulator output did not became stable\n", 17954e743f1fSMarkus Mayer mmc_hostname(mmc)); 17966231f3deSPhilip Rakity 1797f2119df6SArindam Nath return -EAGAIN; 179820b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_120: 17993a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 18003a48edc4STim Kryger ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, 18013a48edc4STim Kryger 1300000); 180220b92a30SKevin Liu if (ret) { 18036606110dSJoe Perches pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 18046606110dSJoe Perches mmc_hostname(mmc)); 180520b92a30SKevin Liu return -EIO; 18066231f3deSPhilip Rakity } 180720b92a30SKevin Liu } 18086231f3deSPhilip Rakity return 0; 180920b92a30SKevin Liu default: 1810f2119df6SArindam Nath /* No signal voltage switch required */ 1811f2119df6SArindam Nath return 0; 1812f2119df6SArindam Nath } 181320b92a30SKevin Liu } 1814f2119df6SArindam Nath 181566fd8ad5SAdrian Hunter static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 181621f5998fSFabio Estevam struct mmc_ios *ios) 181766fd8ad5SAdrian Hunter { 181866fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 181966fd8ad5SAdrian Hunter int err; 182066fd8ad5SAdrian Hunter 182166fd8ad5SAdrian Hunter if (host->version < SDHCI_SPEC_300) 182266fd8ad5SAdrian Hunter return 0; 182366fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 182421f5998fSFabio Estevam err = sdhci_do_start_signal_voltage_switch(host, ios); 182566fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 182666fd8ad5SAdrian Hunter return err; 182766fd8ad5SAdrian Hunter } 182866fd8ad5SAdrian Hunter 182920b92a30SKevin Liu static int sdhci_card_busy(struct mmc_host *mmc) 183020b92a30SKevin Liu { 183120b92a30SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 183220b92a30SKevin Liu u32 present_state; 183320b92a30SKevin Liu 183420b92a30SKevin Liu sdhci_runtime_pm_get(host); 183520b92a30SKevin Liu /* Check whether DAT[3:0] is 0000 */ 183620b92a30SKevin Liu present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 183720b92a30SKevin Liu sdhci_runtime_pm_put(host); 183820b92a30SKevin Liu 183920b92a30SKevin Liu return !(present_state & SDHCI_DATA_LVL_MASK); 184020b92a30SKevin Liu } 184120b92a30SKevin Liu 1842b5540ce1SAdrian Hunter static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1843b5540ce1SAdrian Hunter { 1844b5540ce1SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 1845b5540ce1SAdrian Hunter unsigned long flags; 1846b5540ce1SAdrian Hunter 1847b5540ce1SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 1848b5540ce1SAdrian Hunter host->flags |= SDHCI_HS400_TUNING; 1849b5540ce1SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 1850b5540ce1SAdrian Hunter 1851b5540ce1SAdrian Hunter return 0; 1852b5540ce1SAdrian Hunter } 1853b5540ce1SAdrian Hunter 1854069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1855b513ea25SArindam Nath { 18564b6f37d3SRussell King struct sdhci_host *host = mmc_priv(mmc); 1857b513ea25SArindam Nath u16 ctrl; 1858b513ea25SArindam Nath int tuning_loop_counter = MAX_TUNING_LOOP; 1859b513ea25SArindam Nath int err = 0; 18602b35bd83SAisheng Dong unsigned long flags; 186138e40bf5SAdrian Hunter unsigned int tuning_count = 0; 1862b5540ce1SAdrian Hunter bool hs400_tuning; 1863b513ea25SArindam Nath 186466fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 18652b35bd83SAisheng Dong spin_lock_irqsave(&host->lock, flags); 1866b513ea25SArindam Nath 1867b5540ce1SAdrian Hunter hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1868b5540ce1SAdrian Hunter host->flags &= ~SDHCI_HS400_TUNING; 1869b5540ce1SAdrian Hunter 187038e40bf5SAdrian Hunter if (host->tuning_mode == SDHCI_TUNING_MODE_1) 187138e40bf5SAdrian Hunter tuning_count = host->tuning_count; 187238e40bf5SAdrian Hunter 1873b513ea25SArindam Nath /* 18749faac7b9SWeijun Yang * The Host Controller needs tuning in case of SDR104 and DDR50 18759faac7b9SWeijun Yang * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 18769faac7b9SWeijun Yang * the Capabilities register. 1877069c9f14SGirish K S * If the Host Controller supports the HS200 mode then the 1878069c9f14SGirish K S * tuning function has to be executed. 1879b513ea25SArindam Nath */ 18804b6f37d3SRussell King switch (host->timing) { 1881b5540ce1SAdrian Hunter /* HS400 tuning is done in HS200 mode */ 1882e9fb05d5SAdrian Hunter case MMC_TIMING_MMC_HS400: 1883b5540ce1SAdrian Hunter err = -EINVAL; 1884b5540ce1SAdrian Hunter goto out_unlock; 1885b5540ce1SAdrian Hunter 18864b6f37d3SRussell King case MMC_TIMING_MMC_HS200: 1887b5540ce1SAdrian Hunter /* 1888b5540ce1SAdrian Hunter * Periodic re-tuning for HS400 is not expected to be needed, so 1889b5540ce1SAdrian Hunter * disable it here. 1890b5540ce1SAdrian Hunter */ 1891b5540ce1SAdrian Hunter if (hs400_tuning) 1892b5540ce1SAdrian Hunter tuning_count = 0; 1893b5540ce1SAdrian Hunter break; 1894b5540ce1SAdrian Hunter 18954b6f37d3SRussell King case MMC_TIMING_UHS_SDR104: 18969faac7b9SWeijun Yang case MMC_TIMING_UHS_DDR50: 18974b6f37d3SRussell King break; 1898069c9f14SGirish K S 18994b6f37d3SRussell King case MMC_TIMING_UHS_SDR50: 19004b6f37d3SRussell King if (host->flags & SDHCI_SDR50_NEEDS_TUNING || 19014b6f37d3SRussell King host->flags & SDHCI_SDR104_NEEDS_TUNING) 19024b6f37d3SRussell King break; 19034b6f37d3SRussell King /* FALLTHROUGH */ 19044b6f37d3SRussell King 19054b6f37d3SRussell King default: 1906d519c863SAdrian Hunter goto out_unlock; 1907b513ea25SArindam Nath } 1908b513ea25SArindam Nath 190945251812SDong Aisheng if (host->ops->platform_execute_tuning) { 19102b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 191145251812SDong Aisheng err = host->ops->platform_execute_tuning(host, opcode); 191245251812SDong Aisheng sdhci_runtime_pm_put(host); 191345251812SDong Aisheng return err; 191445251812SDong Aisheng } 191545251812SDong Aisheng 19164b6f37d3SRussell King ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 19174b6f37d3SRussell King ctrl |= SDHCI_CTRL_EXEC_TUNING; 191867d0d04aSVincent Yang if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 191967d0d04aSVincent Yang ctrl |= SDHCI_CTRL_TUNED_CLK; 1920b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1921b513ea25SArindam Nath 1922b513ea25SArindam Nath /* 1923b513ea25SArindam Nath * As per the Host Controller spec v3.00, tuning command 1924b513ea25SArindam Nath * generates Buffer Read Ready interrupt, so enable that. 1925b513ea25SArindam Nath * 1926b513ea25SArindam Nath * Note: The spec clearly says that when tuning sequence 1927b513ea25SArindam Nath * is being performed, the controller does not generate 1928b513ea25SArindam Nath * interrupts other than Buffer Read Ready interrupt. But 1929b513ea25SArindam Nath * to make sure we don't hit a controller bug, we _only_ 1930b513ea25SArindam Nath * enable Buffer Read Ready interrupt here. 1931b513ea25SArindam Nath */ 1932b537f94cSRussell King sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1933b537f94cSRussell King sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1934b513ea25SArindam Nath 1935b513ea25SArindam Nath /* 1936b513ea25SArindam Nath * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1937b513ea25SArindam Nath * of loops reaches 40 times or a timeout of 150ms occurs. 1938b513ea25SArindam Nath */ 1939b513ea25SArindam Nath do { 1940b513ea25SArindam Nath struct mmc_command cmd = {0}; 194166fd8ad5SAdrian Hunter struct mmc_request mrq = {NULL}; 1942b513ea25SArindam Nath 1943069c9f14SGirish K S cmd.opcode = opcode; 1944b513ea25SArindam Nath cmd.arg = 0; 1945b513ea25SArindam Nath cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1946b513ea25SArindam Nath cmd.retries = 0; 1947b513ea25SArindam Nath cmd.data = NULL; 1948b513ea25SArindam Nath cmd.error = 0; 1949b513ea25SArindam Nath 19507ce45e95SAl Cooper if (tuning_loop_counter-- == 0) 19517ce45e95SAl Cooper break; 19527ce45e95SAl Cooper 1953b513ea25SArindam Nath mrq.cmd = &cmd; 1954b513ea25SArindam Nath host->mrq = &mrq; 1955b513ea25SArindam Nath 1956b513ea25SArindam Nath /* 1957b513ea25SArindam Nath * In response to CMD19, the card sends 64 bytes of tuning 1958b513ea25SArindam Nath * block to the Host Controller. So we set the block size 1959b513ea25SArindam Nath * to 64 here. 1960b513ea25SArindam Nath */ 1961069c9f14SGirish K S if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1962069c9f14SGirish K S if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1963069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1964069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1965069c9f14SGirish K S else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1966069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1967069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1968069c9f14SGirish K S } else { 1969069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1970069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1971069c9f14SGirish K S } 1972b513ea25SArindam Nath 1973b513ea25SArindam Nath /* 1974b513ea25SArindam Nath * The tuning block is sent by the card to the host controller. 1975b513ea25SArindam Nath * So we set the TRNS_READ bit in the Transfer Mode register. 1976b513ea25SArindam Nath * This also takes care of setting DMA Enable and Multi Block 1977b513ea25SArindam Nath * Select in the same register to 0. 1978b513ea25SArindam Nath */ 1979b513ea25SArindam Nath sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1980b513ea25SArindam Nath 1981b513ea25SArindam Nath sdhci_send_command(host, &cmd); 1982b513ea25SArindam Nath 1983b513ea25SArindam Nath host->cmd = NULL; 1984b513ea25SArindam Nath host->mrq = NULL; 1985b513ea25SArindam Nath 19862b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 1987b513ea25SArindam Nath /* Wait for Buffer Read Ready interrupt */ 1988b513ea25SArindam Nath wait_event_interruptible_timeout(host->buf_ready_int, 1989b513ea25SArindam Nath (host->tuning_done == 1), 1990b513ea25SArindam Nath msecs_to_jiffies(50)); 19912b35bd83SAisheng Dong spin_lock_irqsave(&host->lock, flags); 1992b513ea25SArindam Nath 1993b513ea25SArindam Nath if (!host->tuning_done) { 19942e4456f0SMarek Vasut pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); 1995b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1996b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1997b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1998b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1999b513ea25SArindam Nath 2000b513ea25SArindam Nath err = -EIO; 2001b513ea25SArindam Nath goto out; 2002b513ea25SArindam Nath } 2003b513ea25SArindam Nath 2004b513ea25SArindam Nath host->tuning_done = 0; 2005b513ea25SArindam Nath 2006b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2007197160d5SNick Sanders 2008197160d5SNick Sanders /* eMMC spec does not require a delay between tuning cycles */ 2009197160d5SNick Sanders if (opcode == MMC_SEND_TUNING_BLOCK) 2010b513ea25SArindam Nath mdelay(1); 2011b513ea25SArindam Nath } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 2012b513ea25SArindam Nath 2013b513ea25SArindam Nath /* 2014b513ea25SArindam Nath * The Host Driver has exhausted the maximum number of loops allowed, 2015b513ea25SArindam Nath * so use fixed sampling frequency. 2016b513ea25SArindam Nath */ 20177ce45e95SAl Cooper if (tuning_loop_counter < 0) { 2018b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2019b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 20207ce45e95SAl Cooper } 2021b513ea25SArindam Nath if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 20222e4456f0SMarek Vasut pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); 2023b513ea25SArindam Nath err = -EIO; 2024b513ea25SArindam Nath } 2025b513ea25SArindam Nath 2026b513ea25SArindam Nath out: 202738e40bf5SAdrian Hunter if (tuning_count) { 202866c39dfcSAdrian Hunter /* 202966c39dfcSAdrian Hunter * In case tuning fails, host controllers which support 203066c39dfcSAdrian Hunter * re-tuning can try tuning again at a later time, when the 203166c39dfcSAdrian Hunter * re-tuning timer expires. So for these controllers, we 203266c39dfcSAdrian Hunter * return 0. Since there might be other controllers who do not 203366c39dfcSAdrian Hunter * have this capability, we return error for them. 203466c39dfcSAdrian Hunter */ 203566c39dfcSAdrian Hunter err = 0; 2036cf2b5eeaSArindam Nath } 2037cf2b5eeaSArindam Nath 203866c39dfcSAdrian Hunter host->mmc->retune_period = err ? 0 : tuning_count; 2039cf2b5eeaSArindam Nath 2040b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2041b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2042d519c863SAdrian Hunter out_unlock: 20432b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 204466fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 2045b513ea25SArindam Nath 2046b513ea25SArindam Nath return err; 2047b513ea25SArindam Nath } 2048b513ea25SArindam Nath 2049cb849648SAdrian Hunter static int sdhci_select_drive_strength(struct mmc_card *card, 2050cb849648SAdrian Hunter unsigned int max_dtr, int host_drv, 2051cb849648SAdrian Hunter int card_drv, int *drv_type) 2052cb849648SAdrian Hunter { 2053cb849648SAdrian Hunter struct sdhci_host *host = mmc_priv(card->host); 2054cb849648SAdrian Hunter 2055cb849648SAdrian Hunter if (!host->ops->select_drive_strength) 2056cb849648SAdrian Hunter return 0; 2057cb849648SAdrian Hunter 2058cb849648SAdrian Hunter return host->ops->select_drive_strength(host, card, max_dtr, host_drv, 2059cb849648SAdrian Hunter card_drv, drv_type); 2060cb849648SAdrian Hunter } 206152983382SKevin Liu 206252983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 20634d55c5a1SArindam Nath { 20644d55c5a1SArindam Nath /* Host Controller v3.00 defines preset value registers */ 20654d55c5a1SArindam Nath if (host->version < SDHCI_SPEC_300) 20664d55c5a1SArindam Nath return; 20674d55c5a1SArindam Nath 20684d55c5a1SArindam Nath /* 20694d55c5a1SArindam Nath * We only enable or disable Preset Value if they are not already 20704d55c5a1SArindam Nath * enabled or disabled respectively. Otherwise, we bail out. 20714d55c5a1SArindam Nath */ 2072da91a8f9SRussell King if (host->preset_enabled != enable) { 2073da91a8f9SRussell King u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2074da91a8f9SRussell King 2075da91a8f9SRussell King if (enable) 20764d55c5a1SArindam Nath ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2077da91a8f9SRussell King else 20784d55c5a1SArindam Nath ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2079da91a8f9SRussell King 20804d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2081da91a8f9SRussell King 2082da91a8f9SRussell King if (enable) 2083da91a8f9SRussell King host->flags |= SDHCI_PV_ENABLED; 2084da91a8f9SRussell King else 208566fd8ad5SAdrian Hunter host->flags &= ~SDHCI_PV_ENABLED; 2086da91a8f9SRussell King 2087da91a8f9SRussell King host->preset_enabled = enable; 20884d55c5a1SArindam Nath } 208966fd8ad5SAdrian Hunter } 209066fd8ad5SAdrian Hunter 2091348487cbSHaibo Chen static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2092348487cbSHaibo Chen int err) 2093348487cbSHaibo Chen { 2094348487cbSHaibo Chen struct sdhci_host *host = mmc_priv(mmc); 2095348487cbSHaibo Chen struct mmc_data *data = mrq->data; 2096348487cbSHaibo Chen 2097d31911b9SHaibo Chen if (data->host_cookie == COOKIE_GIVEN || 2098d31911b9SHaibo Chen data->host_cookie == COOKIE_MAPPED) 2099348487cbSHaibo Chen dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2100348487cbSHaibo Chen data->flags & MMC_DATA_WRITE ? 2101348487cbSHaibo Chen DMA_TO_DEVICE : DMA_FROM_DEVICE); 2102771a3dc2SRussell King 2103d31911b9SHaibo Chen data->host_cookie = COOKIE_UNMAPPED; 2104348487cbSHaibo Chen } 2105348487cbSHaibo Chen 2106348487cbSHaibo Chen static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 2107348487cbSHaibo Chen bool is_first_req) 2108348487cbSHaibo Chen { 2109348487cbSHaibo Chen struct sdhci_host *host = mmc_priv(mmc); 2110348487cbSHaibo Chen 2111d31911b9SHaibo Chen mrq->data->host_cookie = COOKIE_UNMAPPED; 2112348487cbSHaibo Chen 2113348487cbSHaibo Chen if (host->flags & SDHCI_REQ_USE_DMA) 2114d31911b9SHaibo Chen sdhci_pre_dma_transfer(host, mrq->data); 2115348487cbSHaibo Chen } 2116348487cbSHaibo Chen 211771e69211SGuennadi Liakhovetski static void sdhci_card_event(struct mmc_host *mmc) 21181c6a0718SPierre Ossman { 211971e69211SGuennadi Liakhovetski struct sdhci_host *host = mmc_priv(mmc); 21201c6a0718SPierre Ossman unsigned long flags; 21212836766aSKrzysztof Kozlowski int present; 21221c6a0718SPierre Ossman 2123722e1280SChristian Daudt /* First check if client has provided their own card event */ 2124722e1280SChristian Daudt if (host->ops->card_event) 2125722e1280SChristian Daudt host->ops->card_event(host); 2126722e1280SChristian Daudt 21272836766aSKrzysztof Kozlowski present = sdhci_do_get_cd(host); 21282836766aSKrzysztof Kozlowski 21291c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 21301c6a0718SPierre Ossman 213166fd8ad5SAdrian Hunter /* Check host->mrq first in case we are runtime suspended */ 21322836766aSKrzysztof Kozlowski if (host->mrq && !present) { 2133a3c76eb9SGirish K S pr_err("%s: Card removed during transfer!\n", 21341c6a0718SPierre Ossman mmc_hostname(host->mmc)); 2135a3c76eb9SGirish K S pr_err("%s: Resetting controller.\n", 21361c6a0718SPierre Ossman mmc_hostname(host->mmc)); 21371c6a0718SPierre Ossman 213803231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 213903231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 21401c6a0718SPierre Ossman 214117b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 21421c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 21431c6a0718SPierre Ossman } 21441c6a0718SPierre Ossman 21451c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 214671e69211SGuennadi Liakhovetski } 214771e69211SGuennadi Liakhovetski 214871e69211SGuennadi Liakhovetski static const struct mmc_host_ops sdhci_ops = { 214971e69211SGuennadi Liakhovetski .request = sdhci_request, 2150348487cbSHaibo Chen .post_req = sdhci_post_req, 2151348487cbSHaibo Chen .pre_req = sdhci_pre_req, 215271e69211SGuennadi Liakhovetski .set_ios = sdhci_set_ios, 215394144a46SKevin Liu .get_cd = sdhci_get_cd, 215471e69211SGuennadi Liakhovetski .get_ro = sdhci_get_ro, 215571e69211SGuennadi Liakhovetski .hw_reset = sdhci_hw_reset, 215671e69211SGuennadi Liakhovetski .enable_sdio_irq = sdhci_enable_sdio_irq, 215771e69211SGuennadi Liakhovetski .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2158b5540ce1SAdrian Hunter .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 215971e69211SGuennadi Liakhovetski .execute_tuning = sdhci_execute_tuning, 2160cb849648SAdrian Hunter .select_drive_strength = sdhci_select_drive_strength, 216171e69211SGuennadi Liakhovetski .card_event = sdhci_card_event, 216220b92a30SKevin Liu .card_busy = sdhci_card_busy, 216371e69211SGuennadi Liakhovetski }; 216471e69211SGuennadi Liakhovetski 216571e69211SGuennadi Liakhovetski /*****************************************************************************\ 216671e69211SGuennadi Liakhovetski * * 216771e69211SGuennadi Liakhovetski * Tasklets * 216871e69211SGuennadi Liakhovetski * * 216971e69211SGuennadi Liakhovetski \*****************************************************************************/ 217071e69211SGuennadi Liakhovetski 21711c6a0718SPierre Ossman static void sdhci_tasklet_finish(unsigned long param) 21721c6a0718SPierre Ossman { 21731c6a0718SPierre Ossman struct sdhci_host *host; 21741c6a0718SPierre Ossman unsigned long flags; 21751c6a0718SPierre Ossman struct mmc_request *mrq; 21761c6a0718SPierre Ossman 21771c6a0718SPierre Ossman host = (struct sdhci_host*)param; 21781c6a0718SPierre Ossman 217966fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 218066fd8ad5SAdrian Hunter 21810c9c99a7SChris Ball /* 21820c9c99a7SChris Ball * If this tasklet gets rescheduled while running, it will 21830c9c99a7SChris Ball * be run again afterwards but without any active request. 21840c9c99a7SChris Ball */ 218566fd8ad5SAdrian Hunter if (!host->mrq) { 218666fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 21870c9c99a7SChris Ball return; 218866fd8ad5SAdrian Hunter } 21891c6a0718SPierre Ossman 21901c6a0718SPierre Ossman del_timer(&host->timer); 21911c6a0718SPierre Ossman 21921c6a0718SPierre Ossman mrq = host->mrq; 21931c6a0718SPierre Ossman 21941c6a0718SPierre Ossman /* 2195054cedffSRussell King * Always unmap the data buffers if they were mapped by 2196054cedffSRussell King * sdhci_prepare_data() whenever we finish with a request. 2197054cedffSRussell King * This avoids leaking DMA mappings on error. 2198054cedffSRussell King */ 2199054cedffSRussell King if (host->flags & SDHCI_REQ_USE_DMA) { 2200054cedffSRussell King struct mmc_data *data = mrq->data; 2201054cedffSRussell King 2202054cedffSRussell King if (data && data->host_cookie == COOKIE_MAPPED) { 2203054cedffSRussell King dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2204054cedffSRussell King (data->flags & MMC_DATA_READ) ? 2205054cedffSRussell King DMA_FROM_DEVICE : DMA_TO_DEVICE); 2206054cedffSRussell King data->host_cookie = COOKIE_UNMAPPED; 2207054cedffSRussell King } 2208054cedffSRussell King } 2209054cedffSRussell King 2210054cedffSRussell King /* 22111c6a0718SPierre Ossman * The controller needs a reset of internal state machines 22121c6a0718SPierre Ossman * upon error conditions. 22131c6a0718SPierre Ossman */ 22141e72859eSPierre Ossman if (!(host->flags & SDHCI_DEVICE_DEAD) && 2215b7b4d342SBen Dooks ((mrq->cmd && mrq->cmd->error) || 2216fce9d33fSAndrew Gabbasov (mrq->sbc && mrq->sbc->error) || 2217fce9d33fSAndrew Gabbasov (mrq->data && ((mrq->data->error && !mrq->data->stop) || 221884c46a53SPierre Ossman (mrq->data->stop && mrq->data->stop->error))) || 22191e72859eSPierre Ossman (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 22201c6a0718SPierre Ossman 22211c6a0718SPierre Ossman /* Some controllers need this kick or reset won't work here */ 22228213af3bSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 22231c6a0718SPierre Ossman /* This is to force an update */ 22241771059cSRussell King host->ops->set_clock(host, host->clock); 22251c6a0718SPierre Ossman 22261c6a0718SPierre Ossman /* Spec says we should do both at the same time, but Ricoh 22271c6a0718SPierre Ossman controllers do not like that. */ 222803231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 222903231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 22301c6a0718SPierre Ossman } 22311c6a0718SPierre Ossman 22321c6a0718SPierre Ossman host->mrq = NULL; 22331c6a0718SPierre Ossman host->cmd = NULL; 22341c6a0718SPierre Ossman host->data = NULL; 22351c6a0718SPierre Ossman 2236f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 22371c6a0718SPierre Ossman sdhci_deactivate_led(host); 22382f730fecSPierre Ossman #endif 22391c6a0718SPierre Ossman 22401c6a0718SPierre Ossman mmiowb(); 22411c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 22421c6a0718SPierre Ossman 22431c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 224466fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 22451c6a0718SPierre Ossman } 22461c6a0718SPierre Ossman 22471c6a0718SPierre Ossman static void sdhci_timeout_timer(unsigned long data) 22481c6a0718SPierre Ossman { 22491c6a0718SPierre Ossman struct sdhci_host *host; 22501c6a0718SPierre Ossman unsigned long flags; 22511c6a0718SPierre Ossman 22521c6a0718SPierre Ossman host = (struct sdhci_host*)data; 22531c6a0718SPierre Ossman 22541c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 22551c6a0718SPierre Ossman 22561c6a0718SPierre Ossman if (host->mrq) { 22572e4456f0SMarek Vasut pr_err("%s: Timeout waiting for hardware interrupt.\n", 22582e4456f0SMarek Vasut mmc_hostname(host->mmc)); 22591c6a0718SPierre Ossman sdhci_dumpregs(host); 22601c6a0718SPierre Ossman 22611c6a0718SPierre Ossman if (host->data) { 226217b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 22631c6a0718SPierre Ossman sdhci_finish_data(host); 22641c6a0718SPierre Ossman } else { 22651c6a0718SPierre Ossman if (host->cmd) 226617b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 22671c6a0718SPierre Ossman else 226817b0429dSPierre Ossman host->mrq->cmd->error = -ETIMEDOUT; 22691c6a0718SPierre Ossman 22701c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 22711c6a0718SPierre Ossman } 22721c6a0718SPierre Ossman } 22731c6a0718SPierre Ossman 22741c6a0718SPierre Ossman mmiowb(); 22751c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 22761c6a0718SPierre Ossman } 22771c6a0718SPierre Ossman 22781c6a0718SPierre Ossman /*****************************************************************************\ 22791c6a0718SPierre Ossman * * 22801c6a0718SPierre Ossman * Interrupt handling * 22811c6a0718SPierre Ossman * * 22821c6a0718SPierre Ossman \*****************************************************************************/ 22831c6a0718SPierre Ossman 228461541397SAdrian Hunter static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 22851c6a0718SPierre Ossman { 22861c6a0718SPierre Ossman BUG_ON(intmask == 0); 22871c6a0718SPierre Ossman 22881c6a0718SPierre Ossman if (!host->cmd) { 22892e4456f0SMarek Vasut pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2290b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 22911c6a0718SPierre Ossman sdhci_dumpregs(host); 22921c6a0718SPierre Ossman return; 22931c6a0718SPierre Ossman } 22941c6a0718SPierre Ossman 2295ec014cbaSRussell King if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2296ec014cbaSRussell King SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 22971c6a0718SPierre Ossman if (intmask & SDHCI_INT_TIMEOUT) 229817b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 2299ec014cbaSRussell King else 230017b0429dSPierre Ossman host->cmd->error = -EILSEQ; 23011c6a0718SPierre Ossman 230271fcbda0SRussell King /* 230371fcbda0SRussell King * If this command initiates a data phase and a response 230471fcbda0SRussell King * CRC error is signalled, the card can start transferring 230571fcbda0SRussell King * data - the card may have received the command without 230671fcbda0SRussell King * error. We must not terminate the mmc_request early. 230771fcbda0SRussell King * 230871fcbda0SRussell King * If the card did not receive the command or returned an 230971fcbda0SRussell King * error which prevented it sending data, the data phase 231071fcbda0SRussell King * will time out. 231171fcbda0SRussell King */ 231271fcbda0SRussell King if (host->cmd->data && 231371fcbda0SRussell King (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 231471fcbda0SRussell King SDHCI_INT_CRC) { 231571fcbda0SRussell King host->cmd = NULL; 231671fcbda0SRussell King return; 231771fcbda0SRussell King } 231871fcbda0SRussell King 23191c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 2320e809517fSPierre Ossman return; 2321e809517fSPierre Ossman } 2322e809517fSPierre Ossman 2323e809517fSPierre Ossman /* 2324e809517fSPierre Ossman * The host can send and interrupt when the busy state has 2325e809517fSPierre Ossman * ended, allowing us to wait without wasting CPU cycles. 2326e809517fSPierre Ossman * Unfortunately this is overloaded on the "data complete" 2327e809517fSPierre Ossman * interrupt, so we need to take some care when handling 2328e809517fSPierre Ossman * it. 2329e809517fSPierre Ossman * 2330e809517fSPierre Ossman * Note: The 1.0 specification is a bit ambiguous about this 2331e809517fSPierre Ossman * feature so there might be some problems with older 2332e809517fSPierre Ossman * controllers. 2333e809517fSPierre Ossman */ 2334e809517fSPierre Ossman if (host->cmd->flags & MMC_RSP_BUSY) { 2335e809517fSPierre Ossman if (host->cmd->data) 23362e4456f0SMarek Vasut DBG("Cannot wait for busy signal when also doing a data transfer"); 2337e99783a4SChanho Min else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) 2338e99783a4SChanho Min && !host->busy_handle) { 2339e99783a4SChanho Min /* Mark that command complete before busy is ended */ 2340e99783a4SChanho Min host->busy_handle = 1; 2341e809517fSPierre Ossman return; 2342e99783a4SChanho Min } 2343f945405cSBen Dooks 2344f945405cSBen Dooks /* The controller does not support the end-of-busy IRQ, 2345f945405cSBen Dooks * fall through and take the SDHCI_INT_RESPONSE */ 234661541397SAdrian Hunter } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 234761541397SAdrian Hunter host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { 234861541397SAdrian Hunter *mask &= ~SDHCI_INT_DATA_END; 2349e809517fSPierre Ossman } 2350e809517fSPierre Ossman 2351e809517fSPierre Ossman if (intmask & SDHCI_INT_RESPONSE) 235243b58b36SPierre Ossman sdhci_finish_command(host); 23531c6a0718SPierre Ossman } 23541c6a0718SPierre Ossman 23550957c333SGeorge G. Davis #ifdef CONFIG_MMC_DEBUG 235608621b18SAdrian Hunter static void sdhci_adma_show_error(struct sdhci_host *host) 23576882a8c0SBen Dooks { 23586882a8c0SBen Dooks const char *name = mmc_hostname(host->mmc); 23591c3d5f6dSAdrian Hunter void *desc = host->adma_table; 23606882a8c0SBen Dooks 23616882a8c0SBen Dooks sdhci_dumpregs(host); 23626882a8c0SBen Dooks 23636882a8c0SBen Dooks while (true) { 2364e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 23656882a8c0SBen Dooks 2366e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 2367e57a5f61SAdrian Hunter DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2368e57a5f61SAdrian Hunter name, desc, le32_to_cpu(dma_desc->addr_hi), 2369e57a5f61SAdrian Hunter le32_to_cpu(dma_desc->addr_lo), 2370e57a5f61SAdrian Hunter le16_to_cpu(dma_desc->len), 2371e57a5f61SAdrian Hunter le16_to_cpu(dma_desc->cmd)); 2372e57a5f61SAdrian Hunter else 23736882a8c0SBen Dooks DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2374e57a5f61SAdrian Hunter name, desc, le32_to_cpu(dma_desc->addr_lo), 23750545230fSAdrian Hunter le16_to_cpu(dma_desc->len), 23760545230fSAdrian Hunter le16_to_cpu(dma_desc->cmd)); 23776882a8c0SBen Dooks 237876fe379aSAdrian Hunter desc += host->desc_sz; 23796882a8c0SBen Dooks 23800545230fSAdrian Hunter if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 23816882a8c0SBen Dooks break; 23826882a8c0SBen Dooks } 23836882a8c0SBen Dooks } 23846882a8c0SBen Dooks #else 238508621b18SAdrian Hunter static void sdhci_adma_show_error(struct sdhci_host *host) { } 23866882a8c0SBen Dooks #endif 23876882a8c0SBen Dooks 23881c6a0718SPierre Ossman static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 23891c6a0718SPierre Ossman { 2390069c9f14SGirish K S u32 command; 23911c6a0718SPierre Ossman BUG_ON(intmask == 0); 23921c6a0718SPierre Ossman 2393b513ea25SArindam Nath /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2394b513ea25SArindam Nath if (intmask & SDHCI_INT_DATA_AVAIL) { 2395069c9f14SGirish K S command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2396069c9f14SGirish K S if (command == MMC_SEND_TUNING_BLOCK || 2397069c9f14SGirish K S command == MMC_SEND_TUNING_BLOCK_HS200) { 2398b513ea25SArindam Nath host->tuning_done = 1; 2399b513ea25SArindam Nath wake_up(&host->buf_ready_int); 2400b513ea25SArindam Nath return; 2401b513ea25SArindam Nath } 2402b513ea25SArindam Nath } 2403b513ea25SArindam Nath 24041c6a0718SPierre Ossman if (!host->data) { 24051c6a0718SPierre Ossman /* 2406e809517fSPierre Ossman * The "data complete" interrupt is also used to 2407e809517fSPierre Ossman * indicate that a busy state has ended. See comment 2408e809517fSPierre Ossman * above in sdhci_cmd_irq(). 24091c6a0718SPierre Ossman */ 2410e809517fSPierre Ossman if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2411c5abd5e8SMatthieu CASTET if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2412c5abd5e8SMatthieu CASTET host->cmd->error = -ETIMEDOUT; 2413c5abd5e8SMatthieu CASTET tasklet_schedule(&host->finish_tasklet); 2414c5abd5e8SMatthieu CASTET return; 2415c5abd5e8SMatthieu CASTET } 2416e809517fSPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2417e99783a4SChanho Min /* 2418e99783a4SChanho Min * Some cards handle busy-end interrupt 2419e99783a4SChanho Min * before the command completed, so make 2420e99783a4SChanho Min * sure we do things in the proper order. 2421e99783a4SChanho Min */ 2422e99783a4SChanho Min if (host->busy_handle) 2423e809517fSPierre Ossman sdhci_finish_command(host); 2424e99783a4SChanho Min else 2425e99783a4SChanho Min host->busy_handle = 1; 24261c6a0718SPierre Ossman return; 2427e809517fSPierre Ossman } 2428e809517fSPierre Ossman } 24291c6a0718SPierre Ossman 24302e4456f0SMarek Vasut pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2431b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 24321c6a0718SPierre Ossman sdhci_dumpregs(host); 24331c6a0718SPierre Ossman 24341c6a0718SPierre Ossman return; 24351c6a0718SPierre Ossman } 24361c6a0718SPierre Ossman 24371c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_TIMEOUT) 243817b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 243922113efdSAries Lee else if (intmask & SDHCI_INT_DATA_END_BIT) 244022113efdSAries Lee host->data->error = -EILSEQ; 244122113efdSAries Lee else if ((intmask & SDHCI_INT_DATA_CRC) && 244222113efdSAries Lee SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 244322113efdSAries Lee != MMC_BUS_TEST_R) 244417b0429dSPierre Ossman host->data->error = -EILSEQ; 24456882a8c0SBen Dooks else if (intmask & SDHCI_INT_ADMA_ERROR) { 2446a3c76eb9SGirish K S pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 244708621b18SAdrian Hunter sdhci_adma_show_error(host); 24482134a922SPierre Ossman host->data->error = -EIO; 2449a4071fbbSHaijun Zhang if (host->ops->adma_workaround) 2450a4071fbbSHaijun Zhang host->ops->adma_workaround(host, intmask); 24516882a8c0SBen Dooks } 24521c6a0718SPierre Ossman 245317b0429dSPierre Ossman if (host->data->error) 24541c6a0718SPierre Ossman sdhci_finish_data(host); 24551c6a0718SPierre Ossman else { 24561c6a0718SPierre Ossman if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 24571c6a0718SPierre Ossman sdhci_transfer_pio(host); 24581c6a0718SPierre Ossman 24596ba736a1SPierre Ossman /* 24606ba736a1SPierre Ossman * We currently don't do anything fancy with DMA 24616ba736a1SPierre Ossman * boundaries, but as we can't disable the feature 24626ba736a1SPierre Ossman * we need to at least restart the transfer. 2463f6a03cbfSMikko Vinni * 2464f6a03cbfSMikko Vinni * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2465f6a03cbfSMikko Vinni * should return a valid address to continue from, but as 2466f6a03cbfSMikko Vinni * some controllers are faulty, don't trust them. 24676ba736a1SPierre Ossman */ 2468f6a03cbfSMikko Vinni if (intmask & SDHCI_INT_DMA_END) { 2469f6a03cbfSMikko Vinni u32 dmastart, dmanow; 2470f6a03cbfSMikko Vinni dmastart = sg_dma_address(host->data->sg); 2471f6a03cbfSMikko Vinni dmanow = dmastart + host->data->bytes_xfered; 2472f6a03cbfSMikko Vinni /* 2473f6a03cbfSMikko Vinni * Force update to the next DMA block boundary. 2474f6a03cbfSMikko Vinni */ 2475f6a03cbfSMikko Vinni dmanow = (dmanow & 2476f6a03cbfSMikko Vinni ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2477f6a03cbfSMikko Vinni SDHCI_DEFAULT_BOUNDARY_SIZE; 2478f6a03cbfSMikko Vinni host->data->bytes_xfered = dmanow - dmastart; 2479f6a03cbfSMikko Vinni DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2480f6a03cbfSMikko Vinni " next 0x%08x\n", 2481f6a03cbfSMikko Vinni mmc_hostname(host->mmc), dmastart, 2482f6a03cbfSMikko Vinni host->data->bytes_xfered, dmanow); 2483f6a03cbfSMikko Vinni sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2484f6a03cbfSMikko Vinni } 24856ba736a1SPierre Ossman 2486e538fbe8SPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2487e538fbe8SPierre Ossman if (host->cmd) { 2488e538fbe8SPierre Ossman /* 2489e538fbe8SPierre Ossman * Data managed to finish before the 2490e538fbe8SPierre Ossman * command completed. Make sure we do 2491e538fbe8SPierre Ossman * things in the proper order. 2492e538fbe8SPierre Ossman */ 2493e538fbe8SPierre Ossman host->data_early = 1; 2494e538fbe8SPierre Ossman } else { 24951c6a0718SPierre Ossman sdhci_finish_data(host); 24961c6a0718SPierre Ossman } 24971c6a0718SPierre Ossman } 2498e538fbe8SPierre Ossman } 2499e538fbe8SPierre Ossman } 25001c6a0718SPierre Ossman 25011c6a0718SPierre Ossman static irqreturn_t sdhci_irq(int irq, void *dev_id) 25021c6a0718SPierre Ossman { 2503781e989cSRussell King irqreturn_t result = IRQ_NONE; 25041c6a0718SPierre Ossman struct sdhci_host *host = dev_id; 250541005003SRussell King u32 intmask, mask, unexpected = 0; 2506781e989cSRussell King int max_loops = 16; 25071c6a0718SPierre Ossman 25081c6a0718SPierre Ossman spin_lock(&host->lock); 25091c6a0718SPierre Ossman 2510be138554SRussell King if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 251166fd8ad5SAdrian Hunter spin_unlock(&host->lock); 2512655bca76SAdrian Hunter return IRQ_NONE; 251366fd8ad5SAdrian Hunter } 251466fd8ad5SAdrian Hunter 25154e4141a5SAnton Vorontsov intmask = sdhci_readl(host, SDHCI_INT_STATUS); 25161c6a0718SPierre Ossman if (!intmask || intmask == 0xffffffff) { 25171c6a0718SPierre Ossman result = IRQ_NONE; 25181c6a0718SPierre Ossman goto out; 25191c6a0718SPierre Ossman } 25201c6a0718SPierre Ossman 252141005003SRussell King do { 252241005003SRussell King /* Clear selected interrupts. */ 252341005003SRussell King mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 252441005003SRussell King SDHCI_INT_BUS_POWER); 252541005003SRussell King sdhci_writel(host, mask, SDHCI_INT_STATUS); 252641005003SRussell King 2527b69c9058SPierre Ossman DBG("*** %s got interrupt: 0x%08x\n", 2528b69c9058SPierre Ossman mmc_hostname(host->mmc), intmask); 25291c6a0718SPierre Ossman 25301c6a0718SPierre Ossman if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2531d25928d1SShawn Guo u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2532d25928d1SShawn Guo SDHCI_CARD_PRESENT; 2533d25928d1SShawn Guo 2534d25928d1SShawn Guo /* 253541005003SRussell King * There is a observation on i.mx esdhc. INSERT 253641005003SRussell King * bit will be immediately set again when it gets 253741005003SRussell King * cleared, if a card is inserted. We have to mask 253841005003SRussell King * the irq to prevent interrupt storm which will 253941005003SRussell King * freeze the system. And the REMOVE gets the 254041005003SRussell King * same situation. 2541d25928d1SShawn Guo * 254241005003SRussell King * More testing are needed here to ensure it works 254341005003SRussell King * for other platforms though. 2544d25928d1SShawn Guo */ 2545b537f94cSRussell King host->ier &= ~(SDHCI_INT_CARD_INSERT | 2546d25928d1SShawn Guo SDHCI_INT_CARD_REMOVE); 2547b537f94cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2548b537f94cSRussell King SDHCI_INT_CARD_INSERT; 2549b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2550b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2551d25928d1SShawn Guo 25524e4141a5SAnton Vorontsov sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 25534e4141a5SAnton Vorontsov SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 25543560db8eSRussell King 25553560db8eSRussell King host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 25563560db8eSRussell King SDHCI_INT_CARD_REMOVE); 25573560db8eSRussell King result = IRQ_WAKE_THREAD; 25581c6a0718SPierre Ossman } 25591c6a0718SPierre Ossman 256041005003SRussell King if (intmask & SDHCI_INT_CMD_MASK) 256161541397SAdrian Hunter sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, 256261541397SAdrian Hunter &intmask); 25631c6a0718SPierre Ossman 256441005003SRussell King if (intmask & SDHCI_INT_DATA_MASK) 25651c6a0718SPierre Ossman sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 25661c6a0718SPierre Ossman 256741005003SRussell King if (intmask & SDHCI_INT_BUS_POWER) 2568a3c76eb9SGirish K S pr_err("%s: Card is consuming too much power!\n", 25691c6a0718SPierre Ossman mmc_hostname(host->mmc)); 25701c6a0718SPierre Ossman 2571781e989cSRussell King if (intmask & SDHCI_INT_CARD_INT) { 2572781e989cSRussell King sdhci_enable_sdio_irq_nolock(host, false); 2573781e989cSRussell King host->thread_isr |= SDHCI_INT_CARD_INT; 2574781e989cSRussell King result = IRQ_WAKE_THREAD; 2575781e989cSRussell King } 2576f75979b7SPierre Ossman 257741005003SRussell King intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 257841005003SRussell King SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 257941005003SRussell King SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 258041005003SRussell King SDHCI_INT_CARD_INT); 2581f75979b7SPierre Ossman 25821c6a0718SPierre Ossman if (intmask) { 25836379b237SAlexander Stein unexpected |= intmask; 25844e4141a5SAnton Vorontsov sdhci_writel(host, intmask, SDHCI_INT_STATUS); 25851c6a0718SPierre Ossman } 25861c6a0718SPierre Ossman 2587781e989cSRussell King if (result == IRQ_NONE) 25881c6a0718SPierre Ossman result = IRQ_HANDLED; 25891c6a0718SPierre Ossman 25906379b237SAlexander Stein intmask = sdhci_readl(host, SDHCI_INT_STATUS); 259141005003SRussell King } while (intmask && --max_loops); 25921c6a0718SPierre Ossman out: 25931c6a0718SPierre Ossman spin_unlock(&host->lock); 25941c6a0718SPierre Ossman 25956379b237SAlexander Stein if (unexpected) { 25966379b237SAlexander Stein pr_err("%s: Unexpected interrupt 0x%08x.\n", 25976379b237SAlexander Stein mmc_hostname(host->mmc), unexpected); 25986379b237SAlexander Stein sdhci_dumpregs(host); 25996379b237SAlexander Stein } 2600f75979b7SPierre Ossman 26011c6a0718SPierre Ossman return result; 26021c6a0718SPierre Ossman } 26031c6a0718SPierre Ossman 2604781e989cSRussell King static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2605781e989cSRussell King { 2606781e989cSRussell King struct sdhci_host *host = dev_id; 2607781e989cSRussell King unsigned long flags; 2608781e989cSRussell King u32 isr; 2609781e989cSRussell King 2610781e989cSRussell King spin_lock_irqsave(&host->lock, flags); 2611781e989cSRussell King isr = host->thread_isr; 2612781e989cSRussell King host->thread_isr = 0; 2613781e989cSRussell King spin_unlock_irqrestore(&host->lock, flags); 2614781e989cSRussell King 26153560db8eSRussell King if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 26163560db8eSRussell King sdhci_card_event(host->mmc); 26173560db8eSRussell King mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 26183560db8eSRussell King } 26193560db8eSRussell King 2620781e989cSRussell King if (isr & SDHCI_INT_CARD_INT) { 2621781e989cSRussell King sdio_run_irqs(host->mmc); 2622781e989cSRussell King 2623781e989cSRussell King spin_lock_irqsave(&host->lock, flags); 2624781e989cSRussell King if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2625781e989cSRussell King sdhci_enable_sdio_irq_nolock(host, true); 2626781e989cSRussell King spin_unlock_irqrestore(&host->lock, flags); 2627781e989cSRussell King } 2628781e989cSRussell King 2629781e989cSRussell King return isr ? IRQ_HANDLED : IRQ_NONE; 2630781e989cSRussell King } 2631781e989cSRussell King 26321c6a0718SPierre Ossman /*****************************************************************************\ 26331c6a0718SPierre Ossman * * 26341c6a0718SPierre Ossman * Suspend/resume * 26351c6a0718SPierre Ossman * * 26361c6a0718SPierre Ossman \*****************************************************************************/ 26371c6a0718SPierre Ossman 26381c6a0718SPierre Ossman #ifdef CONFIG_PM 2639ad080d79SKevin Liu void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2640ad080d79SKevin Liu { 2641ad080d79SKevin Liu u8 val; 2642ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2643ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2644ad080d79SKevin Liu 2645ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2646ad080d79SKevin Liu val |= mask ; 2647ad080d79SKevin Liu /* Avoid fake wake up */ 2648ad080d79SKevin Liu if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2649ad080d79SKevin Liu val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2650ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2651ad080d79SKevin Liu } 2652ad080d79SKevin Liu EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2653ad080d79SKevin Liu 26540b10f478SFabio Estevam static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2655ad080d79SKevin Liu { 2656ad080d79SKevin Liu u8 val; 2657ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2658ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2659ad080d79SKevin Liu 2660ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2661ad080d79SKevin Liu val &= ~mask; 2662ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2663ad080d79SKevin Liu } 26641c6a0718SPierre Ossman 266529495aa0SManuel Lauss int sdhci_suspend_host(struct sdhci_host *host) 26661c6a0718SPierre Ossman { 26677260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 26687260cf5eSAnton Vorontsov 266966c39dfcSAdrian Hunter mmc_retune_timer_stop(host->mmc); 267066c39dfcSAdrian Hunter mmc_retune_needed(host->mmc); 2671cf2b5eeaSArindam Nath 2672ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2673b537f94cSRussell King host->ier = 0; 2674b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2675b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2676b8c86fc5SPierre Ossman free_irq(host->irq, host); 2677ad080d79SKevin Liu } else { 2678ad080d79SKevin Liu sdhci_enable_irq_wakeups(host); 2679ad080d79SKevin Liu enable_irq_wake(host->irq); 2680ad080d79SKevin Liu } 26814ee14ec6SUlf Hansson return 0; 2682b8c86fc5SPierre Ossman } 2683b8c86fc5SPierre Ossman 2684b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2685b8c86fc5SPierre Ossman 2686b8c86fc5SPierre Ossman int sdhci_resume_host(struct sdhci_host *host) 2687b8c86fc5SPierre Ossman { 26884ee14ec6SUlf Hansson int ret = 0; 2689b8c86fc5SPierre Ossman 2690a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2691b8c86fc5SPierre Ossman if (host->ops->enable_dma) 2692b8c86fc5SPierre Ossman host->ops->enable_dma(host); 2693b8c86fc5SPierre Ossman } 2694b8c86fc5SPierre Ossman 26956308d290SAdrian Hunter if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 26966308d290SAdrian Hunter (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 26976308d290SAdrian Hunter /* Card keeps power but host controller does not */ 26986308d290SAdrian Hunter sdhci_init(host, 0); 26996308d290SAdrian Hunter host->pwr = 0; 27006308d290SAdrian Hunter host->clock = 0; 27016308d290SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 27026308d290SAdrian Hunter } else { 27032f4cbb3dSNicolas Pitre sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 27041c6a0718SPierre Ossman mmiowb(); 27056308d290SAdrian Hunter } 2706b8c86fc5SPierre Ossman 270714a7b416SHaibo Chen if (!device_may_wakeup(mmc_dev(host->mmc))) { 270814a7b416SHaibo Chen ret = request_threaded_irq(host->irq, sdhci_irq, 270914a7b416SHaibo Chen sdhci_thread_irq, IRQF_SHARED, 271014a7b416SHaibo Chen mmc_hostname(host->mmc), host); 271114a7b416SHaibo Chen if (ret) 271214a7b416SHaibo Chen return ret; 271314a7b416SHaibo Chen } else { 271414a7b416SHaibo Chen sdhci_disable_irq_wakeups(host); 271514a7b416SHaibo Chen disable_irq_wake(host->irq); 271614a7b416SHaibo Chen } 271714a7b416SHaibo Chen 27187260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 27197260cf5eSAnton Vorontsov 27202f4cbb3dSNicolas Pitre return ret; 27211c6a0718SPierre Ossman } 27221c6a0718SPierre Ossman 2723b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_resume_host); 272466fd8ad5SAdrian Hunter 272566fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host) 272666fd8ad5SAdrian Hunter { 272766fd8ad5SAdrian Hunter return pm_runtime_get_sync(host->mmc->parent); 272866fd8ad5SAdrian Hunter } 272966fd8ad5SAdrian Hunter 273066fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host) 273166fd8ad5SAdrian Hunter { 273266fd8ad5SAdrian Hunter pm_runtime_mark_last_busy(host->mmc->parent); 273366fd8ad5SAdrian Hunter return pm_runtime_put_autosuspend(host->mmc->parent); 273466fd8ad5SAdrian Hunter } 273566fd8ad5SAdrian Hunter 2736f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2737f0710a55SAdrian Hunter { 27385c671c41SAdrian Hunter if (host->bus_on) 2739f0710a55SAdrian Hunter return; 2740f0710a55SAdrian Hunter host->bus_on = true; 2741f0710a55SAdrian Hunter pm_runtime_get_noresume(host->mmc->parent); 2742f0710a55SAdrian Hunter } 2743f0710a55SAdrian Hunter 2744f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2745f0710a55SAdrian Hunter { 27465c671c41SAdrian Hunter if (!host->bus_on) 2747f0710a55SAdrian Hunter return; 2748f0710a55SAdrian Hunter host->bus_on = false; 2749f0710a55SAdrian Hunter pm_runtime_put_noidle(host->mmc->parent); 2750f0710a55SAdrian Hunter } 2751f0710a55SAdrian Hunter 275266fd8ad5SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host) 275366fd8ad5SAdrian Hunter { 275466fd8ad5SAdrian Hunter unsigned long flags; 275566fd8ad5SAdrian Hunter 275666c39dfcSAdrian Hunter mmc_retune_timer_stop(host->mmc); 275766c39dfcSAdrian Hunter mmc_retune_needed(host->mmc); 275866fd8ad5SAdrian Hunter 275966fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2760b537f94cSRussell King host->ier &= SDHCI_INT_CARD_INT; 2761b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2762b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 276366fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 276466fd8ad5SAdrian Hunter 2765781e989cSRussell King synchronize_hardirq(host->irq); 276666fd8ad5SAdrian Hunter 276766fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 276866fd8ad5SAdrian Hunter host->runtime_suspended = true; 276966fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 277066fd8ad5SAdrian Hunter 27718a125badSMarkus Pargmann return 0; 277266fd8ad5SAdrian Hunter } 277366fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 277466fd8ad5SAdrian Hunter 277566fd8ad5SAdrian Hunter int sdhci_runtime_resume_host(struct sdhci_host *host) 277666fd8ad5SAdrian Hunter { 277766fd8ad5SAdrian Hunter unsigned long flags; 27788a125badSMarkus Pargmann int host_flags = host->flags; 277966fd8ad5SAdrian Hunter 278066fd8ad5SAdrian Hunter if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 278166fd8ad5SAdrian Hunter if (host->ops->enable_dma) 278266fd8ad5SAdrian Hunter host->ops->enable_dma(host); 278366fd8ad5SAdrian Hunter } 278466fd8ad5SAdrian Hunter 278566fd8ad5SAdrian Hunter sdhci_init(host, 0); 278666fd8ad5SAdrian Hunter 278766fd8ad5SAdrian Hunter /* Force clock and power re-program */ 278866fd8ad5SAdrian Hunter host->pwr = 0; 278966fd8ad5SAdrian Hunter host->clock = 0; 27903396e736SJisheng Zhang sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 279166fd8ad5SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 279266fd8ad5SAdrian Hunter 279352983382SKevin Liu if ((host_flags & SDHCI_PV_ENABLED) && 279452983382SKevin Liu !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 279552983382SKevin Liu spin_lock_irqsave(&host->lock, flags); 279652983382SKevin Liu sdhci_enable_preset_value(host, true); 279752983382SKevin Liu spin_unlock_irqrestore(&host->lock, flags); 279852983382SKevin Liu } 279966fd8ad5SAdrian Hunter 280066fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 280166fd8ad5SAdrian Hunter 280266fd8ad5SAdrian Hunter host->runtime_suspended = false; 280366fd8ad5SAdrian Hunter 280466fd8ad5SAdrian Hunter /* Enable SDIO IRQ */ 2805ef104333SRussell King if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 280666fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 280766fd8ad5SAdrian Hunter 280866fd8ad5SAdrian Hunter /* Enable Card Detection */ 280966fd8ad5SAdrian Hunter sdhci_enable_card_detection(host); 281066fd8ad5SAdrian Hunter 281166fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 281266fd8ad5SAdrian Hunter 28138a125badSMarkus Pargmann return 0; 281466fd8ad5SAdrian Hunter } 281566fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 281666fd8ad5SAdrian Hunter 2817162d6f98SRafael J. Wysocki #endif /* CONFIG_PM */ 281866fd8ad5SAdrian Hunter 28191c6a0718SPierre Ossman /*****************************************************************************\ 28201c6a0718SPierre Ossman * * 2821b8c86fc5SPierre Ossman * Device allocation/registration * 28221c6a0718SPierre Ossman * * 28231c6a0718SPierre Ossman \*****************************************************************************/ 28241c6a0718SPierre Ossman 2825b8c86fc5SPierre Ossman struct sdhci_host *sdhci_alloc_host(struct device *dev, 2826b8c86fc5SPierre Ossman size_t priv_size) 28271c6a0718SPierre Ossman { 28281c6a0718SPierre Ossman struct mmc_host *mmc; 28291c6a0718SPierre Ossman struct sdhci_host *host; 28301c6a0718SPierre Ossman 2831b8c86fc5SPierre Ossman WARN_ON(dev == NULL); 28321c6a0718SPierre Ossman 2833b8c86fc5SPierre Ossman mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 28341c6a0718SPierre Ossman if (!mmc) 2835b8c86fc5SPierre Ossman return ERR_PTR(-ENOMEM); 28361c6a0718SPierre Ossman 28371c6a0718SPierre Ossman host = mmc_priv(mmc); 28381c6a0718SPierre Ossman host->mmc = mmc; 2839bf60e592SAdrian Hunter host->mmc_host_ops = sdhci_ops; 2840bf60e592SAdrian Hunter mmc->ops = &host->mmc_host_ops; 28411c6a0718SPierre Ossman 2842b8c86fc5SPierre Ossman return host; 28431c6a0718SPierre Ossman } 28441c6a0718SPierre Ossman 2845b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2846b8c86fc5SPierre Ossman 2847b8c86fc5SPierre Ossman int sdhci_add_host(struct sdhci_host *host) 2848b8c86fc5SPierre Ossman { 2849b8c86fc5SPierre Ossman struct mmc_host *mmc; 2850bd6a8c30SPhilip Rakity u32 caps[2] = {0, 0}; 2851f2119df6SArindam Nath u32 max_current_caps; 2852f2119df6SArindam Nath unsigned int ocr_avail; 2853f5fa92e5SAdrian Hunter unsigned int override_timeout_clk; 285459241757SDong Aisheng u32 max_clk; 2855b8c86fc5SPierre Ossman int ret; 2856b8c86fc5SPierre Ossman 2857b8c86fc5SPierre Ossman WARN_ON(host == NULL); 2858b8c86fc5SPierre Ossman if (host == NULL) 2859b8c86fc5SPierre Ossman return -EINVAL; 2860b8c86fc5SPierre Ossman 2861b8c86fc5SPierre Ossman mmc = host->mmc; 2862b8c86fc5SPierre Ossman 2863b8c86fc5SPierre Ossman if (debug_quirks) 2864b8c86fc5SPierre Ossman host->quirks = debug_quirks; 286566fd8ad5SAdrian Hunter if (debug_quirks2) 286666fd8ad5SAdrian Hunter host->quirks2 = debug_quirks2; 2867b8c86fc5SPierre Ossman 2868f5fa92e5SAdrian Hunter override_timeout_clk = host->timeout_clk; 2869f5fa92e5SAdrian Hunter 287003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 28711c6a0718SPierre Ossman 28724e4141a5SAnton Vorontsov host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 28732134a922SPierre Ossman host->version = (host->version & SDHCI_SPEC_VER_MASK) 28742134a922SPierre Ossman >> SDHCI_SPEC_VER_SHIFT; 287585105c53SZhangfei Gao if (host->version > SDHCI_SPEC_300) { 28762e4456f0SMarek Vasut pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 28772e4456f0SMarek Vasut mmc_hostname(mmc), host->version); 28781c6a0718SPierre Ossman } 28791c6a0718SPierre Ossman 2880f2119df6SArindam Nath caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2881ccc92c23SMaxim Levitsky sdhci_readl(host, SDHCI_CAPABILITIES); 28821c6a0718SPierre Ossman 2883bd6a8c30SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 2884bd6a8c30SPhilip Rakity caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2885bd6a8c30SPhilip Rakity host->caps1 : 2886bd6a8c30SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1); 2887f2119df6SArindam Nath 2888b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2889a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 2890f2119df6SArindam Nath else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2891a13abc7bSRichard Röjfors DBG("Controller doesn't have SDMA capability\n"); 28921c6a0718SPierre Ossman else 2893a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 28941c6a0718SPierre Ossman 2895b8c86fc5SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2896a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA)) { 2897cee687ceSRolf Eike Beer DBG("Disabling DMA as it is marked broken\n"); 2898a13abc7bSRichard Röjfors host->flags &= ~SDHCI_USE_SDMA; 28997c168e3dSFeng Tang } 29007c168e3dSFeng Tang 2901f2119df6SArindam Nath if ((host->version >= SDHCI_SPEC_200) && 2902f2119df6SArindam Nath (caps[0] & SDHCI_CAN_DO_ADMA2)) 29032134a922SPierre Ossman host->flags |= SDHCI_USE_ADMA; 29042134a922SPierre Ossman 29052134a922SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 29062134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) { 29072134a922SPierre Ossman DBG("Disabling ADMA as it is marked broken\n"); 29082134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 29092134a922SPierre Ossman } 29102134a922SPierre Ossman 2911e57a5f61SAdrian Hunter /* 2912e57a5f61SAdrian Hunter * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 2913e57a5f61SAdrian Hunter * and *must* do 64-bit DMA. A driver has the opportunity to change 2914e57a5f61SAdrian Hunter * that during the first call to ->enable_dma(). Similarly 2915e57a5f61SAdrian Hunter * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 2916e57a5f61SAdrian Hunter * implement. 2917e57a5f61SAdrian Hunter */ 29185eaa7476SAl Cooper if (caps[0] & SDHCI_CAN_64BIT) 2919e57a5f61SAdrian Hunter host->flags |= SDHCI_USE_64_BIT_DMA; 2920e57a5f61SAdrian Hunter 2921a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2922b8c86fc5SPierre Ossman if (host->ops->enable_dma) { 2923b8c86fc5SPierre Ossman if (host->ops->enable_dma(host)) { 29246606110dSJoe Perches pr_warn("%s: No suitable DMA available - falling back to PIO\n", 2925b8c86fc5SPierre Ossman mmc_hostname(mmc)); 2926a13abc7bSRichard Röjfors host->flags &= 2927a13abc7bSRichard Röjfors ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 29281c6a0718SPierre Ossman } 29291c6a0718SPierre Ossman } 2930b8c86fc5SPierre Ossman } 29311c6a0718SPierre Ossman 2932e57a5f61SAdrian Hunter /* SDMA does not support 64-bit DMA */ 2933e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 2934e57a5f61SAdrian Hunter host->flags &= ~SDHCI_USE_SDMA; 2935e57a5f61SAdrian Hunter 29362134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 2937e66e61cbSRussell King dma_addr_t dma; 2938e66e61cbSRussell King void *buf; 2939e66e61cbSRussell King 29402134a922SPierre Ossman /* 294176fe379aSAdrian Hunter * The DMA descriptor table size is calculated as the maximum 294276fe379aSAdrian Hunter * number of segments times 2, to allow for an alignment 294376fe379aSAdrian Hunter * descriptor for each segment, plus 1 for a nop end descriptor, 294476fe379aSAdrian Hunter * all multipled by the descriptor size. 29452134a922SPierre Ossman */ 2946e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) { 2947e57a5f61SAdrian Hunter host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 2948e57a5f61SAdrian Hunter SDHCI_ADMA2_64_DESC_SZ; 2949e57a5f61SAdrian Hunter host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 2950e57a5f61SAdrian Hunter } else { 2951739d46dcSAdrian Hunter host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 2952739d46dcSAdrian Hunter SDHCI_ADMA2_32_DESC_SZ; 2953739d46dcSAdrian Hunter host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 2954e57a5f61SAdrian Hunter } 2955e66e61cbSRussell King 295604a5ae6fSAdrian Hunter host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 2957e66e61cbSRussell King buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + 2958e66e61cbSRussell King host->adma_table_sz, &dma, GFP_KERNEL); 2959e66e61cbSRussell King if (!buf) { 29606606110dSJoe Perches pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 29612134a922SPierre Ossman mmc_hostname(mmc)); 29622134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 2963e66e61cbSRussell King } else if ((dma + host->align_buffer_sz) & 2964e66e61cbSRussell King (SDHCI_ADMA2_DESC_ALIGN - 1)) { 29656606110dSJoe Perches pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 2966d1e49f77SRussell King mmc_hostname(mmc)); 2967d1e49f77SRussell King host->flags &= ~SDHCI_USE_ADMA; 2968e66e61cbSRussell King dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 2969e66e61cbSRussell King host->adma_table_sz, buf, dma); 2970e66e61cbSRussell King } else { 2971e66e61cbSRussell King host->align_buffer = buf; 2972e66e61cbSRussell King host->align_addr = dma; 2973edd63fccSRussell King 2974e66e61cbSRussell King host->adma_table = buf + host->align_buffer_sz; 2975e66e61cbSRussell King host->adma_addr = dma + host->align_buffer_sz; 2976e66e61cbSRussell King } 29772134a922SPierre Ossman } 29782134a922SPierre Ossman 29797659150cSPierre Ossman /* 29807659150cSPierre Ossman * If we use DMA, then it's up to the caller to set the DMA 29817659150cSPierre Ossman * mask, but PIO does not need the hw shim so we set a new 29827659150cSPierre Ossman * mask here in that case. 29837659150cSPierre Ossman */ 2984a13abc7bSRichard Röjfors if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 29857659150cSPierre Ossman host->dma_mask = DMA_BIT_MASK(64); 29864e743f1fSMarkus Mayer mmc_dev(mmc)->dma_mask = &host->dma_mask; 29877659150cSPierre Ossman } 29881c6a0718SPierre Ossman 2989c4687d5fSZhangfei Gao if (host->version >= SDHCI_SPEC_300) 2990f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2991c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2992c4687d5fSZhangfei Gao else 2993f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2994c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2995c4687d5fSZhangfei Gao 29964240ff0aSBen Dooks host->max_clk *= 1000000; 2997f27f47efSAnton Vorontsov if (host->max_clk == 0 || host->quirks & 2998f27f47efSAnton Vorontsov SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 29994240ff0aSBen Dooks if (!host->ops->get_max_clock) { 30002e4456f0SMarek Vasut pr_err("%s: Hardware doesn't specify base clock frequency.\n", 30012e4456f0SMarek Vasut mmc_hostname(mmc)); 3002b8c86fc5SPierre Ossman return -ENODEV; 30031c6a0718SPierre Ossman } 30044240ff0aSBen Dooks host->max_clk = host->ops->get_max_clock(host); 30054240ff0aSBen Dooks } 30061c6a0718SPierre Ossman 30071c6a0718SPierre Ossman /* 3008c3ed3877SArindam Nath * In case of Host Controller v3.00, find out whether clock 3009c3ed3877SArindam Nath * multiplier is supported. 3010c3ed3877SArindam Nath */ 3011c3ed3877SArindam Nath host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 3012c3ed3877SArindam Nath SDHCI_CLOCK_MUL_SHIFT; 3013c3ed3877SArindam Nath 3014c3ed3877SArindam Nath /* 3015c3ed3877SArindam Nath * In case the value in Clock Multiplier is 0, then programmable 3016c3ed3877SArindam Nath * clock mode is not supported, otherwise the actual clock 3017c3ed3877SArindam Nath * multiplier is one more than the value of Clock Multiplier 3018c3ed3877SArindam Nath * in the Capabilities Register. 3019c3ed3877SArindam Nath */ 3020c3ed3877SArindam Nath if (host->clk_mul) 3021c3ed3877SArindam Nath host->clk_mul += 1; 3022c3ed3877SArindam Nath 3023c3ed3877SArindam Nath /* 30241c6a0718SPierre Ossman * Set host parameters. 30251c6a0718SPierre Ossman */ 302659241757SDong Aisheng max_clk = host->max_clk; 302759241757SDong Aisheng 3028ce5f036bSMarek Szyprowski if (host->ops->get_min_clock) 3029a9e58f25SAnton Vorontsov mmc->f_min = host->ops->get_min_clock(host); 3030c3ed3877SArindam Nath else if (host->version >= SDHCI_SPEC_300) { 3031c3ed3877SArindam Nath if (host->clk_mul) { 3032c3ed3877SArindam Nath mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 303359241757SDong Aisheng max_clk = host->max_clk * host->clk_mul; 3034c3ed3877SArindam Nath } else 30350397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3036c3ed3877SArindam Nath } else 30370397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 303815ec4461SPhilip Rakity 303959241757SDong Aisheng if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk))) 304059241757SDong Aisheng mmc->f_max = max_clk; 304159241757SDong Aisheng 304228aab053SAisheng Dong if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 304328aab053SAisheng Dong host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> 304428aab053SAisheng Dong SDHCI_TIMEOUT_CLK_SHIFT; 3045272308caSAndy Shevchenko if (host->timeout_clk == 0) { 3046272308caSAndy Shevchenko if (host->ops->get_timeout_clock) { 304728aab053SAisheng Dong host->timeout_clk = 304828aab053SAisheng Dong host->ops->get_timeout_clock(host); 304928aab053SAisheng Dong } else { 305028aab053SAisheng Dong pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 305128aab053SAisheng Dong mmc_hostname(mmc)); 3052272308caSAndy Shevchenko return -ENODEV; 3053272308caSAndy Shevchenko } 3054272308caSAndy Shevchenko } 305528aab053SAisheng Dong 3056272308caSAndy Shevchenko if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 3057272308caSAndy Shevchenko host->timeout_clk *= 1000; 3058272308caSAndy Shevchenko 3059a6ff5aebSAisheng Dong mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3060a6ff5aebSAisheng Dong host->ops->get_max_timeout_count(host) : 1 << 27; 3061a6ff5aebSAisheng Dong mmc->max_busy_timeout /= host->timeout_clk; 306228aab053SAisheng Dong } 306358d1246dSAdrian Hunter 3064f5fa92e5SAdrian Hunter if (override_timeout_clk) 3065f5fa92e5SAdrian Hunter host->timeout_clk = override_timeout_clk; 3066f5fa92e5SAdrian Hunter 3067e89d456fSAndrei Warkentin mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3068781e989cSRussell King mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3069e89d456fSAndrei Warkentin 3070e89d456fSAndrei Warkentin if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3071e89d456fSAndrei Warkentin host->flags |= SDHCI_AUTO_CMD12; 30725fe23c7fSAnton Vorontsov 30738edf6371SAndrei Warkentin /* Auto-CMD23 stuff only works in ADMA or PIO. */ 30744f3d3e9bSAndrei Warkentin if ((host->version >= SDHCI_SPEC_300) && 30758edf6371SAndrei Warkentin ((host->flags & SDHCI_USE_ADMA) || 30763bfa6f03SScott Branden !(host->flags & SDHCI_USE_SDMA)) && 30773bfa6f03SScott Branden !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 30788edf6371SAndrei Warkentin host->flags |= SDHCI_AUTO_CMD23; 30798edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 30808edf6371SAndrei Warkentin } else { 30818edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 30828edf6371SAndrei Warkentin } 30838edf6371SAndrei Warkentin 308415ec4461SPhilip Rakity /* 308515ec4461SPhilip Rakity * A controller may support 8-bit width, but the board itself 308615ec4461SPhilip Rakity * might not have the pins brought out. Boards that support 308715ec4461SPhilip Rakity * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 308815ec4461SPhilip Rakity * their platform code before calling sdhci_add_host(), and we 308915ec4461SPhilip Rakity * won't assume 8-bit width for hosts without that CAP. 309015ec4461SPhilip Rakity */ 30915fe23c7fSAnton Vorontsov if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 309215ec4461SPhilip Rakity mmc->caps |= MMC_CAP_4_BIT_DATA; 30931c6a0718SPierre Ossman 309463ef5d8cSJerry Huang if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 309563ef5d8cSJerry Huang mmc->caps &= ~MMC_CAP_CMD23; 309663ef5d8cSJerry Huang 3097f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_DO_HISPD) 3098a29e7e18SZhangfei Gao mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 30991c6a0718SPierre Ossman 3100176d1ed4SJaehoon Chung if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3101c31d22ebSIvan T. Ivanov !(mmc->caps & MMC_CAP_NONREMOVABLE) && 3102c31d22ebSIvan T. Ivanov IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) 310368d1fb7eSAnton Vorontsov mmc->caps |= MMC_CAP_NEEDS_POLL; 310468d1fb7eSAnton Vorontsov 31053a48edc4STim Kryger /* If there are external regulators, get them */ 31063a48edc4STim Kryger if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) 31073a48edc4STim Kryger return -EPROBE_DEFER; 31083a48edc4STim Kryger 31096231f3deSPhilip Rakity /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 31103a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 31113a48edc4STim Kryger ret = regulator_enable(mmc->supply.vqmmc); 31123a48edc4STim Kryger if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3113cec2e216SKevin Liu 1950000)) 31148363c374SKevin Liu caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 31158363c374SKevin Liu SDHCI_SUPPORT_SDR50 | 31166231f3deSPhilip Rakity SDHCI_SUPPORT_DDR50); 3117a3361abaSChris Ball if (ret) { 3118a3361abaSChris Ball pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3119a3361abaSChris Ball mmc_hostname(mmc), ret); 31204bb74313SAdrian Hunter mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3121a3361abaSChris Ball } 31228363c374SKevin Liu } 31236231f3deSPhilip Rakity 31246a66180aSDaniel Drake if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 31256a66180aSDaniel Drake caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 31266a66180aSDaniel Drake SDHCI_SUPPORT_DDR50); 31276a66180aSDaniel Drake 31284188bba0SAl Cooper /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 31294188bba0SAl Cooper if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 31304188bba0SAl Cooper SDHCI_SUPPORT_DDR50)) 3131f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3132f2119df6SArindam Nath 3133f2119df6SArindam Nath /* SDR104 supports also implies SDR50 support */ 3134156e14b1SGiuseppe CAVALLARO if (caps[1] & SDHCI_SUPPORT_SDR104) { 3135f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3136156e14b1SGiuseppe CAVALLARO /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3137156e14b1SGiuseppe CAVALLARO * field can be promoted to support HS200. 3138156e14b1SGiuseppe CAVALLARO */ 3139549c0b18SAdrian Hunter if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3140156e14b1SGiuseppe CAVALLARO mmc->caps2 |= MMC_CAP2_HS200; 3141156e14b1SGiuseppe CAVALLARO } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3142f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR50; 3143f2119df6SArindam Nath 3144e9fb05d5SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3145e9fb05d5SAdrian Hunter (caps[1] & SDHCI_SUPPORT_HS400)) 3146e9fb05d5SAdrian Hunter mmc->caps2 |= MMC_CAP2_HS400; 3147e9fb05d5SAdrian Hunter 3148549c0b18SAdrian Hunter if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3149549c0b18SAdrian Hunter (IS_ERR(mmc->supply.vqmmc) || 3150549c0b18SAdrian Hunter !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3151549c0b18SAdrian Hunter 1300000))) 3152549c0b18SAdrian Hunter mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3153549c0b18SAdrian Hunter 31549107ebbfSMicky Ching if ((caps[1] & SDHCI_SUPPORT_DDR50) && 31559107ebbfSMicky Ching !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3156f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_DDR50; 3157f2119df6SArindam Nath 3158069c9f14SGirish K S /* Does the host need tuning for SDR50? */ 3159b513ea25SArindam Nath if (caps[1] & SDHCI_USE_SDR50_TUNING) 3160b513ea25SArindam Nath host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3161b513ea25SArindam Nath 3162156e14b1SGiuseppe CAVALLARO /* Does the host need tuning for SDR104 / HS200? */ 3163069c9f14SGirish K S if (mmc->caps2 & MMC_CAP2_HS200) 3164156e14b1SGiuseppe CAVALLARO host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3165069c9f14SGirish K S 3166d6d50a15SArindam Nath /* Driver Type(s) (A, C, D) supported by the host */ 3167d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_A) 3168d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3169d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_C) 3170d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3171d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_D) 3172d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3173d6d50a15SArindam Nath 3174cf2b5eeaSArindam Nath /* Initial value for re-tuning timer count */ 3175cf2b5eeaSArindam Nath host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3176cf2b5eeaSArindam Nath SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3177cf2b5eeaSArindam Nath 3178cf2b5eeaSArindam Nath /* 3179cf2b5eeaSArindam Nath * In case Re-tuning Timer is not disabled, the actual value of 3180cf2b5eeaSArindam Nath * re-tuning timer will be 2 ^ (n - 1). 3181cf2b5eeaSArindam Nath */ 3182cf2b5eeaSArindam Nath if (host->tuning_count) 3183cf2b5eeaSArindam Nath host->tuning_count = 1 << (host->tuning_count - 1); 3184cf2b5eeaSArindam Nath 3185cf2b5eeaSArindam Nath /* Re-tuning mode supported by the Host Controller */ 3186cf2b5eeaSArindam Nath host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3187cf2b5eeaSArindam Nath SDHCI_RETUNING_MODE_SHIFT; 3188cf2b5eeaSArindam Nath 31898f230f45STakashi Iwai ocr_avail = 0; 3190bad37e1aSPhilip Rakity 3191f2119df6SArindam Nath /* 3192f2119df6SArindam Nath * According to SD Host Controller spec v3.00, if the Host System 3193f2119df6SArindam Nath * can afford more than 150mA, Host Driver should set XPC to 1. Also 3194f2119df6SArindam Nath * the value is meaningful only if Voltage Support in the Capabilities 3195f2119df6SArindam Nath * register is set. The actual current value is 4 times the register 3196f2119df6SArindam Nath * value. 3197f2119df6SArindam Nath */ 3198f2119df6SArindam Nath max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 31993a48edc4STim Kryger if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3200ae906037SChuanxiao.Dong int curr = regulator_get_current_limit(mmc->supply.vmmc); 3201bad37e1aSPhilip Rakity if (curr > 0) { 3202bad37e1aSPhilip Rakity 3203bad37e1aSPhilip Rakity /* convert to SDHCI_MAX_CURRENT format */ 3204bad37e1aSPhilip Rakity curr = curr/1000; /* convert to mA */ 3205bad37e1aSPhilip Rakity curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3206bad37e1aSPhilip Rakity 3207bad37e1aSPhilip Rakity curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3208bad37e1aSPhilip Rakity max_current_caps = 3209bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3210bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3211bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3212bad37e1aSPhilip Rakity } 3213bad37e1aSPhilip Rakity } 3214f2119df6SArindam Nath 3215f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_330) { 32168f230f45STakashi Iwai ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3217f2119df6SArindam Nath 321855c4665eSAaron Lu mmc->max_current_330 = ((max_current_caps & 3219f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_MASK) >> 3220f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_SHIFT) * 3221f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3222f2119df6SArindam Nath } 3223f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_300) { 32248f230f45STakashi Iwai ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3225f2119df6SArindam Nath 322655c4665eSAaron Lu mmc->max_current_300 = ((max_current_caps & 3227f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_MASK) >> 3228f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_SHIFT) * 3229f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3230f2119df6SArindam Nath } 3231f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_180) { 32328f230f45STakashi Iwai ocr_avail |= MMC_VDD_165_195; 32338f230f45STakashi Iwai 323455c4665eSAaron Lu mmc->max_current_180 = ((max_current_caps & 3235f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_MASK) >> 3236f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_SHIFT) * 3237f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3238f2119df6SArindam Nath } 3239f2119df6SArindam Nath 32405fd26c7eSUlf Hansson /* If OCR set by host, use it instead. */ 32415fd26c7eSUlf Hansson if (host->ocr_mask) 32425fd26c7eSUlf Hansson ocr_avail = host->ocr_mask; 32435fd26c7eSUlf Hansson 32445fd26c7eSUlf Hansson /* If OCR set by external regulators, give it highest prio. */ 32453a48edc4STim Kryger if (mmc->ocr_avail) 324652221610STim Kryger ocr_avail = mmc->ocr_avail; 32473a48edc4STim Kryger 32488f230f45STakashi Iwai mmc->ocr_avail = ocr_avail; 32498f230f45STakashi Iwai mmc->ocr_avail_sdio = ocr_avail; 32508f230f45STakashi Iwai if (host->ocr_avail_sdio) 32518f230f45STakashi Iwai mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 32528f230f45STakashi Iwai mmc->ocr_avail_sd = ocr_avail; 32538f230f45STakashi Iwai if (host->ocr_avail_sd) 32548f230f45STakashi Iwai mmc->ocr_avail_sd &= host->ocr_avail_sd; 32558f230f45STakashi Iwai else /* normal SD controllers don't support 1.8V */ 32568f230f45STakashi Iwai mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 32578f230f45STakashi Iwai mmc->ocr_avail_mmc = ocr_avail; 32588f230f45STakashi Iwai if (host->ocr_avail_mmc) 32598f230f45STakashi Iwai mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 32601c6a0718SPierre Ossman 32611c6a0718SPierre Ossman if (mmc->ocr_avail == 0) { 32622e4456f0SMarek Vasut pr_err("%s: Hardware doesn't report any support voltages.\n", 32632e4456f0SMarek Vasut mmc_hostname(mmc)); 3264b8c86fc5SPierre Ossman return -ENODEV; 32651c6a0718SPierre Ossman } 32661c6a0718SPierre Ossman 32671c6a0718SPierre Ossman spin_lock_init(&host->lock); 32681c6a0718SPierre Ossman 32691c6a0718SPierre Ossman /* 32702134a922SPierre Ossman * Maximum number of segments. Depends on if the hardware 32712134a922SPierre Ossman * can do scatter/gather or not. 32721c6a0718SPierre Ossman */ 32732134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 32744fb213f8SAdrian Hunter mmc->max_segs = SDHCI_MAX_SEGS; 3275a13abc7bSRichard Röjfors else if (host->flags & SDHCI_USE_SDMA) 3276a36274e0SMartin K. Petersen mmc->max_segs = 1; 32772134a922SPierre Ossman else /* PIO */ 32784fb213f8SAdrian Hunter mmc->max_segs = SDHCI_MAX_SEGS; 32791c6a0718SPierre Ossman 32801c6a0718SPierre Ossman /* 3281ac00531dSAdrian Hunter * Maximum number of sectors in one transfer. Limited by SDMA boundary 3282ac00531dSAdrian Hunter * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3283ac00531dSAdrian Hunter * is less anyway. 32841c6a0718SPierre Ossman */ 32851c6a0718SPierre Ossman mmc->max_req_size = 524288; 32861c6a0718SPierre Ossman 32871c6a0718SPierre Ossman /* 32881c6a0718SPierre Ossman * Maximum segment size. Could be one segment with the maximum number 32892134a922SPierre Ossman * of bytes. When doing hardware scatter/gather, each entry cannot 32902134a922SPierre Ossman * be larger than 64 KiB though. 32911c6a0718SPierre Ossman */ 329230652aa3SOlof Johansson if (host->flags & SDHCI_USE_ADMA) { 329330652aa3SOlof Johansson if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 329430652aa3SOlof Johansson mmc->max_seg_size = 65535; 32952134a922SPierre Ossman else 329630652aa3SOlof Johansson mmc->max_seg_size = 65536; 329730652aa3SOlof Johansson } else { 32981c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 329930652aa3SOlof Johansson } 33001c6a0718SPierre Ossman 33011c6a0718SPierre Ossman /* 33021c6a0718SPierre Ossman * Maximum block size. This varies from controller to controller and 33031c6a0718SPierre Ossman * is specified in the capabilities register. 33041c6a0718SPierre Ossman */ 33050633f654SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 33060633f654SAnton Vorontsov mmc->max_blk_size = 2; 33070633f654SAnton Vorontsov } else { 3308f2119df6SArindam Nath mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 33090633f654SAnton Vorontsov SDHCI_MAX_BLOCK_SHIFT; 33101c6a0718SPierre Ossman if (mmc->max_blk_size >= 3) { 33116606110dSJoe Perches pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 33126606110dSJoe Perches mmc_hostname(mmc)); 33130633f654SAnton Vorontsov mmc->max_blk_size = 0; 33140633f654SAnton Vorontsov } 33150633f654SAnton Vorontsov } 33160633f654SAnton Vorontsov 33171c6a0718SPierre Ossman mmc->max_blk_size = 512 << mmc->max_blk_size; 33181c6a0718SPierre Ossman 33191c6a0718SPierre Ossman /* 33201c6a0718SPierre Ossman * Maximum block count. 33211c6a0718SPierre Ossman */ 33221388eefdSBen Dooks mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 33231c6a0718SPierre Ossman 33241c6a0718SPierre Ossman /* 33251c6a0718SPierre Ossman * Init tasklets. 33261c6a0718SPierre Ossman */ 33271c6a0718SPierre Ossman tasklet_init(&host->finish_tasklet, 33281c6a0718SPierre Ossman sdhci_tasklet_finish, (unsigned long)host); 33291c6a0718SPierre Ossman 33301c6a0718SPierre Ossman setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 33311c6a0718SPierre Ossman 3332b513ea25SArindam Nath init_waitqueue_head(&host->buf_ready_int); 3333b513ea25SArindam Nath 33342af502caSShawn Guo sdhci_init(host, 0); 33352af502caSShawn Guo 3336781e989cSRussell King ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3337781e989cSRussell King IRQF_SHARED, mmc_hostname(mmc), host); 33380fc81ee3SMark Brown if (ret) { 33390fc81ee3SMark Brown pr_err("%s: Failed to request IRQ %d: %d\n", 33400fc81ee3SMark Brown mmc_hostname(mmc), host->irq, ret); 33411c6a0718SPierre Ossman goto untasklet; 33420fc81ee3SMark Brown } 33431c6a0718SPierre Ossman 33441c6a0718SPierre Ossman #ifdef CONFIG_MMC_DEBUG 33451c6a0718SPierre Ossman sdhci_dumpregs(host); 33461c6a0718SPierre Ossman #endif 33471c6a0718SPierre Ossman 3348f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 33495dbace0cSHelmut Schaa snprintf(host->led_name, sizeof(host->led_name), 33505dbace0cSHelmut Schaa "%s::", mmc_hostname(mmc)); 33515dbace0cSHelmut Schaa host->led.name = host->led_name; 33522f730fecSPierre Ossman host->led.brightness = LED_OFF; 33532f730fecSPierre Ossman host->led.default_trigger = mmc_hostname(mmc); 33542f730fecSPierre Ossman host->led.brightness_set = sdhci_led_control; 33552f730fecSPierre Ossman 3356b8c86fc5SPierre Ossman ret = led_classdev_register(mmc_dev(mmc), &host->led); 33570fc81ee3SMark Brown if (ret) { 33580fc81ee3SMark Brown pr_err("%s: Failed to register LED device: %d\n", 33590fc81ee3SMark Brown mmc_hostname(mmc), ret); 33602f730fecSPierre Ossman goto reset; 33610fc81ee3SMark Brown } 33622f730fecSPierre Ossman #endif 33632f730fecSPierre Ossman 33641c6a0718SPierre Ossman mmiowb(); 33651c6a0718SPierre Ossman 33661c6a0718SPierre Ossman mmc_add_host(mmc); 33671c6a0718SPierre Ossman 3368a3c76eb9SGirish K S pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3369d1b26863SKay Sievers mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3370e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_ADMA) ? 3371e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3372a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 33731c6a0718SPierre Ossman 33747260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 33757260cf5eSAnton Vorontsov 33761c6a0718SPierre Ossman return 0; 33771c6a0718SPierre Ossman 3378f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 33792f730fecSPierre Ossman reset: 338003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 3381b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3382b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 33832f730fecSPierre Ossman free_irq(host->irq, host); 33842f730fecSPierre Ossman #endif 33851c6a0718SPierre Ossman untasklet: 33861c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 33871c6a0718SPierre Ossman 33881c6a0718SPierre Ossman return ret; 33891c6a0718SPierre Ossman } 33901c6a0718SPierre Ossman 3391b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_add_host); 3392b8c86fc5SPierre Ossman 33931e72859eSPierre Ossman void sdhci_remove_host(struct sdhci_host *host, int dead) 33941c6a0718SPierre Ossman { 33953a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 33961e72859eSPierre Ossman unsigned long flags; 33971e72859eSPierre Ossman 33981e72859eSPierre Ossman if (dead) { 33991e72859eSPierre Ossman spin_lock_irqsave(&host->lock, flags); 34001e72859eSPierre Ossman 34011e72859eSPierre Ossman host->flags |= SDHCI_DEVICE_DEAD; 34021e72859eSPierre Ossman 34031e72859eSPierre Ossman if (host->mrq) { 3404a3c76eb9SGirish K S pr_err("%s: Controller removed during " 34054e743f1fSMarkus Mayer " transfer!\n", mmc_hostname(mmc)); 34061e72859eSPierre Ossman 34071e72859eSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 34081e72859eSPierre Ossman tasklet_schedule(&host->finish_tasklet); 34091e72859eSPierre Ossman } 34101e72859eSPierre Ossman 34111e72859eSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 34121e72859eSPierre Ossman } 34131e72859eSPierre Ossman 34147260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 34157260cf5eSAnton Vorontsov 34164e743f1fSMarkus Mayer mmc_remove_host(mmc); 34171c6a0718SPierre Ossman 3418f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 34192f730fecSPierre Ossman led_classdev_unregister(&host->led); 34202f730fecSPierre Ossman #endif 34212f730fecSPierre Ossman 34221e72859eSPierre Ossman if (!dead) 342303231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 34241c6a0718SPierre Ossman 3425b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3426b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 34271c6a0718SPierre Ossman free_irq(host->irq, host); 34281c6a0718SPierre Ossman 34291c6a0718SPierre Ossman del_timer_sync(&host->timer); 34301c6a0718SPierre Ossman 34311c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 34322134a922SPierre Ossman 34333a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) 34343a48edc4STim Kryger regulator_disable(mmc->supply.vqmmc); 34356231f3deSPhilip Rakity 3436edd63fccSRussell King if (host->align_buffer) 3437e66e61cbSRussell King dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3438e66e61cbSRussell King host->adma_table_sz, host->align_buffer, 3439e66e61cbSRussell King host->align_addr); 34402134a922SPierre Ossman 34414efaa6fbSAdrian Hunter host->adma_table = NULL; 34422134a922SPierre Ossman host->align_buffer = NULL; 34431c6a0718SPierre Ossman } 34441c6a0718SPierre Ossman 3445b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_remove_host); 3446b8c86fc5SPierre Ossman 3447b8c86fc5SPierre Ossman void sdhci_free_host(struct sdhci_host *host) 34481c6a0718SPierre Ossman { 3449b8c86fc5SPierre Ossman mmc_free_host(host->mmc); 34501c6a0718SPierre Ossman } 34511c6a0718SPierre Ossman 3452b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_free_host); 34531c6a0718SPierre Ossman 34541c6a0718SPierre Ossman /*****************************************************************************\ 34551c6a0718SPierre Ossman * * 34561c6a0718SPierre Ossman * Driver init/exit * 34571c6a0718SPierre Ossman * * 34581c6a0718SPierre Ossman \*****************************************************************************/ 34591c6a0718SPierre Ossman 34601c6a0718SPierre Ossman static int __init sdhci_drv_init(void) 34611c6a0718SPierre Ossman { 3462a3c76eb9SGirish K S pr_info(DRIVER_NAME 34631c6a0718SPierre Ossman ": Secure Digital Host Controller Interface driver\n"); 3464a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 34651c6a0718SPierre Ossman 3466b8c86fc5SPierre Ossman return 0; 34671c6a0718SPierre Ossman } 34681c6a0718SPierre Ossman 34691c6a0718SPierre Ossman static void __exit sdhci_drv_exit(void) 34701c6a0718SPierre Ossman { 34711c6a0718SPierre Ossman } 34721c6a0718SPierre Ossman 34731c6a0718SPierre Ossman module_init(sdhci_drv_init); 34741c6a0718SPierre Ossman module_exit(sdhci_drv_exit); 34751c6a0718SPierre Ossman 34761c6a0718SPierre Ossman module_param(debug_quirks, uint, 0444); 347766fd8ad5SAdrian Hunter module_param(debug_quirks2, uint, 0444); 34781c6a0718SPierre Ossman 347932710e8fSPierre Ossman MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3480b8c86fc5SPierre Ossman MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 34811c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 34821c6a0718SPierre Ossman 34831c6a0718SPierre Ossman MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 348466fd8ad5SAdrian Hunter MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3485