12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 41c6a0718SPierre Ossman * 5b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 61c6a0718SPierre Ossman * 784c46a53SPierre Ossman * Thanks to the following companies for their support: 884c46a53SPierre Ossman * 984c46a53SPierre Ossman * - JMicron (hardware and technical support) 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman 121c6a0718SPierre Ossman #include <linux/delay.h> 135a436cc0SAdrian Hunter #include <linux/ktime.h> 141c6a0718SPierre Ossman #include <linux/highmem.h> 15b8c86fc5SPierre Ossman #include <linux/io.h> 1688b47679SPaul Gortmaker #include <linux/module.h> 171c6a0718SPierre Ossman #include <linux/dma-mapping.h> 185a0e3ad6STejun Heo #include <linux/slab.h> 1911763609SRalf Baechle #include <linux/scatterlist.h> 20bd9b9027SLinus Walleij #include <linux/sizes.h> 21250dcd11SUlf Hansson #include <linux/swiotlb.h> 229bea3c85SMarek Szyprowski #include <linux/regulator/consumer.h> 2366fd8ad5SAdrian Hunter #include <linux/pm_runtime.h> 2492e0c44bSZach Brown #include <linux/of.h> 251c6a0718SPierre Ossman 262f730fecSPierre Ossman #include <linux/leds.h> 272f730fecSPierre Ossman 2822113efdSAries Lee #include <linux/mmc/mmc.h> 291c6a0718SPierre Ossman #include <linux/mmc/host.h> 30473b095aSAaron Lu #include <linux/mmc/card.h> 3185cc1c33SCorneliu Doban #include <linux/mmc/sdio.h> 32bec9d4e5SGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #include "sdhci.h" 351c6a0718SPierre Ossman 361c6a0718SPierre Ossman #define DRIVER_NAME "sdhci" 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman #define DBG(f, x...) \ 39f421865dSAdrian Hunter pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 401c6a0718SPierre Ossman 4185ad90e2SAdrian Hunter #define SDHCI_DUMP(f, x...) \ 4285ad90e2SAdrian Hunter pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 4385ad90e2SAdrian Hunter 44b513ea25SArindam Nath #define MAX_TUNING_LOOP 40 45b513ea25SArindam Nath 461c6a0718SPierre Ossman static unsigned int debug_quirks = 0; 4766fd8ad5SAdrian Hunter static unsigned int debug_quirks2; 481c6a0718SPierre Ossman 491c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *); 501c6a0718SPierre Ossman 5152983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 521c6a0718SPierre Ossman 53d2898172SAdrian Hunter void sdhci_dumpregs(struct sdhci_host *host) 541c6a0718SPierre Ossman { 5585ad90e2SAdrian Hunter SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n"); 561c6a0718SPierre Ossman 5785ad90e2SAdrian Hunter SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n", 584e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_DMA_ADDRESS), 594e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_HOST_VERSION)); 6085ad90e2SAdrian Hunter SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n", 614e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_SIZE), 624e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_COUNT)); 6385ad90e2SAdrian Hunter SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n", 644e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_ARGUMENT), 654e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_TRANSFER_MODE)); 6685ad90e2SAdrian Hunter SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n", 674e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_PRESENT_STATE), 684e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_HOST_CONTROL)); 6985ad90e2SAdrian Hunter SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n", 704e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_POWER_CONTROL), 714e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 7285ad90e2SAdrian Hunter SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n", 734e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 744e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 7585ad90e2SAdrian Hunter SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n", 764e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 774e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_STATUS)); 7885ad90e2SAdrian Hunter SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n", 794e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_ENABLE), 804e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 81869f8a69SAdrian Hunter SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n", 82869f8a69SAdrian Hunter sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), 834e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 8485ad90e2SAdrian Hunter SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n", 854e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_CAPABILITIES), 86e8120ad1SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1)); 8785ad90e2SAdrian Hunter SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n", 88e8120ad1SPhilip Rakity sdhci_readw(host, SDHCI_COMMAND), 894e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_MAX_CURRENT)); 9085ad90e2SAdrian Hunter SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n", 917962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE), 927962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE + 4)); 9385ad90e2SAdrian Hunter SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n", 947962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE + 8), 957962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE + 12)); 9685ad90e2SAdrian Hunter SDHCI_DUMP("Host ctl2: 0x%08x\n", 97f2119df6SArindam Nath sdhci_readw(host, SDHCI_HOST_CONTROL2)); 981c6a0718SPierre Ossman 99e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_ADMA) { 10085ad90e2SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) { 10185ad90e2SAdrian Hunter SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 102c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ERROR), 103c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI), 104c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ADDRESS)); 10585ad90e2SAdrian Hunter } else { 10685ad90e2SAdrian Hunter SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 107c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ERROR), 108c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ADDRESS)); 109e57a5f61SAdrian Hunter } 11085ad90e2SAdrian Hunter } 111be3f4ae0SBen Dooks 11285ad90e2SAdrian Hunter SDHCI_DUMP("============================================\n"); 1131c6a0718SPierre Ossman } 114d2898172SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_dumpregs); 1151c6a0718SPierre Ossman 1161c6a0718SPierre Ossman /*****************************************************************************\ 1171c6a0718SPierre Ossman * * 1181c6a0718SPierre Ossman * Low level functions * 1191c6a0718SPierre Ossman * * 1201c6a0718SPierre Ossman \*****************************************************************************/ 1211c6a0718SPierre Ossman 122b3f80b43SChunyan Zhang static void sdhci_do_enable_v4_mode(struct sdhci_host *host) 123b3f80b43SChunyan Zhang { 124b3f80b43SChunyan Zhang u16 ctrl2; 125b3f80b43SChunyan Zhang 12697207c12SSowjanya Komatineni ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 127b3f80b43SChunyan Zhang if (ctrl2 & SDHCI_CTRL_V4_MODE) 128b3f80b43SChunyan Zhang return; 129b3f80b43SChunyan Zhang 130b3f80b43SChunyan Zhang ctrl2 |= SDHCI_CTRL_V4_MODE; 13197207c12SSowjanya Komatineni sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 132b3f80b43SChunyan Zhang } 133b3f80b43SChunyan Zhang 134b3f80b43SChunyan Zhang /* 135b3f80b43SChunyan Zhang * This can be called before sdhci_add_host() by Vendor's host controller 136b3f80b43SChunyan Zhang * driver to enable v4 mode if supported. 137b3f80b43SChunyan Zhang */ 138b3f80b43SChunyan Zhang void sdhci_enable_v4_mode(struct sdhci_host *host) 139b3f80b43SChunyan Zhang { 140b3f80b43SChunyan Zhang host->v4_mode = true; 141b3f80b43SChunyan Zhang sdhci_do_enable_v4_mode(host); 142b3f80b43SChunyan Zhang } 143b3f80b43SChunyan Zhang EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); 144b3f80b43SChunyan Zhang 14556a590dcSAdrian Hunter static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 14656a590dcSAdrian Hunter { 14756a590dcSAdrian Hunter return cmd->data || cmd->flags & MMC_RSP_BUSY; 14856a590dcSAdrian Hunter } 14956a590dcSAdrian Hunter 1507260cf5eSAnton Vorontsov static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 1517260cf5eSAnton Vorontsov { 1525b4f1f6cSRussell King u32 present; 1537260cf5eSAnton Vorontsov 154c79396c1SAdrian Hunter if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 155860951c5SJaehoon Chung !mmc_card_is_removable(host->mmc)) 15666fd8ad5SAdrian Hunter return; 15766fd8ad5SAdrian Hunter 1585b4f1f6cSRussell King if (enable) { 159d25928d1SShawn Guo present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 160d25928d1SShawn Guo SDHCI_CARD_PRESENT; 161d25928d1SShawn Guo 1625b4f1f6cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 1635b4f1f6cSRussell King SDHCI_INT_CARD_INSERT; 1645b4f1f6cSRussell King } else { 1655b4f1f6cSRussell King host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 1665b4f1f6cSRussell King } 167b537f94cSRussell King 168b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 169b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1707260cf5eSAnton Vorontsov } 1717260cf5eSAnton Vorontsov 1727260cf5eSAnton Vorontsov static void sdhci_enable_card_detection(struct sdhci_host *host) 1737260cf5eSAnton Vorontsov { 1747260cf5eSAnton Vorontsov sdhci_set_card_detection(host, true); 1757260cf5eSAnton Vorontsov } 1767260cf5eSAnton Vorontsov 1777260cf5eSAnton Vorontsov static void sdhci_disable_card_detection(struct sdhci_host *host) 1787260cf5eSAnton Vorontsov { 1797260cf5eSAnton Vorontsov sdhci_set_card_detection(host, false); 1807260cf5eSAnton Vorontsov } 1817260cf5eSAnton Vorontsov 18202d0b685SUlf Hansson static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 18302d0b685SUlf Hansson { 18402d0b685SUlf Hansson if (host->bus_on) 18502d0b685SUlf Hansson return; 18602d0b685SUlf Hansson host->bus_on = true; 18702d0b685SUlf Hansson pm_runtime_get_noresume(host->mmc->parent); 18802d0b685SUlf Hansson } 18902d0b685SUlf Hansson 19002d0b685SUlf Hansson static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 19102d0b685SUlf Hansson { 19202d0b685SUlf Hansson if (!host->bus_on) 19302d0b685SUlf Hansson return; 19402d0b685SUlf Hansson host->bus_on = false; 19502d0b685SUlf Hansson pm_runtime_put_noidle(host->mmc->parent); 19602d0b685SUlf Hansson } 19702d0b685SUlf Hansson 19803231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask) 1991c6a0718SPierre Ossman { 2005a436cc0SAdrian Hunter ktime_t timeout; 201393c1a34SPhilip Rakity 2024e4141a5SAnton Vorontsov sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 2031c6a0718SPierre Ossman 204f0710a55SAdrian Hunter if (mask & SDHCI_RESET_ALL) { 2051c6a0718SPierre Ossman host->clock = 0; 206f0710a55SAdrian Hunter /* Reset-all turns off SD Bus Power */ 207f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 208f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 209f0710a55SAdrian Hunter } 2101c6a0718SPierre Ossman 2111c6a0718SPierre Ossman /* Wait max 100 ms */ 2125a436cc0SAdrian Hunter timeout = ktime_add_ms(ktime_get(), 100); 2131c6a0718SPierre Ossman 2141c6a0718SPierre Ossman /* hw clears the bit when it's done */ 215b704441eSAlek Du while (1) { 216b704441eSAlek Du bool timedout = ktime_after(ktime_get(), timeout); 217b704441eSAlek Du 218b704441eSAlek Du if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) 219b704441eSAlek Du break; 220b704441eSAlek Du if (timedout) { 221a3c76eb9SGirish K S pr_err("%s: Reset 0x%x never completed.\n", 2221c6a0718SPierre Ossman mmc_hostname(host->mmc), (int)mask); 2231c6a0718SPierre Ossman sdhci_dumpregs(host); 2241c6a0718SPierre Ossman return; 2251c6a0718SPierre Ossman } 2265a436cc0SAdrian Hunter udelay(10); 2271c6a0718SPierre Ossman } 22803231f9bSRussell King } 22903231f9bSRussell King EXPORT_SYMBOL_GPL(sdhci_reset); 230063a9dbbSAnton Vorontsov 23103231f9bSRussell King static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 23203231f9bSRussell King { 23303231f9bSRussell King if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 234d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 235d3940f27SAdrian Hunter 236d3940f27SAdrian Hunter if (!mmc->ops->get_cd(mmc)) 23703231f9bSRussell King return; 23803231f9bSRussell King } 23903231f9bSRussell King 24003231f9bSRussell King host->ops->reset(host, mask); 241393c1a34SPhilip Rakity 242da91a8f9SRussell King if (mask & SDHCI_RESET_ALL) { 2433abc1e80SShaohui Xie if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 244da91a8f9SRussell King if (host->ops->enable_dma) 2453abc1e80SShaohui Xie host->ops->enable_dma(host); 2463abc1e80SShaohui Xie } 247da91a8f9SRussell King 248da91a8f9SRussell King /* Resetting the controller clears many */ 249da91a8f9SRussell King host->preset_enabled = false; 250da91a8f9SRussell King } 2511c6a0718SPierre Ossman } 2521c6a0718SPierre Ossman 253f5c1ab82SAdrian Hunter static void sdhci_set_default_irqs(struct sdhci_host *host) 2541c6a0718SPierre Ossman { 255b537f94cSRussell King host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 256b537f94cSRussell King SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 257b537f94cSRussell King SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 258b537f94cSRussell King SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 259b537f94cSRussell King SDHCI_INT_RESPONSE; 260b537f94cSRussell King 261f37b20ebSDong Aisheng if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 262f37b20ebSDong Aisheng host->tuning_mode == SDHCI_TUNING_MODE_3) 263f37b20ebSDong Aisheng host->ier |= SDHCI_INT_RETUNE; 264f37b20ebSDong Aisheng 265b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 266b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 267f5c1ab82SAdrian Hunter } 268f5c1ab82SAdrian Hunter 269685e444bSChunyan Zhang static void sdhci_config_dma(struct sdhci_host *host) 270685e444bSChunyan Zhang { 271685e444bSChunyan Zhang u8 ctrl; 272685e444bSChunyan Zhang u16 ctrl2; 273685e444bSChunyan Zhang 274685e444bSChunyan Zhang if (host->version < SDHCI_SPEC_200) 275685e444bSChunyan Zhang return; 276685e444bSChunyan Zhang 277685e444bSChunyan Zhang ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 278685e444bSChunyan Zhang 279685e444bSChunyan Zhang /* 280685e444bSChunyan Zhang * Always adjust the DMA selection as some controllers 281685e444bSChunyan Zhang * (e.g. JMicron) can't do PIO properly when the selection 282685e444bSChunyan Zhang * is ADMA. 283685e444bSChunyan Zhang */ 284685e444bSChunyan Zhang ctrl &= ~SDHCI_CTRL_DMA_MASK; 285685e444bSChunyan Zhang if (!(host->flags & SDHCI_REQ_USE_DMA)) 286685e444bSChunyan Zhang goto out; 287685e444bSChunyan Zhang 288685e444bSChunyan Zhang /* Note if DMA Select is zero then SDMA is selected */ 289685e444bSChunyan Zhang if (host->flags & SDHCI_USE_ADMA) 290685e444bSChunyan Zhang ctrl |= SDHCI_CTRL_ADMA32; 291685e444bSChunyan Zhang 292685e444bSChunyan Zhang if (host->flags & SDHCI_USE_64_BIT_DMA) { 293685e444bSChunyan Zhang /* 294685e444bSChunyan Zhang * If v4 mode, all supported DMA can be 64-bit addressing if 295685e444bSChunyan Zhang * controller supports 64-bit system address, otherwise only 296685e444bSChunyan Zhang * ADMA can support 64-bit addressing. 297685e444bSChunyan Zhang */ 298685e444bSChunyan Zhang if (host->v4_mode) { 299685e444bSChunyan Zhang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 300685e444bSChunyan Zhang ctrl2 |= SDHCI_CTRL_64BIT_ADDR; 301685e444bSChunyan Zhang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 302685e444bSChunyan Zhang } else if (host->flags & SDHCI_USE_ADMA) { 303685e444bSChunyan Zhang /* 304685e444bSChunyan Zhang * Don't need to undo SDHCI_CTRL_ADMA32 in order to 305685e444bSChunyan Zhang * set SDHCI_CTRL_ADMA64. 306685e444bSChunyan Zhang */ 307685e444bSChunyan Zhang ctrl |= SDHCI_CTRL_ADMA64; 308685e444bSChunyan Zhang } 309685e444bSChunyan Zhang } 310685e444bSChunyan Zhang 311685e444bSChunyan Zhang out: 312685e444bSChunyan Zhang sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 313685e444bSChunyan Zhang } 314685e444bSChunyan Zhang 315f5c1ab82SAdrian Hunter static void sdhci_init(struct sdhci_host *host, int soft) 316f5c1ab82SAdrian Hunter { 317f5c1ab82SAdrian Hunter struct mmc_host *mmc = host->mmc; 318f5c1ab82SAdrian Hunter 319f5c1ab82SAdrian Hunter if (soft) 320f5c1ab82SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 321f5c1ab82SAdrian Hunter else 322f5c1ab82SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_ALL); 323f5c1ab82SAdrian Hunter 324b3f80b43SChunyan Zhang if (host->v4_mode) 325b3f80b43SChunyan Zhang sdhci_do_enable_v4_mode(host); 326b3f80b43SChunyan Zhang 327f5c1ab82SAdrian Hunter sdhci_set_default_irqs(host); 3282f4cbb3dSNicolas Pitre 329f12e39dbSAdrian Hunter host->cqe_on = false; 330f12e39dbSAdrian Hunter 3312f4cbb3dSNicolas Pitre if (soft) { 3322f4cbb3dSNicolas Pitre /* force clock reconfiguration */ 3332f4cbb3dSNicolas Pitre host->clock = 0; 334d3940f27SAdrian Hunter mmc->ops->set_ios(mmc, &mmc->ios); 3352f4cbb3dSNicolas Pitre } 3367260cf5eSAnton Vorontsov } 3371c6a0718SPierre Ossman 3387260cf5eSAnton Vorontsov static void sdhci_reinit(struct sdhci_host *host) 3397260cf5eSAnton Vorontsov { 3402f4cbb3dSNicolas Pitre sdhci_init(host, 0); 3417260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 3421c6a0718SPierre Ossman } 3431c6a0718SPierre Ossman 344061d17a6SAdrian Hunter static void __sdhci_led_activate(struct sdhci_host *host) 3451c6a0718SPierre Ossman { 3461c6a0718SPierre Ossman u8 ctrl; 3471c6a0718SPierre Ossman 348bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 349bd29f58bSAdrian Hunter return; 350bd29f58bSAdrian Hunter 3514e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3521c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_LED; 3534e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3541c6a0718SPierre Ossman } 3551c6a0718SPierre Ossman 356061d17a6SAdrian Hunter static void __sdhci_led_deactivate(struct sdhci_host *host) 3571c6a0718SPierre Ossman { 3581c6a0718SPierre Ossman u8 ctrl; 3591c6a0718SPierre Ossman 360bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 361bd29f58bSAdrian Hunter return; 362bd29f58bSAdrian Hunter 3634e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3641c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_LED; 3654e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3661c6a0718SPierre Ossman } 3671c6a0718SPierre Ossman 3684f78230fSMasahiro Yamada #if IS_REACHABLE(CONFIG_LEDS_CLASS) 3692f730fecSPierre Ossman static void sdhci_led_control(struct led_classdev *led, 3702f730fecSPierre Ossman enum led_brightness brightness) 3712f730fecSPierre Ossman { 3722f730fecSPierre Ossman struct sdhci_host *host = container_of(led, struct sdhci_host, led); 3732f730fecSPierre Ossman unsigned long flags; 3742f730fecSPierre Ossman 3752f730fecSPierre Ossman spin_lock_irqsave(&host->lock, flags); 3762f730fecSPierre Ossman 37766fd8ad5SAdrian Hunter if (host->runtime_suspended) 37866fd8ad5SAdrian Hunter goto out; 37966fd8ad5SAdrian Hunter 3802f730fecSPierre Ossman if (brightness == LED_OFF) 381061d17a6SAdrian Hunter __sdhci_led_deactivate(host); 3822f730fecSPierre Ossman else 383061d17a6SAdrian Hunter __sdhci_led_activate(host); 38466fd8ad5SAdrian Hunter out: 3852f730fecSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 3862f730fecSPierre Ossman } 387061d17a6SAdrian Hunter 388061d17a6SAdrian Hunter static int sdhci_led_register(struct sdhci_host *host) 389061d17a6SAdrian Hunter { 390061d17a6SAdrian Hunter struct mmc_host *mmc = host->mmc; 391061d17a6SAdrian Hunter 392bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 393bd29f58bSAdrian Hunter return 0; 394bd29f58bSAdrian Hunter 395061d17a6SAdrian Hunter snprintf(host->led_name, sizeof(host->led_name), 396061d17a6SAdrian Hunter "%s::", mmc_hostname(mmc)); 397061d17a6SAdrian Hunter 398061d17a6SAdrian Hunter host->led.name = host->led_name; 399061d17a6SAdrian Hunter host->led.brightness = LED_OFF; 400061d17a6SAdrian Hunter host->led.default_trigger = mmc_hostname(mmc); 401061d17a6SAdrian Hunter host->led.brightness_set = sdhci_led_control; 402061d17a6SAdrian Hunter 403061d17a6SAdrian Hunter return led_classdev_register(mmc_dev(mmc), &host->led); 404061d17a6SAdrian Hunter } 405061d17a6SAdrian Hunter 406061d17a6SAdrian Hunter static void sdhci_led_unregister(struct sdhci_host *host) 407061d17a6SAdrian Hunter { 408bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 409bd29f58bSAdrian Hunter return; 410bd29f58bSAdrian Hunter 411061d17a6SAdrian Hunter led_classdev_unregister(&host->led); 412061d17a6SAdrian Hunter } 413061d17a6SAdrian Hunter 414061d17a6SAdrian Hunter static inline void sdhci_led_activate(struct sdhci_host *host) 415061d17a6SAdrian Hunter { 416061d17a6SAdrian Hunter } 417061d17a6SAdrian Hunter 418061d17a6SAdrian Hunter static inline void sdhci_led_deactivate(struct sdhci_host *host) 419061d17a6SAdrian Hunter { 420061d17a6SAdrian Hunter } 421061d17a6SAdrian Hunter 422061d17a6SAdrian Hunter #else 423061d17a6SAdrian Hunter 424061d17a6SAdrian Hunter static inline int sdhci_led_register(struct sdhci_host *host) 425061d17a6SAdrian Hunter { 426061d17a6SAdrian Hunter return 0; 427061d17a6SAdrian Hunter } 428061d17a6SAdrian Hunter 429061d17a6SAdrian Hunter static inline void sdhci_led_unregister(struct sdhci_host *host) 430061d17a6SAdrian Hunter { 431061d17a6SAdrian Hunter } 432061d17a6SAdrian Hunter 433061d17a6SAdrian Hunter static inline void sdhci_led_activate(struct sdhci_host *host) 434061d17a6SAdrian Hunter { 435061d17a6SAdrian Hunter __sdhci_led_activate(host); 436061d17a6SAdrian Hunter } 437061d17a6SAdrian Hunter 438061d17a6SAdrian Hunter static inline void sdhci_led_deactivate(struct sdhci_host *host) 439061d17a6SAdrian Hunter { 440061d17a6SAdrian Hunter __sdhci_led_deactivate(host); 441061d17a6SAdrian Hunter } 442061d17a6SAdrian Hunter 4432f730fecSPierre Ossman #endif 4442f730fecSPierre Ossman 44597a1abaeSAdrian Hunter static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 44697a1abaeSAdrian Hunter unsigned long timeout) 44797a1abaeSAdrian Hunter { 44897a1abaeSAdrian Hunter if (sdhci_data_line_cmd(mrq->cmd)) 44997a1abaeSAdrian Hunter mod_timer(&host->data_timer, timeout); 45097a1abaeSAdrian Hunter else 45197a1abaeSAdrian Hunter mod_timer(&host->timer, timeout); 45297a1abaeSAdrian Hunter } 45397a1abaeSAdrian Hunter 45497a1abaeSAdrian Hunter static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 45597a1abaeSAdrian Hunter { 45697a1abaeSAdrian Hunter if (sdhci_data_line_cmd(mrq->cmd)) 45797a1abaeSAdrian Hunter del_timer(&host->data_timer); 45897a1abaeSAdrian Hunter else 45997a1abaeSAdrian Hunter del_timer(&host->timer); 46097a1abaeSAdrian Hunter } 46197a1abaeSAdrian Hunter 46297a1abaeSAdrian Hunter static inline bool sdhci_has_requests(struct sdhci_host *host) 46397a1abaeSAdrian Hunter { 46497a1abaeSAdrian Hunter return host->cmd || host->data_cmd; 46597a1abaeSAdrian Hunter } 46697a1abaeSAdrian Hunter 4671c6a0718SPierre Ossman /*****************************************************************************\ 4681c6a0718SPierre Ossman * * 4691c6a0718SPierre Ossman * Core functions * 4701c6a0718SPierre Ossman * * 4711c6a0718SPierre Ossman \*****************************************************************************/ 4721c6a0718SPierre Ossman 4731c6a0718SPierre Ossman static void sdhci_read_block_pio(struct sdhci_host *host) 4741c6a0718SPierre Ossman { 4757659150cSPierre Ossman unsigned long flags; 4767659150cSPierre Ossman size_t blksize, len, chunk; 4777244b85bSSteven Noonan u32 uninitialized_var(scratch); 4787659150cSPierre Ossman u8 *buf; 4791c6a0718SPierre Ossman 4801c6a0718SPierre Ossman DBG("PIO reading\n"); 4811c6a0718SPierre Ossman 4821c6a0718SPierre Ossman blksize = host->data->blksz; 4837659150cSPierre Ossman chunk = 0; 4841c6a0718SPierre Ossman 4857659150cSPierre Ossman local_irq_save(flags); 4861c6a0718SPierre Ossman 4871c6a0718SPierre Ossman while (blksize) { 488bf3a35acSFabio Estevam BUG_ON(!sg_miter_next(&host->sg_miter)); 4897659150cSPierre Ossman 4907659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 4917659150cSPierre Ossman 4927659150cSPierre Ossman blksize -= len; 4937659150cSPierre Ossman host->sg_miter.consumed = len; 4947659150cSPierre Ossman 4957659150cSPierre Ossman buf = host->sg_miter.addr; 4967659150cSPierre Ossman 4977659150cSPierre Ossman while (len) { 4987659150cSPierre Ossman if (chunk == 0) { 4994e4141a5SAnton Vorontsov scratch = sdhci_readl(host, SDHCI_BUFFER); 5007659150cSPierre Ossman chunk = 4; 5011c6a0718SPierre Ossman } 5021c6a0718SPierre Ossman 5037659150cSPierre Ossman *buf = scratch & 0xFF; 5041c6a0718SPierre Ossman 5057659150cSPierre Ossman buf++; 5067659150cSPierre Ossman scratch >>= 8; 5077659150cSPierre Ossman chunk--; 5087659150cSPierre Ossman len--; 5097659150cSPierre Ossman } 5101c6a0718SPierre Ossman } 5111c6a0718SPierre Ossman 5127659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 5137659150cSPierre Ossman 5147659150cSPierre Ossman local_irq_restore(flags); 5151c6a0718SPierre Ossman } 5161c6a0718SPierre Ossman 5171c6a0718SPierre Ossman static void sdhci_write_block_pio(struct sdhci_host *host) 5181c6a0718SPierre Ossman { 5197659150cSPierre Ossman unsigned long flags; 5207659150cSPierre Ossman size_t blksize, len, chunk; 5217659150cSPierre Ossman u32 scratch; 5227659150cSPierre Ossman u8 *buf; 5231c6a0718SPierre Ossman 5241c6a0718SPierre Ossman DBG("PIO writing\n"); 5251c6a0718SPierre Ossman 5261c6a0718SPierre Ossman blksize = host->data->blksz; 5277659150cSPierre Ossman chunk = 0; 5287659150cSPierre Ossman scratch = 0; 5291c6a0718SPierre Ossman 5307659150cSPierre Ossman local_irq_save(flags); 5311c6a0718SPierre Ossman 5321c6a0718SPierre Ossman while (blksize) { 533bf3a35acSFabio Estevam BUG_ON(!sg_miter_next(&host->sg_miter)); 5341c6a0718SPierre Ossman 5357659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 5361c6a0718SPierre Ossman 5377659150cSPierre Ossman blksize -= len; 5387659150cSPierre Ossman host->sg_miter.consumed = len; 5397659150cSPierre Ossman 5407659150cSPierre Ossman buf = host->sg_miter.addr; 5417659150cSPierre Ossman 5427659150cSPierre Ossman while (len) { 5437659150cSPierre Ossman scratch |= (u32)*buf << (chunk * 8); 5447659150cSPierre Ossman 5457659150cSPierre Ossman buf++; 5467659150cSPierre Ossman chunk++; 5477659150cSPierre Ossman len--; 5487659150cSPierre Ossman 5497659150cSPierre Ossman if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 5504e4141a5SAnton Vorontsov sdhci_writel(host, scratch, SDHCI_BUFFER); 5517659150cSPierre Ossman chunk = 0; 5527659150cSPierre Ossman scratch = 0; 5537659150cSPierre Ossman } 5547659150cSPierre Ossman } 5551c6a0718SPierre Ossman } 5561c6a0718SPierre Ossman 5577659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 5581c6a0718SPierre Ossman 5597659150cSPierre Ossman local_irq_restore(flags); 5601c6a0718SPierre Ossman } 5611c6a0718SPierre Ossman 5621c6a0718SPierre Ossman static void sdhci_transfer_pio(struct sdhci_host *host) 5631c6a0718SPierre Ossman { 5641c6a0718SPierre Ossman u32 mask; 5651c6a0718SPierre Ossman 5667659150cSPierre Ossman if (host->blocks == 0) 5671c6a0718SPierre Ossman return; 5681c6a0718SPierre Ossman 5691c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 5701c6a0718SPierre Ossman mask = SDHCI_DATA_AVAILABLE; 5711c6a0718SPierre Ossman else 5721c6a0718SPierre Ossman mask = SDHCI_SPACE_AVAILABLE; 5731c6a0718SPierre Ossman 5744a3cba32SPierre Ossman /* 5754a3cba32SPierre Ossman * Some controllers (JMicron JMB38x) mess up the buffer bits 5764a3cba32SPierre Ossman * for transfers < 4 bytes. As long as it is just one block, 5774a3cba32SPierre Ossman * we can ignore the bits. 5784a3cba32SPierre Ossman */ 5794a3cba32SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 5804a3cba32SPierre Ossman (host->data->blocks == 1)) 5814a3cba32SPierre Ossman mask = ~0; 5824a3cba32SPierre Ossman 5834e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 5843e3bf207SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 5853e3bf207SAnton Vorontsov udelay(100); 5863e3bf207SAnton Vorontsov 5871c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 5881c6a0718SPierre Ossman sdhci_read_block_pio(host); 5891c6a0718SPierre Ossman else 5901c6a0718SPierre Ossman sdhci_write_block_pio(host); 5911c6a0718SPierre Ossman 5927659150cSPierre Ossman host->blocks--; 5937659150cSPierre Ossman if (host->blocks == 0) 5941c6a0718SPierre Ossman break; 5951c6a0718SPierre Ossman } 5961c6a0718SPierre Ossman 5971c6a0718SPierre Ossman DBG("PIO transfer complete.\n"); 5981c6a0718SPierre Ossman } 5991c6a0718SPierre Ossman 60048857d9bSRussell King static int sdhci_pre_dma_transfer(struct sdhci_host *host, 601c0999b72SRussell King struct mmc_data *data, int cookie) 60248857d9bSRussell King { 60348857d9bSRussell King int sg_count; 60448857d9bSRussell King 60594538e51SRussell King /* 60694538e51SRussell King * If the data buffers are already mapped, return the previous 60794538e51SRussell King * dma_map_sg() result. 60894538e51SRussell King */ 60994538e51SRussell King if (data->host_cookie == COOKIE_PRE_MAPPED) 61048857d9bSRussell King return data->sg_count; 61148857d9bSRussell King 612bd9b9027SLinus Walleij /* Bounce write requests to the bounce buffer */ 613bd9b9027SLinus Walleij if (host->bounce_buffer) { 614bd9b9027SLinus Walleij unsigned int length = data->blksz * data->blocks; 615bd9b9027SLinus Walleij 616bd9b9027SLinus Walleij if (length > host->bounce_buffer_size) { 617bd9b9027SLinus Walleij pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n", 618bd9b9027SLinus Walleij mmc_hostname(host->mmc), length, 619bd9b9027SLinus Walleij host->bounce_buffer_size); 620bd9b9027SLinus Walleij return -EIO; 621bd9b9027SLinus Walleij } 622bd9b9027SLinus Walleij if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) { 623bd9b9027SLinus Walleij /* Copy the data to the bounce buffer */ 624bd9b9027SLinus Walleij sg_copy_to_buffer(data->sg, data->sg_len, 625bd9b9027SLinus Walleij host->bounce_buffer, 626bd9b9027SLinus Walleij length); 627bd9b9027SLinus Walleij } 628bd9b9027SLinus Walleij /* Switch ownership to the DMA */ 629bd9b9027SLinus Walleij dma_sync_single_for_device(host->mmc->parent, 630bd9b9027SLinus Walleij host->bounce_addr, 631bd9b9027SLinus Walleij host->bounce_buffer_size, 632feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 633bd9b9027SLinus Walleij /* Just a dummy value */ 634bd9b9027SLinus Walleij sg_count = 1; 635bd9b9027SLinus Walleij } else { 636bd9b9027SLinus Walleij /* Just access the data directly from memory */ 637bd9b9027SLinus Walleij sg_count = dma_map_sg(mmc_dev(host->mmc), 638bd9b9027SLinus Walleij data->sg, data->sg_len, 639bd9b9027SLinus Walleij mmc_get_dma_dir(data)); 640bd9b9027SLinus Walleij } 64148857d9bSRussell King 64248857d9bSRussell King if (sg_count == 0) 64348857d9bSRussell King return -ENOSPC; 64448857d9bSRussell King 64548857d9bSRussell King data->sg_count = sg_count; 646c0999b72SRussell King data->host_cookie = cookie; 64748857d9bSRussell King 64848857d9bSRussell King return sg_count; 64948857d9bSRussell King } 65048857d9bSRussell King 6512134a922SPierre Ossman static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 6522134a922SPierre Ossman { 6532134a922SPierre Ossman local_irq_save(*flags); 654482fce99SCong Wang return kmap_atomic(sg_page(sg)) + sg->offset; 6552134a922SPierre Ossman } 6562134a922SPierre Ossman 6572134a922SPierre Ossman static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 6582134a922SPierre Ossman { 659482fce99SCong Wang kunmap_atomic(buffer); 6602134a922SPierre Ossman local_irq_restore(*flags); 6612134a922SPierre Ossman } 6622134a922SPierre Ossman 66354552e49SJisheng Zhang void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 66454552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd) 665118cd17dSBen Dooks { 66654552e49SJisheng Zhang struct sdhci_adma2_64_desc *dma_desc = *desc; 667118cd17dSBen Dooks 668e57a5f61SAdrian Hunter /* 32-bit and 64-bit descriptors have these members in same position */ 6690545230fSAdrian Hunter dma_desc->cmd = cpu_to_le16(cmd); 6700545230fSAdrian Hunter dma_desc->len = cpu_to_le16(len); 671e57a5f61SAdrian Hunter dma_desc->addr_lo = cpu_to_le32((u32)addr); 672e57a5f61SAdrian Hunter 673e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 674e57a5f61SAdrian Hunter dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 67554552e49SJisheng Zhang 67654552e49SJisheng Zhang *desc += host->desc_sz; 67754552e49SJisheng Zhang } 67854552e49SJisheng Zhang EXPORT_SYMBOL_GPL(sdhci_adma_write_desc); 67954552e49SJisheng Zhang 68054552e49SJisheng Zhang static inline void __sdhci_adma_write_desc(struct sdhci_host *host, 68154552e49SJisheng Zhang void **desc, dma_addr_t addr, 68254552e49SJisheng Zhang int len, unsigned int cmd) 68354552e49SJisheng Zhang { 68454552e49SJisheng Zhang if (host->ops->adma_write_desc) 68554552e49SJisheng Zhang host->ops->adma_write_desc(host, desc, addr, len, cmd); 68607be55b5SJisheng Zhang else 68754552e49SJisheng Zhang sdhci_adma_write_desc(host, desc, addr, len, cmd); 688118cd17dSBen Dooks } 689118cd17dSBen Dooks 690b5ffa674SAdrian Hunter static void sdhci_adma_mark_end(void *desc) 691b5ffa674SAdrian Hunter { 692e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 693b5ffa674SAdrian Hunter 694e57a5f61SAdrian Hunter /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 6950545230fSAdrian Hunter dma_desc->cmd |= cpu_to_le16(ADMA2_END); 696b5ffa674SAdrian Hunter } 697b5ffa674SAdrian Hunter 69860c64762SRussell King static void sdhci_adma_table_pre(struct sdhci_host *host, 69960c64762SRussell King struct mmc_data *data, int sg_count) 7002134a922SPierre Ossman { 7012134a922SPierre Ossman struct scatterlist *sg; 7022134a922SPierre Ossman unsigned long flags; 703acc3ad13SRussell King dma_addr_t addr, align_addr; 704acc3ad13SRussell King void *desc, *align; 705acc3ad13SRussell King char *buffer; 706acc3ad13SRussell King int len, offset, i; 7072134a922SPierre Ossman 7082134a922SPierre Ossman /* 7092134a922SPierre Ossman * The spec does not specify endianness of descriptor table. 7102134a922SPierre Ossman * We currently guess that it is LE. 7112134a922SPierre Ossman */ 7122134a922SPierre Ossman 71360c64762SRussell King host->sg_count = sg_count; 7142134a922SPierre Ossman 7154efaa6fbSAdrian Hunter desc = host->adma_table; 7162134a922SPierre Ossman align = host->align_buffer; 7172134a922SPierre Ossman 7182134a922SPierre Ossman align_addr = host->align_addr; 7192134a922SPierre Ossman 7202134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 7212134a922SPierre Ossman addr = sg_dma_address(sg); 7222134a922SPierre Ossman len = sg_dma_len(sg); 7232134a922SPierre Ossman 7242134a922SPierre Ossman /* 725acc3ad13SRussell King * The SDHCI specification states that ADMA addresses must 726acc3ad13SRussell King * be 32-bit aligned. If they aren't, then we use a bounce 727acc3ad13SRussell King * buffer for the (up to three) bytes that screw up the 7282134a922SPierre Ossman * alignment. 7292134a922SPierre Ossman */ 73004a5ae6fSAdrian Hunter offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 73104a5ae6fSAdrian Hunter SDHCI_ADMA2_MASK; 7322134a922SPierre Ossman if (offset) { 7332134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 7342134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 7352134a922SPierre Ossman memcpy(align, buffer, offset); 7362134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 7372134a922SPierre Ossman } 7382134a922SPierre Ossman 739118cd17dSBen Dooks /* tran, valid */ 74054552e49SJisheng Zhang __sdhci_adma_write_desc(host, &desc, align_addr, 74154552e49SJisheng Zhang offset, ADMA2_TRAN_VALID); 7422134a922SPierre Ossman 7432134a922SPierre Ossman BUG_ON(offset > 65536); 7442134a922SPierre Ossman 74504a5ae6fSAdrian Hunter align += SDHCI_ADMA2_ALIGN; 74604a5ae6fSAdrian Hunter align_addr += SDHCI_ADMA2_ALIGN; 7472134a922SPierre Ossman 7482134a922SPierre Ossman addr += offset; 7492134a922SPierre Ossman len -= offset; 7502134a922SPierre Ossman } 7512134a922SPierre Ossman 7522134a922SPierre Ossman BUG_ON(len > 65536); 7532134a922SPierre Ossman 754118cd17dSBen Dooks /* tran, valid */ 75554552e49SJisheng Zhang if (len) 75654552e49SJisheng Zhang __sdhci_adma_write_desc(host, &desc, addr, len, 757347ea32dSAdrian Hunter ADMA2_TRAN_VALID); 7582134a922SPierre Ossman 7592134a922SPierre Ossman /* 7602134a922SPierre Ossman * If this triggers then we have a calculation bug 7612134a922SPierre Ossman * somewhere. :/ 7622134a922SPierre Ossman */ 76376fe379aSAdrian Hunter WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 7642134a922SPierre Ossman } 7652134a922SPierre Ossman 76670764a90SThomas Abraham if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 767acc3ad13SRussell King /* Mark the last descriptor as the terminating descriptor */ 7684efaa6fbSAdrian Hunter if (desc != host->adma_table) { 76976fe379aSAdrian Hunter desc -= host->desc_sz; 770b5ffa674SAdrian Hunter sdhci_adma_mark_end(desc); 77170764a90SThomas Abraham } 77270764a90SThomas Abraham } else { 773acc3ad13SRussell King /* Add a terminating entry - nop, end, valid */ 77454552e49SJisheng Zhang __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID); 77570764a90SThomas Abraham } 7762134a922SPierre Ossman } 7772134a922SPierre Ossman 7782134a922SPierre Ossman static void sdhci_adma_table_post(struct sdhci_host *host, 7792134a922SPierre Ossman struct mmc_data *data) 7802134a922SPierre Ossman { 7812134a922SPierre Ossman struct scatterlist *sg; 7822134a922SPierre Ossman int i, size; 7831c3d5f6dSAdrian Hunter void *align; 7842134a922SPierre Ossman char *buffer; 7852134a922SPierre Ossman unsigned long flags; 7862134a922SPierre Ossman 78747fa9613SRussell King if (data->flags & MMC_DATA_READ) { 78847fa9613SRussell King bool has_unaligned = false; 78947fa9613SRussell King 790de0b65a7SRussell King /* Do a quick scan of the SG list for any unaligned mappings */ 791de0b65a7SRussell King for_each_sg(data->sg, sg, host->sg_count, i) 79204a5ae6fSAdrian Hunter if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 793de0b65a7SRussell King has_unaligned = true; 794de0b65a7SRussell King break; 795de0b65a7SRussell King } 796de0b65a7SRussell King 79747fa9613SRussell King if (has_unaligned) { 7982134a922SPierre Ossman dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 799f55c98f7SRussell King data->sg_len, DMA_FROM_DEVICE); 8002134a922SPierre Ossman 8012134a922SPierre Ossman align = host->align_buffer; 8022134a922SPierre Ossman 8032134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 80404a5ae6fSAdrian Hunter if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 80504a5ae6fSAdrian Hunter size = SDHCI_ADMA2_ALIGN - 80604a5ae6fSAdrian Hunter (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 8072134a922SPierre Ossman 8082134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 8092134a922SPierre Ossman memcpy(buffer, align, size); 8102134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 8112134a922SPierre Ossman 81204a5ae6fSAdrian Hunter align += SDHCI_ADMA2_ALIGN; 8132134a922SPierre Ossman } 8142134a922SPierre Ossman } 8152134a922SPierre Ossman } 81647fa9613SRussell King } 8172134a922SPierre Ossman } 8182134a922SPierre Ossman 819917a0c52SChunyan Zhang static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) 820bd9b9027SLinus Walleij { 821bd9b9027SLinus Walleij if (host->bounce_buffer) 822bd9b9027SLinus Walleij return host->bounce_addr; 823bd9b9027SLinus Walleij else 824bd9b9027SLinus Walleij return sg_dma_address(host->data->sg); 825bd9b9027SLinus Walleij } 826bd9b9027SLinus Walleij 827917a0c52SChunyan Zhang static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) 828917a0c52SChunyan Zhang { 829917a0c52SChunyan Zhang if (host->v4_mode) { 830917a0c52SChunyan Zhang sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); 831917a0c52SChunyan Zhang if (host->flags & SDHCI_USE_64_BIT_DMA) 832917a0c52SChunyan Zhang sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); 833917a0c52SChunyan Zhang } else { 834917a0c52SChunyan Zhang sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); 835917a0c52SChunyan Zhang } 836917a0c52SChunyan Zhang } 837917a0c52SChunyan Zhang 8380bb28d73SAdrian Hunter static unsigned int sdhci_target_timeout(struct sdhci_host *host, 8390bb28d73SAdrian Hunter struct mmc_command *cmd, 8400bb28d73SAdrian Hunter struct mmc_data *data) 8410bb28d73SAdrian Hunter { 8420bb28d73SAdrian Hunter unsigned int target_timeout; 8430bb28d73SAdrian Hunter 8440bb28d73SAdrian Hunter /* timeout in us */ 8450bb28d73SAdrian Hunter if (!data) { 8460bb28d73SAdrian Hunter target_timeout = cmd->busy_timeout * 1000; 8470bb28d73SAdrian Hunter } else { 8480bb28d73SAdrian Hunter target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 8490bb28d73SAdrian Hunter if (host->clock && data->timeout_clks) { 8500bb28d73SAdrian Hunter unsigned long long val; 8510bb28d73SAdrian Hunter 8520bb28d73SAdrian Hunter /* 8530bb28d73SAdrian Hunter * data->timeout_clks is in units of clock cycles. 8540bb28d73SAdrian Hunter * host->clock is in Hz. target_timeout is in us. 8550bb28d73SAdrian Hunter * Hence, us = 1000000 * cycles / Hz. Round up. 8560bb28d73SAdrian Hunter */ 8570bb28d73SAdrian Hunter val = 1000000ULL * data->timeout_clks; 8580bb28d73SAdrian Hunter if (do_div(val, host->clock)) 8590bb28d73SAdrian Hunter target_timeout++; 8600bb28d73SAdrian Hunter target_timeout += val; 8610bb28d73SAdrian Hunter } 8620bb28d73SAdrian Hunter } 8630bb28d73SAdrian Hunter 8640bb28d73SAdrian Hunter return target_timeout; 8650bb28d73SAdrian Hunter } 8660bb28d73SAdrian Hunter 867fc1fa1b7SKishon Vijay Abraham I static void sdhci_calc_sw_timeout(struct sdhci_host *host, 868fc1fa1b7SKishon Vijay Abraham I struct mmc_command *cmd) 869fc1fa1b7SKishon Vijay Abraham I { 870fc1fa1b7SKishon Vijay Abraham I struct mmc_data *data = cmd->data; 871fc1fa1b7SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 872fc1fa1b7SKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 873fc1fa1b7SKishon Vijay Abraham I unsigned char bus_width = 1 << ios->bus_width; 874fc1fa1b7SKishon Vijay Abraham I unsigned int blksz; 875fc1fa1b7SKishon Vijay Abraham I unsigned int freq; 876fc1fa1b7SKishon Vijay Abraham I u64 target_timeout; 877fc1fa1b7SKishon Vijay Abraham I u64 transfer_time; 878fc1fa1b7SKishon Vijay Abraham I 879fc1fa1b7SKishon Vijay Abraham I target_timeout = sdhci_target_timeout(host, cmd, data); 880fc1fa1b7SKishon Vijay Abraham I target_timeout *= NSEC_PER_USEC; 881fc1fa1b7SKishon Vijay Abraham I 882fc1fa1b7SKishon Vijay Abraham I if (data) { 883fc1fa1b7SKishon Vijay Abraham I blksz = data->blksz; 884fc1fa1b7SKishon Vijay Abraham I freq = host->mmc->actual_clock ? : host->clock; 885fc1fa1b7SKishon Vijay Abraham I transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width); 886fc1fa1b7SKishon Vijay Abraham I do_div(transfer_time, freq); 887fc1fa1b7SKishon Vijay Abraham I /* multiply by '2' to account for any unknowns */ 888fc1fa1b7SKishon Vijay Abraham I transfer_time = transfer_time * 2; 889fc1fa1b7SKishon Vijay Abraham I /* calculate timeout for the entire data */ 890fc1fa1b7SKishon Vijay Abraham I host->data_timeout = data->blocks * target_timeout + 891fc1fa1b7SKishon Vijay Abraham I transfer_time; 892fc1fa1b7SKishon Vijay Abraham I } else { 893fc1fa1b7SKishon Vijay Abraham I host->data_timeout = target_timeout; 894fc1fa1b7SKishon Vijay Abraham I } 895fc1fa1b7SKishon Vijay Abraham I 896fc1fa1b7SKishon Vijay Abraham I if (host->data_timeout) 897fc1fa1b7SKishon Vijay Abraham I host->data_timeout += MMC_CMD_TRANSFER_TIME; 898fc1fa1b7SKishon Vijay Abraham I } 899fc1fa1b7SKishon Vijay Abraham I 900a999fd93SAdrian Hunter static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd, 901a999fd93SAdrian Hunter bool *too_big) 9021c6a0718SPierre Ossman { 9031c6a0718SPierre Ossman u8 count; 904401059dfSBOUGH CHEN struct mmc_data *data; 9051c6a0718SPierre Ossman unsigned target_timeout, current_timeout; 9061c6a0718SPierre Ossman 907a999fd93SAdrian Hunter *too_big = true; 908a999fd93SAdrian Hunter 909ee53ab5dSPierre Ossman /* 910ee53ab5dSPierre Ossman * If the host controller provides us with an incorrect timeout 911ee53ab5dSPierre Ossman * value, just skip the check and use 0xE. The hardware may take 912ee53ab5dSPierre Ossman * longer to time out, but that's much better than having a too-short 913ee53ab5dSPierre Ossman * timeout value. 914ee53ab5dSPierre Ossman */ 91511a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 916ee53ab5dSPierre Ossman return 0xE; 917e538fbe8SPierre Ossman 918401059dfSBOUGH CHEN /* Unspecified command, asume max */ 919401059dfSBOUGH CHEN if (cmd == NULL) 920401059dfSBOUGH CHEN return 0xE; 921401059dfSBOUGH CHEN 922401059dfSBOUGH CHEN data = cmd->data; 923a3c7778fSAndrei Warkentin /* Unspecified timeout, assume max */ 9241d4d7744SUlf Hansson if (!data && !cmd->busy_timeout) 925a3c7778fSAndrei Warkentin return 0xE; 926a3c7778fSAndrei Warkentin 9271c6a0718SPierre Ossman /* timeout in us */ 9280bb28d73SAdrian Hunter target_timeout = sdhci_target_timeout(host, cmd, data); 9291c6a0718SPierre Ossman 9301c6a0718SPierre Ossman /* 9311c6a0718SPierre Ossman * Figure out needed cycles. 9321c6a0718SPierre Ossman * We do this in steps in order to fit inside a 32 bit int. 9331c6a0718SPierre Ossman * The first step is the minimum timeout, which will have a 9341c6a0718SPierre Ossman * minimum resolution of 6 bits: 9351c6a0718SPierre Ossman * (1) 2^13*1000 > 2^22, 9361c6a0718SPierre Ossman * (2) host->timeout_clk < 2^16 9371c6a0718SPierre Ossman * => 9381c6a0718SPierre Ossman * (1) / (2) > 2^6 9391c6a0718SPierre Ossman */ 9401c6a0718SPierre Ossman count = 0; 9411c6a0718SPierre Ossman current_timeout = (1 << 13) * 1000 / host->timeout_clk; 9421c6a0718SPierre Ossman while (current_timeout < target_timeout) { 9431c6a0718SPierre Ossman count++; 9441c6a0718SPierre Ossman current_timeout <<= 1; 9451c6a0718SPierre Ossman if (count >= 0xF) 9461c6a0718SPierre Ossman break; 9471c6a0718SPierre Ossman } 9481c6a0718SPierre Ossman 9491c6a0718SPierre Ossman if (count >= 0xF) { 950a999fd93SAdrian Hunter if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)) 951f421865dSAdrian Hunter DBG("Too large timeout 0x%x requested for CMD%d!\n", 952f421865dSAdrian Hunter count, cmd->opcode); 9531c6a0718SPierre Ossman count = 0xE; 954a999fd93SAdrian Hunter } else { 955a999fd93SAdrian Hunter *too_big = false; 9561c6a0718SPierre Ossman } 9571c6a0718SPierre Ossman 958ee53ab5dSPierre Ossman return count; 959ee53ab5dSPierre Ossman } 960ee53ab5dSPierre Ossman 9616aa943abSAnton Vorontsov static void sdhci_set_transfer_irqs(struct sdhci_host *host) 9626aa943abSAnton Vorontsov { 9636aa943abSAnton Vorontsov u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 9646aa943abSAnton Vorontsov u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 9656aa943abSAnton Vorontsov 9666aa943abSAnton Vorontsov if (host->flags & SDHCI_REQ_USE_DMA) 967b537f94cSRussell King host->ier = (host->ier & ~pio_irqs) | dma_irqs; 9686aa943abSAnton Vorontsov else 969b537f94cSRussell King host->ier = (host->ier & ~dma_irqs) | pio_irqs; 970b537f94cSRussell King 971af849c86SAdrian Hunter if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12)) 972af849c86SAdrian Hunter host->ier |= SDHCI_INT_AUTO_CMD_ERR; 973af849c86SAdrian Hunter else 974af849c86SAdrian Hunter host->ier &= ~SDHCI_INT_AUTO_CMD_ERR; 975af849c86SAdrian Hunter 976b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 977b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 9786aa943abSAnton Vorontsov } 9796aa943abSAnton Vorontsov 980a999fd93SAdrian Hunter static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable) 981a999fd93SAdrian Hunter { 982a999fd93SAdrian Hunter if (enable) 983a999fd93SAdrian Hunter host->ier |= SDHCI_INT_DATA_TIMEOUT; 984a999fd93SAdrian Hunter else 985a999fd93SAdrian Hunter host->ier &= ~SDHCI_INT_DATA_TIMEOUT; 986a999fd93SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 987a999fd93SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 988a999fd93SAdrian Hunter } 989a999fd93SAdrian Hunter 990b45e668aSAisheng Dong static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 991ee53ab5dSPierre Ossman { 992ee53ab5dSPierre Ossman u8 count; 993b45e668aSAisheng Dong 994b45e668aSAisheng Dong if (host->ops->set_timeout) { 995b45e668aSAisheng Dong host->ops->set_timeout(host, cmd); 996b45e668aSAisheng Dong } else { 997a999fd93SAdrian Hunter bool too_big = false; 998a999fd93SAdrian Hunter 999a999fd93SAdrian Hunter count = sdhci_calc_timeout(host, cmd, &too_big); 1000a999fd93SAdrian Hunter 1001a999fd93SAdrian Hunter if (too_big && 1002a999fd93SAdrian Hunter host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) { 1003fc1fa1b7SKishon Vijay Abraham I sdhci_calc_sw_timeout(host, cmd); 1004a999fd93SAdrian Hunter sdhci_set_data_timeout_irq(host, false); 1005a999fd93SAdrian Hunter } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) { 1006a999fd93SAdrian Hunter sdhci_set_data_timeout_irq(host, true); 1007a999fd93SAdrian Hunter } 1008a999fd93SAdrian Hunter 1009b45e668aSAisheng Dong sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 1010b45e668aSAisheng Dong } 1011b45e668aSAisheng Dong } 1012b45e668aSAisheng Dong 1013b45e668aSAisheng Dong static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 1014b45e668aSAisheng Dong { 1015a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 1016ee53ab5dSPierre Ossman 1017fc1fa1b7SKishon Vijay Abraham I host->data_timeout = 0; 1018fc1fa1b7SKishon Vijay Abraham I 101956a590dcSAdrian Hunter if (sdhci_data_line_cmd(cmd)) 1020b45e668aSAisheng Dong sdhci_set_timeout(host, cmd); 1021a3c7778fSAndrei Warkentin 1022a3c7778fSAndrei Warkentin if (!data) 1023ee53ab5dSPierre Ossman return; 1024ee53ab5dSPierre Ossman 102543dea098SAdrian Hunter WARN_ON(host->data); 102643dea098SAdrian Hunter 1027ee53ab5dSPierre Ossman /* Sanity checks */ 1028ee53ab5dSPierre Ossman BUG_ON(data->blksz * data->blocks > 524288); 1029ee53ab5dSPierre Ossman BUG_ON(data->blksz > host->mmc->max_blk_size); 1030ee53ab5dSPierre Ossman BUG_ON(data->blocks > 65535); 1031ee53ab5dSPierre Ossman 1032ee53ab5dSPierre Ossman host->data = data; 1033ee53ab5dSPierre Ossman host->data_early = 0; 1034f6a03cbfSMikko Vinni host->data->bytes_xfered = 0; 1035ee53ab5dSPierre Ossman 1036fce14421SRussell King if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 1037fce14421SRussell King struct scatterlist *sg; 1038fce14421SRussell King unsigned int length_mask, offset_mask; 1039fce14421SRussell King int i; 1040fce14421SRussell King 1041c9fddbc4SPierre Ossman host->flags |= SDHCI_REQ_USE_DMA; 1042c9fddbc4SPierre Ossman 10432134a922SPierre Ossman /* 10442134a922SPierre Ossman * FIXME: This doesn't account for merging when mapping the 10452134a922SPierre Ossman * scatterlist. 1046df953925SRussell King * 1047df953925SRussell King * The assumption here being that alignment and lengths are 1048df953925SRussell King * the same after DMA mapping to device address space. 10492134a922SPierre Ossman */ 1050a0eaf0f9SRussell King length_mask = 0; 1051df953925SRussell King offset_mask = 0; 10522134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 1053df953925SRussell King if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 1054a0eaf0f9SRussell King length_mask = 3; 1055df953925SRussell King /* 1056df953925SRussell King * As we use up to 3 byte chunks to work 1057df953925SRussell King * around alignment problems, we need to 1058df953925SRussell King * check the offset as well. 1059df953925SRussell King */ 1060df953925SRussell King offset_mask = 3; 1061df953925SRussell King } 10622134a922SPierre Ossman } else { 10632134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 1064a0eaf0f9SRussell King length_mask = 3; 1065df953925SRussell King if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 1066df953925SRussell King offset_mask = 3; 10672134a922SPierre Ossman } 10682134a922SPierre Ossman 1069df953925SRussell King if (unlikely(length_mask | offset_mask)) { 10702134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 1071a0eaf0f9SRussell King if (sg->length & length_mask) { 10722e4456f0SMarek Vasut DBG("Reverting to PIO because of transfer size (%d)\n", 10732134a922SPierre Ossman sg->length); 1074c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 10752134a922SPierre Ossman break; 10762134a922SPierre Ossman } 1077a0eaf0f9SRussell King if (sg->offset & offset_mask) { 10782e4456f0SMarek Vasut DBG("Reverting to PIO because of bad alignment\n"); 1079c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 10802134a922SPierre Ossman break; 10812134a922SPierre Ossman } 10822134a922SPierre Ossman } 10832134a922SPierre Ossman } 10842134a922SPierre Ossman } 10852134a922SPierre Ossman 10868f1934ceSPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 1087c0999b72SRussell King int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 10888f1934ceSPierre Ossman 108962a7f368SJiri Slaby if (sg_cnt <= 0) { 10908f1934ceSPierre Ossman /* 10918f1934ceSPierre Ossman * This only happens when someone fed 10928f1934ceSPierre Ossman * us an invalid request. 10938f1934ceSPierre Ossman */ 10948f1934ceSPierre Ossman WARN_ON(1); 1095ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 109660c64762SRussell King } else if (host->flags & SDHCI_USE_ADMA) { 109760c64762SRussell King sdhci_adma_table_pre(host, data, sg_cnt); 109860c64762SRussell King 109960c64762SRussell King sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 110060c64762SRussell King if (host->flags & SDHCI_USE_64_BIT_DMA) 110160c64762SRussell King sdhci_writel(host, 110260c64762SRussell King (u64)host->adma_addr >> 32, 110360c64762SRussell King SDHCI_ADMA_ADDRESS_HI); 11048f1934ceSPierre Ossman } else { 1105719a61b4SPierre Ossman WARN_ON(sg_cnt != 1); 1106917a0c52SChunyan Zhang sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); 11078f1934ceSPierre Ossman } 11088f1934ceSPierre Ossman } 11098f1934ceSPierre Ossman 1110685e444bSChunyan Zhang sdhci_config_dma(host); 1111c9fddbc4SPierre Ossman 11128f1934ceSPierre Ossman if (!(host->flags & SDHCI_REQ_USE_DMA)) { 1113da60a91dSSebastian Andrzej Siewior int flags; 1114da60a91dSSebastian Andrzej Siewior 1115da60a91dSSebastian Andrzej Siewior flags = SG_MITER_ATOMIC; 1116da60a91dSSebastian Andrzej Siewior if (host->data->flags & MMC_DATA_READ) 1117da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_TO_SG; 1118da60a91dSSebastian Andrzej Siewior else 1119da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_FROM_SG; 1120da60a91dSSebastian Andrzej Siewior sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 11217659150cSPierre Ossman host->blocks = data->blocks; 11221c6a0718SPierre Ossman } 11231c6a0718SPierre Ossman 11246aa943abSAnton Vorontsov sdhci_set_transfer_irqs(host); 11256aa943abSAnton Vorontsov 1126f6a03cbfSMikko Vinni /* Set the DMA boundary value and block size */ 1127c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), 1128c846a00fSSrinivas Kandagatla SDHCI_BLOCK_SIZE); 1129e65953d4SChunyan Zhang 1130e65953d4SChunyan Zhang /* 1131e65953d4SChunyan Zhang * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count 1132e65953d4SChunyan Zhang * can be supported, in that case 16-bit block count register must be 0. 1133e65953d4SChunyan Zhang */ 1134e65953d4SChunyan Zhang if (host->version >= SDHCI_SPEC_410 && host->v4_mode && 1135e65953d4SChunyan Zhang (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { 1136e65953d4SChunyan Zhang if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) 1137e65953d4SChunyan Zhang sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); 1138e65953d4SChunyan Zhang sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); 1139e65953d4SChunyan Zhang } else { 11404e4141a5SAnton Vorontsov sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 11411c6a0718SPierre Ossman } 1142e65953d4SChunyan Zhang } 11431c6a0718SPierre Ossman 11440293d501SAdrian Hunter static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 11450293d501SAdrian Hunter struct mmc_request *mrq) 11460293d501SAdrian Hunter { 114720845befSAdrian Hunter return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 114820845befSAdrian Hunter !mrq->cap_cmd_during_tfr; 11490293d501SAdrian Hunter } 11500293d501SAdrian Hunter 1151427b6514SChunyan Zhang static inline void sdhci_auto_cmd_select(struct sdhci_host *host, 1152427b6514SChunyan Zhang struct mmc_command *cmd, 1153427b6514SChunyan Zhang u16 *mode) 1154427b6514SChunyan Zhang { 1155427b6514SChunyan Zhang bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && 1156427b6514SChunyan Zhang (cmd->opcode != SD_IO_RW_EXTENDED); 1157427b6514SChunyan Zhang bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); 1158427b6514SChunyan Zhang u16 ctrl2; 1159427b6514SChunyan Zhang 1160427b6514SChunyan Zhang /* 1161427b6514SChunyan Zhang * In case of Version 4.10 or later, use of 'Auto CMD Auto 1162427b6514SChunyan Zhang * Select' is recommended rather than use of 'Auto CMD12 1163427b6514SChunyan Zhang * Enable' or 'Auto CMD23 Enable'. 1164427b6514SChunyan Zhang */ 1165427b6514SChunyan Zhang if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { 1166427b6514SChunyan Zhang *mode |= SDHCI_TRNS_AUTO_SEL; 1167427b6514SChunyan Zhang 1168427b6514SChunyan Zhang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1169427b6514SChunyan Zhang if (use_cmd23) 1170427b6514SChunyan Zhang ctrl2 |= SDHCI_CMD23_ENABLE; 1171427b6514SChunyan Zhang else 1172427b6514SChunyan Zhang ctrl2 &= ~SDHCI_CMD23_ENABLE; 1173427b6514SChunyan Zhang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 1174427b6514SChunyan Zhang 1175427b6514SChunyan Zhang return; 1176427b6514SChunyan Zhang } 1177427b6514SChunyan Zhang 1178427b6514SChunyan Zhang /* 1179427b6514SChunyan Zhang * If we are sending CMD23, CMD12 never gets sent 1180427b6514SChunyan Zhang * on successful completion (so no Auto-CMD12). 1181427b6514SChunyan Zhang */ 1182427b6514SChunyan Zhang if (use_cmd12) 1183427b6514SChunyan Zhang *mode |= SDHCI_TRNS_AUTO_CMD12; 1184427b6514SChunyan Zhang else if (use_cmd23) 1185427b6514SChunyan Zhang *mode |= SDHCI_TRNS_AUTO_CMD23; 1186427b6514SChunyan Zhang } 1187427b6514SChunyan Zhang 11881c6a0718SPierre Ossman static void sdhci_set_transfer_mode(struct sdhci_host *host, 1189e89d456fSAndrei Warkentin struct mmc_command *cmd) 11901c6a0718SPierre Ossman { 1191d3fc5d71SVincent Yang u16 mode = 0; 1192e89d456fSAndrei Warkentin struct mmc_data *data = cmd->data; 11931c6a0718SPierre Ossman 11942b558c13SDong Aisheng if (data == NULL) { 11959b8ffea6SVincent Wan if (host->quirks2 & 11969b8ffea6SVincent Wan SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 11970086fc21Sernest.zhang /* must not clear SDHCI_TRANSFER_MODE when tuning */ 11980086fc21Sernest.zhang if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 11999b8ffea6SVincent Wan sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 12009b8ffea6SVincent Wan } else { 12012b558c13SDong Aisheng /* clear Auto CMD settings for no data CMDs */ 12022b558c13SDong Aisheng mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 12032b558c13SDong Aisheng sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 12042b558c13SDong Aisheng SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 12059b8ffea6SVincent Wan } 12061c6a0718SPierre Ossman return; 12072b558c13SDong Aisheng } 12081c6a0718SPierre Ossman 1209e538fbe8SPierre Ossman WARN_ON(!host->data); 1210e538fbe8SPierre Ossman 1211d3fc5d71SVincent Yang if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 12121c6a0718SPierre Ossman mode = SDHCI_TRNS_BLK_CNT_EN; 1213d3fc5d71SVincent Yang 1214e89d456fSAndrei Warkentin if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 1215d3fc5d71SVincent Yang mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 1216427b6514SChunyan Zhang sdhci_auto_cmd_select(host, cmd, &mode); 1217427b6514SChunyan Zhang if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) 1218a4c73abaSAdrian Hunter sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 1219c4512f79SJerry Huang } 12208edf6371SAndrei Warkentin 12211c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 12221c6a0718SPierre Ossman mode |= SDHCI_TRNS_READ; 1223c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) 12241c6a0718SPierre Ossman mode |= SDHCI_TRNS_DMA; 12251c6a0718SPierre Ossman 12264e4141a5SAnton Vorontsov sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 12271c6a0718SPierre Ossman } 12281c6a0718SPierre Ossman 12290cc563ceSAdrian Hunter static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 12300cc563ceSAdrian Hunter { 12310cc563ceSAdrian Hunter return (!(host->flags & SDHCI_DEVICE_DEAD) && 12320cc563ceSAdrian Hunter ((mrq->cmd && mrq->cmd->error) || 12330cc563ceSAdrian Hunter (mrq->sbc && mrq->sbc->error) || 12344bf78099SAdrian Hunter (mrq->data && mrq->data->stop && mrq->data->stop->error) || 12350cc563ceSAdrian Hunter (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 12360cc563ceSAdrian Hunter } 12370cc563ceSAdrian Hunter 12384e9f8fe5SAdrian Hunter static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 12394e9f8fe5SAdrian Hunter { 12404e9f8fe5SAdrian Hunter int i; 12414e9f8fe5SAdrian Hunter 12422e72ab9bSAdrian Hunter if (host->cmd && host->cmd->mrq == mrq) 12432e72ab9bSAdrian Hunter host->cmd = NULL; 12442e72ab9bSAdrian Hunter 12452e72ab9bSAdrian Hunter if (host->data_cmd && host->data_cmd->mrq == mrq) 12462e72ab9bSAdrian Hunter host->data_cmd = NULL; 12472e72ab9bSAdrian Hunter 12482e72ab9bSAdrian Hunter if (host->data && host->data->mrq == mrq) 12492e72ab9bSAdrian Hunter host->data = NULL; 12502e72ab9bSAdrian Hunter 12512e72ab9bSAdrian Hunter if (sdhci_needs_reset(host, mrq)) 12522e72ab9bSAdrian Hunter host->pending_reset = true; 12532e72ab9bSAdrian Hunter 12544e9f8fe5SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 12554e9f8fe5SAdrian Hunter if (host->mrqs_done[i] == mrq) { 12564e9f8fe5SAdrian Hunter WARN_ON(1); 12574e9f8fe5SAdrian Hunter return; 12584e9f8fe5SAdrian Hunter } 12594e9f8fe5SAdrian Hunter } 12604e9f8fe5SAdrian Hunter 12614e9f8fe5SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 12624e9f8fe5SAdrian Hunter if (!host->mrqs_done[i]) { 12634e9f8fe5SAdrian Hunter host->mrqs_done[i] = mrq; 12644e9f8fe5SAdrian Hunter break; 12654e9f8fe5SAdrian Hunter } 12664e9f8fe5SAdrian Hunter } 12674e9f8fe5SAdrian Hunter 12684e9f8fe5SAdrian Hunter WARN_ON(i >= SDHCI_MAX_MRQS); 12694e9f8fe5SAdrian Hunter 1270e9a07299SAdrian Hunter sdhci_del_timer(host, mrq); 1271e9a07299SAdrian Hunter 1272e9a07299SAdrian Hunter if (!sdhci_has_requests(host)) 1273e9a07299SAdrian Hunter sdhci_led_deactivate(host); 12744e9f8fe5SAdrian Hunter } 12754e9f8fe5SAdrian Hunter 1276a6d3bdd5SAdrian Hunter static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 1277a6d3bdd5SAdrian Hunter { 12784e9f8fe5SAdrian Hunter __sdhci_finish_mrq(host, mrq); 12792e72ab9bSAdrian Hunter 1280c07a48c2SAdrian Hunter queue_work(host->complete_wq, &host->complete_work); 1281a6d3bdd5SAdrian Hunter } 1282a6d3bdd5SAdrian Hunter 12831c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *host) 12841c6a0718SPierre Ossman { 128533a57adbSAdrian Hunter struct mmc_command *data_cmd = host->data_cmd; 128633a57adbSAdrian Hunter struct mmc_data *data = host->data; 12871c6a0718SPierre Ossman 12881c6a0718SPierre Ossman host->data = NULL; 12897c89a3d9SAdrian Hunter host->data_cmd = NULL; 12901c6a0718SPierre Ossman 12914bf78099SAdrian Hunter /* 12924bf78099SAdrian Hunter * The controller needs a reset of internal state machines upon error 12934bf78099SAdrian Hunter * conditions. 12944bf78099SAdrian Hunter */ 12954bf78099SAdrian Hunter if (data->error) { 12964bf78099SAdrian Hunter if (!host->cmd || host->cmd == data_cmd) 12974bf78099SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD); 12984bf78099SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_DATA); 12994bf78099SAdrian Hunter } 13004bf78099SAdrian Hunter 1301add8913dSRussell King if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1302add8913dSRussell King (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 13032134a922SPierre Ossman sdhci_adma_table_post(host, data); 1304f55c98f7SRussell King 13051c6a0718SPierre Ossman /* 1306c9b74c5bSPierre Ossman * The specification states that the block count register must 1307c9b74c5bSPierre Ossman * be updated, but it does not specify at what point in the 1308c9b74c5bSPierre Ossman * data flow. That makes the register entirely useless to read 1309c9b74c5bSPierre Ossman * back so we have to assume that nothing made it to the card 1310c9b74c5bSPierre Ossman * in the event of an error. 13111c6a0718SPierre Ossman */ 1312c9b74c5bSPierre Ossman if (data->error) 1313c9b74c5bSPierre Ossman data->bytes_xfered = 0; 13141c6a0718SPierre Ossman else 1315c9b74c5bSPierre Ossman data->bytes_xfered = data->blksz * data->blocks; 13161c6a0718SPierre Ossman 1317e89d456fSAndrei Warkentin /* 1318e89d456fSAndrei Warkentin * Need to send CMD12 if - 1319e89d456fSAndrei Warkentin * a) open-ended multiblock transfer (no CMD23) 1320e89d456fSAndrei Warkentin * b) error in multiblock transfer 1321e89d456fSAndrei Warkentin */ 1322e89d456fSAndrei Warkentin if (data->stop && 1323e89d456fSAndrei Warkentin (data->error || 1324a4c73abaSAdrian Hunter !data->mrq->sbc)) { 132520845befSAdrian Hunter /* 132620845befSAdrian Hunter * 'cap_cmd_during_tfr' request must not use the command line 132720845befSAdrian Hunter * after mmc_command_done() has been called. It is upper layer's 132820845befSAdrian Hunter * responsibility to send the stop command if required. 132920845befSAdrian Hunter */ 133020845befSAdrian Hunter if (data->mrq->cap_cmd_during_tfr) { 133119d2f695SAdrian Hunter __sdhci_finish_mrq(host, data->mrq); 133220845befSAdrian Hunter } else { 13338842fd17SAdrian Hunter /* Avoid triggering warning in sdhci_send_command() */ 13348842fd17SAdrian Hunter host->cmd = NULL; 13351c6a0718SPierre Ossman sdhci_send_command(host, data->stop); 133620845befSAdrian Hunter } 1337a6d3bdd5SAdrian Hunter } else { 133819d2f695SAdrian Hunter __sdhci_finish_mrq(host, data->mrq); 1339a6d3bdd5SAdrian Hunter } 13401c6a0718SPierre Ossman } 13411c6a0718SPierre Ossman 1342c0e55129SDong Aisheng void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 13431c6a0718SPierre Ossman { 13441c6a0718SPierre Ossman int flags; 13451c6a0718SPierre Ossman u32 mask; 13461c6a0718SPierre Ossman unsigned long timeout; 13471c6a0718SPierre Ossman 13481c6a0718SPierre Ossman WARN_ON(host->cmd); 13491c6a0718SPierre Ossman 135096776200SRussell King /* Initially, a command has no error */ 135196776200SRussell King cmd->error = 0; 135296776200SRussell King 1353fc605f1dSAdrian Hunter if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 1354fc605f1dSAdrian Hunter cmd->opcode == MMC_STOP_TRANSMISSION) 1355fc605f1dSAdrian Hunter cmd->flags |= MMC_RSP_BUSY; 1356fc605f1dSAdrian Hunter 13571c6a0718SPierre Ossman /* Wait max 10 ms */ 13581c6a0718SPierre Ossman timeout = 10; 13591c6a0718SPierre Ossman 13601c6a0718SPierre Ossman mask = SDHCI_CMD_INHIBIT; 136156a590dcSAdrian Hunter if (sdhci_data_line_cmd(cmd)) 13621c6a0718SPierre Ossman mask |= SDHCI_DATA_INHIBIT; 13631c6a0718SPierre Ossman 13641c6a0718SPierre Ossman /* We shouldn't wait for data inihibit for stop commands, even 13651c6a0718SPierre Ossman though they might use busy signaling */ 1366a4c73abaSAdrian Hunter if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 13671c6a0718SPierre Ossman mask &= ~SDHCI_DATA_INHIBIT; 13681c6a0718SPierre Ossman 13694e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 13701c6a0718SPierre Ossman if (timeout == 0) { 13712e4456f0SMarek Vasut pr_err("%s: Controller never released inhibit bit(s).\n", 13722e4456f0SMarek Vasut mmc_hostname(host->mmc)); 13731c6a0718SPierre Ossman sdhci_dumpregs(host); 137417b0429dSPierre Ossman cmd->error = -EIO; 1375a6d3bdd5SAdrian Hunter sdhci_finish_mrq(host, cmd->mrq); 13761c6a0718SPierre Ossman return; 13771c6a0718SPierre Ossman } 13781c6a0718SPierre Ossman timeout--; 13791c6a0718SPierre Ossman mdelay(1); 13801c6a0718SPierre Ossman } 13811c6a0718SPierre Ossman 13821c6a0718SPierre Ossman host->cmd = cmd; 138356a590dcSAdrian Hunter if (sdhci_data_line_cmd(cmd)) { 13847c89a3d9SAdrian Hunter WARN_ON(host->data_cmd); 13857c89a3d9SAdrian Hunter host->data_cmd = cmd; 13867c89a3d9SAdrian Hunter } 13871c6a0718SPierre Ossman 1388a3c7778fSAndrei Warkentin sdhci_prepare_data(host, cmd); 13891c6a0718SPierre Ossman 13904e4141a5SAnton Vorontsov sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 13911c6a0718SPierre Ossman 1392e89d456fSAndrei Warkentin sdhci_set_transfer_mode(host, cmd); 13931c6a0718SPierre Ossman 13941c6a0718SPierre Ossman if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1395a3c76eb9SGirish K S pr_err("%s: Unsupported response type!\n", 13961c6a0718SPierre Ossman mmc_hostname(host->mmc)); 139717b0429dSPierre Ossman cmd->error = -EINVAL; 1398a6d3bdd5SAdrian Hunter sdhci_finish_mrq(host, cmd->mrq); 13991c6a0718SPierre Ossman return; 14001c6a0718SPierre Ossman } 14011c6a0718SPierre Ossman 14021c6a0718SPierre Ossman if (!(cmd->flags & MMC_RSP_PRESENT)) 14031c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_NONE; 14041c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_136) 14051c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_LONG; 14061c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_BUSY) 14071c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT_BUSY; 14081c6a0718SPierre Ossman else 14091c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT; 14101c6a0718SPierre Ossman 14111c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_CRC) 14121c6a0718SPierre Ossman flags |= SDHCI_CMD_CRC; 14131c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_OPCODE) 14141c6a0718SPierre Ossman flags |= SDHCI_CMD_INDEX; 1415b513ea25SArindam Nath 1416b513ea25SArindam Nath /* CMD19 is special in that the Data Present Select should be set */ 1417069c9f14SGirish K S if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1418069c9f14SGirish K S cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 14191c6a0718SPierre Ossman flags |= SDHCI_CMD_DATA; 14201c6a0718SPierre Ossman 1421fc1fa1b7SKishon Vijay Abraham I timeout = jiffies; 1422fc1fa1b7SKishon Vijay Abraham I if (host->data_timeout) 1423fc1fa1b7SKishon Vijay Abraham I timeout += nsecs_to_jiffies(host->data_timeout); 1424fc1fa1b7SKishon Vijay Abraham I else if (!cmd->data && cmd->busy_timeout > 9000) 1425fc1fa1b7SKishon Vijay Abraham I timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1426fc1fa1b7SKishon Vijay Abraham I else 1427fc1fa1b7SKishon Vijay Abraham I timeout += 10 * HZ; 1428fc1fa1b7SKishon Vijay Abraham I sdhci_mod_timer(host, cmd->mrq, timeout); 1429fc1fa1b7SKishon Vijay Abraham I 14304e4141a5SAnton Vorontsov sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 14311c6a0718SPierre Ossman } 1432c0e55129SDong Aisheng EXPORT_SYMBOL_GPL(sdhci_send_command); 14331c6a0718SPierre Ossman 14344a5fc119SAdrian Hunter static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd) 14354a5fc119SAdrian Hunter { 14364a5fc119SAdrian Hunter int i, reg; 14374a5fc119SAdrian Hunter 14384a5fc119SAdrian Hunter for (i = 0; i < 4; i++) { 14394a5fc119SAdrian Hunter reg = SDHCI_RESPONSE + (3 - i) * 4; 14404a5fc119SAdrian Hunter cmd->resp[i] = sdhci_readl(host, reg); 14414a5fc119SAdrian Hunter } 14424a5fc119SAdrian Hunter 14431284c248SKishon Vijay Abraham I if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC) 14441284c248SKishon Vijay Abraham I return; 14451284c248SKishon Vijay Abraham I 14464a5fc119SAdrian Hunter /* CRC is stripped so we need to do some shifting */ 14474a5fc119SAdrian Hunter for (i = 0; i < 4; i++) { 14484a5fc119SAdrian Hunter cmd->resp[i] <<= 8; 14494a5fc119SAdrian Hunter if (i != 3) 14504a5fc119SAdrian Hunter cmd->resp[i] |= cmd->resp[i + 1] >> 24; 14514a5fc119SAdrian Hunter } 14524a5fc119SAdrian Hunter } 14534a5fc119SAdrian Hunter 14541c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *host) 14551c6a0718SPierre Ossman { 1456e0a5640aSAdrian Hunter struct mmc_command *cmd = host->cmd; 14571c6a0718SPierre Ossman 1458e0a5640aSAdrian Hunter host->cmd = NULL; 1459e0a5640aSAdrian Hunter 1460e0a5640aSAdrian Hunter if (cmd->flags & MMC_RSP_PRESENT) { 1461e0a5640aSAdrian Hunter if (cmd->flags & MMC_RSP_136) { 14624a5fc119SAdrian Hunter sdhci_read_rsp_136(host, cmd); 14631c6a0718SPierre Ossman } else { 1464e0a5640aSAdrian Hunter cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 14651c6a0718SPierre Ossman } 14661c6a0718SPierre Ossman } 14671c6a0718SPierre Ossman 146820845befSAdrian Hunter if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 146920845befSAdrian Hunter mmc_command_done(host->mmc, cmd->mrq); 147020845befSAdrian Hunter 14716bde8681SAdrian Hunter /* 14726bde8681SAdrian Hunter * The host can send and interrupt when the busy state has 14736bde8681SAdrian Hunter * ended, allowing us to wait without wasting CPU cycles. 14746bde8681SAdrian Hunter * The busy signal uses DAT0 so this is similar to waiting 14756bde8681SAdrian Hunter * for data to complete. 14766bde8681SAdrian Hunter * 14776bde8681SAdrian Hunter * Note: The 1.0 specification is a bit ambiguous about this 14786bde8681SAdrian Hunter * feature so there might be some problems with older 14796bde8681SAdrian Hunter * controllers. 14806bde8681SAdrian Hunter */ 1481e0a5640aSAdrian Hunter if (cmd->flags & MMC_RSP_BUSY) { 1482e0a5640aSAdrian Hunter if (cmd->data) { 14836bde8681SAdrian Hunter DBG("Cannot wait for busy signal when also doing a data transfer"); 14846bde8681SAdrian Hunter } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1485ea968023SAdrian Hunter cmd == host->data_cmd) { 1486ea968023SAdrian Hunter /* Command complete before busy is ended */ 14876bde8681SAdrian Hunter return; 14886bde8681SAdrian Hunter } 14896bde8681SAdrian Hunter } 14906bde8681SAdrian Hunter 1491e89d456fSAndrei Warkentin /* Finished CMD23, now send actual command. */ 1492a4c73abaSAdrian Hunter if (cmd == cmd->mrq->sbc) { 1493a4c73abaSAdrian Hunter sdhci_send_command(host, cmd->mrq->cmd); 1494e89d456fSAndrei Warkentin } else { 1495e89d456fSAndrei Warkentin 1496e89d456fSAndrei Warkentin /* Processed actual command. */ 1497e538fbe8SPierre Ossman if (host->data && host->data_early) 1498e538fbe8SPierre Ossman sdhci_finish_data(host); 1499e538fbe8SPierre Ossman 1500e0a5640aSAdrian Hunter if (!cmd->data) 150119d2f695SAdrian Hunter __sdhci_finish_mrq(host, cmd->mrq); 15021c6a0718SPierre Ossman } 1503e89d456fSAndrei Warkentin } 15041c6a0718SPierre Ossman 150552983382SKevin Liu static u16 sdhci_get_preset_value(struct sdhci_host *host) 150652983382SKevin Liu { 1507d975f121SRussell King u16 preset = 0; 150852983382SKevin Liu 1509d975f121SRussell King switch (host->timing) { 1510d975f121SRussell King case MMC_TIMING_UHS_SDR12: 151152983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 151252983382SKevin Liu break; 1513d975f121SRussell King case MMC_TIMING_UHS_SDR25: 151452983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 151552983382SKevin Liu break; 1516d975f121SRussell King case MMC_TIMING_UHS_SDR50: 151752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 151852983382SKevin Liu break; 1519d975f121SRussell King case MMC_TIMING_UHS_SDR104: 1520d975f121SRussell King case MMC_TIMING_MMC_HS200: 152152983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 152252983382SKevin Liu break; 1523d975f121SRussell King case MMC_TIMING_UHS_DDR50: 15240dafa60eSJisheng Zhang case MMC_TIMING_MMC_DDR52: 152552983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 152652983382SKevin Liu break; 1527e9fb05d5SAdrian Hunter case MMC_TIMING_MMC_HS400: 1528e9fb05d5SAdrian Hunter preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1529e9fb05d5SAdrian Hunter break; 153052983382SKevin Liu default: 153152983382SKevin Liu pr_warn("%s: Invalid UHS-I mode selected\n", 153252983382SKevin Liu mmc_hostname(host->mmc)); 153352983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 153452983382SKevin Liu break; 153552983382SKevin Liu } 153652983382SKevin Liu return preset; 153752983382SKevin Liu } 153852983382SKevin Liu 1539fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1540fb9ee047SLudovic Desroches unsigned int *actual_clock) 15411c6a0718SPierre Ossman { 1542c3ed3877SArindam Nath int div = 0; /* Initialized for compiler warning */ 1543df16219fSGiuseppe CAVALLARO int real_div = div, clk_mul = 1; 1544c3ed3877SArindam Nath u16 clk = 0; 15455497159cSludovic.desroches@atmel.com bool switch_base_clk = false; 15461c6a0718SPierre Ossman 154785105c53SZhangfei Gao if (host->version >= SDHCI_SPEC_300) { 1548da91a8f9SRussell King if (host->preset_enabled) { 154952983382SKevin Liu u16 pre_val; 155052983382SKevin Liu 155152983382SKevin Liu clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 155252983382SKevin Liu pre_val = sdhci_get_preset_value(host); 155352983382SKevin Liu div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 155452983382SKevin Liu >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 155552983382SKevin Liu if (host->clk_mul && 155652983382SKevin Liu (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 155752983382SKevin Liu clk = SDHCI_PROG_CLOCK_MODE; 155852983382SKevin Liu real_div = div + 1; 155952983382SKevin Liu clk_mul = host->clk_mul; 156052983382SKevin Liu } else { 156152983382SKevin Liu real_div = max_t(int, 1, div << 1); 156252983382SKevin Liu } 156352983382SKevin Liu goto clock_set; 156452983382SKevin Liu } 156552983382SKevin Liu 1566c3ed3877SArindam Nath /* 1567c3ed3877SArindam Nath * Check if the Host Controller supports Programmable Clock 1568c3ed3877SArindam Nath * Mode. 1569c3ed3877SArindam Nath */ 1570c3ed3877SArindam Nath if (host->clk_mul) { 1571c3ed3877SArindam Nath for (div = 1; div <= 1024; div++) { 157252983382SKevin Liu if ((host->max_clk * host->clk_mul / div) 157352983382SKevin Liu <= clock) 1574c3ed3877SArindam Nath break; 1575c3ed3877SArindam Nath } 15765497159cSludovic.desroches@atmel.com if ((host->max_clk * host->clk_mul / div) <= clock) { 1577c3ed3877SArindam Nath /* 1578c3ed3877SArindam Nath * Set Programmable Clock Mode in the Clock 1579c3ed3877SArindam Nath * Control register. 1580c3ed3877SArindam Nath */ 1581c3ed3877SArindam Nath clk = SDHCI_PROG_CLOCK_MODE; 1582df16219fSGiuseppe CAVALLARO real_div = div; 1583df16219fSGiuseppe CAVALLARO clk_mul = host->clk_mul; 1584c3ed3877SArindam Nath div--; 1585c3ed3877SArindam Nath } else { 15865497159cSludovic.desroches@atmel.com /* 15875497159cSludovic.desroches@atmel.com * Divisor can be too small to reach clock 15885497159cSludovic.desroches@atmel.com * speed requirement. Then use the base clock. 15895497159cSludovic.desroches@atmel.com */ 15905497159cSludovic.desroches@atmel.com switch_base_clk = true; 15915497159cSludovic.desroches@atmel.com } 15925497159cSludovic.desroches@atmel.com } 15935497159cSludovic.desroches@atmel.com 15945497159cSludovic.desroches@atmel.com if (!host->clk_mul || switch_base_clk) { 159585105c53SZhangfei Gao /* Version 3.00 divisors must be a multiple of 2. */ 159685105c53SZhangfei Gao if (host->max_clk <= clock) 159785105c53SZhangfei Gao div = 1; 159885105c53SZhangfei Gao else { 1599c3ed3877SArindam Nath for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1600c3ed3877SArindam Nath div += 2) { 160185105c53SZhangfei Gao if ((host->max_clk / div) <= clock) 160285105c53SZhangfei Gao break; 160385105c53SZhangfei Gao } 160485105c53SZhangfei Gao } 1605df16219fSGiuseppe CAVALLARO real_div = div; 1606c3ed3877SArindam Nath div >>= 1; 1607d1955c3aSSuneel Garapati if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1608d1955c3aSSuneel Garapati && !div && host->max_clk <= 25000000) 1609d1955c3aSSuneel Garapati div = 1; 1610c3ed3877SArindam Nath } 161185105c53SZhangfei Gao } else { 161285105c53SZhangfei Gao /* Version 2.00 divisors must be a power of 2. */ 16130397526dSZhangfei Gao for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 16141c6a0718SPierre Ossman if ((host->max_clk / div) <= clock) 16151c6a0718SPierre Ossman break; 16161c6a0718SPierre Ossman } 1617df16219fSGiuseppe CAVALLARO real_div = div; 16181c6a0718SPierre Ossman div >>= 1; 1619c3ed3877SArindam Nath } 16201c6a0718SPierre Ossman 162152983382SKevin Liu clock_set: 162203d6f5ffSAisheng Dong if (real_div) 1623fb9ee047SLudovic Desroches *actual_clock = (host->max_clk * clk_mul) / real_div; 1624c3ed3877SArindam Nath clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 162585105c53SZhangfei Gao clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 162685105c53SZhangfei Gao << SDHCI_DIVIDER_HI_SHIFT; 1627fb9ee047SLudovic Desroches 1628fb9ee047SLudovic Desroches return clk; 1629fb9ee047SLudovic Desroches } 1630fb9ee047SLudovic Desroches EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1631fb9ee047SLudovic Desroches 1632fec79673SRitesh Harjani void sdhci_enable_clk(struct sdhci_host *host, u16 clk) 1633fb9ee047SLudovic Desroches { 16345a436cc0SAdrian Hunter ktime_t timeout; 1635fb9ee047SLudovic Desroches 16361c6a0718SPierre Ossman clk |= SDHCI_CLOCK_INT_EN; 16374e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 16381c6a0718SPierre Ossman 16394a9e0d1aSBen Chuang /* Wait max 150 ms */ 16404a9e0d1aSBen Chuang timeout = ktime_add_ms(ktime_get(), 150); 1641b704441eSAlek Du while (1) { 1642b704441eSAlek Du bool timedout = ktime_after(ktime_get(), timeout); 1643b704441eSAlek Du 1644b704441eSAlek Du clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1645b704441eSAlek Du if (clk & SDHCI_CLOCK_INT_STABLE) 1646b704441eSAlek Du break; 1647b704441eSAlek Du if (timedout) { 16482e4456f0SMarek Vasut pr_err("%s: Internal clock never stabilised.\n", 16492e4456f0SMarek Vasut mmc_hostname(host->mmc)); 16501c6a0718SPierre Ossman sdhci_dumpregs(host); 16511c6a0718SPierre Ossman return; 16521c6a0718SPierre Ossman } 16535a436cc0SAdrian Hunter udelay(10); 16541c6a0718SPierre Ossman } 16551c6a0718SPierre Ossman 16561beabbdbSBen Chuang if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { 16571beabbdbSBen Chuang clk |= SDHCI_CLOCK_PLL_EN; 16581beabbdbSBen Chuang clk &= ~SDHCI_CLOCK_INT_STABLE; 16591beabbdbSBen Chuang sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 16601beabbdbSBen Chuang 16611beabbdbSBen Chuang /* Wait max 150 ms */ 16621beabbdbSBen Chuang timeout = ktime_add_ms(ktime_get(), 150); 16631beabbdbSBen Chuang while (1) { 16641beabbdbSBen Chuang bool timedout = ktime_after(ktime_get(), timeout); 16651beabbdbSBen Chuang 16661beabbdbSBen Chuang clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 16671beabbdbSBen Chuang if (clk & SDHCI_CLOCK_INT_STABLE) 16681beabbdbSBen Chuang break; 16691beabbdbSBen Chuang if (timedout) { 16701beabbdbSBen Chuang pr_err("%s: PLL clock never stabilised.\n", 16711beabbdbSBen Chuang mmc_hostname(host->mmc)); 16721beabbdbSBen Chuang sdhci_dumpregs(host); 16731beabbdbSBen Chuang return; 16741beabbdbSBen Chuang } 16751beabbdbSBen Chuang udelay(10); 16761beabbdbSBen Chuang } 16771beabbdbSBen Chuang } 16781beabbdbSBen Chuang 16791c6a0718SPierre Ossman clk |= SDHCI_CLOCK_CARD_EN; 16804e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 16811c6a0718SPierre Ossman } 1682fec79673SRitesh Harjani EXPORT_SYMBOL_GPL(sdhci_enable_clk); 1683fec79673SRitesh Harjani 1684fec79673SRitesh Harjani void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1685fec79673SRitesh Harjani { 1686fec79673SRitesh Harjani u16 clk; 1687fec79673SRitesh Harjani 1688fec79673SRitesh Harjani host->mmc->actual_clock = 0; 1689fec79673SRitesh Harjani 1690fec79673SRitesh Harjani sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1691fec79673SRitesh Harjani 1692fec79673SRitesh Harjani if (clock == 0) 1693fec79673SRitesh Harjani return; 1694fec79673SRitesh Harjani 1695fec79673SRitesh Harjani clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1696fec79673SRitesh Harjani sdhci_enable_clk(host, clk); 1697fec79673SRitesh Harjani } 16981771059cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_clock); 16991c6a0718SPierre Ossman 17001dceb041SAdrian Hunter static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 170124fbb3caSRussell King unsigned short vdd) 17021c6a0718SPierre Ossman { 17033a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 17041dceb041SAdrian Hunter 17051dceb041SAdrian Hunter mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 17061dceb041SAdrian Hunter 17071dceb041SAdrian Hunter if (mode != MMC_POWER_OFF) 17081dceb041SAdrian Hunter sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 17091dceb041SAdrian Hunter else 17101dceb041SAdrian Hunter sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 17111dceb041SAdrian Hunter } 17121dceb041SAdrian Hunter 1713606d3131SAdrian Hunter void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 17141dceb041SAdrian Hunter unsigned short vdd) 17151dceb041SAdrian Hunter { 17168364248aSGiuseppe Cavallaro u8 pwr = 0; 17171c6a0718SPierre Ossman 171824fbb3caSRussell King if (mode != MMC_POWER_OFF) { 171924fbb3caSRussell King switch (1 << vdd) { 1720ae628903SPierre Ossman case MMC_VDD_165_195: 17212a609abeSAndy Shevchenko /* 17222a609abeSAndy Shevchenko * Without a regulator, SDHCI does not support 2.0v 17232a609abeSAndy Shevchenko * so we only get here if the driver deliberately 17242a609abeSAndy Shevchenko * added the 2.0v range to ocr_avail. Map it to 1.8v 17252a609abeSAndy Shevchenko * for the purpose of turning on the power. 17262a609abeSAndy Shevchenko */ 17272a609abeSAndy Shevchenko case MMC_VDD_20_21: 1728ae628903SPierre Ossman pwr = SDHCI_POWER_180; 1729ae628903SPierre Ossman break; 1730ae628903SPierre Ossman case MMC_VDD_29_30: 1731ae628903SPierre Ossman case MMC_VDD_30_31: 1732ae628903SPierre Ossman pwr = SDHCI_POWER_300; 1733ae628903SPierre Ossman break; 1734ae628903SPierre Ossman case MMC_VDD_32_33: 1735ae628903SPierre Ossman case MMC_VDD_33_34: 1736ae628903SPierre Ossman pwr = SDHCI_POWER_330; 1737ae628903SPierre Ossman break; 1738ae628903SPierre Ossman default: 17399d5de93fSAdrian Hunter WARN(1, "%s: Invalid vdd %#x\n", 17409d5de93fSAdrian Hunter mmc_hostname(host->mmc), vdd); 17419d5de93fSAdrian Hunter break; 1742ae628903SPierre Ossman } 1743ae628903SPierre Ossman } 1744ae628903SPierre Ossman 1745ae628903SPierre Ossman if (host->pwr == pwr) 1746e921a8b6SRussell King return; 17471c6a0718SPierre Ossman 1748ae628903SPierre Ossman host->pwr = pwr; 1749ae628903SPierre Ossman 1750ae628903SPierre Ossman if (pwr == 0) { 17514e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1752f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1753f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 1754e921a8b6SRussell King } else { 17551c6a0718SPierre Ossman /* 17561c6a0718SPierre Ossman * Spec says that we should clear the power reg before setting 17571c6a0718SPierre Ossman * a new value. Some controllers don't seem to like this though. 17581c6a0718SPierre Ossman */ 1759b8c86fc5SPierre Ossman if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 17604e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 17611c6a0718SPierre Ossman 1762e08c1694SAndres Salomon /* 1763e921a8b6SRussell King * At least the Marvell CaFe chip gets confused if we set the 1764e921a8b6SRussell King * voltage and set turn on power at the same time, so set the 1765e921a8b6SRussell King * voltage first. 1766e08c1694SAndres Salomon */ 176711a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 17684e4141a5SAnton Vorontsov sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 17691c6a0718SPierre Ossman 1770ae628903SPierre Ossman pwr |= SDHCI_POWER_ON; 1771ae628903SPierre Ossman 1772ae628903SPierre Ossman sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1773557b0697SHarald Welte 1774f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1775f0710a55SAdrian Hunter sdhci_runtime_pm_bus_on(host); 1776f0710a55SAdrian Hunter 1777557b0697SHarald Welte /* 1778e921a8b6SRussell King * Some controllers need an extra 10ms delay of 10ms before 1779e921a8b6SRussell King * they can apply clock after applying power 1780557b0697SHarald Welte */ 178111a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1782557b0697SHarald Welte mdelay(10); 1783e921a8b6SRussell King } 1784918f4cbdSJisheng Zhang } 1785606d3131SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); 17861dceb041SAdrian Hunter 1787606d3131SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 17881dceb041SAdrian Hunter unsigned short vdd) 17891dceb041SAdrian Hunter { 1790606d3131SAdrian Hunter if (IS_ERR(host->mmc->supply.vmmc)) 1791606d3131SAdrian Hunter sdhci_set_power_noreg(host, mode, vdd); 17921dceb041SAdrian Hunter else 1793606d3131SAdrian Hunter sdhci_set_power_reg(host, mode, vdd); 17941c6a0718SPierre Ossman } 1795606d3131SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_set_power); 17961c6a0718SPierre Ossman 17971c6a0718SPierre Ossman /*****************************************************************************\ 17981c6a0718SPierre Ossman * * 17991c6a0718SPierre Ossman * MMC callbacks * 18001c6a0718SPierre Ossman * * 18011c6a0718SPierre Ossman \*****************************************************************************/ 18021c6a0718SPierre Ossman 1803d462c1b4SAapo Vienamo void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 18041c6a0718SPierre Ossman { 18051c6a0718SPierre Ossman struct sdhci_host *host; 1806505a8680SShawn Guo int present; 18071c6a0718SPierre Ossman unsigned long flags; 18081c6a0718SPierre Ossman 18091c6a0718SPierre Ossman host = mmc_priv(mmc); 18101c6a0718SPierre Ossman 181104e079cfSScott Branden /* Firstly check card presence */ 18128d28b7a7SAdrian Hunter present = mmc->ops->get_cd(mmc); 18132836766aSKrzysztof Kozlowski 18141c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 18151c6a0718SPierre Ossman 1816061d17a6SAdrian Hunter sdhci_led_activate(host); 1817e89d456fSAndrei Warkentin 1818e89d456fSAndrei Warkentin /* 1819e89d456fSAndrei Warkentin * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1820e89d456fSAndrei Warkentin * requests if Auto-CMD12 is enabled. 1821e89d456fSAndrei Warkentin */ 18220293d501SAdrian Hunter if (sdhci_auto_cmd12(host, mrq)) { 1823c4512f79SJerry Huang if (mrq->stop) { 1824c4512f79SJerry Huang mrq->data->stop = NULL; 1825c4512f79SJerry Huang mrq->stop = NULL; 1826c4512f79SJerry Huang } 1827c4512f79SJerry Huang } 18281c6a0718SPierre Ossman 182968d1fb7eSAnton Vorontsov if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1830a4c73abaSAdrian Hunter mrq->cmd->error = -ENOMEDIUM; 1831a6d3bdd5SAdrian Hunter sdhci_finish_mrq(host, mrq); 1832cf2b5eeaSArindam Nath } else { 18338edf6371SAndrei Warkentin if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1834e89d456fSAndrei Warkentin sdhci_send_command(host, mrq->sbc); 1835e89d456fSAndrei Warkentin else 18361c6a0718SPierre Ossman sdhci_send_command(host, mrq->cmd); 1837cf2b5eeaSArindam Nath } 18381c6a0718SPierre Ossman 18391c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 18401c6a0718SPierre Ossman } 1841d462c1b4SAapo Vienamo EXPORT_SYMBOL_GPL(sdhci_request); 18421c6a0718SPierre Ossman 18432317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width) 18442317f56cSRussell King { 18452317f56cSRussell King u8 ctrl; 18462317f56cSRussell King 18472317f56cSRussell King ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 18482317f56cSRussell King if (width == MMC_BUS_WIDTH_8) { 18492317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 18502317f56cSRussell King ctrl |= SDHCI_CTRL_8BITBUS; 18512317f56cSRussell King } else { 185298f94ea6SMichał Mirosław if (host->mmc->caps & MMC_CAP_8_BIT_DATA) 18532317f56cSRussell King ctrl &= ~SDHCI_CTRL_8BITBUS; 18542317f56cSRussell King if (width == MMC_BUS_WIDTH_4) 18552317f56cSRussell King ctrl |= SDHCI_CTRL_4BITBUS; 18562317f56cSRussell King else 18572317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 18582317f56cSRussell King } 18592317f56cSRussell King sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 18602317f56cSRussell King } 18612317f56cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 18622317f56cSRussell King 186396d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 186496d7b78cSRussell King { 186596d7b78cSRussell King u16 ctrl_2; 186696d7b78cSRussell King 186796d7b78cSRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 186896d7b78cSRussell King /* Select Bus Speed Mode for host */ 186996d7b78cSRussell King ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 187096d7b78cSRussell King if ((timing == MMC_TIMING_MMC_HS200) || 187196d7b78cSRussell King (timing == MMC_TIMING_UHS_SDR104)) 187296d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 187396d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR12) 187496d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 187596d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR25) 187696d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 187796d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR50) 187896d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 187996d7b78cSRussell King else if ((timing == MMC_TIMING_UHS_DDR50) || 188096d7b78cSRussell King (timing == MMC_TIMING_MMC_DDR52)) 188196d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1882e9fb05d5SAdrian Hunter else if (timing == MMC_TIMING_MMC_HS400) 1883e9fb05d5SAdrian Hunter ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 188496d7b78cSRussell King sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 188596d7b78cSRussell King } 188696d7b78cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 188796d7b78cSRussell King 18886a6d4cebSHu Ziji void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 18891c6a0718SPierre Ossman { 1890ded97e0bSDong Aisheng struct sdhci_host *host = mmc_priv(mmc); 18911c6a0718SPierre Ossman u8 ctrl; 18921c6a0718SPierre Ossman 189384ec048bSAdrian Hunter if (ios->power_mode == MMC_POWER_UNDEFINED) 189484ec048bSAdrian Hunter return; 189584ec048bSAdrian Hunter 1896ceb6143bSAdrian Hunter if (host->flags & SDHCI_DEVICE_DEAD) { 18973a48edc4STim Kryger if (!IS_ERR(mmc->supply.vmmc) && 18983a48edc4STim Kryger ios->power_mode == MMC_POWER_OFF) 18994e743f1fSMarkus Mayer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1900ceb6143bSAdrian Hunter return; 1901ceb6143bSAdrian Hunter } 19021e72859eSPierre Ossman 19031c6a0718SPierre Ossman /* 19041c6a0718SPierre Ossman * Reset the chip on each power off. 19051c6a0718SPierre Ossman * Should clear out any weird states. 19061c6a0718SPierre Ossman */ 19071c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) { 19084e4141a5SAnton Vorontsov sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 19097260cf5eSAnton Vorontsov sdhci_reinit(host); 19101c6a0718SPierre Ossman } 19111c6a0718SPierre Ossman 191252983382SKevin Liu if (host->version >= SDHCI_SPEC_300 && 1913372c4634SDong Aisheng (ios->power_mode == MMC_POWER_UP) && 1914372c4634SDong Aisheng !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 191552983382SKevin Liu sdhci_enable_preset_value(host, false); 191652983382SKevin Liu 1917373073efSRussell King if (!ios->clock || ios->clock != host->clock) { 19181771059cSRussell King host->ops->set_clock(host, ios->clock); 1919373073efSRussell King host->clock = ios->clock; 192003d6f5ffSAisheng Dong 192103d6f5ffSAisheng Dong if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 192203d6f5ffSAisheng Dong host->clock) { 192303d6f5ffSAisheng Dong host->timeout_clk = host->mmc->actual_clock ? 192403d6f5ffSAisheng Dong host->mmc->actual_clock / 1000 : 192503d6f5ffSAisheng Dong host->clock / 1000; 192603d6f5ffSAisheng Dong host->mmc->max_busy_timeout = 192703d6f5ffSAisheng Dong host->ops->get_max_timeout_count ? 192803d6f5ffSAisheng Dong host->ops->get_max_timeout_count(host) : 192903d6f5ffSAisheng Dong 1 << 27; 193003d6f5ffSAisheng Dong host->mmc->max_busy_timeout /= host->timeout_clk; 193103d6f5ffSAisheng Dong } 1932373073efSRussell King } 19331c6a0718SPierre Ossman 1934606d3131SAdrian Hunter if (host->ops->set_power) 1935606d3131SAdrian Hunter host->ops->set_power(host, ios->power_mode, ios->vdd); 1936606d3131SAdrian Hunter else 1937606d3131SAdrian Hunter sdhci_set_power(host, ios->power_mode, ios->vdd); 19381c6a0718SPierre Ossman 1939643a81ffSPhilip Rakity if (host->ops->platform_send_init_74_clocks) 1940643a81ffSPhilip Rakity host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1941643a81ffSPhilip Rakity 19422317f56cSRussell King host->ops->set_bus_width(host, ios->bus_width); 194315ec4461SPhilip Rakity 194415ec4461SPhilip Rakity ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 19451c6a0718SPierre Ossman 1946501639bfSyangbo lu if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) { 1947501639bfSyangbo lu if (ios->timing == MMC_TIMING_SD_HS || 1948273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_HS || 1949273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_HS400 || 1950273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_HS200 || 1951273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_DDR52 || 1952273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_SDR50 || 1953273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_SDR104 || 1954273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 1955273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_SDR25) 19561c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_HISPD; 19571c6a0718SPierre Ossman else 19581c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_HISPD; 1959501639bfSyangbo lu } 19601c6a0718SPierre Ossman 1961d6d50a15SArindam Nath if (host->version >= SDHCI_SPEC_300) { 196249c468fcSArindam Nath u16 clk, ctrl_2; 196349c468fcSArindam Nath 1964da91a8f9SRussell King if (!host->preset_enabled) { 1965758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1966d6d50a15SArindam Nath /* 1967d6d50a15SArindam Nath * We only need to set Driver Strength if the 1968d6d50a15SArindam Nath * preset value enable is not set. 1969d6d50a15SArindam Nath */ 1970da91a8f9SRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1971d6d50a15SArindam Nath ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1972d6d50a15SArindam Nath if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1973d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 197443e943a0SPetri Gynther else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 197543e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1976d6d50a15SArindam Nath else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1977d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 197843e943a0SPetri Gynther else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 197943e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 198043e943a0SPetri Gynther else { 19812e4456f0SMarek Vasut pr_warn("%s: invalid driver type, default to driver type B\n", 19822e4456f0SMarek Vasut mmc_hostname(mmc)); 198343e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 198443e943a0SPetri Gynther } 1985d6d50a15SArindam Nath 1986d6d50a15SArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1987758535c4SArindam Nath } else { 1988758535c4SArindam Nath /* 1989758535c4SArindam Nath * According to SDHC Spec v3.00, if the Preset Value 1990758535c4SArindam Nath * Enable in the Host Control 2 register is set, we 1991758535c4SArindam Nath * need to reset SD Clock Enable before changing High 1992758535c4SArindam Nath * Speed Enable to avoid generating clock gliches. 1993758535c4SArindam Nath */ 1994758535c4SArindam Nath 1995758535c4SArindam Nath /* Reset SD Clock Enable */ 1996758535c4SArindam Nath clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1997758535c4SArindam Nath clk &= ~SDHCI_CLOCK_CARD_EN; 1998758535c4SArindam Nath sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1999758535c4SArindam Nath 2000758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2001758535c4SArindam Nath 2002758535c4SArindam Nath /* Re-enable SD Clock */ 20031771059cSRussell King host->ops->set_clock(host, host->clock); 2004d6d50a15SArindam Nath } 200549c468fcSArindam Nath 20066322cdd0SPhilip Rakity /* Reset SD Clock Enable */ 20076322cdd0SPhilip Rakity clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 20086322cdd0SPhilip Rakity clk &= ~SDHCI_CLOCK_CARD_EN; 20096322cdd0SPhilip Rakity sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 20106322cdd0SPhilip Rakity 20116322cdd0SPhilip Rakity host->ops->set_uhs_signaling(host, ios->timing); 2012d975f121SRussell King host->timing = ios->timing; 201349c468fcSArindam Nath 201452983382SKevin Liu if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 201552983382SKevin Liu ((ios->timing == MMC_TIMING_UHS_SDR12) || 201652983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR25) || 201752983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR50) || 201852983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR104) || 20190dafa60eSJisheng Zhang (ios->timing == MMC_TIMING_UHS_DDR50) || 20200dafa60eSJisheng Zhang (ios->timing == MMC_TIMING_MMC_DDR52))) { 202152983382SKevin Liu u16 preset; 202252983382SKevin Liu 202352983382SKevin Liu sdhci_enable_preset_value(host, true); 202452983382SKevin Liu preset = sdhci_get_preset_value(host); 202552983382SKevin Liu ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 202652983382SKevin Liu >> SDHCI_PRESET_DRV_SHIFT; 202752983382SKevin Liu } 202852983382SKevin Liu 202949c468fcSArindam Nath /* Re-enable SD Clock */ 20301771059cSRussell King host->ops->set_clock(host, host->clock); 2031758535c4SArindam Nath } else 2032758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2033d6d50a15SArindam Nath 2034b8352260SLeandro Dorileo /* 2035b8352260SLeandro Dorileo * Some (ENE) controllers go apeshit on some ios operation, 2036b8352260SLeandro Dorileo * signalling timeout and CRC errors even on CMD0. Resetting 2037b8352260SLeandro Dorileo * it on each ios seems to solve the problem. 2038b8352260SLeandro Dorileo */ 2039b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 204003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 20411c6a0718SPierre Ossman } 20426a6d4cebSHu Ziji EXPORT_SYMBOL_GPL(sdhci_set_ios); 20431c6a0718SPierre Ossman 2044ded97e0bSDong Aisheng static int sdhci_get_cd(struct mmc_host *mmc) 204566fd8ad5SAdrian Hunter { 204666fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 2047ded97e0bSDong Aisheng int gpio_cd = mmc_gpio_get_cd(mmc); 204894144a46SKevin Liu 204994144a46SKevin Liu if (host->flags & SDHCI_DEVICE_DEAD) 205094144a46SKevin Liu return 0; 205194144a46SKevin Liu 205288af5655SIvan T. Ivanov /* If nonremovable, assume that the card is always present. */ 2053860951c5SJaehoon Chung if (!mmc_card_is_removable(host->mmc)) 205494144a46SKevin Liu return 1; 205594144a46SKevin Liu 205688af5655SIvan T. Ivanov /* 205788af5655SIvan T. Ivanov * Try slot gpio detect, if defined it take precedence 205888af5655SIvan T. Ivanov * over build in controller functionality 205988af5655SIvan T. Ivanov */ 2060287980e4SArnd Bergmann if (gpio_cd >= 0) 206194144a46SKevin Liu return !!gpio_cd; 206294144a46SKevin Liu 206388af5655SIvan T. Ivanov /* If polling, assume that the card is always present. */ 206488af5655SIvan T. Ivanov if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 206588af5655SIvan T. Ivanov return 1; 206688af5655SIvan T. Ivanov 206794144a46SKevin Liu /* Host native card detect */ 206894144a46SKevin Liu return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 206994144a46SKevin Liu } 207094144a46SKevin Liu 207166fd8ad5SAdrian Hunter static int sdhci_check_ro(struct sdhci_host *host) 20721c6a0718SPierre Ossman { 20731c6a0718SPierre Ossman unsigned long flags; 20742dfb579cSWolfram Sang int is_readonly; 20751c6a0718SPierre Ossman 20761c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 20771c6a0718SPierre Ossman 20781e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 20792dfb579cSWolfram Sang is_readonly = 0; 20802dfb579cSWolfram Sang else if (host->ops->get_ro) 20812dfb579cSWolfram Sang is_readonly = host->ops->get_ro(host); 20826d5cd068SThomas Petazzoni else if (mmc_can_gpio_ro(host->mmc)) 20836d5cd068SThomas Petazzoni is_readonly = mmc_gpio_get_ro(host->mmc); 20841e72859eSPierre Ossman else 20852dfb579cSWolfram Sang is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 20862dfb579cSWolfram Sang & SDHCI_WRITE_PROTECT); 20871c6a0718SPierre Ossman 20881c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 20891c6a0718SPierre Ossman 20902dfb579cSWolfram Sang /* This quirk needs to be replaced by a callback-function later */ 20912dfb579cSWolfram Sang return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 20922dfb579cSWolfram Sang !is_readonly : is_readonly; 20931c6a0718SPierre Ossman } 20941c6a0718SPierre Ossman 209582b0e23aSTakashi Iwai #define SAMPLE_COUNT 5 209682b0e23aSTakashi Iwai 2097ded97e0bSDong Aisheng static int sdhci_get_ro(struct mmc_host *mmc) 209882b0e23aSTakashi Iwai { 2099ded97e0bSDong Aisheng struct sdhci_host *host = mmc_priv(mmc); 210082b0e23aSTakashi Iwai int i, ro_count; 210182b0e23aSTakashi Iwai 210282b0e23aSTakashi Iwai if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 210366fd8ad5SAdrian Hunter return sdhci_check_ro(host); 210482b0e23aSTakashi Iwai 210582b0e23aSTakashi Iwai ro_count = 0; 210682b0e23aSTakashi Iwai for (i = 0; i < SAMPLE_COUNT; i++) { 210766fd8ad5SAdrian Hunter if (sdhci_check_ro(host)) { 210882b0e23aSTakashi Iwai if (++ro_count > SAMPLE_COUNT / 2) 210982b0e23aSTakashi Iwai return 1; 211082b0e23aSTakashi Iwai } 211182b0e23aSTakashi Iwai msleep(30); 211282b0e23aSTakashi Iwai } 211382b0e23aSTakashi Iwai return 0; 211482b0e23aSTakashi Iwai } 211582b0e23aSTakashi Iwai 211620758b66SAdrian Hunter static void sdhci_hw_reset(struct mmc_host *mmc) 211720758b66SAdrian Hunter { 211820758b66SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 211920758b66SAdrian Hunter 212020758b66SAdrian Hunter if (host->ops && host->ops->hw_reset) 212120758b66SAdrian Hunter host->ops->hw_reset(host); 212220758b66SAdrian Hunter } 212320758b66SAdrian Hunter 212466fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 212566fd8ad5SAdrian Hunter { 2126be138554SRussell King if (!(host->flags & SDHCI_DEVICE_DEAD)) { 212766fd8ad5SAdrian Hunter if (enable) 2128b537f94cSRussell King host->ier |= SDHCI_INT_CARD_INT; 21297260cf5eSAnton Vorontsov else 2130b537f94cSRussell King host->ier &= ~SDHCI_INT_CARD_INT; 2131b537f94cSRussell King 2132b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2133b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 213466fd8ad5SAdrian Hunter } 2135ef104333SRussell King } 2136f75979b7SPierre Ossman 21372f05b6abSHu Ziji void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 213866fd8ad5SAdrian Hunter { 213966fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 214066fd8ad5SAdrian Hunter unsigned long flags; 214166fd8ad5SAdrian Hunter 2142923713b3SHans de Goede if (enable) 2143923713b3SHans de Goede pm_runtime_get_noresume(host->mmc->parent); 2144923713b3SHans de Goede 214566fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2146ef104333SRussell King if (enable) 2147ef104333SRussell King host->flags |= SDHCI_SDIO_IRQ_ENABLED; 2148ef104333SRussell King else 2149ef104333SRussell King host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 2150ef104333SRussell King 215166fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, enable); 2152f75979b7SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 2153923713b3SHans de Goede 2154923713b3SHans de Goede if (!enable) 2155923713b3SHans de Goede pm_runtime_put_noidle(host->mmc->parent); 2156f75979b7SPierre Ossman } 21572f05b6abSHu Ziji EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq); 2158f75979b7SPierre Ossman 215989f3c365SAdrian Hunter static void sdhci_ack_sdio_irq(struct mmc_host *mmc) 216089f3c365SAdrian Hunter { 216189f3c365SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 216289f3c365SAdrian Hunter unsigned long flags; 216389f3c365SAdrian Hunter 216489f3c365SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 216589f3c365SAdrian Hunter if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 216689f3c365SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 216789f3c365SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 216889f3c365SAdrian Hunter } 216989f3c365SAdrian Hunter 2170c376ea9eSHu Ziji int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 217121f5998fSFabio Estevam struct mmc_ios *ios) 2172f2119df6SArindam Nath { 2173ded97e0bSDong Aisheng struct sdhci_host *host = mmc_priv(mmc); 217420b92a30SKevin Liu u16 ctrl; 21756231f3deSPhilip Rakity int ret; 2176f2119df6SArindam Nath 217720b92a30SKevin Liu /* 217820b92a30SKevin Liu * Signal Voltage Switching is only applicable for Host Controllers 217920b92a30SKevin Liu * v3.00 and above. 218020b92a30SKevin Liu */ 218120b92a30SKevin Liu if (host->version < SDHCI_SPEC_300) 218220b92a30SKevin Liu return 0; 218320b92a30SKevin Liu 218420b92a30SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 218520b92a30SKevin Liu 218621f5998fSFabio Estevam switch (ios->signal_voltage) { 218720b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_330: 21888cb851a4SAdrian Hunter if (!(host->flags & SDHCI_SIGNALING_330)) 21898cb851a4SAdrian Hunter return -EINVAL; 2190f2119df6SArindam Nath /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 2191f2119df6SArindam Nath ctrl &= ~SDHCI_CTRL_VDD_180; 2192f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2193f2119df6SArindam Nath 21943a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 2195761daa36SDong Aisheng ret = mmc_regulator_set_vqmmc(mmc, ios); 21966231f3deSPhilip Rakity if (ret) { 21976606110dSJoe Perches pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 21986606110dSJoe Perches mmc_hostname(mmc)); 21996231f3deSPhilip Rakity return -EIO; 22006231f3deSPhilip Rakity } 22016231f3deSPhilip Rakity } 2202f2119df6SArindam Nath /* Wait for 5ms */ 2203f2119df6SArindam Nath usleep_range(5000, 5500); 2204f2119df6SArindam Nath 2205f2119df6SArindam Nath /* 3.3V regulator output should be stable within 5 ms */ 2206f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2207f2119df6SArindam Nath if (!(ctrl & SDHCI_CTRL_VDD_180)) 2208f2119df6SArindam Nath return 0; 22096231f3deSPhilip Rakity 22106606110dSJoe Perches pr_warn("%s: 3.3V regulator output did not became stable\n", 22114e743f1fSMarkus Mayer mmc_hostname(mmc)); 22126231f3deSPhilip Rakity 221320b92a30SKevin Liu return -EAGAIN; 221420b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_180: 22158cb851a4SAdrian Hunter if (!(host->flags & SDHCI_SIGNALING_180)) 22168cb851a4SAdrian Hunter return -EINVAL; 22173a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 2218761daa36SDong Aisheng ret = mmc_regulator_set_vqmmc(mmc, ios); 221920b92a30SKevin Liu if (ret) { 22206606110dSJoe Perches pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 22216606110dSJoe Perches mmc_hostname(mmc)); 2222f2119df6SArindam Nath return -EIO; 2223f2119df6SArindam Nath } 222420b92a30SKevin Liu } 22256231f3deSPhilip Rakity 2226f2119df6SArindam Nath /* 2227f2119df6SArindam Nath * Enable 1.8V Signal Enable in the Host Control2 2228f2119df6SArindam Nath * register 2229f2119df6SArindam Nath */ 2230f2119df6SArindam Nath ctrl |= SDHCI_CTRL_VDD_180; 2231f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2232f2119df6SArindam Nath 22339d967a61SVincent Yang /* Some controller need to do more when switching */ 22349d967a61SVincent Yang if (host->ops->voltage_switch) 22359d967a61SVincent Yang host->ops->voltage_switch(host); 22369d967a61SVincent Yang 223720b92a30SKevin Liu /* 1.8V regulator output should be stable within 5 ms */ 2238f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 223920b92a30SKevin Liu if (ctrl & SDHCI_CTRL_VDD_180) 2240f2119df6SArindam Nath return 0; 2241f2119df6SArindam Nath 22426606110dSJoe Perches pr_warn("%s: 1.8V regulator output did not became stable\n", 22434e743f1fSMarkus Mayer mmc_hostname(mmc)); 22446231f3deSPhilip Rakity 2245f2119df6SArindam Nath return -EAGAIN; 224620b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_120: 22478cb851a4SAdrian Hunter if (!(host->flags & SDHCI_SIGNALING_120)) 22488cb851a4SAdrian Hunter return -EINVAL; 22493a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 2250761daa36SDong Aisheng ret = mmc_regulator_set_vqmmc(mmc, ios); 225120b92a30SKevin Liu if (ret) { 22526606110dSJoe Perches pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 22536606110dSJoe Perches mmc_hostname(mmc)); 225420b92a30SKevin Liu return -EIO; 22556231f3deSPhilip Rakity } 225620b92a30SKevin Liu } 22576231f3deSPhilip Rakity return 0; 225820b92a30SKevin Liu default: 2259f2119df6SArindam Nath /* No signal voltage switch required */ 2260f2119df6SArindam Nath return 0; 2261f2119df6SArindam Nath } 226220b92a30SKevin Liu } 2263c376ea9eSHu Ziji EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch); 2264f2119df6SArindam Nath 226520b92a30SKevin Liu static int sdhci_card_busy(struct mmc_host *mmc) 226620b92a30SKevin Liu { 226720b92a30SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 226820b92a30SKevin Liu u32 present_state; 226920b92a30SKevin Liu 2270e613cc47SAdrian Hunter /* Check whether DAT[0] is 0 */ 227120b92a30SKevin Liu present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 227220b92a30SKevin Liu 2273e613cc47SAdrian Hunter return !(present_state & SDHCI_DATA_0_LVL_MASK); 227420b92a30SKevin Liu } 227520b92a30SKevin Liu 2276b5540ce1SAdrian Hunter static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2277b5540ce1SAdrian Hunter { 2278b5540ce1SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 2279b5540ce1SAdrian Hunter unsigned long flags; 2280b5540ce1SAdrian Hunter 2281b5540ce1SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2282b5540ce1SAdrian Hunter host->flags |= SDHCI_HS400_TUNING; 2283b5540ce1SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 2284b5540ce1SAdrian Hunter 2285b5540ce1SAdrian Hunter return 0; 2286b5540ce1SAdrian Hunter } 2287b5540ce1SAdrian Hunter 22886663c419Sernest.zhang void sdhci_start_tuning(struct sdhci_host *host) 2289da4bc4f2SAdrian Hunter { 2290da4bc4f2SAdrian Hunter u16 ctrl; 2291da4bc4f2SAdrian Hunter 2292da4bc4f2SAdrian Hunter ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2293da4bc4f2SAdrian Hunter ctrl |= SDHCI_CTRL_EXEC_TUNING; 2294da4bc4f2SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 2295da4bc4f2SAdrian Hunter ctrl |= SDHCI_CTRL_TUNED_CLK; 2296da4bc4f2SAdrian Hunter sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2297da4bc4f2SAdrian Hunter 2298da4bc4f2SAdrian Hunter /* 2299da4bc4f2SAdrian Hunter * As per the Host Controller spec v3.00, tuning command 2300da4bc4f2SAdrian Hunter * generates Buffer Read Ready interrupt, so enable that. 2301da4bc4f2SAdrian Hunter * 2302da4bc4f2SAdrian Hunter * Note: The spec clearly says that when tuning sequence 2303da4bc4f2SAdrian Hunter * is being performed, the controller does not generate 2304da4bc4f2SAdrian Hunter * interrupts other than Buffer Read Ready interrupt. But 2305da4bc4f2SAdrian Hunter * to make sure we don't hit a controller bug, we _only_ 2306da4bc4f2SAdrian Hunter * enable Buffer Read Ready interrupt here. 2307da4bc4f2SAdrian Hunter */ 2308da4bc4f2SAdrian Hunter sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 2309da4bc4f2SAdrian Hunter sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 2310da4bc4f2SAdrian Hunter } 23116663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_start_tuning); 2312da4bc4f2SAdrian Hunter 23136663c419Sernest.zhang void sdhci_end_tuning(struct sdhci_host *host) 2314da4bc4f2SAdrian Hunter { 2315da4bc4f2SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2316da4bc4f2SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2317da4bc4f2SAdrian Hunter } 23186663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_end_tuning); 2319da4bc4f2SAdrian Hunter 23206663c419Sernest.zhang void sdhci_reset_tuning(struct sdhci_host *host) 2321da4bc4f2SAdrian Hunter { 2322da4bc4f2SAdrian Hunter u16 ctrl; 2323da4bc4f2SAdrian Hunter 2324da4bc4f2SAdrian Hunter ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2325da4bc4f2SAdrian Hunter ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2326da4bc4f2SAdrian Hunter ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2327da4bc4f2SAdrian Hunter sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2328da4bc4f2SAdrian Hunter } 23296663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_reset_tuning); 2330da4bc4f2SAdrian Hunter 23312a85ef25SAdrian Hunter static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) 2332da4bc4f2SAdrian Hunter { 2333da4bc4f2SAdrian Hunter sdhci_reset_tuning(host); 2334da4bc4f2SAdrian Hunter 2335da4bc4f2SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD); 2336da4bc4f2SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_DATA); 2337da4bc4f2SAdrian Hunter 2338da4bc4f2SAdrian Hunter sdhci_end_tuning(host); 2339da4bc4f2SAdrian Hunter 2340da4bc4f2SAdrian Hunter mmc_abort_tuning(host->mmc, opcode); 2341da4bc4f2SAdrian Hunter } 2342da4bc4f2SAdrian Hunter 2343da4bc4f2SAdrian Hunter /* 2344da4bc4f2SAdrian Hunter * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI 2345da4bc4f2SAdrian Hunter * tuning command does not have a data payload (or rather the hardware does it 2346da4bc4f2SAdrian Hunter * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command 2347da4bc4f2SAdrian Hunter * interrupt setup is different to other commands and there is no timeout 2348da4bc4f2SAdrian Hunter * interrupt so special handling is needed. 2349da4bc4f2SAdrian Hunter */ 23506663c419Sernest.zhang void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 2351da4bc4f2SAdrian Hunter { 2352da4bc4f2SAdrian Hunter struct mmc_host *mmc = host->mmc; 2353c7836d15SMasahiro Yamada struct mmc_command cmd = {}; 2354c7836d15SMasahiro Yamada struct mmc_request mrq = {}; 23552a85ef25SAdrian Hunter unsigned long flags; 2356c846a00fSSrinivas Kandagatla u32 b = host->sdma_boundary; 23572a85ef25SAdrian Hunter 23582a85ef25SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2359da4bc4f2SAdrian Hunter 2360da4bc4f2SAdrian Hunter cmd.opcode = opcode; 2361da4bc4f2SAdrian Hunter cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2362da4bc4f2SAdrian Hunter cmd.mrq = &mrq; 2363da4bc4f2SAdrian Hunter 2364da4bc4f2SAdrian Hunter mrq.cmd = &cmd; 2365da4bc4f2SAdrian Hunter /* 2366da4bc4f2SAdrian Hunter * In response to CMD19, the card sends 64 bytes of tuning 2367da4bc4f2SAdrian Hunter * block to the Host Controller. So we set the block size 2368da4bc4f2SAdrian Hunter * to 64 here. 2369da4bc4f2SAdrian Hunter */ 237085336109SAdrian Hunter if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 && 237185336109SAdrian Hunter mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2372c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE); 237385336109SAdrian Hunter else 2374c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE); 2375da4bc4f2SAdrian Hunter 2376da4bc4f2SAdrian Hunter /* 2377da4bc4f2SAdrian Hunter * The tuning block is sent by the card to the host controller. 2378da4bc4f2SAdrian Hunter * So we set the TRNS_READ bit in the Transfer Mode register. 2379da4bc4f2SAdrian Hunter * This also takes care of setting DMA Enable and Multi Block 2380da4bc4f2SAdrian Hunter * Select in the same register to 0. 2381da4bc4f2SAdrian Hunter */ 2382da4bc4f2SAdrian Hunter sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2383da4bc4f2SAdrian Hunter 2384da4bc4f2SAdrian Hunter sdhci_send_command(host, &cmd); 2385da4bc4f2SAdrian Hunter 2386da4bc4f2SAdrian Hunter host->cmd = NULL; 2387da4bc4f2SAdrian Hunter 2388da4bc4f2SAdrian Hunter sdhci_del_timer(host, &mrq); 2389da4bc4f2SAdrian Hunter 2390da4bc4f2SAdrian Hunter host->tuning_done = 0; 2391da4bc4f2SAdrian Hunter 2392da4bc4f2SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 2393da4bc4f2SAdrian Hunter 2394da4bc4f2SAdrian Hunter /* Wait for Buffer Read Ready interrupt */ 2395da4bc4f2SAdrian Hunter wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), 2396da4bc4f2SAdrian Hunter msecs_to_jiffies(50)); 2397da4bc4f2SAdrian Hunter 2398da4bc4f2SAdrian Hunter } 23996663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_send_tuning); 2400da4bc4f2SAdrian Hunter 24017d8bb1f4SYinbo Zhu static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 24026b11e70bSAdrian Hunter { 24036b11e70bSAdrian Hunter int i; 24046b11e70bSAdrian Hunter 24056b11e70bSAdrian Hunter /* 24066b11e70bSAdrian Hunter * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 24071d8cd065SSowjanya Komatineni * of loops reaches tuning loop count. 24086b11e70bSAdrian Hunter */ 24091d8cd065SSowjanya Komatineni for (i = 0; i < host->tuning_loop_count; i++) { 24106b11e70bSAdrian Hunter u16 ctrl; 24116b11e70bSAdrian Hunter 24122a85ef25SAdrian Hunter sdhci_send_tuning(host, opcode); 24136b11e70bSAdrian Hunter 24146b11e70bSAdrian Hunter if (!host->tuning_done) { 24156b11e70bSAdrian Hunter pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 24166b11e70bSAdrian Hunter mmc_hostname(host->mmc)); 24172a85ef25SAdrian Hunter sdhci_abort_tuning(host, opcode); 24187d8bb1f4SYinbo Zhu return -ETIMEDOUT; 24196b11e70bSAdrian Hunter } 24206b11e70bSAdrian Hunter 24212b06e159SBOUGH CHEN /* Spec does not require a delay between tuning cycles */ 24222b06e159SBOUGH CHEN if (host->tuning_delay > 0) 24232b06e159SBOUGH CHEN mdelay(host->tuning_delay); 24242b06e159SBOUGH CHEN 24256b11e70bSAdrian Hunter ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 24266b11e70bSAdrian Hunter if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 24276b11e70bSAdrian Hunter if (ctrl & SDHCI_CTRL_TUNED_CLK) 24287d8bb1f4SYinbo Zhu return 0; /* Success! */ 24296b11e70bSAdrian Hunter break; 24306b11e70bSAdrian Hunter } 24316b11e70bSAdrian Hunter 24326b11e70bSAdrian Hunter } 24336b11e70bSAdrian Hunter 24346b11e70bSAdrian Hunter pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 24356b11e70bSAdrian Hunter mmc_hostname(host->mmc)); 24366b11e70bSAdrian Hunter sdhci_reset_tuning(host); 24377d8bb1f4SYinbo Zhu return -EAGAIN; 24386b11e70bSAdrian Hunter } 24396b11e70bSAdrian Hunter 244085a882c2SMasahiro Yamada int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 2441b513ea25SArindam Nath { 24424b6f37d3SRussell King struct sdhci_host *host = mmc_priv(mmc); 2443b513ea25SArindam Nath int err = 0; 244438e40bf5SAdrian Hunter unsigned int tuning_count = 0; 2445b5540ce1SAdrian Hunter bool hs400_tuning; 2446b513ea25SArindam Nath 2447b5540ce1SAdrian Hunter hs400_tuning = host->flags & SDHCI_HS400_TUNING; 2448b5540ce1SAdrian Hunter 244938e40bf5SAdrian Hunter if (host->tuning_mode == SDHCI_TUNING_MODE_1) 245038e40bf5SAdrian Hunter tuning_count = host->tuning_count; 245138e40bf5SAdrian Hunter 2452b513ea25SArindam Nath /* 24539faac7b9SWeijun Yang * The Host Controller needs tuning in case of SDR104 and DDR50 24549faac7b9SWeijun Yang * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 24559faac7b9SWeijun Yang * the Capabilities register. 2456069c9f14SGirish K S * If the Host Controller supports the HS200 mode then the 2457069c9f14SGirish K S * tuning function has to be executed. 2458b513ea25SArindam Nath */ 24594b6f37d3SRussell King switch (host->timing) { 2460b5540ce1SAdrian Hunter /* HS400 tuning is done in HS200 mode */ 2461e9fb05d5SAdrian Hunter case MMC_TIMING_MMC_HS400: 2462b5540ce1SAdrian Hunter err = -EINVAL; 24632a85ef25SAdrian Hunter goto out; 2464b5540ce1SAdrian Hunter 24654b6f37d3SRussell King case MMC_TIMING_MMC_HS200: 2466b5540ce1SAdrian Hunter /* 2467b5540ce1SAdrian Hunter * Periodic re-tuning for HS400 is not expected to be needed, so 2468b5540ce1SAdrian Hunter * disable it here. 2469b5540ce1SAdrian Hunter */ 2470b5540ce1SAdrian Hunter if (hs400_tuning) 2471b5540ce1SAdrian Hunter tuning_count = 0; 2472b5540ce1SAdrian Hunter break; 2473b5540ce1SAdrian Hunter 24744b6f37d3SRussell King case MMC_TIMING_UHS_SDR104: 24759faac7b9SWeijun Yang case MMC_TIMING_UHS_DDR50: 24764b6f37d3SRussell King break; 2477069c9f14SGirish K S 24784b6f37d3SRussell King case MMC_TIMING_UHS_SDR50: 24794228b213SAdrian Hunter if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 24804b6f37d3SRussell King break; 24814b6f37d3SRussell King /* FALLTHROUGH */ 24824b6f37d3SRussell King 24834b6f37d3SRussell King default: 24842a85ef25SAdrian Hunter goto out; 2485b513ea25SArindam Nath } 2486b513ea25SArindam Nath 248745251812SDong Aisheng if (host->ops->platform_execute_tuning) { 24888a8fa879SRitesh Harjani err = host->ops->platform_execute_tuning(host, opcode); 24892a85ef25SAdrian Hunter goto out; 249045251812SDong Aisheng } 249145251812SDong Aisheng 24926b11e70bSAdrian Hunter host->mmc->retune_period = tuning_count; 24936b11e70bSAdrian Hunter 249483b600b8SAdrian Hunter if (host->tuning_delay < 0) 249583b600b8SAdrian Hunter host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK; 249683b600b8SAdrian Hunter 2497da4bc4f2SAdrian Hunter sdhci_start_tuning(host); 2498b513ea25SArindam Nath 24997d8bb1f4SYinbo Zhu host->tuning_err = __sdhci_execute_tuning(host, opcode); 2500cf2b5eeaSArindam Nath 2501da4bc4f2SAdrian Hunter sdhci_end_tuning(host); 25022a85ef25SAdrian Hunter out: 25038a8fa879SRitesh Harjani host->flags &= ~SDHCI_HS400_TUNING; 25046b11e70bSAdrian Hunter 2505b513ea25SArindam Nath return err; 2506b513ea25SArindam Nath } 250785a882c2SMasahiro Yamada EXPORT_SYMBOL_GPL(sdhci_execute_tuning); 2508b513ea25SArindam Nath 250952983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 25104d55c5a1SArindam Nath { 25114d55c5a1SArindam Nath /* Host Controller v3.00 defines preset value registers */ 25124d55c5a1SArindam Nath if (host->version < SDHCI_SPEC_300) 25134d55c5a1SArindam Nath return; 25144d55c5a1SArindam Nath 25154d55c5a1SArindam Nath /* 25164d55c5a1SArindam Nath * We only enable or disable Preset Value if they are not already 25174d55c5a1SArindam Nath * enabled or disabled respectively. Otherwise, we bail out. 25184d55c5a1SArindam Nath */ 2519da91a8f9SRussell King if (host->preset_enabled != enable) { 2520da91a8f9SRussell King u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2521da91a8f9SRussell King 2522da91a8f9SRussell King if (enable) 25234d55c5a1SArindam Nath ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2524da91a8f9SRussell King else 25254d55c5a1SArindam Nath ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2526da91a8f9SRussell King 25274d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2528da91a8f9SRussell King 2529da91a8f9SRussell King if (enable) 2530da91a8f9SRussell King host->flags |= SDHCI_PV_ENABLED; 2531da91a8f9SRussell King else 253266fd8ad5SAdrian Hunter host->flags &= ~SDHCI_PV_ENABLED; 2533da91a8f9SRussell King 2534da91a8f9SRussell King host->preset_enabled = enable; 25354d55c5a1SArindam Nath } 253666fd8ad5SAdrian Hunter } 253766fd8ad5SAdrian Hunter 2538348487cbSHaibo Chen static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2539348487cbSHaibo Chen int err) 2540348487cbSHaibo Chen { 2541348487cbSHaibo Chen struct sdhci_host *host = mmc_priv(mmc); 2542348487cbSHaibo Chen struct mmc_data *data = mrq->data; 2543348487cbSHaibo Chen 2544f48f039cSRussell King if (data->host_cookie != COOKIE_UNMAPPED) 2545348487cbSHaibo Chen dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2546feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 2547771a3dc2SRussell King 2548d31911b9SHaibo Chen data->host_cookie = COOKIE_UNMAPPED; 2549348487cbSHaibo Chen } 2550348487cbSHaibo Chen 2551d3c6aac3SLinus Walleij static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 2552348487cbSHaibo Chen { 2553348487cbSHaibo Chen struct sdhci_host *host = mmc_priv(mmc); 2554348487cbSHaibo Chen 2555d31911b9SHaibo Chen mrq->data->host_cookie = COOKIE_UNMAPPED; 2556348487cbSHaibo Chen 2557bd9b9027SLinus Walleij /* 2558bd9b9027SLinus Walleij * No pre-mapping in the pre hook if we're using the bounce buffer, 2559bd9b9027SLinus Walleij * for that we would need two bounce buffers since one buffer is 2560bd9b9027SLinus Walleij * in flight when this is getting called. 2561bd9b9027SLinus Walleij */ 2562bd9b9027SLinus Walleij if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer) 256394538e51SRussell King sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2564348487cbSHaibo Chen } 2565348487cbSHaibo Chen 25665d0d11c5SAdrian Hunter static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 25675d0d11c5SAdrian Hunter { 25685d0d11c5SAdrian Hunter if (host->data_cmd) { 25695d0d11c5SAdrian Hunter host->data_cmd->error = err; 25705d0d11c5SAdrian Hunter sdhci_finish_mrq(host, host->data_cmd->mrq); 25715d0d11c5SAdrian Hunter } 25725d0d11c5SAdrian Hunter 25735d0d11c5SAdrian Hunter if (host->cmd) { 25745d0d11c5SAdrian Hunter host->cmd->error = err; 25755d0d11c5SAdrian Hunter sdhci_finish_mrq(host, host->cmd->mrq); 25765d0d11c5SAdrian Hunter } 25775d0d11c5SAdrian Hunter } 25785d0d11c5SAdrian Hunter 257971e69211SGuennadi Liakhovetski static void sdhci_card_event(struct mmc_host *mmc) 25801c6a0718SPierre Ossman { 258171e69211SGuennadi Liakhovetski struct sdhci_host *host = mmc_priv(mmc); 25821c6a0718SPierre Ossman unsigned long flags; 25832836766aSKrzysztof Kozlowski int present; 25841c6a0718SPierre Ossman 2585722e1280SChristian Daudt /* First check if client has provided their own card event */ 2586722e1280SChristian Daudt if (host->ops->card_event) 2587722e1280SChristian Daudt host->ops->card_event(host); 2588722e1280SChristian Daudt 2589d3940f27SAdrian Hunter present = mmc->ops->get_cd(mmc); 25902836766aSKrzysztof Kozlowski 25911c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 25921c6a0718SPierre Ossman 25935d0d11c5SAdrian Hunter /* Check sdhci_has_requests() first in case we are runtime suspended */ 25945d0d11c5SAdrian Hunter if (sdhci_has_requests(host) && !present) { 2595a3c76eb9SGirish K S pr_err("%s: Card removed during transfer!\n", 25961c6a0718SPierre Ossman mmc_hostname(host->mmc)); 2597a3c76eb9SGirish K S pr_err("%s: Resetting controller.\n", 25981c6a0718SPierre Ossman mmc_hostname(host->mmc)); 25991c6a0718SPierre Ossman 260003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 260103231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 26021c6a0718SPierre Ossman 26035d0d11c5SAdrian Hunter sdhci_error_out_mrqs(host, -ENOMEDIUM); 26041c6a0718SPierre Ossman } 26051c6a0718SPierre Ossman 26061c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 260771e69211SGuennadi Liakhovetski } 260871e69211SGuennadi Liakhovetski 260971e69211SGuennadi Liakhovetski static const struct mmc_host_ops sdhci_ops = { 261071e69211SGuennadi Liakhovetski .request = sdhci_request, 2611348487cbSHaibo Chen .post_req = sdhci_post_req, 2612348487cbSHaibo Chen .pre_req = sdhci_pre_req, 261371e69211SGuennadi Liakhovetski .set_ios = sdhci_set_ios, 261494144a46SKevin Liu .get_cd = sdhci_get_cd, 261571e69211SGuennadi Liakhovetski .get_ro = sdhci_get_ro, 261671e69211SGuennadi Liakhovetski .hw_reset = sdhci_hw_reset, 261771e69211SGuennadi Liakhovetski .enable_sdio_irq = sdhci_enable_sdio_irq, 261889f3c365SAdrian Hunter .ack_sdio_irq = sdhci_ack_sdio_irq, 261971e69211SGuennadi Liakhovetski .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2620b5540ce1SAdrian Hunter .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 262171e69211SGuennadi Liakhovetski .execute_tuning = sdhci_execute_tuning, 262271e69211SGuennadi Liakhovetski .card_event = sdhci_card_event, 262320b92a30SKevin Liu .card_busy = sdhci_card_busy, 262471e69211SGuennadi Liakhovetski }; 262571e69211SGuennadi Liakhovetski 262671e69211SGuennadi Liakhovetski /*****************************************************************************\ 262771e69211SGuennadi Liakhovetski * * 2628c07a48c2SAdrian Hunter * Request done * 262971e69211SGuennadi Liakhovetski * * 263071e69211SGuennadi Liakhovetski \*****************************************************************************/ 263171e69211SGuennadi Liakhovetski 26324e9f8fe5SAdrian Hunter static bool sdhci_request_done(struct sdhci_host *host) 26331c6a0718SPierre Ossman { 26341c6a0718SPierre Ossman unsigned long flags; 26351c6a0718SPierre Ossman struct mmc_request *mrq; 26364e9f8fe5SAdrian Hunter int i; 26371c6a0718SPierre Ossman 263866fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 263966fd8ad5SAdrian Hunter 26404e9f8fe5SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 26414e9f8fe5SAdrian Hunter mrq = host->mrqs_done[i]; 26426ebebeabSAdrian Hunter if (mrq) 26434e9f8fe5SAdrian Hunter break; 26444e9f8fe5SAdrian Hunter } 26451c6a0718SPierre Ossman 26464e9f8fe5SAdrian Hunter if (!mrq) { 26474e9f8fe5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 26484e9f8fe5SAdrian Hunter return true; 26494e9f8fe5SAdrian Hunter } 26501c6a0718SPierre Ossman 26511c6a0718SPierre Ossman /* 2652054cedffSRussell King * Always unmap the data buffers if they were mapped by 2653054cedffSRussell King * sdhci_prepare_data() whenever we finish with a request. 2654054cedffSRussell King * This avoids leaking DMA mappings on error. 2655054cedffSRussell King */ 2656054cedffSRussell King if (host->flags & SDHCI_REQ_USE_DMA) { 2657054cedffSRussell King struct mmc_data *data = mrq->data; 2658054cedffSRussell King 2659054cedffSRussell King if (data && data->host_cookie == COOKIE_MAPPED) { 2660bd9b9027SLinus Walleij if (host->bounce_buffer) { 2661bd9b9027SLinus Walleij /* 2662bd9b9027SLinus Walleij * On reads, copy the bounced data into the 2663bd9b9027SLinus Walleij * sglist 2664bd9b9027SLinus Walleij */ 2665bd9b9027SLinus Walleij if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { 2666bd9b9027SLinus Walleij unsigned int length = data->bytes_xfered; 2667bd9b9027SLinus Walleij 2668bd9b9027SLinus Walleij if (length > host->bounce_buffer_size) { 2669bd9b9027SLinus Walleij pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", 2670bd9b9027SLinus Walleij mmc_hostname(host->mmc), 2671bd9b9027SLinus Walleij host->bounce_buffer_size, 2672bd9b9027SLinus Walleij data->bytes_xfered); 2673bd9b9027SLinus Walleij /* Cap it down and continue */ 2674bd9b9027SLinus Walleij length = host->bounce_buffer_size; 2675bd9b9027SLinus Walleij } 2676bd9b9027SLinus Walleij dma_sync_single_for_cpu( 2677bd9b9027SLinus Walleij host->mmc->parent, 2678bd9b9027SLinus Walleij host->bounce_addr, 2679bd9b9027SLinus Walleij host->bounce_buffer_size, 2680bd9b9027SLinus Walleij DMA_FROM_DEVICE); 2681bd9b9027SLinus Walleij sg_copy_from_buffer(data->sg, 2682bd9b9027SLinus Walleij data->sg_len, 2683bd9b9027SLinus Walleij host->bounce_buffer, 2684bd9b9027SLinus Walleij length); 2685bd9b9027SLinus Walleij } else { 2686bd9b9027SLinus Walleij /* No copying, just switch ownership */ 2687bd9b9027SLinus Walleij dma_sync_single_for_cpu( 2688bd9b9027SLinus Walleij host->mmc->parent, 2689bd9b9027SLinus Walleij host->bounce_addr, 2690bd9b9027SLinus Walleij host->bounce_buffer_size, 2691feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 2692bd9b9027SLinus Walleij } 2693bd9b9027SLinus Walleij } else { 2694bd9b9027SLinus Walleij /* Unmap the raw data */ 2695bd9b9027SLinus Walleij dma_unmap_sg(mmc_dev(host->mmc), data->sg, 2696bd9b9027SLinus Walleij data->sg_len, 2697bd9b9027SLinus Walleij mmc_get_dma_dir(data)); 2698bd9b9027SLinus Walleij } 2699054cedffSRussell King data->host_cookie = COOKIE_UNMAPPED; 2700054cedffSRussell King } 2701054cedffSRussell King } 2702054cedffSRussell King 2703054cedffSRussell King /* 27041c6a0718SPierre Ossman * The controller needs a reset of internal state machines 27051c6a0718SPierre Ossman * upon error conditions. 27061c6a0718SPierre Ossman */ 27070cc563ceSAdrian Hunter if (sdhci_needs_reset(host, mrq)) { 27086ebebeabSAdrian Hunter /* 27096ebebeabSAdrian Hunter * Do not finish until command and data lines are available for 27106ebebeabSAdrian Hunter * reset. Note there can only be one other mrq, so it cannot 27116ebebeabSAdrian Hunter * also be in mrqs_done, otherwise host->cmd and host->data_cmd 27126ebebeabSAdrian Hunter * would both be null. 27136ebebeabSAdrian Hunter */ 27146ebebeabSAdrian Hunter if (host->cmd || host->data_cmd) { 27156ebebeabSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 27166ebebeabSAdrian Hunter return true; 27176ebebeabSAdrian Hunter } 27186ebebeabSAdrian Hunter 27191c6a0718SPierre Ossman /* Some controllers need this kick or reset won't work here */ 27208213af3bSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 27211c6a0718SPierre Ossman /* This is to force an update */ 27221771059cSRussell King host->ops->set_clock(host, host->clock); 27231c6a0718SPierre Ossman 27241c6a0718SPierre Ossman /* Spec says we should do both at the same time, but Ricoh 27251c6a0718SPierre Ossman controllers do not like that. */ 272603231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 272703231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 2728ed1563deSAdrian Hunter 2729ed1563deSAdrian Hunter host->pending_reset = false; 27301c6a0718SPierre Ossman } 27311c6a0718SPierre Ossman 27326ebebeabSAdrian Hunter host->mrqs_done[i] = NULL; 27336ebebeabSAdrian Hunter 27341c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 27351c6a0718SPierre Ossman 27361c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 27374e9f8fe5SAdrian Hunter 27384e9f8fe5SAdrian Hunter return false; 27394e9f8fe5SAdrian Hunter } 27404e9f8fe5SAdrian Hunter 2741c07a48c2SAdrian Hunter static void sdhci_complete_work(struct work_struct *work) 27424e9f8fe5SAdrian Hunter { 2743c07a48c2SAdrian Hunter struct sdhci_host *host = container_of(work, struct sdhci_host, 2744c07a48c2SAdrian Hunter complete_work); 27454e9f8fe5SAdrian Hunter 27464e9f8fe5SAdrian Hunter while (!sdhci_request_done(host)) 27474e9f8fe5SAdrian Hunter ; 27481c6a0718SPierre Ossman } 27491c6a0718SPierre Ossman 27502ee4f620SKees Cook static void sdhci_timeout_timer(struct timer_list *t) 27511c6a0718SPierre Ossman { 27521c6a0718SPierre Ossman struct sdhci_host *host; 27531c6a0718SPierre Ossman unsigned long flags; 27541c6a0718SPierre Ossman 27552ee4f620SKees Cook host = from_timer(host, t, timer); 27561c6a0718SPierre Ossman 27571c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 27581c6a0718SPierre Ossman 2759d7422fb4SAdrian Hunter if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2760d7422fb4SAdrian Hunter pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2761d7422fb4SAdrian Hunter mmc_hostname(host->mmc)); 2762d7422fb4SAdrian Hunter sdhci_dumpregs(host); 2763d7422fb4SAdrian Hunter 2764d7422fb4SAdrian Hunter host->cmd->error = -ETIMEDOUT; 2765d7422fb4SAdrian Hunter sdhci_finish_mrq(host, host->cmd->mrq); 2766d7422fb4SAdrian Hunter } 2767d7422fb4SAdrian Hunter 2768d7422fb4SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 2769d7422fb4SAdrian Hunter } 2770d7422fb4SAdrian Hunter 27712ee4f620SKees Cook static void sdhci_timeout_data_timer(struct timer_list *t) 2772d7422fb4SAdrian Hunter { 2773d7422fb4SAdrian Hunter struct sdhci_host *host; 2774d7422fb4SAdrian Hunter unsigned long flags; 2775d7422fb4SAdrian Hunter 27762ee4f620SKees Cook host = from_timer(host, t, data_timer); 2777d7422fb4SAdrian Hunter 2778d7422fb4SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2779d7422fb4SAdrian Hunter 2780d7422fb4SAdrian Hunter if (host->data || host->data_cmd || 2781d7422fb4SAdrian Hunter (host->cmd && sdhci_data_line_cmd(host->cmd))) { 27822e4456f0SMarek Vasut pr_err("%s: Timeout waiting for hardware interrupt.\n", 27832e4456f0SMarek Vasut mmc_hostname(host->mmc)); 27841c6a0718SPierre Ossman sdhci_dumpregs(host); 27851c6a0718SPierre Ossman 27861c6a0718SPierre Ossman if (host->data) { 278717b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 27881c6a0718SPierre Ossman sdhci_finish_data(host); 2789c07a48c2SAdrian Hunter queue_work(host->complete_wq, &host->complete_work); 2790d7422fb4SAdrian Hunter } else if (host->data_cmd) { 2791d7422fb4SAdrian Hunter host->data_cmd->error = -ETIMEDOUT; 2792d7422fb4SAdrian Hunter sdhci_finish_mrq(host, host->data_cmd->mrq); 27931c6a0718SPierre Ossman } else { 279417b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 2795d7422fb4SAdrian Hunter sdhci_finish_mrq(host, host->cmd->mrq); 27961c6a0718SPierre Ossman } 27971c6a0718SPierre Ossman } 27981c6a0718SPierre Ossman 27991c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 28001c6a0718SPierre Ossman } 28011c6a0718SPierre Ossman 28021c6a0718SPierre Ossman /*****************************************************************************\ 28031c6a0718SPierre Ossman * * 28041c6a0718SPierre Ossman * Interrupt handling * 28051c6a0718SPierre Ossman * * 28061c6a0718SPierre Ossman \*****************************************************************************/ 28071c6a0718SPierre Ossman 28084bf78099SAdrian Hunter static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p) 28091c6a0718SPierre Ossman { 2810af849c86SAdrian Hunter /* Handle auto-CMD12 error */ 2811af849c86SAdrian Hunter if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) { 2812af849c86SAdrian Hunter struct mmc_request *mrq = host->data_cmd->mrq; 2813af849c86SAdrian Hunter u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); 2814af849c86SAdrian Hunter int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? 2815af849c86SAdrian Hunter SDHCI_INT_DATA_TIMEOUT : 2816af849c86SAdrian Hunter SDHCI_INT_DATA_CRC; 2817af849c86SAdrian Hunter 2818af849c86SAdrian Hunter /* Treat auto-CMD12 error the same as data error */ 2819af849c86SAdrian Hunter if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 2820af849c86SAdrian Hunter *intmask_p |= data_err_bit; 2821af849c86SAdrian Hunter return; 2822af849c86SAdrian Hunter } 2823af849c86SAdrian Hunter } 2824af849c86SAdrian Hunter 28251c6a0718SPierre Ossman if (!host->cmd) { 2826ed1563deSAdrian Hunter /* 2827ed1563deSAdrian Hunter * SDHCI recovers from errors by resetting the cmd and data 2828ed1563deSAdrian Hunter * circuits. Until that is done, there very well might be more 2829ed1563deSAdrian Hunter * interrupts, so ignore them in that case. 2830ed1563deSAdrian Hunter */ 2831ed1563deSAdrian Hunter if (host->pending_reset) 2832ed1563deSAdrian Hunter return; 28332e4456f0SMarek Vasut pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2834b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 28351c6a0718SPierre Ossman sdhci_dumpregs(host); 28361c6a0718SPierre Ossman return; 28371c6a0718SPierre Ossman } 28381c6a0718SPierre Ossman 2839ec014cbaSRussell King if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2840ec014cbaSRussell King SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 28411c6a0718SPierre Ossman if (intmask & SDHCI_INT_TIMEOUT) 284217b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 2843ec014cbaSRussell King else 284417b0429dSPierre Ossman host->cmd->error = -EILSEQ; 28451c6a0718SPierre Ossman 28464bf78099SAdrian Hunter /* Treat data command CRC error the same as data CRC error */ 284771fcbda0SRussell King if (host->cmd->data && 284871fcbda0SRussell King (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 284971fcbda0SRussell King SDHCI_INT_CRC) { 285071fcbda0SRussell King host->cmd = NULL; 28514bf78099SAdrian Hunter *intmask_p |= SDHCI_INT_DATA_CRC; 285271fcbda0SRussell King return; 285371fcbda0SRussell King } 285471fcbda0SRussell King 285519d2f695SAdrian Hunter __sdhci_finish_mrq(host, host->cmd->mrq); 2856e809517fSPierre Ossman return; 2857e809517fSPierre Ossman } 2858e809517fSPierre Ossman 2859af849c86SAdrian Hunter /* Handle auto-CMD23 error */ 2860af849c86SAdrian Hunter if (intmask & SDHCI_INT_AUTO_CMD_ERR) { 2861af849c86SAdrian Hunter struct mmc_request *mrq = host->cmd->mrq; 2862af849c86SAdrian Hunter u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); 2863af849c86SAdrian Hunter int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? 2864af849c86SAdrian Hunter -ETIMEDOUT : 2865af849c86SAdrian Hunter -EILSEQ; 2866af849c86SAdrian Hunter 2867af849c86SAdrian Hunter if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 2868af849c86SAdrian Hunter mrq->sbc->error = err; 286919d2f695SAdrian Hunter __sdhci_finish_mrq(host, mrq); 2870af849c86SAdrian Hunter return; 2871af849c86SAdrian Hunter } 2872af849c86SAdrian Hunter } 2873af849c86SAdrian Hunter 2874e809517fSPierre Ossman if (intmask & SDHCI_INT_RESPONSE) 287543b58b36SPierre Ossman sdhci_finish_command(host); 28761c6a0718SPierre Ossman } 28771c6a0718SPierre Ossman 287808621b18SAdrian Hunter static void sdhci_adma_show_error(struct sdhci_host *host) 28796882a8c0SBen Dooks { 28801c3d5f6dSAdrian Hunter void *desc = host->adma_table; 28816882a8c0SBen Dooks 28826882a8c0SBen Dooks sdhci_dumpregs(host); 28836882a8c0SBen Dooks 28846882a8c0SBen Dooks while (true) { 2885e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 28866882a8c0SBen Dooks 2887e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 2888f421865dSAdrian Hunter DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2889f421865dSAdrian Hunter desc, le32_to_cpu(dma_desc->addr_hi), 2890e57a5f61SAdrian Hunter le32_to_cpu(dma_desc->addr_lo), 2891e57a5f61SAdrian Hunter le16_to_cpu(dma_desc->len), 2892e57a5f61SAdrian Hunter le16_to_cpu(dma_desc->cmd)); 2893e57a5f61SAdrian Hunter else 2894f421865dSAdrian Hunter DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2895f421865dSAdrian Hunter desc, le32_to_cpu(dma_desc->addr_lo), 28960545230fSAdrian Hunter le16_to_cpu(dma_desc->len), 28970545230fSAdrian Hunter le16_to_cpu(dma_desc->cmd)); 28986882a8c0SBen Dooks 289976fe379aSAdrian Hunter desc += host->desc_sz; 29006882a8c0SBen Dooks 29010545230fSAdrian Hunter if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 29026882a8c0SBen Dooks break; 29036882a8c0SBen Dooks } 29046882a8c0SBen Dooks } 29056882a8c0SBen Dooks 29061c6a0718SPierre Ossman static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 29071c6a0718SPierre Ossman { 2908069c9f14SGirish K S u32 command; 29091c6a0718SPierre Ossman 2910b513ea25SArindam Nath /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2911b513ea25SArindam Nath if (intmask & SDHCI_INT_DATA_AVAIL) { 2912069c9f14SGirish K S command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2913069c9f14SGirish K S if (command == MMC_SEND_TUNING_BLOCK || 2914069c9f14SGirish K S command == MMC_SEND_TUNING_BLOCK_HS200) { 2915b513ea25SArindam Nath host->tuning_done = 1; 2916b513ea25SArindam Nath wake_up(&host->buf_ready_int); 2917b513ea25SArindam Nath return; 2918b513ea25SArindam Nath } 2919b513ea25SArindam Nath } 2920b513ea25SArindam Nath 29211c6a0718SPierre Ossman if (!host->data) { 29227c89a3d9SAdrian Hunter struct mmc_command *data_cmd = host->data_cmd; 29237c89a3d9SAdrian Hunter 29241c6a0718SPierre Ossman /* 2925e809517fSPierre Ossman * The "data complete" interrupt is also used to 2926e809517fSPierre Ossman * indicate that a busy state has ended. See comment 2927e809517fSPierre Ossman * above in sdhci_cmd_irq(). 29281c6a0718SPierre Ossman */ 29297c89a3d9SAdrian Hunter if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 2930c5abd5e8SMatthieu CASTET if (intmask & SDHCI_INT_DATA_TIMEOUT) { 293169b962a6SAdrian Hunter host->data_cmd = NULL; 29327c89a3d9SAdrian Hunter data_cmd->error = -ETIMEDOUT; 293319d2f695SAdrian Hunter __sdhci_finish_mrq(host, data_cmd->mrq); 2934c5abd5e8SMatthieu CASTET return; 2935c5abd5e8SMatthieu CASTET } 2936e809517fSPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 293769b962a6SAdrian Hunter host->data_cmd = NULL; 2938e99783a4SChanho Min /* 2939e99783a4SChanho Min * Some cards handle busy-end interrupt 2940e99783a4SChanho Min * before the command completed, so make 2941e99783a4SChanho Min * sure we do things in the proper order. 2942e99783a4SChanho Min */ 2943ea968023SAdrian Hunter if (host->cmd == data_cmd) 2944ea968023SAdrian Hunter return; 2945ea968023SAdrian Hunter 294619d2f695SAdrian Hunter __sdhci_finish_mrq(host, data_cmd->mrq); 29471c6a0718SPierre Ossman return; 2948e809517fSPierre Ossman } 2949e809517fSPierre Ossman } 29501c6a0718SPierre Ossman 2951ed1563deSAdrian Hunter /* 2952ed1563deSAdrian Hunter * SDHCI recovers from errors by resetting the cmd and data 2953ed1563deSAdrian Hunter * circuits. Until that is done, there very well might be more 2954ed1563deSAdrian Hunter * interrupts, so ignore them in that case. 2955ed1563deSAdrian Hunter */ 2956ed1563deSAdrian Hunter if (host->pending_reset) 2957ed1563deSAdrian Hunter return; 2958ed1563deSAdrian Hunter 29592e4456f0SMarek Vasut pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2960b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 29611c6a0718SPierre Ossman sdhci_dumpregs(host); 29621c6a0718SPierre Ossman 29631c6a0718SPierre Ossman return; 29641c6a0718SPierre Ossman } 29651c6a0718SPierre Ossman 29661c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_TIMEOUT) 296717b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 296822113efdSAries Lee else if (intmask & SDHCI_INT_DATA_END_BIT) 296922113efdSAries Lee host->data->error = -EILSEQ; 297022113efdSAries Lee else if ((intmask & SDHCI_INT_DATA_CRC) && 297122113efdSAries Lee SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 297222113efdSAries Lee != MMC_BUS_TEST_R) 297317b0429dSPierre Ossman host->data->error = -EILSEQ; 29746882a8c0SBen Dooks else if (intmask & SDHCI_INT_ADMA_ERROR) { 2975a3c76eb9SGirish K S pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 297608621b18SAdrian Hunter sdhci_adma_show_error(host); 29772134a922SPierre Ossman host->data->error = -EIO; 2978a4071fbbSHaijun Zhang if (host->ops->adma_workaround) 2979a4071fbbSHaijun Zhang host->ops->adma_workaround(host, intmask); 29806882a8c0SBen Dooks } 29811c6a0718SPierre Ossman 298217b0429dSPierre Ossman if (host->data->error) 29831c6a0718SPierre Ossman sdhci_finish_data(host); 29841c6a0718SPierre Ossman else { 29851c6a0718SPierre Ossman if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 29861c6a0718SPierre Ossman sdhci_transfer_pio(host); 29871c6a0718SPierre Ossman 29886ba736a1SPierre Ossman /* 29896ba736a1SPierre Ossman * We currently don't do anything fancy with DMA 29906ba736a1SPierre Ossman * boundaries, but as we can't disable the feature 29916ba736a1SPierre Ossman * we need to at least restart the transfer. 2992f6a03cbfSMikko Vinni * 2993f6a03cbfSMikko Vinni * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2994f6a03cbfSMikko Vinni * should return a valid address to continue from, but as 2995f6a03cbfSMikko Vinni * some controllers are faulty, don't trust them. 29966ba736a1SPierre Ossman */ 2997f6a03cbfSMikko Vinni if (intmask & SDHCI_INT_DMA_END) { 2998917a0c52SChunyan Zhang dma_addr_t dmastart, dmanow; 2999bd9b9027SLinus Walleij 3000bd9b9027SLinus Walleij dmastart = sdhci_sdma_address(host); 3001f6a03cbfSMikko Vinni dmanow = dmastart + host->data->bytes_xfered; 3002f6a03cbfSMikko Vinni /* 3003f6a03cbfSMikko Vinni * Force update to the next DMA block boundary. 3004f6a03cbfSMikko Vinni */ 3005f6a03cbfSMikko Vinni dmanow = (dmanow & 3006917a0c52SChunyan Zhang ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 3007f6a03cbfSMikko Vinni SDHCI_DEFAULT_BOUNDARY_SIZE; 3008f6a03cbfSMikko Vinni host->data->bytes_xfered = dmanow - dmastart; 3009917a0c52SChunyan Zhang DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", 3010917a0c52SChunyan Zhang &dmastart, host->data->bytes_xfered, &dmanow); 3011917a0c52SChunyan Zhang sdhci_set_sdma_addr(host, dmanow); 3012f6a03cbfSMikko Vinni } 30136ba736a1SPierre Ossman 3014e538fbe8SPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 30157c89a3d9SAdrian Hunter if (host->cmd == host->data_cmd) { 3016e538fbe8SPierre Ossman /* 3017e538fbe8SPierre Ossman * Data managed to finish before the 3018e538fbe8SPierre Ossman * command completed. Make sure we do 3019e538fbe8SPierre Ossman * things in the proper order. 3020e538fbe8SPierre Ossman */ 3021e538fbe8SPierre Ossman host->data_early = 1; 3022e538fbe8SPierre Ossman } else { 30231c6a0718SPierre Ossman sdhci_finish_data(host); 30241c6a0718SPierre Ossman } 30251c6a0718SPierre Ossman } 3026e538fbe8SPierre Ossman } 3027e538fbe8SPierre Ossman } 30281c6a0718SPierre Ossman 302919d2f695SAdrian Hunter static inline bool sdhci_defer_done(struct sdhci_host *host, 303019d2f695SAdrian Hunter struct mmc_request *mrq) 303119d2f695SAdrian Hunter { 303219d2f695SAdrian Hunter struct mmc_data *data = mrq->data; 303319d2f695SAdrian Hunter 303419d2f695SAdrian Hunter return host->pending_reset || 303519d2f695SAdrian Hunter ((host->flags & SDHCI_REQ_USE_DMA) && data && 303619d2f695SAdrian Hunter data->host_cookie == COOKIE_MAPPED); 303719d2f695SAdrian Hunter } 303819d2f695SAdrian Hunter 30391c6a0718SPierre Ossman static irqreturn_t sdhci_irq(int irq, void *dev_id) 30401c6a0718SPierre Ossman { 304119d2f695SAdrian Hunter struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0}; 3042781e989cSRussell King irqreturn_t result = IRQ_NONE; 30431c6a0718SPierre Ossman struct sdhci_host *host = dev_id; 304441005003SRussell King u32 intmask, mask, unexpected = 0; 3045781e989cSRussell King int max_loops = 16; 304619d2f695SAdrian Hunter int i; 30471c6a0718SPierre Ossman 30481c6a0718SPierre Ossman spin_lock(&host->lock); 30491c6a0718SPierre Ossman 3050be138554SRussell King if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 305166fd8ad5SAdrian Hunter spin_unlock(&host->lock); 3052655bca76SAdrian Hunter return IRQ_NONE; 305366fd8ad5SAdrian Hunter } 305466fd8ad5SAdrian Hunter 30554e4141a5SAnton Vorontsov intmask = sdhci_readl(host, SDHCI_INT_STATUS); 30561c6a0718SPierre Ossman if (!intmask || intmask == 0xffffffff) { 30571c6a0718SPierre Ossman result = IRQ_NONE; 30581c6a0718SPierre Ossman goto out; 30591c6a0718SPierre Ossman } 30601c6a0718SPierre Ossman 306141005003SRussell King do { 3062f12e39dbSAdrian Hunter DBG("IRQ status 0x%08x\n", intmask); 3063f12e39dbSAdrian Hunter 3064f12e39dbSAdrian Hunter if (host->ops->irq) { 3065f12e39dbSAdrian Hunter intmask = host->ops->irq(host, intmask); 3066f12e39dbSAdrian Hunter if (!intmask) 3067f12e39dbSAdrian Hunter goto cont; 3068f12e39dbSAdrian Hunter } 3069f12e39dbSAdrian Hunter 307041005003SRussell King /* Clear selected interrupts. */ 307141005003SRussell King mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 307241005003SRussell King SDHCI_INT_BUS_POWER); 307341005003SRussell King sdhci_writel(host, mask, SDHCI_INT_STATUS); 307441005003SRussell King 30751c6a0718SPierre Ossman if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 3076d25928d1SShawn Guo u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 3077d25928d1SShawn Guo SDHCI_CARD_PRESENT; 3078d25928d1SShawn Guo 3079d25928d1SShawn Guo /* 308041005003SRussell King * There is a observation on i.mx esdhc. INSERT 308141005003SRussell King * bit will be immediately set again when it gets 308241005003SRussell King * cleared, if a card is inserted. We have to mask 308341005003SRussell King * the irq to prevent interrupt storm which will 308441005003SRussell King * freeze the system. And the REMOVE gets the 308541005003SRussell King * same situation. 3086d25928d1SShawn Guo * 308741005003SRussell King * More testing are needed here to ensure it works 308841005003SRussell King * for other platforms though. 3089d25928d1SShawn Guo */ 3090b537f94cSRussell King host->ier &= ~(SDHCI_INT_CARD_INSERT | 3091d25928d1SShawn Guo SDHCI_INT_CARD_REMOVE); 3092b537f94cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 3093b537f94cSRussell King SDHCI_INT_CARD_INSERT; 3094b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3095b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3096d25928d1SShawn Guo 30974e4141a5SAnton Vorontsov sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 30984e4141a5SAnton Vorontsov SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 30993560db8eSRussell King 31003560db8eSRussell King host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 31013560db8eSRussell King SDHCI_INT_CARD_REMOVE); 31023560db8eSRussell King result = IRQ_WAKE_THREAD; 31031c6a0718SPierre Ossman } 31041c6a0718SPierre Ossman 310541005003SRussell King if (intmask & SDHCI_INT_CMD_MASK) 31064bf78099SAdrian Hunter sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask); 31071c6a0718SPierre Ossman 310841005003SRussell King if (intmask & SDHCI_INT_DATA_MASK) 31091c6a0718SPierre Ossman sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 31101c6a0718SPierre Ossman 311141005003SRussell King if (intmask & SDHCI_INT_BUS_POWER) 3112a3c76eb9SGirish K S pr_err("%s: Card is consuming too much power!\n", 31131c6a0718SPierre Ossman mmc_hostname(host->mmc)); 31141c6a0718SPierre Ossman 3115f37b20ebSDong Aisheng if (intmask & SDHCI_INT_RETUNE) 3116f37b20ebSDong Aisheng mmc_retune_needed(host->mmc); 3117f37b20ebSDong Aisheng 3118161e6d44SGabriel Krisman Bertazi if ((intmask & SDHCI_INT_CARD_INT) && 3119161e6d44SGabriel Krisman Bertazi (host->ier & SDHCI_INT_CARD_INT)) { 3120781e989cSRussell King sdhci_enable_sdio_irq_nolock(host, false); 312189f3c365SAdrian Hunter sdio_signal_irq(host->mmc); 3122781e989cSRussell King } 3123f75979b7SPierre Ossman 312441005003SRussell King intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 312541005003SRussell King SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 312641005003SRussell King SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 3127f37b20ebSDong Aisheng SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 3128f75979b7SPierre Ossman 31291c6a0718SPierre Ossman if (intmask) { 31306379b237SAlexander Stein unexpected |= intmask; 31314e4141a5SAnton Vorontsov sdhci_writel(host, intmask, SDHCI_INT_STATUS); 31321c6a0718SPierre Ossman } 3133f12e39dbSAdrian Hunter cont: 3134781e989cSRussell King if (result == IRQ_NONE) 31351c6a0718SPierre Ossman result = IRQ_HANDLED; 31361c6a0718SPierre Ossman 31376379b237SAlexander Stein intmask = sdhci_readl(host, SDHCI_INT_STATUS); 313841005003SRussell King } while (intmask && --max_loops); 313919d2f695SAdrian Hunter 314019d2f695SAdrian Hunter /* Determine if mrqs can be completed immediately */ 314119d2f695SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 314219d2f695SAdrian Hunter struct mmc_request *mrq = host->mrqs_done[i]; 314319d2f695SAdrian Hunter 314419d2f695SAdrian Hunter if (!mrq) 314519d2f695SAdrian Hunter continue; 314619d2f695SAdrian Hunter 314719d2f695SAdrian Hunter if (sdhci_defer_done(host, mrq)) { 3148c07a48c2SAdrian Hunter result = IRQ_WAKE_THREAD; 314919d2f695SAdrian Hunter } else { 315019d2f695SAdrian Hunter mrqs_done[i] = mrq; 315119d2f695SAdrian Hunter host->mrqs_done[i] = NULL; 315219d2f695SAdrian Hunter } 315319d2f695SAdrian Hunter } 31541c6a0718SPierre Ossman out: 31551c6a0718SPierre Ossman spin_unlock(&host->lock); 31561c6a0718SPierre Ossman 315719d2f695SAdrian Hunter /* Process mrqs ready for immediate completion */ 315819d2f695SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 315919d2f695SAdrian Hunter if (mrqs_done[i]) 316019d2f695SAdrian Hunter mmc_request_done(host->mmc, mrqs_done[i]); 316119d2f695SAdrian Hunter } 316219d2f695SAdrian Hunter 31636379b237SAlexander Stein if (unexpected) { 31646379b237SAlexander Stein pr_err("%s: Unexpected interrupt 0x%08x.\n", 31656379b237SAlexander Stein mmc_hostname(host->mmc), unexpected); 31666379b237SAlexander Stein sdhci_dumpregs(host); 31676379b237SAlexander Stein } 3168f75979b7SPierre Ossman 31691c6a0718SPierre Ossman return result; 31701c6a0718SPierre Ossman } 31711c6a0718SPierre Ossman 3172781e989cSRussell King static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 3173781e989cSRussell King { 3174781e989cSRussell King struct sdhci_host *host = dev_id; 3175781e989cSRussell King unsigned long flags; 3176781e989cSRussell King u32 isr; 3177781e989cSRussell King 3178c07a48c2SAdrian Hunter while (!sdhci_request_done(host)) 3179c07a48c2SAdrian Hunter ; 3180c07a48c2SAdrian Hunter 3181781e989cSRussell King spin_lock_irqsave(&host->lock, flags); 3182781e989cSRussell King isr = host->thread_isr; 3183781e989cSRussell King host->thread_isr = 0; 3184781e989cSRussell King spin_unlock_irqrestore(&host->lock, flags); 3185781e989cSRussell King 31863560db8eSRussell King if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 3187d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 3188d3940f27SAdrian Hunter 3189d3940f27SAdrian Hunter mmc->ops->card_event(mmc); 3190d3940f27SAdrian Hunter mmc_detect_change(mmc, msecs_to_jiffies(200)); 31913560db8eSRussell King } 31923560db8eSRussell King 3193c07a48c2SAdrian Hunter return IRQ_HANDLED; 3194781e989cSRussell King } 3195781e989cSRussell King 31961c6a0718SPierre Ossman /*****************************************************************************\ 31971c6a0718SPierre Ossman * * 31981c6a0718SPierre Ossman * Suspend/resume * 31991c6a0718SPierre Ossman * * 32001c6a0718SPierre Ossman \*****************************************************************************/ 32011c6a0718SPierre Ossman 32021c6a0718SPierre Ossman #ifdef CONFIG_PM 32039c316b38SAdrian Hunter 32049c316b38SAdrian Hunter static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host) 32059c316b38SAdrian Hunter { 32069c316b38SAdrian Hunter return mmc_card_is_removable(host->mmc) && 32079c316b38SAdrian Hunter !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 32089c316b38SAdrian Hunter !mmc_can_gpio_cd(host->mmc); 32099c316b38SAdrian Hunter } 32109c316b38SAdrian Hunter 321184d62605SLudovic Desroches /* 321284d62605SLudovic Desroches * To enable wakeup events, the corresponding events have to be enabled in 321384d62605SLudovic Desroches * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 321484d62605SLudovic Desroches * Table' in the SD Host Controller Standard Specification. 321584d62605SLudovic Desroches * It is useless to restore SDHCI_INT_ENABLE state in 321684d62605SLudovic Desroches * sdhci_disable_irq_wakeups() since it will be set by 321784d62605SLudovic Desroches * sdhci_enable_card_detection() or sdhci_init(). 321884d62605SLudovic Desroches */ 321958e79b60SAdrian Hunter static bool sdhci_enable_irq_wakeups(struct sdhci_host *host) 3220ad080d79SKevin Liu { 322181b14543SAdrian Hunter u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | 322281b14543SAdrian Hunter SDHCI_WAKE_ON_INT; 322381b14543SAdrian Hunter u32 irq_val = 0; 322481b14543SAdrian Hunter u8 wake_val = 0; 3225ad080d79SKevin Liu u8 val; 322681b14543SAdrian Hunter 32279c316b38SAdrian Hunter if (sdhci_cd_irq_can_wakeup(host)) { 322881b14543SAdrian Hunter wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE; 322981b14543SAdrian Hunter irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE; 323081b14543SAdrian Hunter } 323181b14543SAdrian Hunter 3232d5d568faSAdrian Hunter if (mmc_card_wake_sdio_irq(host->mmc)) { 323381b14543SAdrian Hunter wake_val |= SDHCI_WAKE_ON_INT; 323481b14543SAdrian Hunter irq_val |= SDHCI_INT_CARD_INT; 3235d5d568faSAdrian Hunter } 3236d5d568faSAdrian Hunter 3237d5d568faSAdrian Hunter if (!irq_val) 3238d5d568faSAdrian Hunter return false; 3239ad080d79SKevin Liu 3240ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 324181b14543SAdrian Hunter val &= ~mask; 324281b14543SAdrian Hunter val |= wake_val; 3243ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 324481b14543SAdrian Hunter 324584d62605SLudovic Desroches sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 324658e79b60SAdrian Hunter 324758e79b60SAdrian Hunter host->irq_wake_enabled = !enable_irq_wake(host->irq); 324858e79b60SAdrian Hunter 324958e79b60SAdrian Hunter return host->irq_wake_enabled; 3250ad080d79SKevin Liu } 3251ad080d79SKevin Liu 32520b10f478SFabio Estevam static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 3253ad080d79SKevin Liu { 3254ad080d79SKevin Liu u8 val; 3255ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 3256ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 3257ad080d79SKevin Liu 3258ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 3259ad080d79SKevin Liu val &= ~mask; 3260ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 326158e79b60SAdrian Hunter 326258e79b60SAdrian Hunter disable_irq_wake(host->irq); 326358e79b60SAdrian Hunter 326458e79b60SAdrian Hunter host->irq_wake_enabled = false; 3265ad080d79SKevin Liu } 32661c6a0718SPierre Ossman 326729495aa0SManuel Lauss int sdhci_suspend_host(struct sdhci_host *host) 32681c6a0718SPierre Ossman { 32697260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 32707260cf5eSAnton Vorontsov 327166c39dfcSAdrian Hunter mmc_retune_timer_stop(host->mmc); 3272cf2b5eeaSArindam Nath 327358e79b60SAdrian Hunter if (!device_may_wakeup(mmc_dev(host->mmc)) || 327458e79b60SAdrian Hunter !sdhci_enable_irq_wakeups(host)) { 3275b537f94cSRussell King host->ier = 0; 3276b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3277b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3278b8c86fc5SPierre Ossman free_irq(host->irq, host); 3279ad080d79SKevin Liu } 328058e79b60SAdrian Hunter 32814ee14ec6SUlf Hansson return 0; 3282b8c86fc5SPierre Ossman } 3283b8c86fc5SPierre Ossman 3284b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_suspend_host); 3285b8c86fc5SPierre Ossman 3286b8c86fc5SPierre Ossman int sdhci_resume_host(struct sdhci_host *host) 3287b8c86fc5SPierre Ossman { 3288d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 32894ee14ec6SUlf Hansson int ret = 0; 3290b8c86fc5SPierre Ossman 3291a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3292b8c86fc5SPierre Ossman if (host->ops->enable_dma) 3293b8c86fc5SPierre Ossman host->ops->enable_dma(host); 3294b8c86fc5SPierre Ossman } 3295b8c86fc5SPierre Ossman 32966308d290SAdrian Hunter if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 32976308d290SAdrian Hunter (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 32986308d290SAdrian Hunter /* Card keeps power but host controller does not */ 32996308d290SAdrian Hunter sdhci_init(host, 0); 33006308d290SAdrian Hunter host->pwr = 0; 33016308d290SAdrian Hunter host->clock = 0; 3302d3940f27SAdrian Hunter mmc->ops->set_ios(mmc, &mmc->ios); 33036308d290SAdrian Hunter } else { 33042f4cbb3dSNicolas Pitre sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 33056308d290SAdrian Hunter } 3306b8c86fc5SPierre Ossman 330758e79b60SAdrian Hunter if (host->irq_wake_enabled) { 330858e79b60SAdrian Hunter sdhci_disable_irq_wakeups(host); 330958e79b60SAdrian Hunter } else { 331014a7b416SHaibo Chen ret = request_threaded_irq(host->irq, sdhci_irq, 331114a7b416SHaibo Chen sdhci_thread_irq, IRQF_SHARED, 331214a7b416SHaibo Chen mmc_hostname(host->mmc), host); 331314a7b416SHaibo Chen if (ret) 331414a7b416SHaibo Chen return ret; 331514a7b416SHaibo Chen } 331614a7b416SHaibo Chen 33177260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 33187260cf5eSAnton Vorontsov 33192f4cbb3dSNicolas Pitre return ret; 33201c6a0718SPierre Ossman } 33211c6a0718SPierre Ossman 3322b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_resume_host); 332366fd8ad5SAdrian Hunter 332466fd8ad5SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host) 332566fd8ad5SAdrian Hunter { 332666fd8ad5SAdrian Hunter unsigned long flags; 332766fd8ad5SAdrian Hunter 332866c39dfcSAdrian Hunter mmc_retune_timer_stop(host->mmc); 332966fd8ad5SAdrian Hunter 333066fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 3331b537f94cSRussell King host->ier &= SDHCI_INT_CARD_INT; 3332b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3333b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 333466fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 333566fd8ad5SAdrian Hunter 3336781e989cSRussell King synchronize_hardirq(host->irq); 333766fd8ad5SAdrian Hunter 333866fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 333966fd8ad5SAdrian Hunter host->runtime_suspended = true; 334066fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 334166fd8ad5SAdrian Hunter 33428a125badSMarkus Pargmann return 0; 334366fd8ad5SAdrian Hunter } 334466fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 334566fd8ad5SAdrian Hunter 3346c6303c5dSBaolin Wang int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset) 334766fd8ad5SAdrian Hunter { 3348d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 334966fd8ad5SAdrian Hunter unsigned long flags; 33508a125badSMarkus Pargmann int host_flags = host->flags; 335166fd8ad5SAdrian Hunter 335266fd8ad5SAdrian Hunter if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 335366fd8ad5SAdrian Hunter if (host->ops->enable_dma) 335466fd8ad5SAdrian Hunter host->ops->enable_dma(host); 335566fd8ad5SAdrian Hunter } 335666fd8ad5SAdrian Hunter 3357c6303c5dSBaolin Wang sdhci_init(host, soft_reset); 335866fd8ad5SAdrian Hunter 335970bc85adSZhoujie Wu if (mmc->ios.power_mode != MMC_POWER_UNDEFINED && 336070bc85adSZhoujie Wu mmc->ios.power_mode != MMC_POWER_OFF) { 336166fd8ad5SAdrian Hunter /* Force clock and power re-program */ 336266fd8ad5SAdrian Hunter host->pwr = 0; 336366fd8ad5SAdrian Hunter host->clock = 0; 3364d3940f27SAdrian Hunter mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 3365d3940f27SAdrian Hunter mmc->ops->set_ios(mmc, &mmc->ios); 336666fd8ad5SAdrian Hunter 336752983382SKevin Liu if ((host_flags & SDHCI_PV_ENABLED) && 336852983382SKevin Liu !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 336952983382SKevin Liu spin_lock_irqsave(&host->lock, flags); 337052983382SKevin Liu sdhci_enable_preset_value(host, true); 337152983382SKevin Liu spin_unlock_irqrestore(&host->lock, flags); 337252983382SKevin Liu } 337366fd8ad5SAdrian Hunter 3374086b0ddbSAdrian Hunter if ((mmc->caps2 & MMC_CAP2_HS400_ES) && 3375086b0ddbSAdrian Hunter mmc->ops->hs400_enhanced_strobe) 3376086b0ddbSAdrian Hunter mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); 337784ec048bSAdrian Hunter } 3378086b0ddbSAdrian Hunter 337966fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 338066fd8ad5SAdrian Hunter 338166fd8ad5SAdrian Hunter host->runtime_suspended = false; 338266fd8ad5SAdrian Hunter 338366fd8ad5SAdrian Hunter /* Enable SDIO IRQ */ 3384ef104333SRussell King if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 338566fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 338666fd8ad5SAdrian Hunter 338766fd8ad5SAdrian Hunter /* Enable Card Detection */ 338866fd8ad5SAdrian Hunter sdhci_enable_card_detection(host); 338966fd8ad5SAdrian Hunter 339066fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 339166fd8ad5SAdrian Hunter 33928a125badSMarkus Pargmann return 0; 339366fd8ad5SAdrian Hunter } 339466fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 339566fd8ad5SAdrian Hunter 3396162d6f98SRafael J. Wysocki #endif /* CONFIG_PM */ 339766fd8ad5SAdrian Hunter 33981c6a0718SPierre Ossman /*****************************************************************************\ 33991c6a0718SPierre Ossman * * 3400f12e39dbSAdrian Hunter * Command Queue Engine (CQE) helpers * 3401f12e39dbSAdrian Hunter * * 3402f12e39dbSAdrian Hunter \*****************************************************************************/ 3403f12e39dbSAdrian Hunter 3404f12e39dbSAdrian Hunter void sdhci_cqe_enable(struct mmc_host *mmc) 3405f12e39dbSAdrian Hunter { 3406f12e39dbSAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 3407f12e39dbSAdrian Hunter unsigned long flags; 3408f12e39dbSAdrian Hunter u8 ctrl; 3409f12e39dbSAdrian Hunter 3410f12e39dbSAdrian Hunter spin_lock_irqsave(&host->lock, flags); 3411f12e39dbSAdrian Hunter 3412f12e39dbSAdrian Hunter ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3413f12e39dbSAdrian Hunter ctrl &= ~SDHCI_CTRL_DMA_MASK; 34144c4faff6SSowjanya Komatineni /* 34154c4faff6SSowjanya Komatineni * Host from V4.10 supports ADMA3 DMA type. 34164c4faff6SSowjanya Komatineni * ADMA3 performs integrated descriptor which is more suitable 34174c4faff6SSowjanya Komatineni * for cmd queuing to fetch both command and transfer descriptors. 34184c4faff6SSowjanya Komatineni */ 34194c4faff6SSowjanya Komatineni if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3)) 34204c4faff6SSowjanya Komatineni ctrl |= SDHCI_CTRL_ADMA3; 34214c4faff6SSowjanya Komatineni else if (host->flags & SDHCI_USE_64_BIT_DMA) 3422f12e39dbSAdrian Hunter ctrl |= SDHCI_CTRL_ADMA64; 3423f12e39dbSAdrian Hunter else 3424f12e39dbSAdrian Hunter ctrl |= SDHCI_CTRL_ADMA32; 3425f12e39dbSAdrian Hunter sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3426f12e39dbSAdrian Hunter 3427c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512), 3428f12e39dbSAdrian Hunter SDHCI_BLOCK_SIZE); 3429f12e39dbSAdrian Hunter 3430f12e39dbSAdrian Hunter /* Set maximum timeout */ 3431401059dfSBOUGH CHEN sdhci_set_timeout(host, NULL); 3432f12e39dbSAdrian Hunter 3433f12e39dbSAdrian Hunter host->ier = host->cqe_ier; 3434f12e39dbSAdrian Hunter 3435f12e39dbSAdrian Hunter sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3436f12e39dbSAdrian Hunter sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3437f12e39dbSAdrian Hunter 3438f12e39dbSAdrian Hunter host->cqe_on = true; 3439f12e39dbSAdrian Hunter 3440f12e39dbSAdrian Hunter pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n", 3441f12e39dbSAdrian Hunter mmc_hostname(mmc), host->ier, 3442f12e39dbSAdrian Hunter sdhci_readl(host, SDHCI_INT_STATUS)); 3443f12e39dbSAdrian Hunter 3444f12e39dbSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 3445f12e39dbSAdrian Hunter } 3446f12e39dbSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cqe_enable); 3447f12e39dbSAdrian Hunter 3448f12e39dbSAdrian Hunter void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery) 3449f12e39dbSAdrian Hunter { 3450f12e39dbSAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 3451f12e39dbSAdrian Hunter unsigned long flags; 3452f12e39dbSAdrian Hunter 3453f12e39dbSAdrian Hunter spin_lock_irqsave(&host->lock, flags); 3454f12e39dbSAdrian Hunter 3455f12e39dbSAdrian Hunter sdhci_set_default_irqs(host); 3456f12e39dbSAdrian Hunter 3457f12e39dbSAdrian Hunter host->cqe_on = false; 3458f12e39dbSAdrian Hunter 3459f12e39dbSAdrian Hunter if (recovery) { 3460f12e39dbSAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD); 3461f12e39dbSAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_DATA); 3462f12e39dbSAdrian Hunter } 3463f12e39dbSAdrian Hunter 3464f12e39dbSAdrian Hunter pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n", 3465f12e39dbSAdrian Hunter mmc_hostname(mmc), host->ier, 3466f12e39dbSAdrian Hunter sdhci_readl(host, SDHCI_INT_STATUS)); 3467f12e39dbSAdrian Hunter 3468f12e39dbSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 3469f12e39dbSAdrian Hunter } 3470f12e39dbSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cqe_disable); 3471f12e39dbSAdrian Hunter 3472f12e39dbSAdrian Hunter bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 3473f12e39dbSAdrian Hunter int *data_error) 3474f12e39dbSAdrian Hunter { 3475f12e39dbSAdrian Hunter u32 mask; 3476f12e39dbSAdrian Hunter 3477f12e39dbSAdrian Hunter if (!host->cqe_on) 3478f12e39dbSAdrian Hunter return false; 3479f12e39dbSAdrian Hunter 3480f12e39dbSAdrian Hunter if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) 3481f12e39dbSAdrian Hunter *cmd_error = -EILSEQ; 3482f12e39dbSAdrian Hunter else if (intmask & SDHCI_INT_TIMEOUT) 3483f12e39dbSAdrian Hunter *cmd_error = -ETIMEDOUT; 3484f12e39dbSAdrian Hunter else 3485f12e39dbSAdrian Hunter *cmd_error = 0; 3486f12e39dbSAdrian Hunter 3487f12e39dbSAdrian Hunter if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) 3488f12e39dbSAdrian Hunter *data_error = -EILSEQ; 3489f12e39dbSAdrian Hunter else if (intmask & SDHCI_INT_DATA_TIMEOUT) 3490f12e39dbSAdrian Hunter *data_error = -ETIMEDOUT; 3491f12e39dbSAdrian Hunter else if (intmask & SDHCI_INT_ADMA_ERROR) 3492f12e39dbSAdrian Hunter *data_error = -EIO; 3493f12e39dbSAdrian Hunter else 3494f12e39dbSAdrian Hunter *data_error = 0; 3495f12e39dbSAdrian Hunter 3496f12e39dbSAdrian Hunter /* Clear selected interrupts. */ 3497f12e39dbSAdrian Hunter mask = intmask & host->cqe_ier; 3498f12e39dbSAdrian Hunter sdhci_writel(host, mask, SDHCI_INT_STATUS); 3499f12e39dbSAdrian Hunter 3500f12e39dbSAdrian Hunter if (intmask & SDHCI_INT_BUS_POWER) 3501f12e39dbSAdrian Hunter pr_err("%s: Card is consuming too much power!\n", 3502f12e39dbSAdrian Hunter mmc_hostname(host->mmc)); 3503f12e39dbSAdrian Hunter 3504f12e39dbSAdrian Hunter intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR); 3505f12e39dbSAdrian Hunter if (intmask) { 3506f12e39dbSAdrian Hunter sdhci_writel(host, intmask, SDHCI_INT_STATUS); 3507f12e39dbSAdrian Hunter pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n", 3508f12e39dbSAdrian Hunter mmc_hostname(host->mmc), intmask); 3509f12e39dbSAdrian Hunter sdhci_dumpregs(host); 3510f12e39dbSAdrian Hunter } 3511f12e39dbSAdrian Hunter 3512f12e39dbSAdrian Hunter return true; 3513f12e39dbSAdrian Hunter } 3514f12e39dbSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cqe_irq); 3515f12e39dbSAdrian Hunter 3516f12e39dbSAdrian Hunter /*****************************************************************************\ 3517f12e39dbSAdrian Hunter * * 3518b8c86fc5SPierre Ossman * Device allocation/registration * 35191c6a0718SPierre Ossman * * 35201c6a0718SPierre Ossman \*****************************************************************************/ 35211c6a0718SPierre Ossman 3522b8c86fc5SPierre Ossman struct sdhci_host *sdhci_alloc_host(struct device *dev, 3523b8c86fc5SPierre Ossman size_t priv_size) 35241c6a0718SPierre Ossman { 35251c6a0718SPierre Ossman struct mmc_host *mmc; 35261c6a0718SPierre Ossman struct sdhci_host *host; 35271c6a0718SPierre Ossman 3528b8c86fc5SPierre Ossman WARN_ON(dev == NULL); 35291c6a0718SPierre Ossman 3530b8c86fc5SPierre Ossman mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 35311c6a0718SPierre Ossman if (!mmc) 3532b8c86fc5SPierre Ossman return ERR_PTR(-ENOMEM); 35331c6a0718SPierre Ossman 35341c6a0718SPierre Ossman host = mmc_priv(mmc); 35351c6a0718SPierre Ossman host->mmc = mmc; 3536bf60e592SAdrian Hunter host->mmc_host_ops = sdhci_ops; 3537bf60e592SAdrian Hunter mmc->ops = &host->mmc_host_ops; 35381c6a0718SPierre Ossman 35398cb851a4SAdrian Hunter host->flags = SDHCI_SIGNALING_330; 35408cb851a4SAdrian Hunter 3541f12e39dbSAdrian Hunter host->cqe_ier = SDHCI_CQE_INT_MASK; 3542f12e39dbSAdrian Hunter host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK; 3543f12e39dbSAdrian Hunter 354483b600b8SAdrian Hunter host->tuning_delay = -1; 35451d8cd065SSowjanya Komatineni host->tuning_loop_count = MAX_TUNING_LOOP; 354683b600b8SAdrian Hunter 3547c846a00fSSrinivas Kandagatla host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG; 3548c846a00fSSrinivas Kandagatla 3549e93be38aSJisheng Zhang /* 3550e93be38aSJisheng Zhang * The DMA table descriptor count is calculated as the maximum 3551e93be38aSJisheng Zhang * number of segments times 2, to allow for an alignment 3552e93be38aSJisheng Zhang * descriptor for each segment, plus 1 for a nop end descriptor. 3553e93be38aSJisheng Zhang */ 3554e93be38aSJisheng Zhang host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1; 3555e93be38aSJisheng Zhang 3556b8c86fc5SPierre Ossman return host; 35571c6a0718SPierre Ossman } 35581c6a0718SPierre Ossman 3559b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_alloc_host); 3560b8c86fc5SPierre Ossman 35617b91369bSAlexandre Courbot static int sdhci_set_dma_mask(struct sdhci_host *host) 35627b91369bSAlexandre Courbot { 35637b91369bSAlexandre Courbot struct mmc_host *mmc = host->mmc; 35647b91369bSAlexandre Courbot struct device *dev = mmc_dev(mmc); 35657b91369bSAlexandre Courbot int ret = -EINVAL; 35667b91369bSAlexandre Courbot 35677b91369bSAlexandre Courbot if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 35687b91369bSAlexandre Courbot host->flags &= ~SDHCI_USE_64_BIT_DMA; 35697b91369bSAlexandre Courbot 35707b91369bSAlexandre Courbot /* Try 64-bit mask if hardware is capable of it */ 35717b91369bSAlexandre Courbot if (host->flags & SDHCI_USE_64_BIT_DMA) { 35727b91369bSAlexandre Courbot ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 35737b91369bSAlexandre Courbot if (ret) { 35747b91369bSAlexandre Courbot pr_warn("%s: Failed to set 64-bit DMA mask.\n", 35757b91369bSAlexandre Courbot mmc_hostname(mmc)); 35767b91369bSAlexandre Courbot host->flags &= ~SDHCI_USE_64_BIT_DMA; 35777b91369bSAlexandre Courbot } 35787b91369bSAlexandre Courbot } 35797b91369bSAlexandre Courbot 35807b91369bSAlexandre Courbot /* 32-bit mask as default & fallback */ 35817b91369bSAlexandre Courbot if (ret) { 35827b91369bSAlexandre Courbot ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 35837b91369bSAlexandre Courbot if (ret) 35847b91369bSAlexandre Courbot pr_warn("%s: Failed to set 32-bit DMA mask.\n", 35857b91369bSAlexandre Courbot mmc_hostname(mmc)); 35867b91369bSAlexandre Courbot } 35877b91369bSAlexandre Courbot 35887b91369bSAlexandre Courbot return ret; 35897b91369bSAlexandre Courbot } 35907b91369bSAlexandre Courbot 35916132a3bfSAdrian Hunter void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 35926132a3bfSAdrian Hunter { 35936132a3bfSAdrian Hunter u16 v; 359492e0c44bSZach Brown u64 dt_caps_mask = 0; 359592e0c44bSZach Brown u64 dt_caps = 0; 35966132a3bfSAdrian Hunter 35976132a3bfSAdrian Hunter if (host->read_caps) 35986132a3bfSAdrian Hunter return; 35996132a3bfSAdrian Hunter 36006132a3bfSAdrian Hunter host->read_caps = true; 36016132a3bfSAdrian Hunter 36026132a3bfSAdrian Hunter if (debug_quirks) 36036132a3bfSAdrian Hunter host->quirks = debug_quirks; 36046132a3bfSAdrian Hunter 36056132a3bfSAdrian Hunter if (debug_quirks2) 36066132a3bfSAdrian Hunter host->quirks2 = debug_quirks2; 36076132a3bfSAdrian Hunter 36086132a3bfSAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_ALL); 36096132a3bfSAdrian Hunter 3610b3f80b43SChunyan Zhang if (host->v4_mode) 3611b3f80b43SChunyan Zhang sdhci_do_enable_v4_mode(host); 3612b3f80b43SChunyan Zhang 361392e0c44bSZach Brown of_property_read_u64(mmc_dev(host->mmc)->of_node, 361492e0c44bSZach Brown "sdhci-caps-mask", &dt_caps_mask); 361592e0c44bSZach Brown of_property_read_u64(mmc_dev(host->mmc)->of_node, 361692e0c44bSZach Brown "sdhci-caps", &dt_caps); 361792e0c44bSZach Brown 36186132a3bfSAdrian Hunter v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 36196132a3bfSAdrian Hunter host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 36206132a3bfSAdrian Hunter 36216132a3bfSAdrian Hunter if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 36226132a3bfSAdrian Hunter return; 36236132a3bfSAdrian Hunter 362492e0c44bSZach Brown if (caps) { 362592e0c44bSZach Brown host->caps = *caps; 362692e0c44bSZach Brown } else { 362792e0c44bSZach Brown host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 362892e0c44bSZach Brown host->caps &= ~lower_32_bits(dt_caps_mask); 362992e0c44bSZach Brown host->caps |= lower_32_bits(dt_caps); 363092e0c44bSZach Brown } 36316132a3bfSAdrian Hunter 36326132a3bfSAdrian Hunter if (host->version < SDHCI_SPEC_300) 36336132a3bfSAdrian Hunter return; 36346132a3bfSAdrian Hunter 363592e0c44bSZach Brown if (caps1) { 363692e0c44bSZach Brown host->caps1 = *caps1; 363792e0c44bSZach Brown } else { 363892e0c44bSZach Brown host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 363992e0c44bSZach Brown host->caps1 &= ~upper_32_bits(dt_caps_mask); 364092e0c44bSZach Brown host->caps1 |= upper_32_bits(dt_caps); 364192e0c44bSZach Brown } 36426132a3bfSAdrian Hunter } 36436132a3bfSAdrian Hunter EXPORT_SYMBOL_GPL(__sdhci_read_caps); 36446132a3bfSAdrian Hunter 3645a68dd9a0SChunyan Zhang static void sdhci_allocate_bounce_buffer(struct sdhci_host *host) 3646bd9b9027SLinus Walleij { 3647bd9b9027SLinus Walleij struct mmc_host *mmc = host->mmc; 3648bd9b9027SLinus Walleij unsigned int max_blocks; 3649bd9b9027SLinus Walleij unsigned int bounce_size; 3650bd9b9027SLinus Walleij int ret; 3651bd9b9027SLinus Walleij 3652bd9b9027SLinus Walleij /* 3653bd9b9027SLinus Walleij * Cap the bounce buffer at 64KB. Using a bigger bounce buffer 3654bd9b9027SLinus Walleij * has diminishing returns, this is probably because SD/MMC 3655bd9b9027SLinus Walleij * cards are usually optimized to handle this size of requests. 3656bd9b9027SLinus Walleij */ 3657bd9b9027SLinus Walleij bounce_size = SZ_64K; 3658bd9b9027SLinus Walleij /* 3659bd9b9027SLinus Walleij * Adjust downwards to maximum request size if this is less 3660bd9b9027SLinus Walleij * than our segment size, else hammer down the maximum 3661bd9b9027SLinus Walleij * request size to the maximum buffer size. 3662bd9b9027SLinus Walleij */ 3663bd9b9027SLinus Walleij if (mmc->max_req_size < bounce_size) 3664bd9b9027SLinus Walleij bounce_size = mmc->max_req_size; 3665bd9b9027SLinus Walleij max_blocks = bounce_size / 512; 3666bd9b9027SLinus Walleij 3667bd9b9027SLinus Walleij /* 3668bd9b9027SLinus Walleij * When we just support one segment, we can get significant 3669bd9b9027SLinus Walleij * speedups by the help of a bounce buffer to group scattered 3670bd9b9027SLinus Walleij * reads/writes together. 3671bd9b9027SLinus Walleij */ 3672bd9b9027SLinus Walleij host->bounce_buffer = devm_kmalloc(mmc->parent, 3673bd9b9027SLinus Walleij bounce_size, 3674bd9b9027SLinus Walleij GFP_KERNEL); 3675bd9b9027SLinus Walleij if (!host->bounce_buffer) { 3676bd9b9027SLinus Walleij pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n", 3677bd9b9027SLinus Walleij mmc_hostname(mmc), 3678bd9b9027SLinus Walleij bounce_size); 3679bd9b9027SLinus Walleij /* 3680bd9b9027SLinus Walleij * Exiting with zero here makes sure we proceed with 3681bd9b9027SLinus Walleij * mmc->max_segs == 1. 3682bd9b9027SLinus Walleij */ 3683a68dd9a0SChunyan Zhang return; 3684bd9b9027SLinus Walleij } 3685bd9b9027SLinus Walleij 3686bd9b9027SLinus Walleij host->bounce_addr = dma_map_single(mmc->parent, 3687bd9b9027SLinus Walleij host->bounce_buffer, 3688bd9b9027SLinus Walleij bounce_size, 3689bd9b9027SLinus Walleij DMA_BIDIRECTIONAL); 3690bd9b9027SLinus Walleij ret = dma_mapping_error(mmc->parent, host->bounce_addr); 3691bd9b9027SLinus Walleij if (ret) 3692bd9b9027SLinus Walleij /* Again fall back to max_segs == 1 */ 3693a68dd9a0SChunyan Zhang return; 3694bd9b9027SLinus Walleij host->bounce_buffer_size = bounce_size; 3695bd9b9027SLinus Walleij 3696bd9b9027SLinus Walleij /* Lie about this since we're bouncing */ 3697bd9b9027SLinus Walleij mmc->max_segs = max_blocks; 3698bd9b9027SLinus Walleij mmc->max_seg_size = bounce_size; 3699bd9b9027SLinus Walleij mmc->max_req_size = bounce_size; 3700bd9b9027SLinus Walleij 3701bd9b9027SLinus Walleij pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n", 3702bd9b9027SLinus Walleij mmc_hostname(mmc), max_blocks, bounce_size); 3703bd9b9027SLinus Walleij } 3704bd9b9027SLinus Walleij 3705685e444bSChunyan Zhang static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) 3706685e444bSChunyan Zhang { 3707685e444bSChunyan Zhang /* 3708685e444bSChunyan Zhang * According to SD Host Controller spec v4.10, bit[27] added from 3709685e444bSChunyan Zhang * version 4.10 in Capabilities Register is used as 64-bit System 3710685e444bSChunyan Zhang * Address support for V4 mode. 3711685e444bSChunyan Zhang */ 3712685e444bSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && host->v4_mode) 3713685e444bSChunyan Zhang return host->caps & SDHCI_CAN_64BIT_V4; 3714685e444bSChunyan Zhang 3715685e444bSChunyan Zhang return host->caps & SDHCI_CAN_64BIT; 3716685e444bSChunyan Zhang } 3717685e444bSChunyan Zhang 371852f5336dSAdrian Hunter int sdhci_setup_host(struct sdhci_host *host) 3719b8c86fc5SPierre Ossman { 3720b8c86fc5SPierre Ossman struct mmc_host *mmc; 3721f2119df6SArindam Nath u32 max_current_caps; 3722f2119df6SArindam Nath unsigned int ocr_avail; 3723f5fa92e5SAdrian Hunter unsigned int override_timeout_clk; 372459241757SDong Aisheng u32 max_clk; 3725b8c86fc5SPierre Ossman int ret; 3726b8c86fc5SPierre Ossman 3727b8c86fc5SPierre Ossman WARN_ON(host == NULL); 3728b8c86fc5SPierre Ossman if (host == NULL) 3729b8c86fc5SPierre Ossman return -EINVAL; 3730b8c86fc5SPierre Ossman 3731b8c86fc5SPierre Ossman mmc = host->mmc; 3732b8c86fc5SPierre Ossman 3733efba142bSJon Hunter /* 3734efba142bSJon Hunter * If there are external regulators, get them. Note this must be done 3735efba142bSJon Hunter * early before resetting the host and reading the capabilities so that 3736efba142bSJon Hunter * the host can take the appropriate action if regulators are not 3737efba142bSJon Hunter * available. 3738efba142bSJon Hunter */ 3739efba142bSJon Hunter ret = mmc_regulator_get_supply(mmc); 37402a63303dSWolfram Sang if (ret) 3741efba142bSJon Hunter return ret; 3742efba142bSJon Hunter 374306ebc601SShawn Lin DBG("Version: 0x%08x | Present: 0x%08x\n", 374406ebc601SShawn Lin sdhci_readw(host, SDHCI_HOST_VERSION), 374506ebc601SShawn Lin sdhci_readl(host, SDHCI_PRESENT_STATE)); 374606ebc601SShawn Lin DBG("Caps: 0x%08x | Caps_1: 0x%08x\n", 374706ebc601SShawn Lin sdhci_readl(host, SDHCI_CAPABILITIES), 374806ebc601SShawn Lin sdhci_readl(host, SDHCI_CAPABILITIES_1)); 374906ebc601SShawn Lin 37506132a3bfSAdrian Hunter sdhci_read_caps(host); 3751b8c86fc5SPierre Ossman 3752f5fa92e5SAdrian Hunter override_timeout_clk = host->timeout_clk; 3753f5fa92e5SAdrian Hunter 375418da1990SChunyan Zhang if (host->version > SDHCI_SPEC_420) { 37552e4456f0SMarek Vasut pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 37562e4456f0SMarek Vasut mmc_hostname(mmc), host->version); 37571c6a0718SPierre Ossman } 37581c6a0718SPierre Ossman 3759b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3760a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 376128da3589SAdrian Hunter else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3762a13abc7bSRichard Röjfors DBG("Controller doesn't have SDMA capability\n"); 37631c6a0718SPierre Ossman else 3764a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 37651c6a0718SPierre Ossman 3766b8c86fc5SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3767a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA)) { 3768cee687ceSRolf Eike Beer DBG("Disabling DMA as it is marked broken\n"); 3769a13abc7bSRichard Röjfors host->flags &= ~SDHCI_USE_SDMA; 37707c168e3dSFeng Tang } 37717c168e3dSFeng Tang 3772f2119df6SArindam Nath if ((host->version >= SDHCI_SPEC_200) && 377328da3589SAdrian Hunter (host->caps & SDHCI_CAN_DO_ADMA2)) 37742134a922SPierre Ossman host->flags |= SDHCI_USE_ADMA; 37752134a922SPierre Ossman 37762134a922SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 37772134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) { 37782134a922SPierre Ossman DBG("Disabling ADMA as it is marked broken\n"); 37792134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 37802134a922SPierre Ossman } 37812134a922SPierre Ossman 3782e57a5f61SAdrian Hunter /* 3783e57a5f61SAdrian Hunter * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 3784e57a5f61SAdrian Hunter * and *must* do 64-bit DMA. A driver has the opportunity to change 3785e57a5f61SAdrian Hunter * that during the first call to ->enable_dma(). Similarly 3786e57a5f61SAdrian Hunter * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3787e57a5f61SAdrian Hunter * implement. 3788e57a5f61SAdrian Hunter */ 3789685e444bSChunyan Zhang if (sdhci_can_64bit_dma(host)) 3790e57a5f61SAdrian Hunter host->flags |= SDHCI_USE_64_BIT_DMA; 3791e57a5f61SAdrian Hunter 3792a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 37937b91369bSAlexandre Courbot ret = sdhci_set_dma_mask(host); 37947b91369bSAlexandre Courbot 37957b91369bSAlexandre Courbot if (!ret && host->ops->enable_dma) 37967b91369bSAlexandre Courbot ret = host->ops->enable_dma(host); 37977b91369bSAlexandre Courbot 37987b91369bSAlexandre Courbot if (ret) { 37996606110dSJoe Perches pr_warn("%s: No suitable DMA available - falling back to PIO\n", 3800b8c86fc5SPierre Ossman mmc_hostname(mmc)); 38017b91369bSAlexandre Courbot host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 38027b91369bSAlexandre Courbot 38037b91369bSAlexandre Courbot ret = 0; 38041c6a0718SPierre Ossman } 3805b8c86fc5SPierre Ossman } 38061c6a0718SPierre Ossman 3807917a0c52SChunyan Zhang /* SDMA does not support 64-bit DMA if v4 mode not set */ 3808917a0c52SChunyan Zhang if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) 3809e57a5f61SAdrian Hunter host->flags &= ~SDHCI_USE_SDMA; 3810e57a5f61SAdrian Hunter 38112134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 3812e66e61cbSRussell King dma_addr_t dma; 3813e66e61cbSRussell King void *buf; 3814e66e61cbSRussell King 3815e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) { 3816e93be38aSJisheng Zhang host->adma_table_sz = host->adma_table_cnt * 3817685e444bSChunyan Zhang SDHCI_ADMA2_64_DESC_SZ(host); 3818685e444bSChunyan Zhang host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); 3819e57a5f61SAdrian Hunter } else { 3820e93be38aSJisheng Zhang host->adma_table_sz = host->adma_table_cnt * 3821739d46dcSAdrian Hunter SDHCI_ADMA2_32_DESC_SZ; 3822739d46dcSAdrian Hunter host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 3823e57a5f61SAdrian Hunter } 3824e66e61cbSRussell King 382504a5ae6fSAdrian Hunter host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 3826685e444bSChunyan Zhang /* 3827685e444bSChunyan Zhang * Use zalloc to zero the reserved high 32-bits of 128-bit 3828685e444bSChunyan Zhang * descriptors so that they never need to be written. 3829685e444bSChunyan Zhang */ 3830750afb08SLuis Chamberlain buf = dma_alloc_coherent(mmc_dev(mmc), 3831750afb08SLuis Chamberlain host->align_buffer_sz + host->adma_table_sz, 3832750afb08SLuis Chamberlain &dma, GFP_KERNEL); 3833e66e61cbSRussell King if (!buf) { 38346606110dSJoe Perches pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 38352134a922SPierre Ossman mmc_hostname(mmc)); 38362134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 3837e66e61cbSRussell King } else if ((dma + host->align_buffer_sz) & 3838e66e61cbSRussell King (SDHCI_ADMA2_DESC_ALIGN - 1)) { 38396606110dSJoe Perches pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 3840d1e49f77SRussell King mmc_hostname(mmc)); 3841d1e49f77SRussell King host->flags &= ~SDHCI_USE_ADMA; 3842e66e61cbSRussell King dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3843e66e61cbSRussell King host->adma_table_sz, buf, dma); 3844e66e61cbSRussell King } else { 3845e66e61cbSRussell King host->align_buffer = buf; 3846e66e61cbSRussell King host->align_addr = dma; 3847edd63fccSRussell King 3848e66e61cbSRussell King host->adma_table = buf + host->align_buffer_sz; 3849e66e61cbSRussell King host->adma_addr = dma + host->align_buffer_sz; 3850e66e61cbSRussell King } 38512134a922SPierre Ossman } 38522134a922SPierre Ossman 38537659150cSPierre Ossman /* 38547659150cSPierre Ossman * If we use DMA, then it's up to the caller to set the DMA 38557659150cSPierre Ossman * mask, but PIO does not need the hw shim so we set a new 38567659150cSPierre Ossman * mask here in that case. 38577659150cSPierre Ossman */ 3858a13abc7bSRichard Röjfors if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 38597659150cSPierre Ossman host->dma_mask = DMA_BIT_MASK(64); 38604e743f1fSMarkus Mayer mmc_dev(mmc)->dma_mask = &host->dma_mask; 38617659150cSPierre Ossman } 38621c6a0718SPierre Ossman 3863c4687d5fSZhangfei Gao if (host->version >= SDHCI_SPEC_300) 386428da3589SAdrian Hunter host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 3865c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 3866c4687d5fSZhangfei Gao else 386728da3589SAdrian Hunter host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 3868c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 3869c4687d5fSZhangfei Gao 38704240ff0aSBen Dooks host->max_clk *= 1000000; 3871f27f47efSAnton Vorontsov if (host->max_clk == 0 || host->quirks & 3872f27f47efSAnton Vorontsov SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 38734240ff0aSBen Dooks if (!host->ops->get_max_clock) { 38742e4456f0SMarek Vasut pr_err("%s: Hardware doesn't specify base clock frequency.\n", 38752e4456f0SMarek Vasut mmc_hostname(mmc)); 3876eb5c20deSAdrian Hunter ret = -ENODEV; 3877eb5c20deSAdrian Hunter goto undma; 38781c6a0718SPierre Ossman } 38794240ff0aSBen Dooks host->max_clk = host->ops->get_max_clock(host); 38804240ff0aSBen Dooks } 38811c6a0718SPierre Ossman 38821c6a0718SPierre Ossman /* 3883c3ed3877SArindam Nath * In case of Host Controller v3.00, find out whether clock 3884c3ed3877SArindam Nath * multiplier is supported. 3885c3ed3877SArindam Nath */ 388628da3589SAdrian Hunter host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 3887c3ed3877SArindam Nath SDHCI_CLOCK_MUL_SHIFT; 3888c3ed3877SArindam Nath 3889c3ed3877SArindam Nath /* 3890c3ed3877SArindam Nath * In case the value in Clock Multiplier is 0, then programmable 3891c3ed3877SArindam Nath * clock mode is not supported, otherwise the actual clock 3892c3ed3877SArindam Nath * multiplier is one more than the value of Clock Multiplier 3893c3ed3877SArindam Nath * in the Capabilities Register. 3894c3ed3877SArindam Nath */ 3895c3ed3877SArindam Nath if (host->clk_mul) 3896c3ed3877SArindam Nath host->clk_mul += 1; 3897c3ed3877SArindam Nath 3898c3ed3877SArindam Nath /* 38991c6a0718SPierre Ossman * Set host parameters. 39001c6a0718SPierre Ossman */ 390159241757SDong Aisheng max_clk = host->max_clk; 390259241757SDong Aisheng 3903ce5f036bSMarek Szyprowski if (host->ops->get_min_clock) 3904a9e58f25SAnton Vorontsov mmc->f_min = host->ops->get_min_clock(host); 3905c3ed3877SArindam Nath else if (host->version >= SDHCI_SPEC_300) { 3906c3ed3877SArindam Nath if (host->clk_mul) { 3907c3ed3877SArindam Nath mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 390859241757SDong Aisheng max_clk = host->max_clk * host->clk_mul; 3909c3ed3877SArindam Nath } else 39100397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3911c3ed3877SArindam Nath } else 39120397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 391315ec4461SPhilip Rakity 3914d310ae49SAdrian Hunter if (!mmc->f_max || mmc->f_max > max_clk) 391559241757SDong Aisheng mmc->f_max = max_clk; 391659241757SDong Aisheng 391728aab053SAisheng Dong if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 391828da3589SAdrian Hunter host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 391928aab053SAisheng Dong SDHCI_TIMEOUT_CLK_SHIFT; 39208cc35289SShawn Lin 39218cc35289SShawn Lin if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 39228cc35289SShawn Lin host->timeout_clk *= 1000; 39238cc35289SShawn Lin 3924272308caSAndy Shevchenko if (host->timeout_clk == 0) { 39258cc35289SShawn Lin if (!host->ops->get_timeout_clock) { 392628aab053SAisheng Dong pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 392728aab053SAisheng Dong mmc_hostname(mmc)); 3928eb5c20deSAdrian Hunter ret = -ENODEV; 3929eb5c20deSAdrian Hunter goto undma; 3930272308caSAndy Shevchenko } 393128aab053SAisheng Dong 39328cc35289SShawn Lin host->timeout_clk = 39338cc35289SShawn Lin DIV_ROUND_UP(host->ops->get_timeout_clock(host), 39348cc35289SShawn Lin 1000); 39358cc35289SShawn Lin } 3936272308caSAndy Shevchenko 393799513624SAdrian Hunter if (override_timeout_clk) 393899513624SAdrian Hunter host->timeout_clk = override_timeout_clk; 393999513624SAdrian Hunter 3940a6ff5aebSAisheng Dong mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3941a6ff5aebSAisheng Dong host->ops->get_max_timeout_count(host) : 1 << 27; 3942a6ff5aebSAisheng Dong mmc->max_busy_timeout /= host->timeout_clk; 394328aab053SAisheng Dong } 394458d1246dSAdrian Hunter 3945a999fd93SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && 3946a999fd93SAdrian Hunter !host->ops->get_max_timeout_count) 3947a999fd93SAdrian Hunter mmc->max_busy_timeout = 0; 3948a999fd93SAdrian Hunter 3949e89d456fSAndrei Warkentin mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3950781e989cSRussell King mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3951e89d456fSAndrei Warkentin 3952e89d456fSAndrei Warkentin if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3953e89d456fSAndrei Warkentin host->flags |= SDHCI_AUTO_CMD12; 39545fe23c7fSAnton Vorontsov 39557ed71a9dSChunyan Zhang /* 39567ed71a9dSChunyan Zhang * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO. 39577ed71a9dSChunyan Zhang * For v4 mode, SDMA may use Auto-CMD23 as well. 39587ed71a9dSChunyan Zhang */ 39594f3d3e9bSAndrei Warkentin if ((host->version >= SDHCI_SPEC_300) && 39608edf6371SAndrei Warkentin ((host->flags & SDHCI_USE_ADMA) || 39617ed71a9dSChunyan Zhang !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) && 39623bfa6f03SScott Branden !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 39638edf6371SAndrei Warkentin host->flags |= SDHCI_AUTO_CMD23; 3964f421865dSAdrian Hunter DBG("Auto-CMD23 available\n"); 39658edf6371SAndrei Warkentin } else { 3966f421865dSAdrian Hunter DBG("Auto-CMD23 unavailable\n"); 39678edf6371SAndrei Warkentin } 39688edf6371SAndrei Warkentin 396915ec4461SPhilip Rakity /* 397015ec4461SPhilip Rakity * A controller may support 8-bit width, but the board itself 397115ec4461SPhilip Rakity * might not have the pins brought out. Boards that support 397215ec4461SPhilip Rakity * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 397315ec4461SPhilip Rakity * their platform code before calling sdhci_add_host(), and we 397415ec4461SPhilip Rakity * won't assume 8-bit width for hosts without that CAP. 397515ec4461SPhilip Rakity */ 39765fe23c7fSAnton Vorontsov if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 397715ec4461SPhilip Rakity mmc->caps |= MMC_CAP_4_BIT_DATA; 39781c6a0718SPierre Ossman 397963ef5d8cSJerry Huang if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 398063ef5d8cSJerry Huang mmc->caps &= ~MMC_CAP_CMD23; 398163ef5d8cSJerry Huang 398228da3589SAdrian Hunter if (host->caps & SDHCI_CAN_DO_HISPD) 3983a29e7e18SZhangfei Gao mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 39841c6a0718SPierre Ossman 3985176d1ed4SJaehoon Chung if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3986860951c5SJaehoon Chung mmc_card_is_removable(mmc) && 3987287980e4SArnd Bergmann mmc_gpio_get_cd(host->mmc) < 0) 398868d1fb7eSAnton Vorontsov mmc->caps |= MMC_CAP_NEEDS_POLL; 398968d1fb7eSAnton Vorontsov 39903a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 39913a48edc4STim Kryger ret = regulator_enable(mmc->supply.vqmmc); 39921b5190c2SStefan Agner 39931b5190c2SStefan Agner /* If vqmmc provides no 1.8V signalling, then there's no UHS */ 39943a48edc4STim Kryger if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3995cec2e216SKevin Liu 1950000)) 399628da3589SAdrian Hunter host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 39978363c374SKevin Liu SDHCI_SUPPORT_SDR50 | 39986231f3deSPhilip Rakity SDHCI_SUPPORT_DDR50); 39991b5190c2SStefan Agner 40001b5190c2SStefan Agner /* In eMMC case vqmmc might be a fixed 1.8V regulator */ 40011b5190c2SStefan Agner if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, 40021b5190c2SStefan Agner 3600000)) 40031b5190c2SStefan Agner host->flags &= ~SDHCI_SIGNALING_330; 40041b5190c2SStefan Agner 4005a3361abaSChris Ball if (ret) { 4006a3361abaSChris Ball pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 4007a3361abaSChris Ball mmc_hostname(mmc), ret); 40084bb74313SAdrian Hunter mmc->supply.vqmmc = ERR_PTR(-EINVAL); 4009a3361abaSChris Ball } 40108363c374SKevin Liu } 40116231f3deSPhilip Rakity 401228da3589SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 401328da3589SAdrian Hunter host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 40146a66180aSDaniel Drake SDHCI_SUPPORT_DDR50); 4015c16bc9a7SKishon Vijay Abraham I /* 4016c16bc9a7SKishon Vijay Abraham I * The SDHCI controller in a SoC might support HS200/HS400 4017c16bc9a7SKishon Vijay Abraham I * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property), 4018c16bc9a7SKishon Vijay Abraham I * but if the board is modeled such that the IO lines are not 4019c16bc9a7SKishon Vijay Abraham I * connected to 1.8v then HS200/HS400 cannot be supported. 4020c16bc9a7SKishon Vijay Abraham I * Disable HS200/HS400 if the board does not have 1.8v connected 4021c16bc9a7SKishon Vijay Abraham I * to the IO lines. (Applicable for other modes in 1.8v) 4022c16bc9a7SKishon Vijay Abraham I */ 4023c16bc9a7SKishon Vijay Abraham I mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES); 4024c16bc9a7SKishon Vijay Abraham I mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS); 402528da3589SAdrian Hunter } 40266a66180aSDaniel Drake 40274188bba0SAl Cooper /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 402828da3589SAdrian Hunter if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 40294188bba0SAl Cooper SDHCI_SUPPORT_DDR50)) 4030f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 4031f2119df6SArindam Nath 4032f2119df6SArindam Nath /* SDR104 supports also implies SDR50 support */ 403328da3589SAdrian Hunter if (host->caps1 & SDHCI_SUPPORT_SDR104) { 4034f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 4035156e14b1SGiuseppe CAVALLARO /* SD3.0: SDR104 is supported so (for eMMC) the caps2 4036156e14b1SGiuseppe CAVALLARO * field can be promoted to support HS200. 4037156e14b1SGiuseppe CAVALLARO */ 4038549c0b18SAdrian Hunter if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 4039156e14b1SGiuseppe CAVALLARO mmc->caps2 |= MMC_CAP2_HS200; 404028da3589SAdrian Hunter } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 4041f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR50; 404228da3589SAdrian Hunter } 4043f2119df6SArindam Nath 4044e9fb05d5SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 404528da3589SAdrian Hunter (host->caps1 & SDHCI_SUPPORT_HS400)) 4046e9fb05d5SAdrian Hunter mmc->caps2 |= MMC_CAP2_HS400; 4047e9fb05d5SAdrian Hunter 4048549c0b18SAdrian Hunter if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 4049549c0b18SAdrian Hunter (IS_ERR(mmc->supply.vqmmc) || 4050549c0b18SAdrian Hunter !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 4051549c0b18SAdrian Hunter 1300000))) 4052549c0b18SAdrian Hunter mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 4053549c0b18SAdrian Hunter 405428da3589SAdrian Hunter if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 40559107ebbfSMicky Ching !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 4056f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_DDR50; 4057f2119df6SArindam Nath 4058069c9f14SGirish K S /* Does the host need tuning for SDR50? */ 405928da3589SAdrian Hunter if (host->caps1 & SDHCI_USE_SDR50_TUNING) 4060b513ea25SArindam Nath host->flags |= SDHCI_SDR50_NEEDS_TUNING; 4061b513ea25SArindam Nath 4062d6d50a15SArindam Nath /* Driver Type(s) (A, C, D) supported by the host */ 406328da3589SAdrian Hunter if (host->caps1 & SDHCI_DRIVER_TYPE_A) 4064d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 406528da3589SAdrian Hunter if (host->caps1 & SDHCI_DRIVER_TYPE_C) 4066d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 406728da3589SAdrian Hunter if (host->caps1 & SDHCI_DRIVER_TYPE_D) 4068d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 4069d6d50a15SArindam Nath 4070cf2b5eeaSArindam Nath /* Initial value for re-tuning timer count */ 407128da3589SAdrian Hunter host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 4072cf2b5eeaSArindam Nath SDHCI_RETUNING_TIMER_COUNT_SHIFT; 4073cf2b5eeaSArindam Nath 4074cf2b5eeaSArindam Nath /* 4075cf2b5eeaSArindam Nath * In case Re-tuning Timer is not disabled, the actual value of 4076cf2b5eeaSArindam Nath * re-tuning timer will be 2 ^ (n - 1). 4077cf2b5eeaSArindam Nath */ 4078cf2b5eeaSArindam Nath if (host->tuning_count) 4079cf2b5eeaSArindam Nath host->tuning_count = 1 << (host->tuning_count - 1); 4080cf2b5eeaSArindam Nath 4081cf2b5eeaSArindam Nath /* Re-tuning mode supported by the Host Controller */ 408228da3589SAdrian Hunter host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 4083cf2b5eeaSArindam Nath SDHCI_RETUNING_MODE_SHIFT; 4084cf2b5eeaSArindam Nath 40858f230f45STakashi Iwai ocr_avail = 0; 4086bad37e1aSPhilip Rakity 4087f2119df6SArindam Nath /* 4088f2119df6SArindam Nath * According to SD Host Controller spec v3.00, if the Host System 4089f2119df6SArindam Nath * can afford more than 150mA, Host Driver should set XPC to 1. Also 4090f2119df6SArindam Nath * the value is meaningful only if Voltage Support in the Capabilities 4091f2119df6SArindam Nath * register is set. The actual current value is 4 times the register 4092f2119df6SArindam Nath * value. 4093f2119df6SArindam Nath */ 4094f2119df6SArindam Nath max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 40953a48edc4STim Kryger if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 4096ae906037SChuanxiao.Dong int curr = regulator_get_current_limit(mmc->supply.vmmc); 4097bad37e1aSPhilip Rakity if (curr > 0) { 4098bad37e1aSPhilip Rakity 4099bad37e1aSPhilip Rakity /* convert to SDHCI_MAX_CURRENT format */ 4100bad37e1aSPhilip Rakity curr = curr/1000; /* convert to mA */ 4101bad37e1aSPhilip Rakity curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 4102bad37e1aSPhilip Rakity 4103bad37e1aSPhilip Rakity curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 4104bad37e1aSPhilip Rakity max_current_caps = 4105bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 4106bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 4107bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_180_SHIFT); 4108bad37e1aSPhilip Rakity } 4109bad37e1aSPhilip Rakity } 4110f2119df6SArindam Nath 411128da3589SAdrian Hunter if (host->caps & SDHCI_CAN_VDD_330) { 41128f230f45STakashi Iwai ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 4113f2119df6SArindam Nath 411455c4665eSAaron Lu mmc->max_current_330 = ((max_current_caps & 4115f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_MASK) >> 4116f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_SHIFT) * 4117f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 4118f2119df6SArindam Nath } 411928da3589SAdrian Hunter if (host->caps & SDHCI_CAN_VDD_300) { 41208f230f45STakashi Iwai ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 4121f2119df6SArindam Nath 412255c4665eSAaron Lu mmc->max_current_300 = ((max_current_caps & 4123f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_MASK) >> 4124f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_SHIFT) * 4125f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 4126f2119df6SArindam Nath } 412728da3589SAdrian Hunter if (host->caps & SDHCI_CAN_VDD_180) { 41288f230f45STakashi Iwai ocr_avail |= MMC_VDD_165_195; 41298f230f45STakashi Iwai 413055c4665eSAaron Lu mmc->max_current_180 = ((max_current_caps & 4131f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_MASK) >> 4132f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_SHIFT) * 4133f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 4134f2119df6SArindam Nath } 4135f2119df6SArindam Nath 41365fd26c7eSUlf Hansson /* If OCR set by host, use it instead. */ 41375fd26c7eSUlf Hansson if (host->ocr_mask) 41385fd26c7eSUlf Hansson ocr_avail = host->ocr_mask; 41395fd26c7eSUlf Hansson 41405fd26c7eSUlf Hansson /* If OCR set by external regulators, give it highest prio. */ 41413a48edc4STim Kryger if (mmc->ocr_avail) 414252221610STim Kryger ocr_avail = mmc->ocr_avail; 41433a48edc4STim Kryger 41448f230f45STakashi Iwai mmc->ocr_avail = ocr_avail; 41458f230f45STakashi Iwai mmc->ocr_avail_sdio = ocr_avail; 41468f230f45STakashi Iwai if (host->ocr_avail_sdio) 41478f230f45STakashi Iwai mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 41488f230f45STakashi Iwai mmc->ocr_avail_sd = ocr_avail; 41498f230f45STakashi Iwai if (host->ocr_avail_sd) 41508f230f45STakashi Iwai mmc->ocr_avail_sd &= host->ocr_avail_sd; 41518f230f45STakashi Iwai else /* normal SD controllers don't support 1.8V */ 41528f230f45STakashi Iwai mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 41538f230f45STakashi Iwai mmc->ocr_avail_mmc = ocr_avail; 41548f230f45STakashi Iwai if (host->ocr_avail_mmc) 41558f230f45STakashi Iwai mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 41561c6a0718SPierre Ossman 41571c6a0718SPierre Ossman if (mmc->ocr_avail == 0) { 41582e4456f0SMarek Vasut pr_err("%s: Hardware doesn't report any support voltages.\n", 41592e4456f0SMarek Vasut mmc_hostname(mmc)); 4160eb5c20deSAdrian Hunter ret = -ENODEV; 4161eb5c20deSAdrian Hunter goto unreg; 41621c6a0718SPierre Ossman } 41631c6a0718SPierre Ossman 41648cb851a4SAdrian Hunter if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 41658cb851a4SAdrian Hunter MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 41668cb851a4SAdrian Hunter MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 41678cb851a4SAdrian Hunter (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 41688cb851a4SAdrian Hunter host->flags |= SDHCI_SIGNALING_180; 41698cb851a4SAdrian Hunter 41708cb851a4SAdrian Hunter if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 41718cb851a4SAdrian Hunter host->flags |= SDHCI_SIGNALING_120; 41728cb851a4SAdrian Hunter 41731c6a0718SPierre Ossman spin_lock_init(&host->lock); 41741c6a0718SPierre Ossman 41751c6a0718SPierre Ossman /* 4176ac00531dSAdrian Hunter * Maximum number of sectors in one transfer. Limited by SDMA boundary 4177ac00531dSAdrian Hunter * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 4178ac00531dSAdrian Hunter * is less anyway. 41791c6a0718SPierre Ossman */ 41801c6a0718SPierre Ossman mmc->max_req_size = 524288; 41811c6a0718SPierre Ossman 41821c6a0718SPierre Ossman /* 4183250dcd11SUlf Hansson * Maximum number of segments. Depends on if the hardware 4184250dcd11SUlf Hansson * can do scatter/gather or not. 4185250dcd11SUlf Hansson */ 4186250dcd11SUlf Hansson if (host->flags & SDHCI_USE_ADMA) { 4187250dcd11SUlf Hansson mmc->max_segs = SDHCI_MAX_SEGS; 4188250dcd11SUlf Hansson } else if (host->flags & SDHCI_USE_SDMA) { 4189250dcd11SUlf Hansson mmc->max_segs = 1; 4190250dcd11SUlf Hansson if (swiotlb_max_segment()) { 4191250dcd11SUlf Hansson unsigned int max_req_size = (1 << IO_TLB_SHIFT) * 4192250dcd11SUlf Hansson IO_TLB_SEGSIZE; 4193250dcd11SUlf Hansson mmc->max_req_size = min(mmc->max_req_size, 4194250dcd11SUlf Hansson max_req_size); 4195250dcd11SUlf Hansson } 4196250dcd11SUlf Hansson } else { /* PIO */ 4197250dcd11SUlf Hansson mmc->max_segs = SDHCI_MAX_SEGS; 4198250dcd11SUlf Hansson } 4199250dcd11SUlf Hansson 4200250dcd11SUlf Hansson /* 42011c6a0718SPierre Ossman * Maximum segment size. Could be one segment with the maximum number 42022134a922SPierre Ossman * of bytes. When doing hardware scatter/gather, each entry cannot 42032134a922SPierre Ossman * be larger than 64 KiB though. 42041c6a0718SPierre Ossman */ 420530652aa3SOlof Johansson if (host->flags & SDHCI_USE_ADMA) { 420630652aa3SOlof Johansson if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 420730652aa3SOlof Johansson mmc->max_seg_size = 65535; 42082134a922SPierre Ossman else 420930652aa3SOlof Johansson mmc->max_seg_size = 65536; 421030652aa3SOlof Johansson } else { 42111c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 421230652aa3SOlof Johansson } 42131c6a0718SPierre Ossman 42141c6a0718SPierre Ossman /* 42151c6a0718SPierre Ossman * Maximum block size. This varies from controller to controller and 42161c6a0718SPierre Ossman * is specified in the capabilities register. 42171c6a0718SPierre Ossman */ 42180633f654SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 42190633f654SAnton Vorontsov mmc->max_blk_size = 2; 42200633f654SAnton Vorontsov } else { 422128da3589SAdrian Hunter mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 42220633f654SAnton Vorontsov SDHCI_MAX_BLOCK_SHIFT; 42231c6a0718SPierre Ossman if (mmc->max_blk_size >= 3) { 42246606110dSJoe Perches pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 42256606110dSJoe Perches mmc_hostname(mmc)); 42260633f654SAnton Vorontsov mmc->max_blk_size = 0; 42270633f654SAnton Vorontsov } 42280633f654SAnton Vorontsov } 42290633f654SAnton Vorontsov 42301c6a0718SPierre Ossman mmc->max_blk_size = 512 << mmc->max_blk_size; 42311c6a0718SPierre Ossman 42321c6a0718SPierre Ossman /* 42331c6a0718SPierre Ossman * Maximum block count. 42341c6a0718SPierre Ossman */ 42351388eefdSBen Dooks mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 42361c6a0718SPierre Ossman 4237a68dd9a0SChunyan Zhang if (mmc->max_segs == 1) 4238bd9b9027SLinus Walleij /* This may alter mmc->*_blk_* parameters */ 4239a68dd9a0SChunyan Zhang sdhci_allocate_bounce_buffer(host); 4240bd9b9027SLinus Walleij 424152f5336dSAdrian Hunter return 0; 424252f5336dSAdrian Hunter 424352f5336dSAdrian Hunter unreg: 424452f5336dSAdrian Hunter if (!IS_ERR(mmc->supply.vqmmc)) 424552f5336dSAdrian Hunter regulator_disable(mmc->supply.vqmmc); 424652f5336dSAdrian Hunter undma: 424752f5336dSAdrian Hunter if (host->align_buffer) 424852f5336dSAdrian Hunter dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 424952f5336dSAdrian Hunter host->adma_table_sz, host->align_buffer, 425052f5336dSAdrian Hunter host->align_addr); 425152f5336dSAdrian Hunter host->adma_table = NULL; 425252f5336dSAdrian Hunter host->align_buffer = NULL; 425352f5336dSAdrian Hunter 425452f5336dSAdrian Hunter return ret; 425552f5336dSAdrian Hunter } 425652f5336dSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_setup_host); 425752f5336dSAdrian Hunter 42584180ffa8SAdrian Hunter void sdhci_cleanup_host(struct sdhci_host *host) 42594180ffa8SAdrian Hunter { 42604180ffa8SAdrian Hunter struct mmc_host *mmc = host->mmc; 42614180ffa8SAdrian Hunter 42624180ffa8SAdrian Hunter if (!IS_ERR(mmc->supply.vqmmc)) 42634180ffa8SAdrian Hunter regulator_disable(mmc->supply.vqmmc); 42644180ffa8SAdrian Hunter 42654180ffa8SAdrian Hunter if (host->align_buffer) 42664180ffa8SAdrian Hunter dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 42674180ffa8SAdrian Hunter host->adma_table_sz, host->align_buffer, 42684180ffa8SAdrian Hunter host->align_addr); 42694180ffa8SAdrian Hunter host->adma_table = NULL; 42704180ffa8SAdrian Hunter host->align_buffer = NULL; 42714180ffa8SAdrian Hunter } 42724180ffa8SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cleanup_host); 42734180ffa8SAdrian Hunter 427452f5336dSAdrian Hunter int __sdhci_add_host(struct sdhci_host *host) 427552f5336dSAdrian Hunter { 4276c07a48c2SAdrian Hunter unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI; 427752f5336dSAdrian Hunter struct mmc_host *mmc = host->mmc; 427852f5336dSAdrian Hunter int ret; 427952f5336dSAdrian Hunter 4280c07a48c2SAdrian Hunter host->complete_wq = alloc_workqueue("sdhci", flags, 0); 4281c07a48c2SAdrian Hunter if (!host->complete_wq) 4282c07a48c2SAdrian Hunter return -ENOMEM; 4283c07a48c2SAdrian Hunter 4284c07a48c2SAdrian Hunter INIT_WORK(&host->complete_work, sdhci_complete_work); 42851c6a0718SPierre Ossman 42862ee4f620SKees Cook timer_setup(&host->timer, sdhci_timeout_timer, 0); 42872ee4f620SKees Cook timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); 42881c6a0718SPierre Ossman 4289b513ea25SArindam Nath init_waitqueue_head(&host->buf_ready_int); 4290b513ea25SArindam Nath 42912af502caSShawn Guo sdhci_init(host, 0); 42922af502caSShawn Guo 4293781e989cSRussell King ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 4294781e989cSRussell King IRQF_SHARED, mmc_hostname(mmc), host); 42950fc81ee3SMark Brown if (ret) { 42960fc81ee3SMark Brown pr_err("%s: Failed to request IRQ %d: %d\n", 42970fc81ee3SMark Brown mmc_hostname(mmc), host->irq, ret); 4298c07a48c2SAdrian Hunter goto unwq; 42990fc81ee3SMark Brown } 43001c6a0718SPierre Ossman 4301061d17a6SAdrian Hunter ret = sdhci_led_register(host); 43020fc81ee3SMark Brown if (ret) { 43030fc81ee3SMark Brown pr_err("%s: Failed to register LED device: %d\n", 43040fc81ee3SMark Brown mmc_hostname(mmc), ret); 4305eb5c20deSAdrian Hunter goto unirq; 43060fc81ee3SMark Brown } 43072f730fecSPierre Ossman 4308eb5c20deSAdrian Hunter ret = mmc_add_host(mmc); 4309eb5c20deSAdrian Hunter if (ret) 4310eb5c20deSAdrian Hunter goto unled; 43111c6a0718SPierre Ossman 4312a3c76eb9SGirish K S pr_info("%s: SDHCI controller on %s [%s] using %s\n", 4313d1b26863SKay Sievers mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 4314e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_ADMA) ? 4315e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 4316a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 43171c6a0718SPierre Ossman 43187260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 43197260cf5eSAnton Vorontsov 43201c6a0718SPierre Ossman return 0; 43211c6a0718SPierre Ossman 4322eb5c20deSAdrian Hunter unled: 4323061d17a6SAdrian Hunter sdhci_led_unregister(host); 4324eb5c20deSAdrian Hunter unirq: 432503231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 4326b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 4327b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 43282f730fecSPierre Ossman free_irq(host->irq, host); 4329c07a48c2SAdrian Hunter unwq: 4330c07a48c2SAdrian Hunter destroy_workqueue(host->complete_wq); 433152f5336dSAdrian Hunter 43321c6a0718SPierre Ossman return ret; 43331c6a0718SPierre Ossman } 433452f5336dSAdrian Hunter EXPORT_SYMBOL_GPL(__sdhci_add_host); 43351c6a0718SPierre Ossman 433652f5336dSAdrian Hunter int sdhci_add_host(struct sdhci_host *host) 433752f5336dSAdrian Hunter { 433852f5336dSAdrian Hunter int ret; 433952f5336dSAdrian Hunter 434052f5336dSAdrian Hunter ret = sdhci_setup_host(host); 434152f5336dSAdrian Hunter if (ret) 434252f5336dSAdrian Hunter return ret; 434352f5336dSAdrian Hunter 43444180ffa8SAdrian Hunter ret = __sdhci_add_host(host); 43454180ffa8SAdrian Hunter if (ret) 43464180ffa8SAdrian Hunter goto cleanup; 43474180ffa8SAdrian Hunter 43484180ffa8SAdrian Hunter return 0; 43494180ffa8SAdrian Hunter 43504180ffa8SAdrian Hunter cleanup: 43514180ffa8SAdrian Hunter sdhci_cleanup_host(host); 43524180ffa8SAdrian Hunter 43534180ffa8SAdrian Hunter return ret; 435452f5336dSAdrian Hunter } 4355b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_add_host); 4356b8c86fc5SPierre Ossman 43571e72859eSPierre Ossman void sdhci_remove_host(struct sdhci_host *host, int dead) 43581c6a0718SPierre Ossman { 43593a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 43601e72859eSPierre Ossman unsigned long flags; 43611e72859eSPierre Ossman 43621e72859eSPierre Ossman if (dead) { 43631e72859eSPierre Ossman spin_lock_irqsave(&host->lock, flags); 43641e72859eSPierre Ossman 43651e72859eSPierre Ossman host->flags |= SDHCI_DEVICE_DEAD; 43661e72859eSPierre Ossman 43675d0d11c5SAdrian Hunter if (sdhci_has_requests(host)) { 4368a3c76eb9SGirish K S pr_err("%s: Controller removed during " 43694e743f1fSMarkus Mayer " transfer!\n", mmc_hostname(mmc)); 43705d0d11c5SAdrian Hunter sdhci_error_out_mrqs(host, -ENOMEDIUM); 43711e72859eSPierre Ossman } 43721e72859eSPierre Ossman 43731e72859eSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 43741e72859eSPierre Ossman } 43751e72859eSPierre Ossman 43767260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 43777260cf5eSAnton Vorontsov 43784e743f1fSMarkus Mayer mmc_remove_host(mmc); 43791c6a0718SPierre Ossman 4380061d17a6SAdrian Hunter sdhci_led_unregister(host); 43812f730fecSPierre Ossman 43821e72859eSPierre Ossman if (!dead) 438303231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 43841c6a0718SPierre Ossman 4385b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 4386b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 43871c6a0718SPierre Ossman free_irq(host->irq, host); 43881c6a0718SPierre Ossman 43891c6a0718SPierre Ossman del_timer_sync(&host->timer); 4390d7422fb4SAdrian Hunter del_timer_sync(&host->data_timer); 43911c6a0718SPierre Ossman 4392c07a48c2SAdrian Hunter destroy_workqueue(host->complete_wq); 43932134a922SPierre Ossman 43943a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) 43953a48edc4STim Kryger regulator_disable(mmc->supply.vqmmc); 43966231f3deSPhilip Rakity 4397edd63fccSRussell King if (host->align_buffer) 4398e66e61cbSRussell King dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 4399e66e61cbSRussell King host->adma_table_sz, host->align_buffer, 4400e66e61cbSRussell King host->align_addr); 44012134a922SPierre Ossman 44024efaa6fbSAdrian Hunter host->adma_table = NULL; 44032134a922SPierre Ossman host->align_buffer = NULL; 44041c6a0718SPierre Ossman } 44051c6a0718SPierre Ossman 4406b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_remove_host); 4407b8c86fc5SPierre Ossman 4408b8c86fc5SPierre Ossman void sdhci_free_host(struct sdhci_host *host) 44091c6a0718SPierre Ossman { 4410b8c86fc5SPierre Ossman mmc_free_host(host->mmc); 44111c6a0718SPierre Ossman } 44121c6a0718SPierre Ossman 4413b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_free_host); 44141c6a0718SPierre Ossman 44151c6a0718SPierre Ossman /*****************************************************************************\ 44161c6a0718SPierre Ossman * * 44171c6a0718SPierre Ossman * Driver init/exit * 44181c6a0718SPierre Ossman * * 44191c6a0718SPierre Ossman \*****************************************************************************/ 44201c6a0718SPierre Ossman 44211c6a0718SPierre Ossman static int __init sdhci_drv_init(void) 44221c6a0718SPierre Ossman { 4423a3c76eb9SGirish K S pr_info(DRIVER_NAME 44241c6a0718SPierre Ossman ": Secure Digital Host Controller Interface driver\n"); 4425a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 44261c6a0718SPierre Ossman 4427b8c86fc5SPierre Ossman return 0; 44281c6a0718SPierre Ossman } 44291c6a0718SPierre Ossman 44301c6a0718SPierre Ossman static void __exit sdhci_drv_exit(void) 44311c6a0718SPierre Ossman { 44321c6a0718SPierre Ossman } 44331c6a0718SPierre Ossman 44341c6a0718SPierre Ossman module_init(sdhci_drv_init); 44351c6a0718SPierre Ossman module_exit(sdhci_drv_exit); 44361c6a0718SPierre Ossman 44371c6a0718SPierre Ossman module_param(debug_quirks, uint, 0444); 443866fd8ad5SAdrian Hunter module_param(debug_quirks2, uint, 0444); 44391c6a0718SPierre Ossman 444032710e8fSPierre Ossman MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 4441b8c86fc5SPierre Ossman MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 44421c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 44431c6a0718SPierre Ossman 44441c6a0718SPierre Ossman MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 444566fd8ad5SAdrian Hunter MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 4446