12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 41c6a0718SPierre Ossman * 5b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 61c6a0718SPierre Ossman * 784c46a53SPierre Ossman * Thanks to the following companies for their support: 884c46a53SPierre Ossman * 984c46a53SPierre Ossman * - JMicron (hardware and technical support) 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman 121c6a0718SPierre Ossman #include <linux/delay.h> 1318e762e3SChunyan Zhang #include <linux/dmaengine.h> 145a436cc0SAdrian Hunter #include <linux/ktime.h> 151c6a0718SPierre Ossman #include <linux/highmem.h> 16b8c86fc5SPierre Ossman #include <linux/io.h> 1788b47679SPaul Gortmaker #include <linux/module.h> 181c6a0718SPierre Ossman #include <linux/dma-mapping.h> 195a0e3ad6STejun Heo #include <linux/slab.h> 2011763609SRalf Baechle #include <linux/scatterlist.h> 21bd9b9027SLinus Walleij #include <linux/sizes.h> 22250dcd11SUlf Hansson #include <linux/swiotlb.h> 239bea3c85SMarek Szyprowski #include <linux/regulator/consumer.h> 2466fd8ad5SAdrian Hunter #include <linux/pm_runtime.h> 2592e0c44bSZach Brown #include <linux/of.h> 261c6a0718SPierre Ossman 272f730fecSPierre Ossman #include <linux/leds.h> 282f730fecSPierre Ossman 2922113efdSAries Lee #include <linux/mmc/mmc.h> 301c6a0718SPierre Ossman #include <linux/mmc/host.h> 31473b095aSAaron Lu #include <linux/mmc/card.h> 3285cc1c33SCorneliu Doban #include <linux/mmc/sdio.h> 33bec9d4e5SGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #include "sdhci.h" 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define DRIVER_NAME "sdhci" 381c6a0718SPierre Ossman 391c6a0718SPierre Ossman #define DBG(f, x...) \ 40f421865dSAdrian Hunter pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 411c6a0718SPierre Ossman 4285ad90e2SAdrian Hunter #define SDHCI_DUMP(f, x...) \ 4385ad90e2SAdrian Hunter pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 4485ad90e2SAdrian Hunter 45b513ea25SArindam Nath #define MAX_TUNING_LOOP 40 46b513ea25SArindam Nath 471c6a0718SPierre Ossman static unsigned int debug_quirks = 0; 4866fd8ad5SAdrian Hunter static unsigned int debug_quirks2; 491c6a0718SPierre Ossman 501c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *); 511c6a0718SPierre Ossman 5252983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 531c6a0718SPierre Ossman 54d2898172SAdrian Hunter void sdhci_dumpregs(struct sdhci_host *host) 551c6a0718SPierre Ossman { 5685ad90e2SAdrian Hunter SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n"); 571c6a0718SPierre Ossman 5885ad90e2SAdrian Hunter SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n", 594e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_DMA_ADDRESS), 604e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_HOST_VERSION)); 6185ad90e2SAdrian Hunter SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n", 624e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_SIZE), 634e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_COUNT)); 6485ad90e2SAdrian Hunter SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n", 654e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_ARGUMENT), 664e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_TRANSFER_MODE)); 6785ad90e2SAdrian Hunter SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n", 684e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_PRESENT_STATE), 694e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_HOST_CONTROL)); 7085ad90e2SAdrian Hunter SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n", 714e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_POWER_CONTROL), 724e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 7385ad90e2SAdrian Hunter SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n", 744e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 754e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 7685ad90e2SAdrian Hunter SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n", 774e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 784e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_STATUS)); 7985ad90e2SAdrian Hunter SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n", 804e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_ENABLE), 814e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 82869f8a69SAdrian Hunter SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n", 83869f8a69SAdrian Hunter sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), 844e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 8585ad90e2SAdrian Hunter SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n", 864e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_CAPABILITIES), 87e8120ad1SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1)); 8885ad90e2SAdrian Hunter SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n", 89e8120ad1SPhilip Rakity sdhci_readw(host, SDHCI_COMMAND), 904e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_MAX_CURRENT)); 9185ad90e2SAdrian Hunter SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n", 927962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE), 937962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE + 4)); 9485ad90e2SAdrian Hunter SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n", 957962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE + 8), 967962302fSAdrian Hunter sdhci_readl(host, SDHCI_RESPONSE + 12)); 9785ad90e2SAdrian Hunter SDHCI_DUMP("Host ctl2: 0x%08x\n", 98f2119df6SArindam Nath sdhci_readw(host, SDHCI_HOST_CONTROL2)); 991c6a0718SPierre Ossman 100e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_ADMA) { 10185ad90e2SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) { 10285ad90e2SAdrian Hunter SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 103c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ERROR), 104c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI), 105c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ADDRESS)); 10685ad90e2SAdrian Hunter } else { 10785ad90e2SAdrian Hunter SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 108c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ERROR), 109c71024deSAdrian Hunter sdhci_readl(host, SDHCI_ADMA_ADDRESS)); 110e57a5f61SAdrian Hunter } 11185ad90e2SAdrian Hunter } 112be3f4ae0SBen Dooks 11385ad90e2SAdrian Hunter SDHCI_DUMP("============================================\n"); 1141c6a0718SPierre Ossman } 115d2898172SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_dumpregs); 1161c6a0718SPierre Ossman 1171c6a0718SPierre Ossman /*****************************************************************************\ 1181c6a0718SPierre Ossman * * 1191c6a0718SPierre Ossman * Low level functions * 1201c6a0718SPierre Ossman * * 1211c6a0718SPierre Ossman \*****************************************************************************/ 1221c6a0718SPierre Ossman 123b3f80b43SChunyan Zhang static void sdhci_do_enable_v4_mode(struct sdhci_host *host) 124b3f80b43SChunyan Zhang { 125b3f80b43SChunyan Zhang u16 ctrl2; 126b3f80b43SChunyan Zhang 12797207c12SSowjanya Komatineni ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 128b3f80b43SChunyan Zhang if (ctrl2 & SDHCI_CTRL_V4_MODE) 129b3f80b43SChunyan Zhang return; 130b3f80b43SChunyan Zhang 131b3f80b43SChunyan Zhang ctrl2 |= SDHCI_CTRL_V4_MODE; 13297207c12SSowjanya Komatineni sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 133b3f80b43SChunyan Zhang } 134b3f80b43SChunyan Zhang 135b3f80b43SChunyan Zhang /* 136b3f80b43SChunyan Zhang * This can be called before sdhci_add_host() by Vendor's host controller 137b3f80b43SChunyan Zhang * driver to enable v4 mode if supported. 138b3f80b43SChunyan Zhang */ 139b3f80b43SChunyan Zhang void sdhci_enable_v4_mode(struct sdhci_host *host) 140b3f80b43SChunyan Zhang { 141b3f80b43SChunyan Zhang host->v4_mode = true; 142b3f80b43SChunyan Zhang sdhci_do_enable_v4_mode(host); 143b3f80b43SChunyan Zhang } 144b3f80b43SChunyan Zhang EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); 145b3f80b43SChunyan Zhang 14656a590dcSAdrian Hunter static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 14756a590dcSAdrian Hunter { 14856a590dcSAdrian Hunter return cmd->data || cmd->flags & MMC_RSP_BUSY; 14956a590dcSAdrian Hunter } 15056a590dcSAdrian Hunter 1517260cf5eSAnton Vorontsov static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 1527260cf5eSAnton Vorontsov { 1535b4f1f6cSRussell King u32 present; 1547260cf5eSAnton Vorontsov 155c79396c1SAdrian Hunter if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 156860951c5SJaehoon Chung !mmc_card_is_removable(host->mmc)) 15766fd8ad5SAdrian Hunter return; 15866fd8ad5SAdrian Hunter 1595b4f1f6cSRussell King if (enable) { 160d25928d1SShawn Guo present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 161d25928d1SShawn Guo SDHCI_CARD_PRESENT; 162d25928d1SShawn Guo 1635b4f1f6cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 1645b4f1f6cSRussell King SDHCI_INT_CARD_INSERT; 1655b4f1f6cSRussell King } else { 1665b4f1f6cSRussell King host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 1675b4f1f6cSRussell King } 168b537f94cSRussell King 169b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 170b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1717260cf5eSAnton Vorontsov } 1727260cf5eSAnton Vorontsov 1737260cf5eSAnton Vorontsov static void sdhci_enable_card_detection(struct sdhci_host *host) 1747260cf5eSAnton Vorontsov { 1757260cf5eSAnton Vorontsov sdhci_set_card_detection(host, true); 1767260cf5eSAnton Vorontsov } 1777260cf5eSAnton Vorontsov 1787260cf5eSAnton Vorontsov static void sdhci_disable_card_detection(struct sdhci_host *host) 1797260cf5eSAnton Vorontsov { 1807260cf5eSAnton Vorontsov sdhci_set_card_detection(host, false); 1817260cf5eSAnton Vorontsov } 1827260cf5eSAnton Vorontsov 18302d0b685SUlf Hansson static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 18402d0b685SUlf Hansson { 18502d0b685SUlf Hansson if (host->bus_on) 18602d0b685SUlf Hansson return; 18702d0b685SUlf Hansson host->bus_on = true; 18802d0b685SUlf Hansson pm_runtime_get_noresume(host->mmc->parent); 18902d0b685SUlf Hansson } 19002d0b685SUlf Hansson 19102d0b685SUlf Hansson static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 19202d0b685SUlf Hansson { 19302d0b685SUlf Hansson if (!host->bus_on) 19402d0b685SUlf Hansson return; 19502d0b685SUlf Hansson host->bus_on = false; 19602d0b685SUlf Hansson pm_runtime_put_noidle(host->mmc->parent); 19702d0b685SUlf Hansson } 19802d0b685SUlf Hansson 19903231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask) 2001c6a0718SPierre Ossman { 2015a436cc0SAdrian Hunter ktime_t timeout; 202393c1a34SPhilip Rakity 2034e4141a5SAnton Vorontsov sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 2041c6a0718SPierre Ossman 205f0710a55SAdrian Hunter if (mask & SDHCI_RESET_ALL) { 2061c6a0718SPierre Ossman host->clock = 0; 207f0710a55SAdrian Hunter /* Reset-all turns off SD Bus Power */ 208f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 209f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 210f0710a55SAdrian Hunter } 2111c6a0718SPierre Ossman 2121c6a0718SPierre Ossman /* Wait max 100 ms */ 2135a436cc0SAdrian Hunter timeout = ktime_add_ms(ktime_get(), 100); 2141c6a0718SPierre Ossman 2151c6a0718SPierre Ossman /* hw clears the bit when it's done */ 216b704441eSAlek Du while (1) { 217b704441eSAlek Du bool timedout = ktime_after(ktime_get(), timeout); 218b704441eSAlek Du 219b704441eSAlek Du if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) 220b704441eSAlek Du break; 221b704441eSAlek Du if (timedout) { 222a3c76eb9SGirish K S pr_err("%s: Reset 0x%x never completed.\n", 2231c6a0718SPierre Ossman mmc_hostname(host->mmc), (int)mask); 2241c6a0718SPierre Ossman sdhci_dumpregs(host); 2251c6a0718SPierre Ossman return; 2261c6a0718SPierre Ossman } 2275a436cc0SAdrian Hunter udelay(10); 2281c6a0718SPierre Ossman } 22903231f9bSRussell King } 23003231f9bSRussell King EXPORT_SYMBOL_GPL(sdhci_reset); 231063a9dbbSAnton Vorontsov 23203231f9bSRussell King static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 23303231f9bSRussell King { 23403231f9bSRussell King if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 235d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 236d3940f27SAdrian Hunter 237d3940f27SAdrian Hunter if (!mmc->ops->get_cd(mmc)) 23803231f9bSRussell King return; 23903231f9bSRussell King } 24003231f9bSRussell King 24103231f9bSRussell King host->ops->reset(host, mask); 242393c1a34SPhilip Rakity 243da91a8f9SRussell King if (mask & SDHCI_RESET_ALL) { 2443abc1e80SShaohui Xie if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 245da91a8f9SRussell King if (host->ops->enable_dma) 2463abc1e80SShaohui Xie host->ops->enable_dma(host); 2473abc1e80SShaohui Xie } 248da91a8f9SRussell King 249da91a8f9SRussell King /* Resetting the controller clears many */ 250da91a8f9SRussell King host->preset_enabled = false; 251da91a8f9SRussell King } 2521c6a0718SPierre Ossman } 2531c6a0718SPierre Ossman 254f5c1ab82SAdrian Hunter static void sdhci_set_default_irqs(struct sdhci_host *host) 2551c6a0718SPierre Ossman { 256b537f94cSRussell King host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 257b537f94cSRussell King SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 258b537f94cSRussell King SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 259b537f94cSRussell King SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 260b537f94cSRussell King SDHCI_INT_RESPONSE; 261b537f94cSRussell King 262f37b20ebSDong Aisheng if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 263f37b20ebSDong Aisheng host->tuning_mode == SDHCI_TUNING_MODE_3) 264f37b20ebSDong Aisheng host->ier |= SDHCI_INT_RETUNE; 265f37b20ebSDong Aisheng 266b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 267b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 268f5c1ab82SAdrian Hunter } 269f5c1ab82SAdrian Hunter 270685e444bSChunyan Zhang static void sdhci_config_dma(struct sdhci_host *host) 271685e444bSChunyan Zhang { 272685e444bSChunyan Zhang u8 ctrl; 273685e444bSChunyan Zhang u16 ctrl2; 274685e444bSChunyan Zhang 275685e444bSChunyan Zhang if (host->version < SDHCI_SPEC_200) 276685e444bSChunyan Zhang return; 277685e444bSChunyan Zhang 278685e444bSChunyan Zhang ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 279685e444bSChunyan Zhang 280685e444bSChunyan Zhang /* 281685e444bSChunyan Zhang * Always adjust the DMA selection as some controllers 282685e444bSChunyan Zhang * (e.g. JMicron) can't do PIO properly when the selection 283685e444bSChunyan Zhang * is ADMA. 284685e444bSChunyan Zhang */ 285685e444bSChunyan Zhang ctrl &= ~SDHCI_CTRL_DMA_MASK; 286685e444bSChunyan Zhang if (!(host->flags & SDHCI_REQ_USE_DMA)) 287685e444bSChunyan Zhang goto out; 288685e444bSChunyan Zhang 289685e444bSChunyan Zhang /* Note if DMA Select is zero then SDMA is selected */ 290685e444bSChunyan Zhang if (host->flags & SDHCI_USE_ADMA) 291685e444bSChunyan Zhang ctrl |= SDHCI_CTRL_ADMA32; 292685e444bSChunyan Zhang 293685e444bSChunyan Zhang if (host->flags & SDHCI_USE_64_BIT_DMA) { 294685e444bSChunyan Zhang /* 295685e444bSChunyan Zhang * If v4 mode, all supported DMA can be 64-bit addressing if 296685e444bSChunyan Zhang * controller supports 64-bit system address, otherwise only 297685e444bSChunyan Zhang * ADMA can support 64-bit addressing. 298685e444bSChunyan Zhang */ 299685e444bSChunyan Zhang if (host->v4_mode) { 300685e444bSChunyan Zhang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 301685e444bSChunyan Zhang ctrl2 |= SDHCI_CTRL_64BIT_ADDR; 302685e444bSChunyan Zhang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 303685e444bSChunyan Zhang } else if (host->flags & SDHCI_USE_ADMA) { 304685e444bSChunyan Zhang /* 305685e444bSChunyan Zhang * Don't need to undo SDHCI_CTRL_ADMA32 in order to 306685e444bSChunyan Zhang * set SDHCI_CTRL_ADMA64. 307685e444bSChunyan Zhang */ 308685e444bSChunyan Zhang ctrl |= SDHCI_CTRL_ADMA64; 309685e444bSChunyan Zhang } 310685e444bSChunyan Zhang } 311685e444bSChunyan Zhang 312685e444bSChunyan Zhang out: 313685e444bSChunyan Zhang sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 314685e444bSChunyan Zhang } 315685e444bSChunyan Zhang 316f5c1ab82SAdrian Hunter static void sdhci_init(struct sdhci_host *host, int soft) 317f5c1ab82SAdrian Hunter { 318f5c1ab82SAdrian Hunter struct mmc_host *mmc = host->mmc; 319f5c1ab82SAdrian Hunter 320f5c1ab82SAdrian Hunter if (soft) 321f5c1ab82SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 322f5c1ab82SAdrian Hunter else 323f5c1ab82SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_ALL); 324f5c1ab82SAdrian Hunter 325b3f80b43SChunyan Zhang if (host->v4_mode) 326b3f80b43SChunyan Zhang sdhci_do_enable_v4_mode(host); 327b3f80b43SChunyan Zhang 328f5c1ab82SAdrian Hunter sdhci_set_default_irqs(host); 3292f4cbb3dSNicolas Pitre 330f12e39dbSAdrian Hunter host->cqe_on = false; 331f12e39dbSAdrian Hunter 3322f4cbb3dSNicolas Pitre if (soft) { 3332f4cbb3dSNicolas Pitre /* force clock reconfiguration */ 3342f4cbb3dSNicolas Pitre host->clock = 0; 335d3940f27SAdrian Hunter mmc->ops->set_ios(mmc, &mmc->ios); 3362f4cbb3dSNicolas Pitre } 3377260cf5eSAnton Vorontsov } 3381c6a0718SPierre Ossman 3397260cf5eSAnton Vorontsov static void sdhci_reinit(struct sdhci_host *host) 3407260cf5eSAnton Vorontsov { 341dcaac3f7SRaul E Rangel u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 342dcaac3f7SRaul E Rangel 3432f4cbb3dSNicolas Pitre sdhci_init(host, 0); 3447260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 345dcaac3f7SRaul E Rangel 346dcaac3f7SRaul E Rangel /* 347dcaac3f7SRaul E Rangel * A change to the card detect bits indicates a change in present state, 348dcaac3f7SRaul E Rangel * refer sdhci_set_card_detection(). A card detect interrupt might have 349dcaac3f7SRaul E Rangel * been missed while the host controller was being reset, so trigger a 350dcaac3f7SRaul E Rangel * rescan to check. 351dcaac3f7SRaul E Rangel */ 352dcaac3f7SRaul E Rangel if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT))) 353dcaac3f7SRaul E Rangel mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 3541c6a0718SPierre Ossman } 3551c6a0718SPierre Ossman 356061d17a6SAdrian Hunter static void __sdhci_led_activate(struct sdhci_host *host) 3571c6a0718SPierre Ossman { 3581c6a0718SPierre Ossman u8 ctrl; 3591c6a0718SPierre Ossman 360bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 361bd29f58bSAdrian Hunter return; 362bd29f58bSAdrian Hunter 3634e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3641c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_LED; 3654e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3661c6a0718SPierre Ossman } 3671c6a0718SPierre Ossman 368061d17a6SAdrian Hunter static void __sdhci_led_deactivate(struct sdhci_host *host) 3691c6a0718SPierre Ossman { 3701c6a0718SPierre Ossman u8 ctrl; 3711c6a0718SPierre Ossman 372bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 373bd29f58bSAdrian Hunter return; 374bd29f58bSAdrian Hunter 3754e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3761c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_LED; 3774e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3781c6a0718SPierre Ossman } 3791c6a0718SPierre Ossman 3804f78230fSMasahiro Yamada #if IS_REACHABLE(CONFIG_LEDS_CLASS) 3812f730fecSPierre Ossman static void sdhci_led_control(struct led_classdev *led, 3822f730fecSPierre Ossman enum led_brightness brightness) 3832f730fecSPierre Ossman { 3842f730fecSPierre Ossman struct sdhci_host *host = container_of(led, struct sdhci_host, led); 3852f730fecSPierre Ossman unsigned long flags; 3862f730fecSPierre Ossman 3872f730fecSPierre Ossman spin_lock_irqsave(&host->lock, flags); 3882f730fecSPierre Ossman 38966fd8ad5SAdrian Hunter if (host->runtime_suspended) 39066fd8ad5SAdrian Hunter goto out; 39166fd8ad5SAdrian Hunter 3922f730fecSPierre Ossman if (brightness == LED_OFF) 393061d17a6SAdrian Hunter __sdhci_led_deactivate(host); 3942f730fecSPierre Ossman else 395061d17a6SAdrian Hunter __sdhci_led_activate(host); 39666fd8ad5SAdrian Hunter out: 3972f730fecSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 3982f730fecSPierre Ossman } 399061d17a6SAdrian Hunter 400061d17a6SAdrian Hunter static int sdhci_led_register(struct sdhci_host *host) 401061d17a6SAdrian Hunter { 402061d17a6SAdrian Hunter struct mmc_host *mmc = host->mmc; 403061d17a6SAdrian Hunter 404bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 405bd29f58bSAdrian Hunter return 0; 406bd29f58bSAdrian Hunter 407061d17a6SAdrian Hunter snprintf(host->led_name, sizeof(host->led_name), 408061d17a6SAdrian Hunter "%s::", mmc_hostname(mmc)); 409061d17a6SAdrian Hunter 410061d17a6SAdrian Hunter host->led.name = host->led_name; 411061d17a6SAdrian Hunter host->led.brightness = LED_OFF; 412061d17a6SAdrian Hunter host->led.default_trigger = mmc_hostname(mmc); 413061d17a6SAdrian Hunter host->led.brightness_set = sdhci_led_control; 414061d17a6SAdrian Hunter 415061d17a6SAdrian Hunter return led_classdev_register(mmc_dev(mmc), &host->led); 416061d17a6SAdrian Hunter } 417061d17a6SAdrian Hunter 418061d17a6SAdrian Hunter static void sdhci_led_unregister(struct sdhci_host *host) 419061d17a6SAdrian Hunter { 420bd29f58bSAdrian Hunter if (host->quirks & SDHCI_QUIRK_NO_LED) 421bd29f58bSAdrian Hunter return; 422bd29f58bSAdrian Hunter 423061d17a6SAdrian Hunter led_classdev_unregister(&host->led); 424061d17a6SAdrian Hunter } 425061d17a6SAdrian Hunter 426061d17a6SAdrian Hunter static inline void sdhci_led_activate(struct sdhci_host *host) 427061d17a6SAdrian Hunter { 428061d17a6SAdrian Hunter } 429061d17a6SAdrian Hunter 430061d17a6SAdrian Hunter static inline void sdhci_led_deactivate(struct sdhci_host *host) 431061d17a6SAdrian Hunter { 432061d17a6SAdrian Hunter } 433061d17a6SAdrian Hunter 434061d17a6SAdrian Hunter #else 435061d17a6SAdrian Hunter 436061d17a6SAdrian Hunter static inline int sdhci_led_register(struct sdhci_host *host) 437061d17a6SAdrian Hunter { 438061d17a6SAdrian Hunter return 0; 439061d17a6SAdrian Hunter } 440061d17a6SAdrian Hunter 441061d17a6SAdrian Hunter static inline void sdhci_led_unregister(struct sdhci_host *host) 442061d17a6SAdrian Hunter { 443061d17a6SAdrian Hunter } 444061d17a6SAdrian Hunter 445061d17a6SAdrian Hunter static inline void sdhci_led_activate(struct sdhci_host *host) 446061d17a6SAdrian Hunter { 447061d17a6SAdrian Hunter __sdhci_led_activate(host); 448061d17a6SAdrian Hunter } 449061d17a6SAdrian Hunter 450061d17a6SAdrian Hunter static inline void sdhci_led_deactivate(struct sdhci_host *host) 451061d17a6SAdrian Hunter { 452061d17a6SAdrian Hunter __sdhci_led_deactivate(host); 453061d17a6SAdrian Hunter } 454061d17a6SAdrian Hunter 4552f730fecSPierre Ossman #endif 4562f730fecSPierre Ossman 45797a1abaeSAdrian Hunter static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 45897a1abaeSAdrian Hunter unsigned long timeout) 45997a1abaeSAdrian Hunter { 46097a1abaeSAdrian Hunter if (sdhci_data_line_cmd(mrq->cmd)) 46197a1abaeSAdrian Hunter mod_timer(&host->data_timer, timeout); 46297a1abaeSAdrian Hunter else 46397a1abaeSAdrian Hunter mod_timer(&host->timer, timeout); 46497a1abaeSAdrian Hunter } 46597a1abaeSAdrian Hunter 46697a1abaeSAdrian Hunter static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 46797a1abaeSAdrian Hunter { 46897a1abaeSAdrian Hunter if (sdhci_data_line_cmd(mrq->cmd)) 46997a1abaeSAdrian Hunter del_timer(&host->data_timer); 47097a1abaeSAdrian Hunter else 47197a1abaeSAdrian Hunter del_timer(&host->timer); 47297a1abaeSAdrian Hunter } 47397a1abaeSAdrian Hunter 47497a1abaeSAdrian Hunter static inline bool sdhci_has_requests(struct sdhci_host *host) 47597a1abaeSAdrian Hunter { 47697a1abaeSAdrian Hunter return host->cmd || host->data_cmd; 47797a1abaeSAdrian Hunter } 47897a1abaeSAdrian Hunter 4791c6a0718SPierre Ossman /*****************************************************************************\ 4801c6a0718SPierre Ossman * * 4811c6a0718SPierre Ossman * Core functions * 4821c6a0718SPierre Ossman * * 4831c6a0718SPierre Ossman \*****************************************************************************/ 4841c6a0718SPierre Ossman 4851c6a0718SPierre Ossman static void sdhci_read_block_pio(struct sdhci_host *host) 4861c6a0718SPierre Ossman { 4877659150cSPierre Ossman unsigned long flags; 4887659150cSPierre Ossman size_t blksize, len, chunk; 4897244b85bSSteven Noonan u32 uninitialized_var(scratch); 4907659150cSPierre Ossman u8 *buf; 4911c6a0718SPierre Ossman 4921c6a0718SPierre Ossman DBG("PIO reading\n"); 4931c6a0718SPierre Ossman 4941c6a0718SPierre Ossman blksize = host->data->blksz; 4957659150cSPierre Ossman chunk = 0; 4961c6a0718SPierre Ossman 4977659150cSPierre Ossman local_irq_save(flags); 4981c6a0718SPierre Ossman 4991c6a0718SPierre Ossman while (blksize) { 500bf3a35acSFabio Estevam BUG_ON(!sg_miter_next(&host->sg_miter)); 5017659150cSPierre Ossman 5027659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 5037659150cSPierre Ossman 5047659150cSPierre Ossman blksize -= len; 5057659150cSPierre Ossman host->sg_miter.consumed = len; 5067659150cSPierre Ossman 5077659150cSPierre Ossman buf = host->sg_miter.addr; 5087659150cSPierre Ossman 5097659150cSPierre Ossman while (len) { 5107659150cSPierre Ossman if (chunk == 0) { 5114e4141a5SAnton Vorontsov scratch = sdhci_readl(host, SDHCI_BUFFER); 5127659150cSPierre Ossman chunk = 4; 5131c6a0718SPierre Ossman } 5141c6a0718SPierre Ossman 5157659150cSPierre Ossman *buf = scratch & 0xFF; 5161c6a0718SPierre Ossman 5177659150cSPierre Ossman buf++; 5187659150cSPierre Ossman scratch >>= 8; 5197659150cSPierre Ossman chunk--; 5207659150cSPierre Ossman len--; 5217659150cSPierre Ossman } 5221c6a0718SPierre Ossman } 5231c6a0718SPierre Ossman 5247659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 5257659150cSPierre Ossman 5267659150cSPierre Ossman local_irq_restore(flags); 5271c6a0718SPierre Ossman } 5281c6a0718SPierre Ossman 5291c6a0718SPierre Ossman static void sdhci_write_block_pio(struct sdhci_host *host) 5301c6a0718SPierre Ossman { 5317659150cSPierre Ossman unsigned long flags; 5327659150cSPierre Ossman size_t blksize, len, chunk; 5337659150cSPierre Ossman u32 scratch; 5347659150cSPierre Ossman u8 *buf; 5351c6a0718SPierre Ossman 5361c6a0718SPierre Ossman DBG("PIO writing\n"); 5371c6a0718SPierre Ossman 5381c6a0718SPierre Ossman blksize = host->data->blksz; 5397659150cSPierre Ossman chunk = 0; 5407659150cSPierre Ossman scratch = 0; 5411c6a0718SPierre Ossman 5427659150cSPierre Ossman local_irq_save(flags); 5431c6a0718SPierre Ossman 5441c6a0718SPierre Ossman while (blksize) { 545bf3a35acSFabio Estevam BUG_ON(!sg_miter_next(&host->sg_miter)); 5461c6a0718SPierre Ossman 5477659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 5481c6a0718SPierre Ossman 5497659150cSPierre Ossman blksize -= len; 5507659150cSPierre Ossman host->sg_miter.consumed = len; 5517659150cSPierre Ossman 5527659150cSPierre Ossman buf = host->sg_miter.addr; 5537659150cSPierre Ossman 5547659150cSPierre Ossman while (len) { 5557659150cSPierre Ossman scratch |= (u32)*buf << (chunk * 8); 5567659150cSPierre Ossman 5577659150cSPierre Ossman buf++; 5587659150cSPierre Ossman chunk++; 5597659150cSPierre Ossman len--; 5607659150cSPierre Ossman 5617659150cSPierre Ossman if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 5624e4141a5SAnton Vorontsov sdhci_writel(host, scratch, SDHCI_BUFFER); 5637659150cSPierre Ossman chunk = 0; 5647659150cSPierre Ossman scratch = 0; 5657659150cSPierre Ossman } 5667659150cSPierre Ossman } 5671c6a0718SPierre Ossman } 5681c6a0718SPierre Ossman 5697659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 5701c6a0718SPierre Ossman 5717659150cSPierre Ossman local_irq_restore(flags); 5721c6a0718SPierre Ossman } 5731c6a0718SPierre Ossman 5741c6a0718SPierre Ossman static void sdhci_transfer_pio(struct sdhci_host *host) 5751c6a0718SPierre Ossman { 5761c6a0718SPierre Ossman u32 mask; 5771c6a0718SPierre Ossman 5787659150cSPierre Ossman if (host->blocks == 0) 5791c6a0718SPierre Ossman return; 5801c6a0718SPierre Ossman 5811c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 5821c6a0718SPierre Ossman mask = SDHCI_DATA_AVAILABLE; 5831c6a0718SPierre Ossman else 5841c6a0718SPierre Ossman mask = SDHCI_SPACE_AVAILABLE; 5851c6a0718SPierre Ossman 5864a3cba32SPierre Ossman /* 5874a3cba32SPierre Ossman * Some controllers (JMicron JMB38x) mess up the buffer bits 5884a3cba32SPierre Ossman * for transfers < 4 bytes. As long as it is just one block, 5894a3cba32SPierre Ossman * we can ignore the bits. 5904a3cba32SPierre Ossman */ 5914a3cba32SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 5924a3cba32SPierre Ossman (host->data->blocks == 1)) 5934a3cba32SPierre Ossman mask = ~0; 5944a3cba32SPierre Ossman 5954e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 5963e3bf207SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 5973e3bf207SAnton Vorontsov udelay(100); 5983e3bf207SAnton Vorontsov 5991c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 6001c6a0718SPierre Ossman sdhci_read_block_pio(host); 6011c6a0718SPierre Ossman else 6021c6a0718SPierre Ossman sdhci_write_block_pio(host); 6031c6a0718SPierre Ossman 6047659150cSPierre Ossman host->blocks--; 6057659150cSPierre Ossman if (host->blocks == 0) 6061c6a0718SPierre Ossman break; 6071c6a0718SPierre Ossman } 6081c6a0718SPierre Ossman 6091c6a0718SPierre Ossman DBG("PIO transfer complete.\n"); 6101c6a0718SPierre Ossman } 6111c6a0718SPierre Ossman 61248857d9bSRussell King static int sdhci_pre_dma_transfer(struct sdhci_host *host, 613c0999b72SRussell King struct mmc_data *data, int cookie) 61448857d9bSRussell King { 61548857d9bSRussell King int sg_count; 61648857d9bSRussell King 61794538e51SRussell King /* 61894538e51SRussell King * If the data buffers are already mapped, return the previous 61994538e51SRussell King * dma_map_sg() result. 62094538e51SRussell King */ 62194538e51SRussell King if (data->host_cookie == COOKIE_PRE_MAPPED) 62248857d9bSRussell King return data->sg_count; 62348857d9bSRussell King 624bd9b9027SLinus Walleij /* Bounce write requests to the bounce buffer */ 625bd9b9027SLinus Walleij if (host->bounce_buffer) { 626bd9b9027SLinus Walleij unsigned int length = data->blksz * data->blocks; 627bd9b9027SLinus Walleij 628bd9b9027SLinus Walleij if (length > host->bounce_buffer_size) { 629bd9b9027SLinus Walleij pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n", 630bd9b9027SLinus Walleij mmc_hostname(host->mmc), length, 631bd9b9027SLinus Walleij host->bounce_buffer_size); 632bd9b9027SLinus Walleij return -EIO; 633bd9b9027SLinus Walleij } 634bd9b9027SLinus Walleij if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) { 635bd9b9027SLinus Walleij /* Copy the data to the bounce buffer */ 636bd9b9027SLinus Walleij sg_copy_to_buffer(data->sg, data->sg_len, 637bd9b9027SLinus Walleij host->bounce_buffer, 638bd9b9027SLinus Walleij length); 639bd9b9027SLinus Walleij } 640bd9b9027SLinus Walleij /* Switch ownership to the DMA */ 641bd9b9027SLinus Walleij dma_sync_single_for_device(host->mmc->parent, 642bd9b9027SLinus Walleij host->bounce_addr, 643bd9b9027SLinus Walleij host->bounce_buffer_size, 644feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 645bd9b9027SLinus Walleij /* Just a dummy value */ 646bd9b9027SLinus Walleij sg_count = 1; 647bd9b9027SLinus Walleij } else { 648bd9b9027SLinus Walleij /* Just access the data directly from memory */ 649bd9b9027SLinus Walleij sg_count = dma_map_sg(mmc_dev(host->mmc), 650bd9b9027SLinus Walleij data->sg, data->sg_len, 651bd9b9027SLinus Walleij mmc_get_dma_dir(data)); 652bd9b9027SLinus Walleij } 65348857d9bSRussell King 65448857d9bSRussell King if (sg_count == 0) 65548857d9bSRussell King return -ENOSPC; 65648857d9bSRussell King 65748857d9bSRussell King data->sg_count = sg_count; 658c0999b72SRussell King data->host_cookie = cookie; 65948857d9bSRussell King 66048857d9bSRussell King return sg_count; 66148857d9bSRussell King } 66248857d9bSRussell King 6632134a922SPierre Ossman static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 6642134a922SPierre Ossman { 6652134a922SPierre Ossman local_irq_save(*flags); 666482fce99SCong Wang return kmap_atomic(sg_page(sg)) + sg->offset; 6672134a922SPierre Ossman } 6682134a922SPierre Ossman 6692134a922SPierre Ossman static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 6702134a922SPierre Ossman { 671482fce99SCong Wang kunmap_atomic(buffer); 6722134a922SPierre Ossman local_irq_restore(*flags); 6732134a922SPierre Ossman } 6742134a922SPierre Ossman 67554552e49SJisheng Zhang void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 67654552e49SJisheng Zhang dma_addr_t addr, int len, unsigned int cmd) 677118cd17dSBen Dooks { 67854552e49SJisheng Zhang struct sdhci_adma2_64_desc *dma_desc = *desc; 679118cd17dSBen Dooks 680e57a5f61SAdrian Hunter /* 32-bit and 64-bit descriptors have these members in same position */ 6810545230fSAdrian Hunter dma_desc->cmd = cpu_to_le16(cmd); 6820545230fSAdrian Hunter dma_desc->len = cpu_to_le16(len); 68338eee2e8SMasahiro Yamada dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr)); 684e57a5f61SAdrian Hunter 685e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 68638eee2e8SMasahiro Yamada dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr)); 68754552e49SJisheng Zhang 68854552e49SJisheng Zhang *desc += host->desc_sz; 68954552e49SJisheng Zhang } 69054552e49SJisheng Zhang EXPORT_SYMBOL_GPL(sdhci_adma_write_desc); 69154552e49SJisheng Zhang 69254552e49SJisheng Zhang static inline void __sdhci_adma_write_desc(struct sdhci_host *host, 69354552e49SJisheng Zhang void **desc, dma_addr_t addr, 69454552e49SJisheng Zhang int len, unsigned int cmd) 69554552e49SJisheng Zhang { 69654552e49SJisheng Zhang if (host->ops->adma_write_desc) 69754552e49SJisheng Zhang host->ops->adma_write_desc(host, desc, addr, len, cmd); 69807be55b5SJisheng Zhang else 69954552e49SJisheng Zhang sdhci_adma_write_desc(host, desc, addr, len, cmd); 700118cd17dSBen Dooks } 701118cd17dSBen Dooks 702b5ffa674SAdrian Hunter static void sdhci_adma_mark_end(void *desc) 703b5ffa674SAdrian Hunter { 704e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 705b5ffa674SAdrian Hunter 706e57a5f61SAdrian Hunter /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 7070545230fSAdrian Hunter dma_desc->cmd |= cpu_to_le16(ADMA2_END); 708b5ffa674SAdrian Hunter } 709b5ffa674SAdrian Hunter 71060c64762SRussell King static void sdhci_adma_table_pre(struct sdhci_host *host, 71160c64762SRussell King struct mmc_data *data, int sg_count) 7122134a922SPierre Ossman { 7132134a922SPierre Ossman struct scatterlist *sg; 7142134a922SPierre Ossman unsigned long flags; 715acc3ad13SRussell King dma_addr_t addr, align_addr; 716acc3ad13SRussell King void *desc, *align; 717acc3ad13SRussell King char *buffer; 718acc3ad13SRussell King int len, offset, i; 7192134a922SPierre Ossman 7202134a922SPierre Ossman /* 7212134a922SPierre Ossman * The spec does not specify endianness of descriptor table. 7222134a922SPierre Ossman * We currently guess that it is LE. 7232134a922SPierre Ossman */ 7242134a922SPierre Ossman 72560c64762SRussell King host->sg_count = sg_count; 7262134a922SPierre Ossman 7274efaa6fbSAdrian Hunter desc = host->adma_table; 7282134a922SPierre Ossman align = host->align_buffer; 7292134a922SPierre Ossman 7302134a922SPierre Ossman align_addr = host->align_addr; 7312134a922SPierre Ossman 7322134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 7332134a922SPierre Ossman addr = sg_dma_address(sg); 7342134a922SPierre Ossman len = sg_dma_len(sg); 7352134a922SPierre Ossman 7362134a922SPierre Ossman /* 737acc3ad13SRussell King * The SDHCI specification states that ADMA addresses must 738acc3ad13SRussell King * be 32-bit aligned. If they aren't, then we use a bounce 739acc3ad13SRussell King * buffer for the (up to three) bytes that screw up the 7402134a922SPierre Ossman * alignment. 7412134a922SPierre Ossman */ 74204a5ae6fSAdrian Hunter offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 74304a5ae6fSAdrian Hunter SDHCI_ADMA2_MASK; 7442134a922SPierre Ossman if (offset) { 7452134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 7462134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 7472134a922SPierre Ossman memcpy(align, buffer, offset); 7482134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 7492134a922SPierre Ossman } 7502134a922SPierre Ossman 751118cd17dSBen Dooks /* tran, valid */ 75254552e49SJisheng Zhang __sdhci_adma_write_desc(host, &desc, align_addr, 75354552e49SJisheng Zhang offset, ADMA2_TRAN_VALID); 7542134a922SPierre Ossman 7552134a922SPierre Ossman BUG_ON(offset > 65536); 7562134a922SPierre Ossman 75704a5ae6fSAdrian Hunter align += SDHCI_ADMA2_ALIGN; 75804a5ae6fSAdrian Hunter align_addr += SDHCI_ADMA2_ALIGN; 7592134a922SPierre Ossman 7602134a922SPierre Ossman addr += offset; 7612134a922SPierre Ossman len -= offset; 7622134a922SPierre Ossman } 7632134a922SPierre Ossman 7642134a922SPierre Ossman BUG_ON(len > 65536); 7652134a922SPierre Ossman 766118cd17dSBen Dooks /* tran, valid */ 76754552e49SJisheng Zhang if (len) 76854552e49SJisheng Zhang __sdhci_adma_write_desc(host, &desc, addr, len, 769347ea32dSAdrian Hunter ADMA2_TRAN_VALID); 7702134a922SPierre Ossman 7712134a922SPierre Ossman /* 7722134a922SPierre Ossman * If this triggers then we have a calculation bug 7732134a922SPierre Ossman * somewhere. :/ 7742134a922SPierre Ossman */ 77576fe379aSAdrian Hunter WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 7762134a922SPierre Ossman } 7772134a922SPierre Ossman 77870764a90SThomas Abraham if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 779acc3ad13SRussell King /* Mark the last descriptor as the terminating descriptor */ 7804efaa6fbSAdrian Hunter if (desc != host->adma_table) { 78176fe379aSAdrian Hunter desc -= host->desc_sz; 782b5ffa674SAdrian Hunter sdhci_adma_mark_end(desc); 78370764a90SThomas Abraham } 78470764a90SThomas Abraham } else { 785acc3ad13SRussell King /* Add a terminating entry - nop, end, valid */ 78654552e49SJisheng Zhang __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID); 78770764a90SThomas Abraham } 7882134a922SPierre Ossman } 7892134a922SPierre Ossman 7902134a922SPierre Ossman static void sdhci_adma_table_post(struct sdhci_host *host, 7912134a922SPierre Ossman struct mmc_data *data) 7922134a922SPierre Ossman { 7932134a922SPierre Ossman struct scatterlist *sg; 7942134a922SPierre Ossman int i, size; 7951c3d5f6dSAdrian Hunter void *align; 7962134a922SPierre Ossman char *buffer; 7972134a922SPierre Ossman unsigned long flags; 7982134a922SPierre Ossman 79947fa9613SRussell King if (data->flags & MMC_DATA_READ) { 80047fa9613SRussell King bool has_unaligned = false; 80147fa9613SRussell King 802de0b65a7SRussell King /* Do a quick scan of the SG list for any unaligned mappings */ 803de0b65a7SRussell King for_each_sg(data->sg, sg, host->sg_count, i) 80404a5ae6fSAdrian Hunter if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 805de0b65a7SRussell King has_unaligned = true; 806de0b65a7SRussell King break; 807de0b65a7SRussell King } 808de0b65a7SRussell King 80947fa9613SRussell King if (has_unaligned) { 8102134a922SPierre Ossman dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 811f55c98f7SRussell King data->sg_len, DMA_FROM_DEVICE); 8122134a922SPierre Ossman 8132134a922SPierre Ossman align = host->align_buffer; 8142134a922SPierre Ossman 8152134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 81604a5ae6fSAdrian Hunter if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 81704a5ae6fSAdrian Hunter size = SDHCI_ADMA2_ALIGN - 81804a5ae6fSAdrian Hunter (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 8192134a922SPierre Ossman 8202134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 8212134a922SPierre Ossman memcpy(buffer, align, size); 8222134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 8232134a922SPierre Ossman 82404a5ae6fSAdrian Hunter align += SDHCI_ADMA2_ALIGN; 8252134a922SPierre Ossman } 8262134a922SPierre Ossman } 8272134a922SPierre Ossman } 82847fa9613SRussell King } 8292134a922SPierre Ossman } 8302134a922SPierre Ossman 83138eee2e8SMasahiro Yamada static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr) 83238eee2e8SMasahiro Yamada { 83338eee2e8SMasahiro Yamada sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS); 83438eee2e8SMasahiro Yamada if (host->flags & SDHCI_USE_64_BIT_DMA) 83538eee2e8SMasahiro Yamada sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI); 83638eee2e8SMasahiro Yamada } 83738eee2e8SMasahiro Yamada 838917a0c52SChunyan Zhang static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) 839bd9b9027SLinus Walleij { 840bd9b9027SLinus Walleij if (host->bounce_buffer) 841bd9b9027SLinus Walleij return host->bounce_addr; 842bd9b9027SLinus Walleij else 843bd9b9027SLinus Walleij return sg_dma_address(host->data->sg); 844bd9b9027SLinus Walleij } 845bd9b9027SLinus Walleij 846917a0c52SChunyan Zhang static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) 847917a0c52SChunyan Zhang { 84838eee2e8SMasahiro Yamada if (host->v4_mode) 84938eee2e8SMasahiro Yamada sdhci_set_adma_addr(host, addr); 85038eee2e8SMasahiro Yamada else 851917a0c52SChunyan Zhang sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); 852917a0c52SChunyan Zhang } 853917a0c52SChunyan Zhang 8540bb28d73SAdrian Hunter static unsigned int sdhci_target_timeout(struct sdhci_host *host, 8550bb28d73SAdrian Hunter struct mmc_command *cmd, 8560bb28d73SAdrian Hunter struct mmc_data *data) 8570bb28d73SAdrian Hunter { 8580bb28d73SAdrian Hunter unsigned int target_timeout; 8590bb28d73SAdrian Hunter 8600bb28d73SAdrian Hunter /* timeout in us */ 8610bb28d73SAdrian Hunter if (!data) { 8620bb28d73SAdrian Hunter target_timeout = cmd->busy_timeout * 1000; 8630bb28d73SAdrian Hunter } else { 8640bb28d73SAdrian Hunter target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 8650bb28d73SAdrian Hunter if (host->clock && data->timeout_clks) { 8660bb28d73SAdrian Hunter unsigned long long val; 8670bb28d73SAdrian Hunter 8680bb28d73SAdrian Hunter /* 8690bb28d73SAdrian Hunter * data->timeout_clks is in units of clock cycles. 8700bb28d73SAdrian Hunter * host->clock is in Hz. target_timeout is in us. 8710bb28d73SAdrian Hunter * Hence, us = 1000000 * cycles / Hz. Round up. 8720bb28d73SAdrian Hunter */ 8730bb28d73SAdrian Hunter val = 1000000ULL * data->timeout_clks; 8740bb28d73SAdrian Hunter if (do_div(val, host->clock)) 8750bb28d73SAdrian Hunter target_timeout++; 8760bb28d73SAdrian Hunter target_timeout += val; 8770bb28d73SAdrian Hunter } 8780bb28d73SAdrian Hunter } 8790bb28d73SAdrian Hunter 8800bb28d73SAdrian Hunter return target_timeout; 8810bb28d73SAdrian Hunter } 8820bb28d73SAdrian Hunter 883fc1fa1b7SKishon Vijay Abraham I static void sdhci_calc_sw_timeout(struct sdhci_host *host, 884fc1fa1b7SKishon Vijay Abraham I struct mmc_command *cmd) 885fc1fa1b7SKishon Vijay Abraham I { 886fc1fa1b7SKishon Vijay Abraham I struct mmc_data *data = cmd->data; 887fc1fa1b7SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 888fc1fa1b7SKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 889fc1fa1b7SKishon Vijay Abraham I unsigned char bus_width = 1 << ios->bus_width; 890fc1fa1b7SKishon Vijay Abraham I unsigned int blksz; 891fc1fa1b7SKishon Vijay Abraham I unsigned int freq; 892fc1fa1b7SKishon Vijay Abraham I u64 target_timeout; 893fc1fa1b7SKishon Vijay Abraham I u64 transfer_time; 894fc1fa1b7SKishon Vijay Abraham I 895fc1fa1b7SKishon Vijay Abraham I target_timeout = sdhci_target_timeout(host, cmd, data); 896fc1fa1b7SKishon Vijay Abraham I target_timeout *= NSEC_PER_USEC; 897fc1fa1b7SKishon Vijay Abraham I 898fc1fa1b7SKishon Vijay Abraham I if (data) { 899fc1fa1b7SKishon Vijay Abraham I blksz = data->blksz; 900fc1fa1b7SKishon Vijay Abraham I freq = host->mmc->actual_clock ? : host->clock; 901fc1fa1b7SKishon Vijay Abraham I transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width); 902fc1fa1b7SKishon Vijay Abraham I do_div(transfer_time, freq); 903fc1fa1b7SKishon Vijay Abraham I /* multiply by '2' to account for any unknowns */ 904fc1fa1b7SKishon Vijay Abraham I transfer_time = transfer_time * 2; 905fc1fa1b7SKishon Vijay Abraham I /* calculate timeout for the entire data */ 906fc1fa1b7SKishon Vijay Abraham I host->data_timeout = data->blocks * target_timeout + 907fc1fa1b7SKishon Vijay Abraham I transfer_time; 908fc1fa1b7SKishon Vijay Abraham I } else { 909fc1fa1b7SKishon Vijay Abraham I host->data_timeout = target_timeout; 910fc1fa1b7SKishon Vijay Abraham I } 911fc1fa1b7SKishon Vijay Abraham I 912fc1fa1b7SKishon Vijay Abraham I if (host->data_timeout) 913fc1fa1b7SKishon Vijay Abraham I host->data_timeout += MMC_CMD_TRANSFER_TIME; 914fc1fa1b7SKishon Vijay Abraham I } 915fc1fa1b7SKishon Vijay Abraham I 916a999fd93SAdrian Hunter static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd, 917a999fd93SAdrian Hunter bool *too_big) 9181c6a0718SPierre Ossman { 9191c6a0718SPierre Ossman u8 count; 920401059dfSBOUGH CHEN struct mmc_data *data; 9211c6a0718SPierre Ossman unsigned target_timeout, current_timeout; 9221c6a0718SPierre Ossman 923a999fd93SAdrian Hunter *too_big = true; 924a999fd93SAdrian Hunter 925ee53ab5dSPierre Ossman /* 926ee53ab5dSPierre Ossman * If the host controller provides us with an incorrect timeout 927ee53ab5dSPierre Ossman * value, just skip the check and use 0xE. The hardware may take 928ee53ab5dSPierre Ossman * longer to time out, but that's much better than having a too-short 929ee53ab5dSPierre Ossman * timeout value. 930ee53ab5dSPierre Ossman */ 93111a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 932ee53ab5dSPierre Ossman return 0xE; 933e538fbe8SPierre Ossman 934401059dfSBOUGH CHEN /* Unspecified command, asume max */ 935401059dfSBOUGH CHEN if (cmd == NULL) 936401059dfSBOUGH CHEN return 0xE; 937401059dfSBOUGH CHEN 938401059dfSBOUGH CHEN data = cmd->data; 939a3c7778fSAndrei Warkentin /* Unspecified timeout, assume max */ 9401d4d7744SUlf Hansson if (!data && !cmd->busy_timeout) 941a3c7778fSAndrei Warkentin return 0xE; 942a3c7778fSAndrei Warkentin 9431c6a0718SPierre Ossman /* timeout in us */ 9440bb28d73SAdrian Hunter target_timeout = sdhci_target_timeout(host, cmd, data); 9451c6a0718SPierre Ossman 9461c6a0718SPierre Ossman /* 9471c6a0718SPierre Ossman * Figure out needed cycles. 9481c6a0718SPierre Ossman * We do this in steps in order to fit inside a 32 bit int. 9491c6a0718SPierre Ossman * The first step is the minimum timeout, which will have a 9501c6a0718SPierre Ossman * minimum resolution of 6 bits: 9511c6a0718SPierre Ossman * (1) 2^13*1000 > 2^22, 9521c6a0718SPierre Ossman * (2) host->timeout_clk < 2^16 9531c6a0718SPierre Ossman * => 9541c6a0718SPierre Ossman * (1) / (2) > 2^6 9551c6a0718SPierre Ossman */ 9561c6a0718SPierre Ossman count = 0; 9571c6a0718SPierre Ossman current_timeout = (1 << 13) * 1000 / host->timeout_clk; 9581c6a0718SPierre Ossman while (current_timeout < target_timeout) { 9591c6a0718SPierre Ossman count++; 9601c6a0718SPierre Ossman current_timeout <<= 1; 9611c6a0718SPierre Ossman if (count >= 0xF) 9621c6a0718SPierre Ossman break; 9631c6a0718SPierre Ossman } 9641c6a0718SPierre Ossman 9651c6a0718SPierre Ossman if (count >= 0xF) { 966a999fd93SAdrian Hunter if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)) 967f421865dSAdrian Hunter DBG("Too large timeout 0x%x requested for CMD%d!\n", 968f421865dSAdrian Hunter count, cmd->opcode); 9691c6a0718SPierre Ossman count = 0xE; 970a999fd93SAdrian Hunter } else { 971a999fd93SAdrian Hunter *too_big = false; 9721c6a0718SPierre Ossman } 9731c6a0718SPierre Ossman 974ee53ab5dSPierre Ossman return count; 975ee53ab5dSPierre Ossman } 976ee53ab5dSPierre Ossman 9776aa943abSAnton Vorontsov static void sdhci_set_transfer_irqs(struct sdhci_host *host) 9786aa943abSAnton Vorontsov { 9796aa943abSAnton Vorontsov u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 9806aa943abSAnton Vorontsov u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 9816aa943abSAnton Vorontsov 9826aa943abSAnton Vorontsov if (host->flags & SDHCI_REQ_USE_DMA) 983b537f94cSRussell King host->ier = (host->ier & ~pio_irqs) | dma_irqs; 9846aa943abSAnton Vorontsov else 985b537f94cSRussell King host->ier = (host->ier & ~dma_irqs) | pio_irqs; 986b537f94cSRussell King 987af849c86SAdrian Hunter if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12)) 988af849c86SAdrian Hunter host->ier |= SDHCI_INT_AUTO_CMD_ERR; 989af849c86SAdrian Hunter else 990af849c86SAdrian Hunter host->ier &= ~SDHCI_INT_AUTO_CMD_ERR; 991af849c86SAdrian Hunter 992b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 993b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 9946aa943abSAnton Vorontsov } 9956aa943abSAnton Vorontsov 9967907ebe7SFaiz Abbas void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable) 997a999fd93SAdrian Hunter { 998a999fd93SAdrian Hunter if (enable) 999a999fd93SAdrian Hunter host->ier |= SDHCI_INT_DATA_TIMEOUT; 1000a999fd93SAdrian Hunter else 1001a999fd93SAdrian Hunter host->ier &= ~SDHCI_INT_DATA_TIMEOUT; 1002a999fd93SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1003a999fd93SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1004a999fd93SAdrian Hunter } 10057907ebe7SFaiz Abbas EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq); 1006a999fd93SAdrian Hunter 10077d76ed77SFaiz Abbas void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1008ee53ab5dSPierre Ossman { 1009a999fd93SAdrian Hunter bool too_big = false; 10107d76ed77SFaiz Abbas u8 count = sdhci_calc_timeout(host, cmd, &too_big); 1011a999fd93SAdrian Hunter 1012a999fd93SAdrian Hunter if (too_big && 1013a999fd93SAdrian Hunter host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) { 1014fc1fa1b7SKishon Vijay Abraham I sdhci_calc_sw_timeout(host, cmd); 1015a999fd93SAdrian Hunter sdhci_set_data_timeout_irq(host, false); 1016a999fd93SAdrian Hunter } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) { 1017a999fd93SAdrian Hunter sdhci_set_data_timeout_irq(host, true); 1018a999fd93SAdrian Hunter } 1019a999fd93SAdrian Hunter 1020b45e668aSAisheng Dong sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 1021b45e668aSAisheng Dong } 10227d76ed77SFaiz Abbas EXPORT_SYMBOL_GPL(__sdhci_set_timeout); 10237d76ed77SFaiz Abbas 10247d76ed77SFaiz Abbas static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 10257d76ed77SFaiz Abbas { 10267d76ed77SFaiz Abbas if (host->ops->set_timeout) 10277d76ed77SFaiz Abbas host->ops->set_timeout(host, cmd); 10287d76ed77SFaiz Abbas else 10297d76ed77SFaiz Abbas __sdhci_set_timeout(host, cmd); 1030b45e668aSAisheng Dong } 1031b45e668aSAisheng Dong 103215db1836SFaiz Abbas static void sdhci_initialize_data(struct sdhci_host *host, 103315db1836SFaiz Abbas struct mmc_data *data) 1034b45e668aSAisheng Dong { 103543dea098SAdrian Hunter WARN_ON(host->data); 103643dea098SAdrian Hunter 1037ee53ab5dSPierre Ossman /* Sanity checks */ 1038ee53ab5dSPierre Ossman BUG_ON(data->blksz * data->blocks > 524288); 1039ee53ab5dSPierre Ossman BUG_ON(data->blksz > host->mmc->max_blk_size); 1040ee53ab5dSPierre Ossman BUG_ON(data->blocks > 65535); 1041ee53ab5dSPierre Ossman 1042ee53ab5dSPierre Ossman host->data = data; 1043ee53ab5dSPierre Ossman host->data_early = 0; 1044f6a03cbfSMikko Vinni host->data->bytes_xfered = 0; 104515db1836SFaiz Abbas } 104615db1836SFaiz Abbas 104715db1836SFaiz Abbas static inline void sdhci_set_block_info(struct sdhci_host *host, 104815db1836SFaiz Abbas struct mmc_data *data) 104915db1836SFaiz Abbas { 105015db1836SFaiz Abbas /* Set the DMA boundary value and block size */ 105115db1836SFaiz Abbas sdhci_writew(host, 105215db1836SFaiz Abbas SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), 105315db1836SFaiz Abbas SDHCI_BLOCK_SIZE); 105415db1836SFaiz Abbas /* 105515db1836SFaiz Abbas * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count 105615db1836SFaiz Abbas * can be supported, in that case 16-bit block count register must be 0. 105715db1836SFaiz Abbas */ 105815db1836SFaiz Abbas if (host->version >= SDHCI_SPEC_410 && host->v4_mode && 105915db1836SFaiz Abbas (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { 106015db1836SFaiz Abbas if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) 106115db1836SFaiz Abbas sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); 106215db1836SFaiz Abbas sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); 106315db1836SFaiz Abbas } else { 106415db1836SFaiz Abbas sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 106515db1836SFaiz Abbas } 106615db1836SFaiz Abbas } 106715db1836SFaiz Abbas 106815db1836SFaiz Abbas static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 106915db1836SFaiz Abbas { 107015db1836SFaiz Abbas struct mmc_data *data = cmd->data; 107115db1836SFaiz Abbas 107215db1836SFaiz Abbas sdhci_initialize_data(host, data); 1073ee53ab5dSPierre Ossman 1074fce14421SRussell King if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 1075fce14421SRussell King struct scatterlist *sg; 1076fce14421SRussell King unsigned int length_mask, offset_mask; 1077fce14421SRussell King int i; 1078fce14421SRussell King 1079c9fddbc4SPierre Ossman host->flags |= SDHCI_REQ_USE_DMA; 1080c9fddbc4SPierre Ossman 10812134a922SPierre Ossman /* 10822134a922SPierre Ossman * FIXME: This doesn't account for merging when mapping the 10832134a922SPierre Ossman * scatterlist. 1084df953925SRussell King * 1085df953925SRussell King * The assumption here being that alignment and lengths are 1086df953925SRussell King * the same after DMA mapping to device address space. 10872134a922SPierre Ossman */ 1088a0eaf0f9SRussell King length_mask = 0; 1089df953925SRussell King offset_mask = 0; 10902134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 1091df953925SRussell King if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 1092a0eaf0f9SRussell King length_mask = 3; 1093df953925SRussell King /* 1094df953925SRussell King * As we use up to 3 byte chunks to work 1095df953925SRussell King * around alignment problems, we need to 1096df953925SRussell King * check the offset as well. 1097df953925SRussell King */ 1098df953925SRussell King offset_mask = 3; 1099df953925SRussell King } 11002134a922SPierre Ossman } else { 11012134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 1102a0eaf0f9SRussell King length_mask = 3; 1103df953925SRussell King if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 1104df953925SRussell King offset_mask = 3; 11052134a922SPierre Ossman } 11062134a922SPierre Ossman 1107df953925SRussell King if (unlikely(length_mask | offset_mask)) { 11082134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 1109a0eaf0f9SRussell King if (sg->length & length_mask) { 11102e4456f0SMarek Vasut DBG("Reverting to PIO because of transfer size (%d)\n", 11112134a922SPierre Ossman sg->length); 1112c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 11132134a922SPierre Ossman break; 11142134a922SPierre Ossman } 1115a0eaf0f9SRussell King if (sg->offset & offset_mask) { 11162e4456f0SMarek Vasut DBG("Reverting to PIO because of bad alignment\n"); 1117c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 11182134a922SPierre Ossman break; 11192134a922SPierre Ossman } 11202134a922SPierre Ossman } 11212134a922SPierre Ossman } 11222134a922SPierre Ossman } 11232134a922SPierre Ossman 11248f1934ceSPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 1125c0999b72SRussell King int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 11268f1934ceSPierre Ossman 112762a7f368SJiri Slaby if (sg_cnt <= 0) { 11288f1934ceSPierre Ossman /* 11298f1934ceSPierre Ossman * This only happens when someone fed 11308f1934ceSPierre Ossman * us an invalid request. 11318f1934ceSPierre Ossman */ 11328f1934ceSPierre Ossman WARN_ON(1); 1133ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 113460c64762SRussell King } else if (host->flags & SDHCI_USE_ADMA) { 113560c64762SRussell King sdhci_adma_table_pre(host, data, sg_cnt); 113638eee2e8SMasahiro Yamada sdhci_set_adma_addr(host, host->adma_addr); 11378f1934ceSPierre Ossman } else { 1138719a61b4SPierre Ossman WARN_ON(sg_cnt != 1); 1139917a0c52SChunyan Zhang sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); 11408f1934ceSPierre Ossman } 11418f1934ceSPierre Ossman } 11428f1934ceSPierre Ossman 1143685e444bSChunyan Zhang sdhci_config_dma(host); 1144c9fddbc4SPierre Ossman 11458f1934ceSPierre Ossman if (!(host->flags & SDHCI_REQ_USE_DMA)) { 1146da60a91dSSebastian Andrzej Siewior int flags; 1147da60a91dSSebastian Andrzej Siewior 1148da60a91dSSebastian Andrzej Siewior flags = SG_MITER_ATOMIC; 1149da60a91dSSebastian Andrzej Siewior if (host->data->flags & MMC_DATA_READ) 1150da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_TO_SG; 1151da60a91dSSebastian Andrzej Siewior else 1152da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_FROM_SG; 1153da60a91dSSebastian Andrzej Siewior sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 11547659150cSPierre Ossman host->blocks = data->blocks; 11551c6a0718SPierre Ossman } 11561c6a0718SPierre Ossman 11576aa943abSAnton Vorontsov sdhci_set_transfer_irqs(host); 11586aa943abSAnton Vorontsov 115915db1836SFaiz Abbas sdhci_set_block_info(host, data); 1160e65953d4SChunyan Zhang } 11611c6a0718SPierre Ossman 116218e762e3SChunyan Zhang #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) 116318e762e3SChunyan Zhang 116418e762e3SChunyan Zhang static int sdhci_external_dma_init(struct sdhci_host *host) 116518e762e3SChunyan Zhang { 116618e762e3SChunyan Zhang int ret = 0; 116718e762e3SChunyan Zhang struct mmc_host *mmc = host->mmc; 116818e762e3SChunyan Zhang 116918e762e3SChunyan Zhang host->tx_chan = dma_request_chan(mmc->parent, "tx"); 117018e762e3SChunyan Zhang if (IS_ERR(host->tx_chan)) { 117118e762e3SChunyan Zhang ret = PTR_ERR(host->tx_chan); 117218e762e3SChunyan Zhang if (ret != -EPROBE_DEFER) 117318e762e3SChunyan Zhang pr_warn("Failed to request TX DMA channel.\n"); 117418e762e3SChunyan Zhang host->tx_chan = NULL; 117518e762e3SChunyan Zhang return ret; 117618e762e3SChunyan Zhang } 117718e762e3SChunyan Zhang 117818e762e3SChunyan Zhang host->rx_chan = dma_request_chan(mmc->parent, "rx"); 117918e762e3SChunyan Zhang if (IS_ERR(host->rx_chan)) { 118018e762e3SChunyan Zhang if (host->tx_chan) { 118118e762e3SChunyan Zhang dma_release_channel(host->tx_chan); 118218e762e3SChunyan Zhang host->tx_chan = NULL; 118318e762e3SChunyan Zhang } 118418e762e3SChunyan Zhang 118518e762e3SChunyan Zhang ret = PTR_ERR(host->rx_chan); 118618e762e3SChunyan Zhang if (ret != -EPROBE_DEFER) 118718e762e3SChunyan Zhang pr_warn("Failed to request RX DMA channel.\n"); 118818e762e3SChunyan Zhang host->rx_chan = NULL; 118918e762e3SChunyan Zhang } 119018e762e3SChunyan Zhang 119118e762e3SChunyan Zhang return ret; 119218e762e3SChunyan Zhang } 119318e762e3SChunyan Zhang 119418e762e3SChunyan Zhang static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, 119518e762e3SChunyan Zhang struct mmc_data *data) 119618e762e3SChunyan Zhang { 119718e762e3SChunyan Zhang return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 119818e762e3SChunyan Zhang } 119918e762e3SChunyan Zhang 120018e762e3SChunyan Zhang static int sdhci_external_dma_setup(struct sdhci_host *host, 120118e762e3SChunyan Zhang struct mmc_command *cmd) 120218e762e3SChunyan Zhang { 120318e762e3SChunyan Zhang int ret, i; 12041215c025SChunyan Zhang enum dma_transfer_direction dir; 120518e762e3SChunyan Zhang struct dma_async_tx_descriptor *desc; 120618e762e3SChunyan Zhang struct mmc_data *data = cmd->data; 120718e762e3SChunyan Zhang struct dma_chan *chan; 120818e762e3SChunyan Zhang struct dma_slave_config cfg; 120918e762e3SChunyan Zhang dma_cookie_t cookie; 121018e762e3SChunyan Zhang int sg_cnt; 121118e762e3SChunyan Zhang 121218e762e3SChunyan Zhang if (!host->mapbase) 121318e762e3SChunyan Zhang return -EINVAL; 121418e762e3SChunyan Zhang 121518e762e3SChunyan Zhang cfg.src_addr = host->mapbase + SDHCI_BUFFER; 121618e762e3SChunyan Zhang cfg.dst_addr = host->mapbase + SDHCI_BUFFER; 121718e762e3SChunyan Zhang cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 121818e762e3SChunyan Zhang cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 121918e762e3SChunyan Zhang cfg.src_maxburst = data->blksz / 4; 122018e762e3SChunyan Zhang cfg.dst_maxburst = data->blksz / 4; 122118e762e3SChunyan Zhang 122218e762e3SChunyan Zhang /* Sanity check: all the SG entries must be aligned by block size. */ 122318e762e3SChunyan Zhang for (i = 0; i < data->sg_len; i++) { 122418e762e3SChunyan Zhang if ((data->sg + i)->length % data->blksz) 122518e762e3SChunyan Zhang return -EINVAL; 122618e762e3SChunyan Zhang } 122718e762e3SChunyan Zhang 122818e762e3SChunyan Zhang chan = sdhci_external_dma_channel(host, data); 122918e762e3SChunyan Zhang 123018e762e3SChunyan Zhang ret = dmaengine_slave_config(chan, &cfg); 123118e762e3SChunyan Zhang if (ret) 123218e762e3SChunyan Zhang return ret; 123318e762e3SChunyan Zhang 123418e762e3SChunyan Zhang sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 123518e762e3SChunyan Zhang if (sg_cnt <= 0) 123618e762e3SChunyan Zhang return -EINVAL; 123718e762e3SChunyan Zhang 12381215c025SChunyan Zhang dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 12391215c025SChunyan Zhang desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir, 124018e762e3SChunyan Zhang DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 124118e762e3SChunyan Zhang if (!desc) 124218e762e3SChunyan Zhang return -EINVAL; 124318e762e3SChunyan Zhang 124418e762e3SChunyan Zhang desc->callback = NULL; 124518e762e3SChunyan Zhang desc->callback_param = NULL; 124618e762e3SChunyan Zhang 124718e762e3SChunyan Zhang cookie = dmaengine_submit(desc); 124818e762e3SChunyan Zhang if (dma_submit_error(cookie)) 124918e762e3SChunyan Zhang ret = cookie; 125018e762e3SChunyan Zhang 125118e762e3SChunyan Zhang return ret; 125218e762e3SChunyan Zhang } 125318e762e3SChunyan Zhang 125418e762e3SChunyan Zhang static void sdhci_external_dma_release(struct sdhci_host *host) 125518e762e3SChunyan Zhang { 125618e762e3SChunyan Zhang if (host->tx_chan) { 125718e762e3SChunyan Zhang dma_release_channel(host->tx_chan); 125818e762e3SChunyan Zhang host->tx_chan = NULL; 125918e762e3SChunyan Zhang } 126018e762e3SChunyan Zhang 126118e762e3SChunyan Zhang if (host->rx_chan) { 126218e762e3SChunyan Zhang dma_release_channel(host->rx_chan); 126318e762e3SChunyan Zhang host->rx_chan = NULL; 126418e762e3SChunyan Zhang } 126518e762e3SChunyan Zhang 126618e762e3SChunyan Zhang sdhci_switch_external_dma(host, false); 126718e762e3SChunyan Zhang } 126818e762e3SChunyan Zhang 126918e762e3SChunyan Zhang static void __sdhci_external_dma_prepare_data(struct sdhci_host *host, 127018e762e3SChunyan Zhang struct mmc_command *cmd) 127118e762e3SChunyan Zhang { 127218e762e3SChunyan Zhang struct mmc_data *data = cmd->data; 127318e762e3SChunyan Zhang 127418e762e3SChunyan Zhang sdhci_initialize_data(host, data); 127518e762e3SChunyan Zhang 127618e762e3SChunyan Zhang host->flags |= SDHCI_REQ_USE_DMA; 127718e762e3SChunyan Zhang sdhci_set_transfer_irqs(host); 127818e762e3SChunyan Zhang 127918e762e3SChunyan Zhang sdhci_set_block_info(host, data); 128018e762e3SChunyan Zhang } 128118e762e3SChunyan Zhang 128218e762e3SChunyan Zhang static void sdhci_external_dma_prepare_data(struct sdhci_host *host, 128318e762e3SChunyan Zhang struct mmc_command *cmd) 128418e762e3SChunyan Zhang { 128518e762e3SChunyan Zhang if (!sdhci_external_dma_setup(host, cmd)) { 128618e762e3SChunyan Zhang __sdhci_external_dma_prepare_data(host, cmd); 128718e762e3SChunyan Zhang } else { 128818e762e3SChunyan Zhang sdhci_external_dma_release(host); 128918e762e3SChunyan Zhang pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n", 129018e762e3SChunyan Zhang mmc_hostname(host->mmc)); 129118e762e3SChunyan Zhang sdhci_prepare_data(host, cmd); 129218e762e3SChunyan Zhang } 129318e762e3SChunyan Zhang } 129418e762e3SChunyan Zhang 129518e762e3SChunyan Zhang static void sdhci_external_dma_pre_transfer(struct sdhci_host *host, 129618e762e3SChunyan Zhang struct mmc_command *cmd) 129718e762e3SChunyan Zhang { 129818e762e3SChunyan Zhang struct dma_chan *chan; 129918e762e3SChunyan Zhang 130018e762e3SChunyan Zhang if (!cmd->data) 130118e762e3SChunyan Zhang return; 130218e762e3SChunyan Zhang 130318e762e3SChunyan Zhang chan = sdhci_external_dma_channel(host, cmd->data); 130418e762e3SChunyan Zhang if (chan) 130518e762e3SChunyan Zhang dma_async_issue_pending(chan); 130618e762e3SChunyan Zhang } 130718e762e3SChunyan Zhang 130818e762e3SChunyan Zhang #else 130918e762e3SChunyan Zhang 131018e762e3SChunyan Zhang static inline int sdhci_external_dma_init(struct sdhci_host *host) 131118e762e3SChunyan Zhang { 131218e762e3SChunyan Zhang return -EOPNOTSUPP; 131318e762e3SChunyan Zhang } 131418e762e3SChunyan Zhang 131518e762e3SChunyan Zhang static inline void sdhci_external_dma_release(struct sdhci_host *host) 131618e762e3SChunyan Zhang { 131718e762e3SChunyan Zhang } 131818e762e3SChunyan Zhang 131918e762e3SChunyan Zhang static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host, 132018e762e3SChunyan Zhang struct mmc_command *cmd) 132118e762e3SChunyan Zhang { 132218e762e3SChunyan Zhang /* This should never happen */ 132318e762e3SChunyan Zhang WARN_ON_ONCE(1); 132418e762e3SChunyan Zhang } 132518e762e3SChunyan Zhang 132618e762e3SChunyan Zhang static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host, 132718e762e3SChunyan Zhang struct mmc_command *cmd) 132818e762e3SChunyan Zhang { 132918e762e3SChunyan Zhang } 133018e762e3SChunyan Zhang 133118e762e3SChunyan Zhang static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, 133218e762e3SChunyan Zhang struct mmc_data *data) 133318e762e3SChunyan Zhang { 133418e762e3SChunyan Zhang return NULL; 133518e762e3SChunyan Zhang } 133618e762e3SChunyan Zhang 133718e762e3SChunyan Zhang #endif 133818e762e3SChunyan Zhang 133918e762e3SChunyan Zhang void sdhci_switch_external_dma(struct sdhci_host *host, bool en) 134018e762e3SChunyan Zhang { 134118e762e3SChunyan Zhang host->use_external_dma = en; 134218e762e3SChunyan Zhang } 134318e762e3SChunyan Zhang EXPORT_SYMBOL_GPL(sdhci_switch_external_dma); 134418e762e3SChunyan Zhang 13450293d501SAdrian Hunter static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 13460293d501SAdrian Hunter struct mmc_request *mrq) 13470293d501SAdrian Hunter { 134820845befSAdrian Hunter return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 134920845befSAdrian Hunter !mrq->cap_cmd_during_tfr; 13500293d501SAdrian Hunter } 13510293d501SAdrian Hunter 1352427b6514SChunyan Zhang static inline void sdhci_auto_cmd_select(struct sdhci_host *host, 1353427b6514SChunyan Zhang struct mmc_command *cmd, 1354427b6514SChunyan Zhang u16 *mode) 1355427b6514SChunyan Zhang { 1356427b6514SChunyan Zhang bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && 1357427b6514SChunyan Zhang (cmd->opcode != SD_IO_RW_EXTENDED); 1358427b6514SChunyan Zhang bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); 1359427b6514SChunyan Zhang u16 ctrl2; 1360427b6514SChunyan Zhang 1361427b6514SChunyan Zhang /* 1362427b6514SChunyan Zhang * In case of Version 4.10 or later, use of 'Auto CMD Auto 1363427b6514SChunyan Zhang * Select' is recommended rather than use of 'Auto CMD12 1364427b6514SChunyan Zhang * Enable' or 'Auto CMD23 Enable'. 1365427b6514SChunyan Zhang */ 1366427b6514SChunyan Zhang if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { 1367427b6514SChunyan Zhang *mode |= SDHCI_TRNS_AUTO_SEL; 1368427b6514SChunyan Zhang 1369427b6514SChunyan Zhang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1370427b6514SChunyan Zhang if (use_cmd23) 1371427b6514SChunyan Zhang ctrl2 |= SDHCI_CMD23_ENABLE; 1372427b6514SChunyan Zhang else 1373427b6514SChunyan Zhang ctrl2 &= ~SDHCI_CMD23_ENABLE; 1374427b6514SChunyan Zhang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 1375427b6514SChunyan Zhang 1376427b6514SChunyan Zhang return; 1377427b6514SChunyan Zhang } 1378427b6514SChunyan Zhang 1379427b6514SChunyan Zhang /* 1380427b6514SChunyan Zhang * If we are sending CMD23, CMD12 never gets sent 1381427b6514SChunyan Zhang * on successful completion (so no Auto-CMD12). 1382427b6514SChunyan Zhang */ 1383427b6514SChunyan Zhang if (use_cmd12) 1384427b6514SChunyan Zhang *mode |= SDHCI_TRNS_AUTO_CMD12; 1385427b6514SChunyan Zhang else if (use_cmd23) 1386427b6514SChunyan Zhang *mode |= SDHCI_TRNS_AUTO_CMD23; 1387427b6514SChunyan Zhang } 1388427b6514SChunyan Zhang 13891c6a0718SPierre Ossman static void sdhci_set_transfer_mode(struct sdhci_host *host, 1390e89d456fSAndrei Warkentin struct mmc_command *cmd) 13911c6a0718SPierre Ossman { 1392d3fc5d71SVincent Yang u16 mode = 0; 1393e89d456fSAndrei Warkentin struct mmc_data *data = cmd->data; 13941c6a0718SPierre Ossman 13952b558c13SDong Aisheng if (data == NULL) { 13969b8ffea6SVincent Wan if (host->quirks2 & 13979b8ffea6SVincent Wan SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 13980086fc21Sernest.zhang /* must not clear SDHCI_TRANSFER_MODE when tuning */ 13990086fc21Sernest.zhang if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 14009b8ffea6SVincent Wan sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 14019b8ffea6SVincent Wan } else { 14022b558c13SDong Aisheng /* clear Auto CMD settings for no data CMDs */ 14032b558c13SDong Aisheng mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 14042b558c13SDong Aisheng sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 14052b558c13SDong Aisheng SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 14069b8ffea6SVincent Wan } 14071c6a0718SPierre Ossman return; 14082b558c13SDong Aisheng } 14091c6a0718SPierre Ossman 1410e538fbe8SPierre Ossman WARN_ON(!host->data); 1411e538fbe8SPierre Ossman 1412d3fc5d71SVincent Yang if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 14131c6a0718SPierre Ossman mode = SDHCI_TRNS_BLK_CNT_EN; 1414d3fc5d71SVincent Yang 1415e89d456fSAndrei Warkentin if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 1416d3fc5d71SVincent Yang mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 1417427b6514SChunyan Zhang sdhci_auto_cmd_select(host, cmd, &mode); 1418427b6514SChunyan Zhang if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) 1419a4c73abaSAdrian Hunter sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 1420c4512f79SJerry Huang } 14218edf6371SAndrei Warkentin 14221c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 14231c6a0718SPierre Ossman mode |= SDHCI_TRNS_READ; 1424c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) 14251c6a0718SPierre Ossman mode |= SDHCI_TRNS_DMA; 14261c6a0718SPierre Ossman 14274e4141a5SAnton Vorontsov sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 14281c6a0718SPierre Ossman } 14291c6a0718SPierre Ossman 14300cc563ceSAdrian Hunter static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 14310cc563ceSAdrian Hunter { 14320cc563ceSAdrian Hunter return (!(host->flags & SDHCI_DEVICE_DEAD) && 14330cc563ceSAdrian Hunter ((mrq->cmd && mrq->cmd->error) || 14340cc563ceSAdrian Hunter (mrq->sbc && mrq->sbc->error) || 14354bf78099SAdrian Hunter (mrq->data && mrq->data->stop && mrq->data->stop->error) || 14360cc563ceSAdrian Hunter (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 14370cc563ceSAdrian Hunter } 14380cc563ceSAdrian Hunter 143915db1836SFaiz Abbas static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) 14404e9f8fe5SAdrian Hunter { 14414e9f8fe5SAdrian Hunter int i; 14424e9f8fe5SAdrian Hunter 14434e9f8fe5SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 14444e9f8fe5SAdrian Hunter if (host->mrqs_done[i] == mrq) { 14454e9f8fe5SAdrian Hunter WARN_ON(1); 14464e9f8fe5SAdrian Hunter return; 14474e9f8fe5SAdrian Hunter } 14484e9f8fe5SAdrian Hunter } 14494e9f8fe5SAdrian Hunter 14504e9f8fe5SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 14514e9f8fe5SAdrian Hunter if (!host->mrqs_done[i]) { 14524e9f8fe5SAdrian Hunter host->mrqs_done[i] = mrq; 14534e9f8fe5SAdrian Hunter break; 14544e9f8fe5SAdrian Hunter } 14554e9f8fe5SAdrian Hunter } 14564e9f8fe5SAdrian Hunter 14574e9f8fe5SAdrian Hunter WARN_ON(i >= SDHCI_MAX_MRQS); 145815db1836SFaiz Abbas } 145915db1836SFaiz Abbas 146015db1836SFaiz Abbas static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 146115db1836SFaiz Abbas { 146215db1836SFaiz Abbas if (host->cmd && host->cmd->mrq == mrq) 146315db1836SFaiz Abbas host->cmd = NULL; 146415db1836SFaiz Abbas 146515db1836SFaiz Abbas if (host->data_cmd && host->data_cmd->mrq == mrq) 146615db1836SFaiz Abbas host->data_cmd = NULL; 146715db1836SFaiz Abbas 146815db1836SFaiz Abbas if (host->data && host->data->mrq == mrq) 146915db1836SFaiz Abbas host->data = NULL; 147015db1836SFaiz Abbas 147115db1836SFaiz Abbas if (sdhci_needs_reset(host, mrq)) 147215db1836SFaiz Abbas host->pending_reset = true; 147315db1836SFaiz Abbas 147415db1836SFaiz Abbas sdhci_set_mrq_done(host, mrq); 14754e9f8fe5SAdrian Hunter 1476e9a07299SAdrian Hunter sdhci_del_timer(host, mrq); 1477e9a07299SAdrian Hunter 1478e9a07299SAdrian Hunter if (!sdhci_has_requests(host)) 1479e9a07299SAdrian Hunter sdhci_led_deactivate(host); 14804e9f8fe5SAdrian Hunter } 14814e9f8fe5SAdrian Hunter 1482a6d3bdd5SAdrian Hunter static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 1483a6d3bdd5SAdrian Hunter { 14844e9f8fe5SAdrian Hunter __sdhci_finish_mrq(host, mrq); 14852e72ab9bSAdrian Hunter 1486c07a48c2SAdrian Hunter queue_work(host->complete_wq, &host->complete_work); 1487a6d3bdd5SAdrian Hunter } 1488a6d3bdd5SAdrian Hunter 14891c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *host) 14901c6a0718SPierre Ossman { 149133a57adbSAdrian Hunter struct mmc_command *data_cmd = host->data_cmd; 149233a57adbSAdrian Hunter struct mmc_data *data = host->data; 14931c6a0718SPierre Ossman 14941c6a0718SPierre Ossman host->data = NULL; 14957c89a3d9SAdrian Hunter host->data_cmd = NULL; 14961c6a0718SPierre Ossman 14974bf78099SAdrian Hunter /* 14984bf78099SAdrian Hunter * The controller needs a reset of internal state machines upon error 14994bf78099SAdrian Hunter * conditions. 15004bf78099SAdrian Hunter */ 15014bf78099SAdrian Hunter if (data->error) { 15024bf78099SAdrian Hunter if (!host->cmd || host->cmd == data_cmd) 15034bf78099SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD); 15044bf78099SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_DATA); 15054bf78099SAdrian Hunter } 15064bf78099SAdrian Hunter 1507add8913dSRussell King if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1508add8913dSRussell King (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 15092134a922SPierre Ossman sdhci_adma_table_post(host, data); 1510f55c98f7SRussell King 15111c6a0718SPierre Ossman /* 1512c9b74c5bSPierre Ossman * The specification states that the block count register must 1513c9b74c5bSPierre Ossman * be updated, but it does not specify at what point in the 1514c9b74c5bSPierre Ossman * data flow. That makes the register entirely useless to read 1515c9b74c5bSPierre Ossman * back so we have to assume that nothing made it to the card 1516c9b74c5bSPierre Ossman * in the event of an error. 15171c6a0718SPierre Ossman */ 1518c9b74c5bSPierre Ossman if (data->error) 1519c9b74c5bSPierre Ossman data->bytes_xfered = 0; 15201c6a0718SPierre Ossman else 1521c9b74c5bSPierre Ossman data->bytes_xfered = data->blksz * data->blocks; 15221c6a0718SPierre Ossman 1523e89d456fSAndrei Warkentin /* 1524e89d456fSAndrei Warkentin * Need to send CMD12 if - 1525fdbbe6cfSYangbo Lu * a) open-ended multiblock transfer not using auto CMD12 (no CMD23) 1526e89d456fSAndrei Warkentin * b) error in multiblock transfer 1527e89d456fSAndrei Warkentin */ 1528e89d456fSAndrei Warkentin if (data->stop && 1529fdbbe6cfSYangbo Lu ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) || 1530fdbbe6cfSYangbo Lu data->error)) { 153120845befSAdrian Hunter /* 153220845befSAdrian Hunter * 'cap_cmd_during_tfr' request must not use the command line 153320845befSAdrian Hunter * after mmc_command_done() has been called. It is upper layer's 153420845befSAdrian Hunter * responsibility to send the stop command if required. 153520845befSAdrian Hunter */ 153620845befSAdrian Hunter if (data->mrq->cap_cmd_during_tfr) { 153719d2f695SAdrian Hunter __sdhci_finish_mrq(host, data->mrq); 153820845befSAdrian Hunter } else { 15398842fd17SAdrian Hunter /* Avoid triggering warning in sdhci_send_command() */ 15408842fd17SAdrian Hunter host->cmd = NULL; 15411c6a0718SPierre Ossman sdhci_send_command(host, data->stop); 154220845befSAdrian Hunter } 1543a6d3bdd5SAdrian Hunter } else { 154419d2f695SAdrian Hunter __sdhci_finish_mrq(host, data->mrq); 1545a6d3bdd5SAdrian Hunter } 15461c6a0718SPierre Ossman } 15471c6a0718SPierre Ossman 1548c0e55129SDong Aisheng void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 15491c6a0718SPierre Ossman { 15501c6a0718SPierre Ossman int flags; 15511c6a0718SPierre Ossman u32 mask; 15521c6a0718SPierre Ossman unsigned long timeout; 15531c6a0718SPierre Ossman 15541c6a0718SPierre Ossman WARN_ON(host->cmd); 15551c6a0718SPierre Ossman 155696776200SRussell King /* Initially, a command has no error */ 155796776200SRussell King cmd->error = 0; 155896776200SRussell King 1559fc605f1dSAdrian Hunter if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 1560fc605f1dSAdrian Hunter cmd->opcode == MMC_STOP_TRANSMISSION) 1561fc605f1dSAdrian Hunter cmd->flags |= MMC_RSP_BUSY; 1562fc605f1dSAdrian Hunter 15631c6a0718SPierre Ossman /* Wait max 10 ms */ 15641c6a0718SPierre Ossman timeout = 10; 15651c6a0718SPierre Ossman 15661c6a0718SPierre Ossman mask = SDHCI_CMD_INHIBIT; 156756a590dcSAdrian Hunter if (sdhci_data_line_cmd(cmd)) 15681c6a0718SPierre Ossman mask |= SDHCI_DATA_INHIBIT; 15691c6a0718SPierre Ossman 15701c6a0718SPierre Ossman /* We shouldn't wait for data inihibit for stop commands, even 15711c6a0718SPierre Ossman though they might use busy signaling */ 1572a4c73abaSAdrian Hunter if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 15731c6a0718SPierre Ossman mask &= ~SDHCI_DATA_INHIBIT; 15741c6a0718SPierre Ossman 15754e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 15761c6a0718SPierre Ossman if (timeout == 0) { 15772e4456f0SMarek Vasut pr_err("%s: Controller never released inhibit bit(s).\n", 15782e4456f0SMarek Vasut mmc_hostname(host->mmc)); 15791c6a0718SPierre Ossman sdhci_dumpregs(host); 158017b0429dSPierre Ossman cmd->error = -EIO; 1581a6d3bdd5SAdrian Hunter sdhci_finish_mrq(host, cmd->mrq); 15821c6a0718SPierre Ossman return; 15831c6a0718SPierre Ossman } 15841c6a0718SPierre Ossman timeout--; 15851c6a0718SPierre Ossman mdelay(1); 15861c6a0718SPierre Ossman } 15871c6a0718SPierre Ossman 15881c6a0718SPierre Ossman host->cmd = cmd; 158915db1836SFaiz Abbas host->data_timeout = 0; 159056a590dcSAdrian Hunter if (sdhci_data_line_cmd(cmd)) { 15917c89a3d9SAdrian Hunter WARN_ON(host->data_cmd); 15927c89a3d9SAdrian Hunter host->data_cmd = cmd; 159315db1836SFaiz Abbas sdhci_set_timeout(host, cmd); 15947c89a3d9SAdrian Hunter } 15951c6a0718SPierre Ossman 159618e762e3SChunyan Zhang if (cmd->data) { 159718e762e3SChunyan Zhang if (host->use_external_dma) 159818e762e3SChunyan Zhang sdhci_external_dma_prepare_data(host, cmd); 159918e762e3SChunyan Zhang else 1600a3c7778fSAndrei Warkentin sdhci_prepare_data(host, cmd); 160118e762e3SChunyan Zhang } 16021c6a0718SPierre Ossman 16034e4141a5SAnton Vorontsov sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 16041c6a0718SPierre Ossman 1605e89d456fSAndrei Warkentin sdhci_set_transfer_mode(host, cmd); 16061c6a0718SPierre Ossman 16071c6a0718SPierre Ossman if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1608a3c76eb9SGirish K S pr_err("%s: Unsupported response type!\n", 16091c6a0718SPierre Ossman mmc_hostname(host->mmc)); 161017b0429dSPierre Ossman cmd->error = -EINVAL; 1611a6d3bdd5SAdrian Hunter sdhci_finish_mrq(host, cmd->mrq); 16121c6a0718SPierre Ossman return; 16131c6a0718SPierre Ossman } 16141c6a0718SPierre Ossman 16151c6a0718SPierre Ossman if (!(cmd->flags & MMC_RSP_PRESENT)) 16161c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_NONE; 16171c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_136) 16181c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_LONG; 16191c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_BUSY) 16201c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT_BUSY; 16211c6a0718SPierre Ossman else 16221c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT; 16231c6a0718SPierre Ossman 16241c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_CRC) 16251c6a0718SPierre Ossman flags |= SDHCI_CMD_CRC; 16261c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_OPCODE) 16271c6a0718SPierre Ossman flags |= SDHCI_CMD_INDEX; 1628b513ea25SArindam Nath 1629b513ea25SArindam Nath /* CMD19 is special in that the Data Present Select should be set */ 1630069c9f14SGirish K S if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1631069c9f14SGirish K S cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 16321c6a0718SPierre Ossman flags |= SDHCI_CMD_DATA; 16331c6a0718SPierre Ossman 1634fc1fa1b7SKishon Vijay Abraham I timeout = jiffies; 1635fc1fa1b7SKishon Vijay Abraham I if (host->data_timeout) 1636fc1fa1b7SKishon Vijay Abraham I timeout += nsecs_to_jiffies(host->data_timeout); 1637fc1fa1b7SKishon Vijay Abraham I else if (!cmd->data && cmd->busy_timeout > 9000) 1638fc1fa1b7SKishon Vijay Abraham I timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1639fc1fa1b7SKishon Vijay Abraham I else 1640fc1fa1b7SKishon Vijay Abraham I timeout += 10 * HZ; 1641fc1fa1b7SKishon Vijay Abraham I sdhci_mod_timer(host, cmd->mrq, timeout); 1642fc1fa1b7SKishon Vijay Abraham I 164318e762e3SChunyan Zhang if (host->use_external_dma) 164418e762e3SChunyan Zhang sdhci_external_dma_pre_transfer(host, cmd); 164518e762e3SChunyan Zhang 16464e4141a5SAnton Vorontsov sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 16471c6a0718SPierre Ossman } 1648c0e55129SDong Aisheng EXPORT_SYMBOL_GPL(sdhci_send_command); 16491c6a0718SPierre Ossman 16504a5fc119SAdrian Hunter static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd) 16514a5fc119SAdrian Hunter { 16524a5fc119SAdrian Hunter int i, reg; 16534a5fc119SAdrian Hunter 16544a5fc119SAdrian Hunter for (i = 0; i < 4; i++) { 16554a5fc119SAdrian Hunter reg = SDHCI_RESPONSE + (3 - i) * 4; 16564a5fc119SAdrian Hunter cmd->resp[i] = sdhci_readl(host, reg); 16574a5fc119SAdrian Hunter } 16584a5fc119SAdrian Hunter 16591284c248SKishon Vijay Abraham I if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC) 16601284c248SKishon Vijay Abraham I return; 16611284c248SKishon Vijay Abraham I 16624a5fc119SAdrian Hunter /* CRC is stripped so we need to do some shifting */ 16634a5fc119SAdrian Hunter for (i = 0; i < 4; i++) { 16644a5fc119SAdrian Hunter cmd->resp[i] <<= 8; 16654a5fc119SAdrian Hunter if (i != 3) 16664a5fc119SAdrian Hunter cmd->resp[i] |= cmd->resp[i + 1] >> 24; 16674a5fc119SAdrian Hunter } 16684a5fc119SAdrian Hunter } 16694a5fc119SAdrian Hunter 16701c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *host) 16711c6a0718SPierre Ossman { 1672e0a5640aSAdrian Hunter struct mmc_command *cmd = host->cmd; 16731c6a0718SPierre Ossman 1674e0a5640aSAdrian Hunter host->cmd = NULL; 1675e0a5640aSAdrian Hunter 1676e0a5640aSAdrian Hunter if (cmd->flags & MMC_RSP_PRESENT) { 1677e0a5640aSAdrian Hunter if (cmd->flags & MMC_RSP_136) { 16784a5fc119SAdrian Hunter sdhci_read_rsp_136(host, cmd); 16791c6a0718SPierre Ossman } else { 1680e0a5640aSAdrian Hunter cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 16811c6a0718SPierre Ossman } 16821c6a0718SPierre Ossman } 16831c6a0718SPierre Ossman 168420845befSAdrian Hunter if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 168520845befSAdrian Hunter mmc_command_done(host->mmc, cmd->mrq); 168620845befSAdrian Hunter 16876bde8681SAdrian Hunter /* 16886bde8681SAdrian Hunter * The host can send and interrupt when the busy state has 16896bde8681SAdrian Hunter * ended, allowing us to wait without wasting CPU cycles. 16906bde8681SAdrian Hunter * The busy signal uses DAT0 so this is similar to waiting 16916bde8681SAdrian Hunter * for data to complete. 16926bde8681SAdrian Hunter * 16936bde8681SAdrian Hunter * Note: The 1.0 specification is a bit ambiguous about this 16946bde8681SAdrian Hunter * feature so there might be some problems with older 16956bde8681SAdrian Hunter * controllers. 16966bde8681SAdrian Hunter */ 1697e0a5640aSAdrian Hunter if (cmd->flags & MMC_RSP_BUSY) { 1698e0a5640aSAdrian Hunter if (cmd->data) { 16996bde8681SAdrian Hunter DBG("Cannot wait for busy signal when also doing a data transfer"); 17006bde8681SAdrian Hunter } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1701ea968023SAdrian Hunter cmd == host->data_cmd) { 1702ea968023SAdrian Hunter /* Command complete before busy is ended */ 17036bde8681SAdrian Hunter return; 17046bde8681SAdrian Hunter } 17056bde8681SAdrian Hunter } 17066bde8681SAdrian Hunter 1707e89d456fSAndrei Warkentin /* Finished CMD23, now send actual command. */ 1708a4c73abaSAdrian Hunter if (cmd == cmd->mrq->sbc) { 1709a4c73abaSAdrian Hunter sdhci_send_command(host, cmd->mrq->cmd); 1710e89d456fSAndrei Warkentin } else { 1711e89d456fSAndrei Warkentin 1712e89d456fSAndrei Warkentin /* Processed actual command. */ 1713e538fbe8SPierre Ossman if (host->data && host->data_early) 1714e538fbe8SPierre Ossman sdhci_finish_data(host); 1715e538fbe8SPierre Ossman 1716e0a5640aSAdrian Hunter if (!cmd->data) 171719d2f695SAdrian Hunter __sdhci_finish_mrq(host, cmd->mrq); 17181c6a0718SPierre Ossman } 1719e89d456fSAndrei Warkentin } 17201c6a0718SPierre Ossman 172152983382SKevin Liu static u16 sdhci_get_preset_value(struct sdhci_host *host) 172252983382SKevin Liu { 1723d975f121SRussell King u16 preset = 0; 172452983382SKevin Liu 1725d975f121SRussell King switch (host->timing) { 1726d975f121SRussell King case MMC_TIMING_UHS_SDR12: 172752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 172852983382SKevin Liu break; 1729d975f121SRussell King case MMC_TIMING_UHS_SDR25: 173052983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 173152983382SKevin Liu break; 1732d975f121SRussell King case MMC_TIMING_UHS_SDR50: 173352983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 173452983382SKevin Liu break; 1735d975f121SRussell King case MMC_TIMING_UHS_SDR104: 1736d975f121SRussell King case MMC_TIMING_MMC_HS200: 173752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 173852983382SKevin Liu break; 1739d975f121SRussell King case MMC_TIMING_UHS_DDR50: 17400dafa60eSJisheng Zhang case MMC_TIMING_MMC_DDR52: 174152983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 174252983382SKevin Liu break; 1743e9fb05d5SAdrian Hunter case MMC_TIMING_MMC_HS400: 1744e9fb05d5SAdrian Hunter preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1745e9fb05d5SAdrian Hunter break; 174652983382SKevin Liu default: 174752983382SKevin Liu pr_warn("%s: Invalid UHS-I mode selected\n", 174852983382SKevin Liu mmc_hostname(host->mmc)); 174952983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 175052983382SKevin Liu break; 175152983382SKevin Liu } 175252983382SKevin Liu return preset; 175352983382SKevin Liu } 175452983382SKevin Liu 1755fb9ee047SLudovic Desroches u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1756fb9ee047SLudovic Desroches unsigned int *actual_clock) 17571c6a0718SPierre Ossman { 1758c3ed3877SArindam Nath int div = 0; /* Initialized for compiler warning */ 1759df16219fSGiuseppe CAVALLARO int real_div = div, clk_mul = 1; 1760c3ed3877SArindam Nath u16 clk = 0; 17615497159cSludovic.desroches@atmel.com bool switch_base_clk = false; 17621c6a0718SPierre Ossman 176385105c53SZhangfei Gao if (host->version >= SDHCI_SPEC_300) { 1764da91a8f9SRussell King if (host->preset_enabled) { 176552983382SKevin Liu u16 pre_val; 176652983382SKevin Liu 176752983382SKevin Liu clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 176852983382SKevin Liu pre_val = sdhci_get_preset_value(host); 176952983382SKevin Liu div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 177052983382SKevin Liu >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 177152983382SKevin Liu if (host->clk_mul && 177252983382SKevin Liu (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 177352983382SKevin Liu clk = SDHCI_PROG_CLOCK_MODE; 177452983382SKevin Liu real_div = div + 1; 177552983382SKevin Liu clk_mul = host->clk_mul; 177652983382SKevin Liu } else { 177752983382SKevin Liu real_div = max_t(int, 1, div << 1); 177852983382SKevin Liu } 177952983382SKevin Liu goto clock_set; 178052983382SKevin Liu } 178152983382SKevin Liu 1782c3ed3877SArindam Nath /* 1783c3ed3877SArindam Nath * Check if the Host Controller supports Programmable Clock 1784c3ed3877SArindam Nath * Mode. 1785c3ed3877SArindam Nath */ 1786c3ed3877SArindam Nath if (host->clk_mul) { 1787c3ed3877SArindam Nath for (div = 1; div <= 1024; div++) { 178852983382SKevin Liu if ((host->max_clk * host->clk_mul / div) 178952983382SKevin Liu <= clock) 1790c3ed3877SArindam Nath break; 1791c3ed3877SArindam Nath } 17925497159cSludovic.desroches@atmel.com if ((host->max_clk * host->clk_mul / div) <= clock) { 1793c3ed3877SArindam Nath /* 1794c3ed3877SArindam Nath * Set Programmable Clock Mode in the Clock 1795c3ed3877SArindam Nath * Control register. 1796c3ed3877SArindam Nath */ 1797c3ed3877SArindam Nath clk = SDHCI_PROG_CLOCK_MODE; 1798df16219fSGiuseppe CAVALLARO real_div = div; 1799df16219fSGiuseppe CAVALLARO clk_mul = host->clk_mul; 1800c3ed3877SArindam Nath div--; 1801c3ed3877SArindam Nath } else { 18025497159cSludovic.desroches@atmel.com /* 18035497159cSludovic.desroches@atmel.com * Divisor can be too small to reach clock 18045497159cSludovic.desroches@atmel.com * speed requirement. Then use the base clock. 18055497159cSludovic.desroches@atmel.com */ 18065497159cSludovic.desroches@atmel.com switch_base_clk = true; 18075497159cSludovic.desroches@atmel.com } 18085497159cSludovic.desroches@atmel.com } 18095497159cSludovic.desroches@atmel.com 18105497159cSludovic.desroches@atmel.com if (!host->clk_mul || switch_base_clk) { 181185105c53SZhangfei Gao /* Version 3.00 divisors must be a multiple of 2. */ 181285105c53SZhangfei Gao if (host->max_clk <= clock) 181385105c53SZhangfei Gao div = 1; 181485105c53SZhangfei Gao else { 1815c3ed3877SArindam Nath for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1816c3ed3877SArindam Nath div += 2) { 181785105c53SZhangfei Gao if ((host->max_clk / div) <= clock) 181885105c53SZhangfei Gao break; 181985105c53SZhangfei Gao } 182085105c53SZhangfei Gao } 1821df16219fSGiuseppe CAVALLARO real_div = div; 1822c3ed3877SArindam Nath div >>= 1; 1823d1955c3aSSuneel Garapati if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1824d1955c3aSSuneel Garapati && !div && host->max_clk <= 25000000) 1825d1955c3aSSuneel Garapati div = 1; 1826c3ed3877SArindam Nath } 182785105c53SZhangfei Gao } else { 182885105c53SZhangfei Gao /* Version 2.00 divisors must be a power of 2. */ 18290397526dSZhangfei Gao for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 18301c6a0718SPierre Ossman if ((host->max_clk / div) <= clock) 18311c6a0718SPierre Ossman break; 18321c6a0718SPierre Ossman } 1833df16219fSGiuseppe CAVALLARO real_div = div; 18341c6a0718SPierre Ossman div >>= 1; 1835c3ed3877SArindam Nath } 18361c6a0718SPierre Ossman 183752983382SKevin Liu clock_set: 183803d6f5ffSAisheng Dong if (real_div) 1839fb9ee047SLudovic Desroches *actual_clock = (host->max_clk * clk_mul) / real_div; 1840c3ed3877SArindam Nath clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 184185105c53SZhangfei Gao clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 184285105c53SZhangfei Gao << SDHCI_DIVIDER_HI_SHIFT; 1843fb9ee047SLudovic Desroches 1844fb9ee047SLudovic Desroches return clk; 1845fb9ee047SLudovic Desroches } 1846fb9ee047SLudovic Desroches EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1847fb9ee047SLudovic Desroches 1848fec79673SRitesh Harjani void sdhci_enable_clk(struct sdhci_host *host, u16 clk) 1849fb9ee047SLudovic Desroches { 18505a436cc0SAdrian Hunter ktime_t timeout; 1851fb9ee047SLudovic Desroches 18521c6a0718SPierre Ossman clk |= SDHCI_CLOCK_INT_EN; 18534e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 18541c6a0718SPierre Ossman 18554a9e0d1aSBen Chuang /* Wait max 150 ms */ 18564a9e0d1aSBen Chuang timeout = ktime_add_ms(ktime_get(), 150); 1857b704441eSAlek Du while (1) { 1858b704441eSAlek Du bool timedout = ktime_after(ktime_get(), timeout); 1859b704441eSAlek Du 1860b704441eSAlek Du clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1861b704441eSAlek Du if (clk & SDHCI_CLOCK_INT_STABLE) 1862b704441eSAlek Du break; 1863b704441eSAlek Du if (timedout) { 18642e4456f0SMarek Vasut pr_err("%s: Internal clock never stabilised.\n", 18652e4456f0SMarek Vasut mmc_hostname(host->mmc)); 18661c6a0718SPierre Ossman sdhci_dumpregs(host); 18671c6a0718SPierre Ossman return; 18681c6a0718SPierre Ossman } 18695a436cc0SAdrian Hunter udelay(10); 18701c6a0718SPierre Ossman } 18711c6a0718SPierre Ossman 18721beabbdbSBen Chuang if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { 18731beabbdbSBen Chuang clk |= SDHCI_CLOCK_PLL_EN; 18741beabbdbSBen Chuang clk &= ~SDHCI_CLOCK_INT_STABLE; 18751beabbdbSBen Chuang sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 18761beabbdbSBen Chuang 18771beabbdbSBen Chuang /* Wait max 150 ms */ 18781beabbdbSBen Chuang timeout = ktime_add_ms(ktime_get(), 150); 18791beabbdbSBen Chuang while (1) { 18801beabbdbSBen Chuang bool timedout = ktime_after(ktime_get(), timeout); 18811beabbdbSBen Chuang 18821beabbdbSBen Chuang clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 18831beabbdbSBen Chuang if (clk & SDHCI_CLOCK_INT_STABLE) 18841beabbdbSBen Chuang break; 18851beabbdbSBen Chuang if (timedout) { 18861beabbdbSBen Chuang pr_err("%s: PLL clock never stabilised.\n", 18871beabbdbSBen Chuang mmc_hostname(host->mmc)); 18881beabbdbSBen Chuang sdhci_dumpregs(host); 18891beabbdbSBen Chuang return; 18901beabbdbSBen Chuang } 18911beabbdbSBen Chuang udelay(10); 18921beabbdbSBen Chuang } 18931beabbdbSBen Chuang } 18941beabbdbSBen Chuang 18951c6a0718SPierre Ossman clk |= SDHCI_CLOCK_CARD_EN; 18964e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 18971c6a0718SPierre Ossman } 1898fec79673SRitesh Harjani EXPORT_SYMBOL_GPL(sdhci_enable_clk); 1899fec79673SRitesh Harjani 1900fec79673SRitesh Harjani void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1901fec79673SRitesh Harjani { 1902fec79673SRitesh Harjani u16 clk; 1903fec79673SRitesh Harjani 1904fec79673SRitesh Harjani host->mmc->actual_clock = 0; 1905fec79673SRitesh Harjani 1906fec79673SRitesh Harjani sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1907fec79673SRitesh Harjani 1908fec79673SRitesh Harjani if (clock == 0) 1909fec79673SRitesh Harjani return; 1910fec79673SRitesh Harjani 1911fec79673SRitesh Harjani clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1912fec79673SRitesh Harjani sdhci_enable_clk(host, clk); 1913fec79673SRitesh Harjani } 19141771059cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_clock); 19151c6a0718SPierre Ossman 19161dceb041SAdrian Hunter static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 191724fbb3caSRussell King unsigned short vdd) 19181c6a0718SPierre Ossman { 19193a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 19201dceb041SAdrian Hunter 19211dceb041SAdrian Hunter mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 19221dceb041SAdrian Hunter 19231dceb041SAdrian Hunter if (mode != MMC_POWER_OFF) 19241dceb041SAdrian Hunter sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 19251dceb041SAdrian Hunter else 19261dceb041SAdrian Hunter sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 19271dceb041SAdrian Hunter } 19281dceb041SAdrian Hunter 1929606d3131SAdrian Hunter void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 19301dceb041SAdrian Hunter unsigned short vdd) 19311dceb041SAdrian Hunter { 19328364248aSGiuseppe Cavallaro u8 pwr = 0; 19331c6a0718SPierre Ossman 193424fbb3caSRussell King if (mode != MMC_POWER_OFF) { 193524fbb3caSRussell King switch (1 << vdd) { 1936ae628903SPierre Ossman case MMC_VDD_165_195: 19372a609abeSAndy Shevchenko /* 19382a609abeSAndy Shevchenko * Without a regulator, SDHCI does not support 2.0v 19392a609abeSAndy Shevchenko * so we only get here if the driver deliberately 19402a609abeSAndy Shevchenko * added the 2.0v range to ocr_avail. Map it to 1.8v 19412a609abeSAndy Shevchenko * for the purpose of turning on the power. 19422a609abeSAndy Shevchenko */ 19432a609abeSAndy Shevchenko case MMC_VDD_20_21: 1944ae628903SPierre Ossman pwr = SDHCI_POWER_180; 1945ae628903SPierre Ossman break; 1946ae628903SPierre Ossman case MMC_VDD_29_30: 1947ae628903SPierre Ossman case MMC_VDD_30_31: 1948ae628903SPierre Ossman pwr = SDHCI_POWER_300; 1949ae628903SPierre Ossman break; 1950ae628903SPierre Ossman case MMC_VDD_32_33: 1951ae628903SPierre Ossman case MMC_VDD_33_34: 1952ae628903SPierre Ossman pwr = SDHCI_POWER_330; 1953ae628903SPierre Ossman break; 1954ae628903SPierre Ossman default: 19559d5de93fSAdrian Hunter WARN(1, "%s: Invalid vdd %#x\n", 19569d5de93fSAdrian Hunter mmc_hostname(host->mmc), vdd); 19579d5de93fSAdrian Hunter break; 1958ae628903SPierre Ossman } 1959ae628903SPierre Ossman } 1960ae628903SPierre Ossman 1961ae628903SPierre Ossman if (host->pwr == pwr) 1962e921a8b6SRussell King return; 19631c6a0718SPierre Ossman 1964ae628903SPierre Ossman host->pwr = pwr; 1965ae628903SPierre Ossman 1966ae628903SPierre Ossman if (pwr == 0) { 19674e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1968f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1969f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 1970e921a8b6SRussell King } else { 19711c6a0718SPierre Ossman /* 19721c6a0718SPierre Ossman * Spec says that we should clear the power reg before setting 19731c6a0718SPierre Ossman * a new value. Some controllers don't seem to like this though. 19741c6a0718SPierre Ossman */ 1975b8c86fc5SPierre Ossman if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 19764e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 19771c6a0718SPierre Ossman 1978e08c1694SAndres Salomon /* 1979e921a8b6SRussell King * At least the Marvell CaFe chip gets confused if we set the 1980e921a8b6SRussell King * voltage and set turn on power at the same time, so set the 1981e921a8b6SRussell King * voltage first. 1982e08c1694SAndres Salomon */ 198311a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 19844e4141a5SAnton Vorontsov sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 19851c6a0718SPierre Ossman 1986ae628903SPierre Ossman pwr |= SDHCI_POWER_ON; 1987ae628903SPierre Ossman 1988ae628903SPierre Ossman sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1989557b0697SHarald Welte 1990f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1991f0710a55SAdrian Hunter sdhci_runtime_pm_bus_on(host); 1992f0710a55SAdrian Hunter 1993557b0697SHarald Welte /* 1994e921a8b6SRussell King * Some controllers need an extra 10ms delay of 10ms before 1995e921a8b6SRussell King * they can apply clock after applying power 1996557b0697SHarald Welte */ 199711a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1998557b0697SHarald Welte mdelay(10); 1999e921a8b6SRussell King } 2000918f4cbdSJisheng Zhang } 2001606d3131SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); 20021dceb041SAdrian Hunter 2003606d3131SAdrian Hunter void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 20041dceb041SAdrian Hunter unsigned short vdd) 20051dceb041SAdrian Hunter { 2006606d3131SAdrian Hunter if (IS_ERR(host->mmc->supply.vmmc)) 2007606d3131SAdrian Hunter sdhci_set_power_noreg(host, mode, vdd); 20081dceb041SAdrian Hunter else 2009606d3131SAdrian Hunter sdhci_set_power_reg(host, mode, vdd); 20101c6a0718SPierre Ossman } 2011606d3131SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_set_power); 20121c6a0718SPierre Ossman 20131c6a0718SPierre Ossman /*****************************************************************************\ 20141c6a0718SPierre Ossman * * 20151c6a0718SPierre Ossman * MMC callbacks * 20161c6a0718SPierre Ossman * * 20171c6a0718SPierre Ossman \*****************************************************************************/ 20181c6a0718SPierre Ossman 2019d462c1b4SAapo Vienamo void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 20201c6a0718SPierre Ossman { 20211c6a0718SPierre Ossman struct sdhci_host *host; 2022505a8680SShawn Guo int present; 20231c6a0718SPierre Ossman unsigned long flags; 20241c6a0718SPierre Ossman 20251c6a0718SPierre Ossman host = mmc_priv(mmc); 20261c6a0718SPierre Ossman 202704e079cfSScott Branden /* Firstly check card presence */ 20288d28b7a7SAdrian Hunter present = mmc->ops->get_cd(mmc); 20292836766aSKrzysztof Kozlowski 20301c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 20311c6a0718SPierre Ossman 2032061d17a6SAdrian Hunter sdhci_led_activate(host); 2033e89d456fSAndrei Warkentin 203468d1fb7eSAnton Vorontsov if (!present || host->flags & SDHCI_DEVICE_DEAD) { 2035a4c73abaSAdrian Hunter mrq->cmd->error = -ENOMEDIUM; 2036a6d3bdd5SAdrian Hunter sdhci_finish_mrq(host, mrq); 2037cf2b5eeaSArindam Nath } else { 20388edf6371SAndrei Warkentin if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 2039e89d456fSAndrei Warkentin sdhci_send_command(host, mrq->sbc); 2040e89d456fSAndrei Warkentin else 20411c6a0718SPierre Ossman sdhci_send_command(host, mrq->cmd); 2042cf2b5eeaSArindam Nath } 20431c6a0718SPierre Ossman 20441c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 20451c6a0718SPierre Ossman } 2046d462c1b4SAapo Vienamo EXPORT_SYMBOL_GPL(sdhci_request); 20471c6a0718SPierre Ossman 20482317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width) 20492317f56cSRussell King { 20502317f56cSRussell King u8 ctrl; 20512317f56cSRussell King 20522317f56cSRussell King ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 20532317f56cSRussell King if (width == MMC_BUS_WIDTH_8) { 20542317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 20552317f56cSRussell King ctrl |= SDHCI_CTRL_8BITBUS; 20562317f56cSRussell King } else { 205798f94ea6SMichał Mirosław if (host->mmc->caps & MMC_CAP_8_BIT_DATA) 20582317f56cSRussell King ctrl &= ~SDHCI_CTRL_8BITBUS; 20592317f56cSRussell King if (width == MMC_BUS_WIDTH_4) 20602317f56cSRussell King ctrl |= SDHCI_CTRL_4BITBUS; 20612317f56cSRussell King else 20622317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 20632317f56cSRussell King } 20642317f56cSRussell King sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 20652317f56cSRussell King } 20662317f56cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 20672317f56cSRussell King 206896d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 206996d7b78cSRussell King { 207096d7b78cSRussell King u16 ctrl_2; 207196d7b78cSRussell King 207296d7b78cSRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 207396d7b78cSRussell King /* Select Bus Speed Mode for host */ 207496d7b78cSRussell King ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 207596d7b78cSRussell King if ((timing == MMC_TIMING_MMC_HS200) || 207696d7b78cSRussell King (timing == MMC_TIMING_UHS_SDR104)) 207796d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 207896d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR12) 207996d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 208007bcc411SFaiz Abbas else if (timing == MMC_TIMING_UHS_SDR25) 208196d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 208296d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR50) 208396d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 208496d7b78cSRussell King else if ((timing == MMC_TIMING_UHS_DDR50) || 208596d7b78cSRussell King (timing == MMC_TIMING_MMC_DDR52)) 208696d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 2087e9fb05d5SAdrian Hunter else if (timing == MMC_TIMING_MMC_HS400) 2088e9fb05d5SAdrian Hunter ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 208996d7b78cSRussell King sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 209096d7b78cSRussell King } 209196d7b78cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 209296d7b78cSRussell King 20936a6d4cebSHu Ziji void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 20941c6a0718SPierre Ossman { 2095ded97e0bSDong Aisheng struct sdhci_host *host = mmc_priv(mmc); 20961c6a0718SPierre Ossman u8 ctrl; 20971c6a0718SPierre Ossman 209884ec048bSAdrian Hunter if (ios->power_mode == MMC_POWER_UNDEFINED) 209984ec048bSAdrian Hunter return; 210084ec048bSAdrian Hunter 2101ceb6143bSAdrian Hunter if (host->flags & SDHCI_DEVICE_DEAD) { 21023a48edc4STim Kryger if (!IS_ERR(mmc->supply.vmmc) && 21033a48edc4STim Kryger ios->power_mode == MMC_POWER_OFF) 21044e743f1fSMarkus Mayer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2105ceb6143bSAdrian Hunter return; 2106ceb6143bSAdrian Hunter } 21071e72859eSPierre Ossman 21081c6a0718SPierre Ossman /* 21091c6a0718SPierre Ossman * Reset the chip on each power off. 21101c6a0718SPierre Ossman * Should clear out any weird states. 21111c6a0718SPierre Ossman */ 21121c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) { 21134e4141a5SAnton Vorontsov sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 21147260cf5eSAnton Vorontsov sdhci_reinit(host); 21151c6a0718SPierre Ossman } 21161c6a0718SPierre Ossman 211752983382SKevin Liu if (host->version >= SDHCI_SPEC_300 && 2118372c4634SDong Aisheng (ios->power_mode == MMC_POWER_UP) && 2119372c4634SDong Aisheng !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 212052983382SKevin Liu sdhci_enable_preset_value(host, false); 212152983382SKevin Liu 2122373073efSRussell King if (!ios->clock || ios->clock != host->clock) { 21231771059cSRussell King host->ops->set_clock(host, ios->clock); 2124373073efSRussell King host->clock = ios->clock; 212503d6f5ffSAisheng Dong 212603d6f5ffSAisheng Dong if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 212703d6f5ffSAisheng Dong host->clock) { 212803d6f5ffSAisheng Dong host->timeout_clk = host->mmc->actual_clock ? 212903d6f5ffSAisheng Dong host->mmc->actual_clock / 1000 : 213003d6f5ffSAisheng Dong host->clock / 1000; 213103d6f5ffSAisheng Dong host->mmc->max_busy_timeout = 213203d6f5ffSAisheng Dong host->ops->get_max_timeout_count ? 213303d6f5ffSAisheng Dong host->ops->get_max_timeout_count(host) : 213403d6f5ffSAisheng Dong 1 << 27; 213503d6f5ffSAisheng Dong host->mmc->max_busy_timeout /= host->timeout_clk; 213603d6f5ffSAisheng Dong } 2137373073efSRussell King } 21381c6a0718SPierre Ossman 2139606d3131SAdrian Hunter if (host->ops->set_power) 2140606d3131SAdrian Hunter host->ops->set_power(host, ios->power_mode, ios->vdd); 2141606d3131SAdrian Hunter else 2142606d3131SAdrian Hunter sdhci_set_power(host, ios->power_mode, ios->vdd); 21431c6a0718SPierre Ossman 2144643a81ffSPhilip Rakity if (host->ops->platform_send_init_74_clocks) 2145643a81ffSPhilip Rakity host->ops->platform_send_init_74_clocks(host, ios->power_mode); 2146643a81ffSPhilip Rakity 21472317f56cSRussell King host->ops->set_bus_width(host, ios->bus_width); 214815ec4461SPhilip Rakity 214915ec4461SPhilip Rakity ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 21501c6a0718SPierre Ossman 2151501639bfSyangbo lu if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) { 2152501639bfSyangbo lu if (ios->timing == MMC_TIMING_SD_HS || 2153273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_HS || 2154273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_HS400 || 2155273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_HS200 || 2156273c5414SJaehoon Chung ios->timing == MMC_TIMING_MMC_DDR52 || 2157273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_SDR50 || 2158273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_SDR104 || 2159273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_DDR50 || 2160273c5414SJaehoon Chung ios->timing == MMC_TIMING_UHS_SDR25) 21611c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_HISPD; 21621c6a0718SPierre Ossman else 21631c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_HISPD; 2164501639bfSyangbo lu } 21651c6a0718SPierre Ossman 2166d6d50a15SArindam Nath if (host->version >= SDHCI_SPEC_300) { 216749c468fcSArindam Nath u16 clk, ctrl_2; 216849c468fcSArindam Nath 2169da91a8f9SRussell King if (!host->preset_enabled) { 2170758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2171d6d50a15SArindam Nath /* 2172d6d50a15SArindam Nath * We only need to set Driver Strength if the 2173d6d50a15SArindam Nath * preset value enable is not set. 2174d6d50a15SArindam Nath */ 2175da91a8f9SRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2176d6d50a15SArindam Nath ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 2177d6d50a15SArindam Nath if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 2178d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 217943e943a0SPetri Gynther else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 218043e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 2181d6d50a15SArindam Nath else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 2182d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 218343e943a0SPetri Gynther else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 218443e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 218543e943a0SPetri Gynther else { 21862e4456f0SMarek Vasut pr_warn("%s: invalid driver type, default to driver type B\n", 21872e4456f0SMarek Vasut mmc_hostname(mmc)); 218843e943a0SPetri Gynther ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 218943e943a0SPetri Gynther } 2190d6d50a15SArindam Nath 2191d6d50a15SArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 2192758535c4SArindam Nath } else { 2193758535c4SArindam Nath /* 2194758535c4SArindam Nath * According to SDHC Spec v3.00, if the Preset Value 2195758535c4SArindam Nath * Enable in the Host Control 2 register is set, we 2196758535c4SArindam Nath * need to reset SD Clock Enable before changing High 2197758535c4SArindam Nath * Speed Enable to avoid generating clock gliches. 2198758535c4SArindam Nath */ 2199758535c4SArindam Nath 2200758535c4SArindam Nath /* Reset SD Clock Enable */ 2201758535c4SArindam Nath clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 2202758535c4SArindam Nath clk &= ~SDHCI_CLOCK_CARD_EN; 2203758535c4SArindam Nath sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 2204758535c4SArindam Nath 2205758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2206758535c4SArindam Nath 2207758535c4SArindam Nath /* Re-enable SD Clock */ 22081771059cSRussell King host->ops->set_clock(host, host->clock); 2209d6d50a15SArindam Nath } 221049c468fcSArindam Nath 22116322cdd0SPhilip Rakity /* Reset SD Clock Enable */ 22126322cdd0SPhilip Rakity clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 22136322cdd0SPhilip Rakity clk &= ~SDHCI_CLOCK_CARD_EN; 22146322cdd0SPhilip Rakity sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 22156322cdd0SPhilip Rakity 22166322cdd0SPhilip Rakity host->ops->set_uhs_signaling(host, ios->timing); 2217d975f121SRussell King host->timing = ios->timing; 221849c468fcSArindam Nath 221952983382SKevin Liu if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 222052983382SKevin Liu ((ios->timing == MMC_TIMING_UHS_SDR12) || 222152983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR25) || 222252983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR50) || 222352983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR104) || 22240dafa60eSJisheng Zhang (ios->timing == MMC_TIMING_UHS_DDR50) || 22250dafa60eSJisheng Zhang (ios->timing == MMC_TIMING_MMC_DDR52))) { 222652983382SKevin Liu u16 preset; 222752983382SKevin Liu 222852983382SKevin Liu sdhci_enable_preset_value(host, true); 222952983382SKevin Liu preset = sdhci_get_preset_value(host); 223052983382SKevin Liu ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 223152983382SKevin Liu >> SDHCI_PRESET_DRV_SHIFT; 223252983382SKevin Liu } 223352983382SKevin Liu 223449c468fcSArindam Nath /* Re-enable SD Clock */ 22351771059cSRussell King host->ops->set_clock(host, host->clock); 2236758535c4SArindam Nath } else 2237758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2238d6d50a15SArindam Nath 2239b8352260SLeandro Dorileo /* 2240b8352260SLeandro Dorileo * Some (ENE) controllers go apeshit on some ios operation, 2241b8352260SLeandro Dorileo * signalling timeout and CRC errors even on CMD0. Resetting 2242b8352260SLeandro Dorileo * it on each ios seems to solve the problem. 2243b8352260SLeandro Dorileo */ 2244b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 224503231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 22461c6a0718SPierre Ossman } 22476a6d4cebSHu Ziji EXPORT_SYMBOL_GPL(sdhci_set_ios); 22481c6a0718SPierre Ossman 2249ded97e0bSDong Aisheng static int sdhci_get_cd(struct mmc_host *mmc) 225066fd8ad5SAdrian Hunter { 225166fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 2252ded97e0bSDong Aisheng int gpio_cd = mmc_gpio_get_cd(mmc); 225394144a46SKevin Liu 225494144a46SKevin Liu if (host->flags & SDHCI_DEVICE_DEAD) 225594144a46SKevin Liu return 0; 225694144a46SKevin Liu 225788af5655SIvan T. Ivanov /* If nonremovable, assume that the card is always present. */ 2258860951c5SJaehoon Chung if (!mmc_card_is_removable(host->mmc)) 225994144a46SKevin Liu return 1; 226094144a46SKevin Liu 226188af5655SIvan T. Ivanov /* 226288af5655SIvan T. Ivanov * Try slot gpio detect, if defined it take precedence 226388af5655SIvan T. Ivanov * over build in controller functionality 226488af5655SIvan T. Ivanov */ 2265287980e4SArnd Bergmann if (gpio_cd >= 0) 226694144a46SKevin Liu return !!gpio_cd; 226794144a46SKevin Liu 226888af5655SIvan T. Ivanov /* If polling, assume that the card is always present. */ 226988af5655SIvan T. Ivanov if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 227088af5655SIvan T. Ivanov return 1; 227188af5655SIvan T. Ivanov 227294144a46SKevin Liu /* Host native card detect */ 227394144a46SKevin Liu return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 227494144a46SKevin Liu } 227594144a46SKevin Liu 227666fd8ad5SAdrian Hunter static int sdhci_check_ro(struct sdhci_host *host) 22771c6a0718SPierre Ossman { 22781c6a0718SPierre Ossman unsigned long flags; 22792dfb579cSWolfram Sang int is_readonly; 22801c6a0718SPierre Ossman 22811c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 22821c6a0718SPierre Ossman 22831e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 22842dfb579cSWolfram Sang is_readonly = 0; 22852dfb579cSWolfram Sang else if (host->ops->get_ro) 22862dfb579cSWolfram Sang is_readonly = host->ops->get_ro(host); 22876d5cd068SThomas Petazzoni else if (mmc_can_gpio_ro(host->mmc)) 22886d5cd068SThomas Petazzoni is_readonly = mmc_gpio_get_ro(host->mmc); 22891e72859eSPierre Ossman else 22902dfb579cSWolfram Sang is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 22912dfb579cSWolfram Sang & SDHCI_WRITE_PROTECT); 22921c6a0718SPierre Ossman 22931c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 22941c6a0718SPierre Ossman 22952dfb579cSWolfram Sang /* This quirk needs to be replaced by a callback-function later */ 22962dfb579cSWolfram Sang return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 22972dfb579cSWolfram Sang !is_readonly : is_readonly; 22981c6a0718SPierre Ossman } 22991c6a0718SPierre Ossman 230082b0e23aSTakashi Iwai #define SAMPLE_COUNT 5 230182b0e23aSTakashi Iwai 2302ded97e0bSDong Aisheng static int sdhci_get_ro(struct mmc_host *mmc) 230382b0e23aSTakashi Iwai { 2304ded97e0bSDong Aisheng struct sdhci_host *host = mmc_priv(mmc); 230582b0e23aSTakashi Iwai int i, ro_count; 230682b0e23aSTakashi Iwai 230782b0e23aSTakashi Iwai if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 230866fd8ad5SAdrian Hunter return sdhci_check_ro(host); 230982b0e23aSTakashi Iwai 231082b0e23aSTakashi Iwai ro_count = 0; 231182b0e23aSTakashi Iwai for (i = 0; i < SAMPLE_COUNT; i++) { 231266fd8ad5SAdrian Hunter if (sdhci_check_ro(host)) { 231382b0e23aSTakashi Iwai if (++ro_count > SAMPLE_COUNT / 2) 231482b0e23aSTakashi Iwai return 1; 231582b0e23aSTakashi Iwai } 231682b0e23aSTakashi Iwai msleep(30); 231782b0e23aSTakashi Iwai } 231882b0e23aSTakashi Iwai return 0; 231982b0e23aSTakashi Iwai } 232082b0e23aSTakashi Iwai 232120758b66SAdrian Hunter static void sdhci_hw_reset(struct mmc_host *mmc) 232220758b66SAdrian Hunter { 232320758b66SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 232420758b66SAdrian Hunter 232520758b66SAdrian Hunter if (host->ops && host->ops->hw_reset) 232620758b66SAdrian Hunter host->ops->hw_reset(host); 232720758b66SAdrian Hunter } 232820758b66SAdrian Hunter 232966fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 233066fd8ad5SAdrian Hunter { 2331be138554SRussell King if (!(host->flags & SDHCI_DEVICE_DEAD)) { 233266fd8ad5SAdrian Hunter if (enable) 2333b537f94cSRussell King host->ier |= SDHCI_INT_CARD_INT; 23347260cf5eSAnton Vorontsov else 2335b537f94cSRussell King host->ier &= ~SDHCI_INT_CARD_INT; 2336b537f94cSRussell King 2337b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2338b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 233966fd8ad5SAdrian Hunter } 2340ef104333SRussell King } 2341f75979b7SPierre Ossman 23422f05b6abSHu Ziji void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 234366fd8ad5SAdrian Hunter { 234466fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 234566fd8ad5SAdrian Hunter unsigned long flags; 234666fd8ad5SAdrian Hunter 2347923713b3SHans de Goede if (enable) 2348923713b3SHans de Goede pm_runtime_get_noresume(host->mmc->parent); 2349923713b3SHans de Goede 235066fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 235166fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, enable); 2352f75979b7SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 2353923713b3SHans de Goede 2354923713b3SHans de Goede if (!enable) 2355923713b3SHans de Goede pm_runtime_put_noidle(host->mmc->parent); 2356f75979b7SPierre Ossman } 23572f05b6abSHu Ziji EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq); 2358f75979b7SPierre Ossman 235989f3c365SAdrian Hunter static void sdhci_ack_sdio_irq(struct mmc_host *mmc) 236089f3c365SAdrian Hunter { 236189f3c365SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 236289f3c365SAdrian Hunter unsigned long flags; 236389f3c365SAdrian Hunter 236489f3c365SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 236589f3c365SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 236689f3c365SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 236789f3c365SAdrian Hunter } 236889f3c365SAdrian Hunter 2369c376ea9eSHu Ziji int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 237021f5998fSFabio Estevam struct mmc_ios *ios) 2371f2119df6SArindam Nath { 2372ded97e0bSDong Aisheng struct sdhci_host *host = mmc_priv(mmc); 237320b92a30SKevin Liu u16 ctrl; 23746231f3deSPhilip Rakity int ret; 2375f2119df6SArindam Nath 237620b92a30SKevin Liu /* 237720b92a30SKevin Liu * Signal Voltage Switching is only applicable for Host Controllers 237820b92a30SKevin Liu * v3.00 and above. 237920b92a30SKevin Liu */ 238020b92a30SKevin Liu if (host->version < SDHCI_SPEC_300) 238120b92a30SKevin Liu return 0; 238220b92a30SKevin Liu 238320b92a30SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 238420b92a30SKevin Liu 238521f5998fSFabio Estevam switch (ios->signal_voltage) { 238620b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_330: 23878cb851a4SAdrian Hunter if (!(host->flags & SDHCI_SIGNALING_330)) 23888cb851a4SAdrian Hunter return -EINVAL; 2389f2119df6SArindam Nath /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 2390f2119df6SArindam Nath ctrl &= ~SDHCI_CTRL_VDD_180; 2391f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2392f2119df6SArindam Nath 23933a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 2394761daa36SDong Aisheng ret = mmc_regulator_set_vqmmc(mmc, ios); 23956231f3deSPhilip Rakity if (ret) { 23966606110dSJoe Perches pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 23976606110dSJoe Perches mmc_hostname(mmc)); 23986231f3deSPhilip Rakity return -EIO; 23996231f3deSPhilip Rakity } 24006231f3deSPhilip Rakity } 2401f2119df6SArindam Nath /* Wait for 5ms */ 2402f2119df6SArindam Nath usleep_range(5000, 5500); 2403f2119df6SArindam Nath 2404f2119df6SArindam Nath /* 3.3V regulator output should be stable within 5 ms */ 2405f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2406f2119df6SArindam Nath if (!(ctrl & SDHCI_CTRL_VDD_180)) 2407f2119df6SArindam Nath return 0; 24086231f3deSPhilip Rakity 2409b0b19ce6SFabio Estevam pr_warn("%s: 3.3V regulator output did not become stable\n", 24104e743f1fSMarkus Mayer mmc_hostname(mmc)); 24116231f3deSPhilip Rakity 241220b92a30SKevin Liu return -EAGAIN; 241320b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_180: 24148cb851a4SAdrian Hunter if (!(host->flags & SDHCI_SIGNALING_180)) 24158cb851a4SAdrian Hunter return -EINVAL; 24163a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 2417761daa36SDong Aisheng ret = mmc_regulator_set_vqmmc(mmc, ios); 241820b92a30SKevin Liu if (ret) { 24196606110dSJoe Perches pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 24206606110dSJoe Perches mmc_hostname(mmc)); 2421f2119df6SArindam Nath return -EIO; 2422f2119df6SArindam Nath } 242320b92a30SKevin Liu } 24246231f3deSPhilip Rakity 2425f2119df6SArindam Nath /* 2426f2119df6SArindam Nath * Enable 1.8V Signal Enable in the Host Control2 2427f2119df6SArindam Nath * register 2428f2119df6SArindam Nath */ 2429f2119df6SArindam Nath ctrl |= SDHCI_CTRL_VDD_180; 2430f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2431f2119df6SArindam Nath 24329d967a61SVincent Yang /* Some controller need to do more when switching */ 24339d967a61SVincent Yang if (host->ops->voltage_switch) 24349d967a61SVincent Yang host->ops->voltage_switch(host); 24359d967a61SVincent Yang 243620b92a30SKevin Liu /* 1.8V regulator output should be stable within 5 ms */ 2437f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 243820b92a30SKevin Liu if (ctrl & SDHCI_CTRL_VDD_180) 2439f2119df6SArindam Nath return 0; 2440f2119df6SArindam Nath 2441b0b19ce6SFabio Estevam pr_warn("%s: 1.8V regulator output did not become stable\n", 24424e743f1fSMarkus Mayer mmc_hostname(mmc)); 24436231f3deSPhilip Rakity 2444f2119df6SArindam Nath return -EAGAIN; 244520b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_120: 24468cb851a4SAdrian Hunter if (!(host->flags & SDHCI_SIGNALING_120)) 24478cb851a4SAdrian Hunter return -EINVAL; 24483a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 2449761daa36SDong Aisheng ret = mmc_regulator_set_vqmmc(mmc, ios); 245020b92a30SKevin Liu if (ret) { 24516606110dSJoe Perches pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 24526606110dSJoe Perches mmc_hostname(mmc)); 245320b92a30SKevin Liu return -EIO; 24546231f3deSPhilip Rakity } 245520b92a30SKevin Liu } 24566231f3deSPhilip Rakity return 0; 245720b92a30SKevin Liu default: 2458f2119df6SArindam Nath /* No signal voltage switch required */ 2459f2119df6SArindam Nath return 0; 2460f2119df6SArindam Nath } 246120b92a30SKevin Liu } 2462c376ea9eSHu Ziji EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch); 2463f2119df6SArindam Nath 246420b92a30SKevin Liu static int sdhci_card_busy(struct mmc_host *mmc) 246520b92a30SKevin Liu { 246620b92a30SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 246720b92a30SKevin Liu u32 present_state; 246820b92a30SKevin Liu 2469e613cc47SAdrian Hunter /* Check whether DAT[0] is 0 */ 247020b92a30SKevin Liu present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 247120b92a30SKevin Liu 2472e613cc47SAdrian Hunter return !(present_state & SDHCI_DATA_0_LVL_MASK); 247320b92a30SKevin Liu } 247420b92a30SKevin Liu 2475b5540ce1SAdrian Hunter static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2476b5540ce1SAdrian Hunter { 2477b5540ce1SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 2478b5540ce1SAdrian Hunter unsigned long flags; 2479b5540ce1SAdrian Hunter 2480b5540ce1SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2481b5540ce1SAdrian Hunter host->flags |= SDHCI_HS400_TUNING; 2482b5540ce1SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 2483b5540ce1SAdrian Hunter 2484b5540ce1SAdrian Hunter return 0; 2485b5540ce1SAdrian Hunter } 2486b5540ce1SAdrian Hunter 24876663c419Sernest.zhang void sdhci_start_tuning(struct sdhci_host *host) 2488da4bc4f2SAdrian Hunter { 2489da4bc4f2SAdrian Hunter u16 ctrl; 2490da4bc4f2SAdrian Hunter 2491da4bc4f2SAdrian Hunter ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2492da4bc4f2SAdrian Hunter ctrl |= SDHCI_CTRL_EXEC_TUNING; 2493da4bc4f2SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 2494da4bc4f2SAdrian Hunter ctrl |= SDHCI_CTRL_TUNED_CLK; 2495da4bc4f2SAdrian Hunter sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2496da4bc4f2SAdrian Hunter 2497da4bc4f2SAdrian Hunter /* 2498da4bc4f2SAdrian Hunter * As per the Host Controller spec v3.00, tuning command 2499da4bc4f2SAdrian Hunter * generates Buffer Read Ready interrupt, so enable that. 2500da4bc4f2SAdrian Hunter * 2501da4bc4f2SAdrian Hunter * Note: The spec clearly says that when tuning sequence 2502da4bc4f2SAdrian Hunter * is being performed, the controller does not generate 2503da4bc4f2SAdrian Hunter * interrupts other than Buffer Read Ready interrupt. But 2504da4bc4f2SAdrian Hunter * to make sure we don't hit a controller bug, we _only_ 2505da4bc4f2SAdrian Hunter * enable Buffer Read Ready interrupt here. 2506da4bc4f2SAdrian Hunter */ 2507da4bc4f2SAdrian Hunter sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 2508da4bc4f2SAdrian Hunter sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 2509da4bc4f2SAdrian Hunter } 25106663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_start_tuning); 2511da4bc4f2SAdrian Hunter 25126663c419Sernest.zhang void sdhci_end_tuning(struct sdhci_host *host) 2513da4bc4f2SAdrian Hunter { 2514da4bc4f2SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2515da4bc4f2SAdrian Hunter sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2516da4bc4f2SAdrian Hunter } 25176663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_end_tuning); 2518da4bc4f2SAdrian Hunter 25196663c419Sernest.zhang void sdhci_reset_tuning(struct sdhci_host *host) 2520da4bc4f2SAdrian Hunter { 2521da4bc4f2SAdrian Hunter u16 ctrl; 2522da4bc4f2SAdrian Hunter 2523da4bc4f2SAdrian Hunter ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2524da4bc4f2SAdrian Hunter ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2525da4bc4f2SAdrian Hunter ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2526da4bc4f2SAdrian Hunter sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2527da4bc4f2SAdrian Hunter } 25286663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_reset_tuning); 2529da4bc4f2SAdrian Hunter 25307353788cSBen Chuang void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) 2531da4bc4f2SAdrian Hunter { 2532da4bc4f2SAdrian Hunter sdhci_reset_tuning(host); 2533da4bc4f2SAdrian Hunter 2534da4bc4f2SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD); 2535da4bc4f2SAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_DATA); 2536da4bc4f2SAdrian Hunter 2537da4bc4f2SAdrian Hunter sdhci_end_tuning(host); 2538da4bc4f2SAdrian Hunter 2539da4bc4f2SAdrian Hunter mmc_abort_tuning(host->mmc, opcode); 2540da4bc4f2SAdrian Hunter } 25417353788cSBen Chuang EXPORT_SYMBOL_GPL(sdhci_abort_tuning); 2542da4bc4f2SAdrian Hunter 2543da4bc4f2SAdrian Hunter /* 2544da4bc4f2SAdrian Hunter * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI 2545da4bc4f2SAdrian Hunter * tuning command does not have a data payload (or rather the hardware does it 2546da4bc4f2SAdrian Hunter * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command 2547da4bc4f2SAdrian Hunter * interrupt setup is different to other commands and there is no timeout 2548da4bc4f2SAdrian Hunter * interrupt so special handling is needed. 2549da4bc4f2SAdrian Hunter */ 25506663c419Sernest.zhang void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 2551da4bc4f2SAdrian Hunter { 2552da4bc4f2SAdrian Hunter struct mmc_host *mmc = host->mmc; 2553c7836d15SMasahiro Yamada struct mmc_command cmd = {}; 2554c7836d15SMasahiro Yamada struct mmc_request mrq = {}; 25552a85ef25SAdrian Hunter unsigned long flags; 2556c846a00fSSrinivas Kandagatla u32 b = host->sdma_boundary; 25572a85ef25SAdrian Hunter 25582a85ef25SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2559da4bc4f2SAdrian Hunter 2560da4bc4f2SAdrian Hunter cmd.opcode = opcode; 2561da4bc4f2SAdrian Hunter cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2562da4bc4f2SAdrian Hunter cmd.mrq = &mrq; 2563da4bc4f2SAdrian Hunter 2564da4bc4f2SAdrian Hunter mrq.cmd = &cmd; 2565da4bc4f2SAdrian Hunter /* 2566da4bc4f2SAdrian Hunter * In response to CMD19, the card sends 64 bytes of tuning 2567da4bc4f2SAdrian Hunter * block to the Host Controller. So we set the block size 2568da4bc4f2SAdrian Hunter * to 64 here. 2569da4bc4f2SAdrian Hunter */ 257085336109SAdrian Hunter if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 && 257185336109SAdrian Hunter mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2572c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE); 257385336109SAdrian Hunter else 2574c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE); 2575da4bc4f2SAdrian Hunter 2576da4bc4f2SAdrian Hunter /* 2577da4bc4f2SAdrian Hunter * The tuning block is sent by the card to the host controller. 2578da4bc4f2SAdrian Hunter * So we set the TRNS_READ bit in the Transfer Mode register. 2579da4bc4f2SAdrian Hunter * This also takes care of setting DMA Enable and Multi Block 2580da4bc4f2SAdrian Hunter * Select in the same register to 0. 2581da4bc4f2SAdrian Hunter */ 2582da4bc4f2SAdrian Hunter sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2583da4bc4f2SAdrian Hunter 2584da4bc4f2SAdrian Hunter sdhci_send_command(host, &cmd); 2585da4bc4f2SAdrian Hunter 2586da4bc4f2SAdrian Hunter host->cmd = NULL; 2587da4bc4f2SAdrian Hunter 2588da4bc4f2SAdrian Hunter sdhci_del_timer(host, &mrq); 2589da4bc4f2SAdrian Hunter 2590da4bc4f2SAdrian Hunter host->tuning_done = 0; 2591da4bc4f2SAdrian Hunter 2592da4bc4f2SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 2593da4bc4f2SAdrian Hunter 2594da4bc4f2SAdrian Hunter /* Wait for Buffer Read Ready interrupt */ 2595da4bc4f2SAdrian Hunter wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), 2596da4bc4f2SAdrian Hunter msecs_to_jiffies(50)); 2597da4bc4f2SAdrian Hunter 2598da4bc4f2SAdrian Hunter } 25996663c419Sernest.zhang EXPORT_SYMBOL_GPL(sdhci_send_tuning); 2600da4bc4f2SAdrian Hunter 26017d8bb1f4SYinbo Zhu static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 26026b11e70bSAdrian Hunter { 26036b11e70bSAdrian Hunter int i; 26046b11e70bSAdrian Hunter 26056b11e70bSAdrian Hunter /* 26066b11e70bSAdrian Hunter * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 26071d8cd065SSowjanya Komatineni * of loops reaches tuning loop count. 26086b11e70bSAdrian Hunter */ 26091d8cd065SSowjanya Komatineni for (i = 0; i < host->tuning_loop_count; i++) { 26106b11e70bSAdrian Hunter u16 ctrl; 26116b11e70bSAdrian Hunter 26122a85ef25SAdrian Hunter sdhci_send_tuning(host, opcode); 26136b11e70bSAdrian Hunter 26146b11e70bSAdrian Hunter if (!host->tuning_done) { 2615811ba676SFaiz Abbas pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n", 26166b11e70bSAdrian Hunter mmc_hostname(host->mmc)); 26172a85ef25SAdrian Hunter sdhci_abort_tuning(host, opcode); 26187d8bb1f4SYinbo Zhu return -ETIMEDOUT; 26196b11e70bSAdrian Hunter } 26206b11e70bSAdrian Hunter 26212b06e159SBOUGH CHEN /* Spec does not require a delay between tuning cycles */ 26222b06e159SBOUGH CHEN if (host->tuning_delay > 0) 26232b06e159SBOUGH CHEN mdelay(host->tuning_delay); 26242b06e159SBOUGH CHEN 26256b11e70bSAdrian Hunter ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 26266b11e70bSAdrian Hunter if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 26276b11e70bSAdrian Hunter if (ctrl & SDHCI_CTRL_TUNED_CLK) 26287d8bb1f4SYinbo Zhu return 0; /* Success! */ 26296b11e70bSAdrian Hunter break; 26306b11e70bSAdrian Hunter } 26316b11e70bSAdrian Hunter 26326b11e70bSAdrian Hunter } 26336b11e70bSAdrian Hunter 26346b11e70bSAdrian Hunter pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 26356b11e70bSAdrian Hunter mmc_hostname(host->mmc)); 26366b11e70bSAdrian Hunter sdhci_reset_tuning(host); 26377d8bb1f4SYinbo Zhu return -EAGAIN; 26386b11e70bSAdrian Hunter } 26396b11e70bSAdrian Hunter 264085a882c2SMasahiro Yamada int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 2641b513ea25SArindam Nath { 26424b6f37d3SRussell King struct sdhci_host *host = mmc_priv(mmc); 2643b513ea25SArindam Nath int err = 0; 264438e40bf5SAdrian Hunter unsigned int tuning_count = 0; 2645b5540ce1SAdrian Hunter bool hs400_tuning; 2646b513ea25SArindam Nath 2647b5540ce1SAdrian Hunter hs400_tuning = host->flags & SDHCI_HS400_TUNING; 2648b5540ce1SAdrian Hunter 264938e40bf5SAdrian Hunter if (host->tuning_mode == SDHCI_TUNING_MODE_1) 265038e40bf5SAdrian Hunter tuning_count = host->tuning_count; 265138e40bf5SAdrian Hunter 2652b513ea25SArindam Nath /* 26539faac7b9SWeijun Yang * The Host Controller needs tuning in case of SDR104 and DDR50 26549faac7b9SWeijun Yang * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 26559faac7b9SWeijun Yang * the Capabilities register. 2656069c9f14SGirish K S * If the Host Controller supports the HS200 mode then the 2657069c9f14SGirish K S * tuning function has to be executed. 2658b513ea25SArindam Nath */ 26594b6f37d3SRussell King switch (host->timing) { 2660b5540ce1SAdrian Hunter /* HS400 tuning is done in HS200 mode */ 2661e9fb05d5SAdrian Hunter case MMC_TIMING_MMC_HS400: 2662b5540ce1SAdrian Hunter err = -EINVAL; 26632a85ef25SAdrian Hunter goto out; 2664b5540ce1SAdrian Hunter 26654b6f37d3SRussell King case MMC_TIMING_MMC_HS200: 2666b5540ce1SAdrian Hunter /* 2667b5540ce1SAdrian Hunter * Periodic re-tuning for HS400 is not expected to be needed, so 2668b5540ce1SAdrian Hunter * disable it here. 2669b5540ce1SAdrian Hunter */ 2670b5540ce1SAdrian Hunter if (hs400_tuning) 2671b5540ce1SAdrian Hunter tuning_count = 0; 2672b5540ce1SAdrian Hunter break; 2673b5540ce1SAdrian Hunter 26744b6f37d3SRussell King case MMC_TIMING_UHS_SDR104: 26759faac7b9SWeijun Yang case MMC_TIMING_UHS_DDR50: 26764b6f37d3SRussell King break; 2677069c9f14SGirish K S 26784b6f37d3SRussell King case MMC_TIMING_UHS_SDR50: 26794228b213SAdrian Hunter if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 26804b6f37d3SRussell King break; 26814b6f37d3SRussell King /* FALLTHROUGH */ 26824b6f37d3SRussell King 26834b6f37d3SRussell King default: 26842a85ef25SAdrian Hunter goto out; 2685b513ea25SArindam Nath } 2686b513ea25SArindam Nath 268745251812SDong Aisheng if (host->ops->platform_execute_tuning) { 26888a8fa879SRitesh Harjani err = host->ops->platform_execute_tuning(host, opcode); 26892a85ef25SAdrian Hunter goto out; 269045251812SDong Aisheng } 269145251812SDong Aisheng 26926b11e70bSAdrian Hunter host->mmc->retune_period = tuning_count; 26936b11e70bSAdrian Hunter 269483b600b8SAdrian Hunter if (host->tuning_delay < 0) 269583b600b8SAdrian Hunter host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK; 269683b600b8SAdrian Hunter 2697da4bc4f2SAdrian Hunter sdhci_start_tuning(host); 2698b513ea25SArindam Nath 26997d8bb1f4SYinbo Zhu host->tuning_err = __sdhci_execute_tuning(host, opcode); 2700cf2b5eeaSArindam Nath 2701da4bc4f2SAdrian Hunter sdhci_end_tuning(host); 27022a85ef25SAdrian Hunter out: 27038a8fa879SRitesh Harjani host->flags &= ~SDHCI_HS400_TUNING; 27046b11e70bSAdrian Hunter 2705b513ea25SArindam Nath return err; 2706b513ea25SArindam Nath } 270785a882c2SMasahiro Yamada EXPORT_SYMBOL_GPL(sdhci_execute_tuning); 2708b513ea25SArindam Nath 270952983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 27104d55c5a1SArindam Nath { 27114d55c5a1SArindam Nath /* Host Controller v3.00 defines preset value registers */ 27124d55c5a1SArindam Nath if (host->version < SDHCI_SPEC_300) 27134d55c5a1SArindam Nath return; 27144d55c5a1SArindam Nath 27154d55c5a1SArindam Nath /* 27164d55c5a1SArindam Nath * We only enable or disable Preset Value if they are not already 27174d55c5a1SArindam Nath * enabled or disabled respectively. Otherwise, we bail out. 27184d55c5a1SArindam Nath */ 2719da91a8f9SRussell King if (host->preset_enabled != enable) { 2720da91a8f9SRussell King u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2721da91a8f9SRussell King 2722da91a8f9SRussell King if (enable) 27234d55c5a1SArindam Nath ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2724da91a8f9SRussell King else 27254d55c5a1SArindam Nath ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2726da91a8f9SRussell King 27274d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2728da91a8f9SRussell King 2729da91a8f9SRussell King if (enable) 2730da91a8f9SRussell King host->flags |= SDHCI_PV_ENABLED; 2731da91a8f9SRussell King else 273266fd8ad5SAdrian Hunter host->flags &= ~SDHCI_PV_ENABLED; 2733da91a8f9SRussell King 2734da91a8f9SRussell King host->preset_enabled = enable; 27354d55c5a1SArindam Nath } 273666fd8ad5SAdrian Hunter } 273766fd8ad5SAdrian Hunter 2738348487cbSHaibo Chen static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2739348487cbSHaibo Chen int err) 2740348487cbSHaibo Chen { 2741348487cbSHaibo Chen struct sdhci_host *host = mmc_priv(mmc); 2742348487cbSHaibo Chen struct mmc_data *data = mrq->data; 2743348487cbSHaibo Chen 2744f48f039cSRussell King if (data->host_cookie != COOKIE_UNMAPPED) 2745348487cbSHaibo Chen dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2746feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 2747771a3dc2SRussell King 2748d31911b9SHaibo Chen data->host_cookie = COOKIE_UNMAPPED; 2749348487cbSHaibo Chen } 2750348487cbSHaibo Chen 2751d3c6aac3SLinus Walleij static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 2752348487cbSHaibo Chen { 2753348487cbSHaibo Chen struct sdhci_host *host = mmc_priv(mmc); 2754348487cbSHaibo Chen 2755d31911b9SHaibo Chen mrq->data->host_cookie = COOKIE_UNMAPPED; 2756348487cbSHaibo Chen 2757bd9b9027SLinus Walleij /* 2758bd9b9027SLinus Walleij * No pre-mapping in the pre hook if we're using the bounce buffer, 2759bd9b9027SLinus Walleij * for that we would need two bounce buffers since one buffer is 2760bd9b9027SLinus Walleij * in flight when this is getting called. 2761bd9b9027SLinus Walleij */ 2762bd9b9027SLinus Walleij if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer) 276394538e51SRussell King sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2764348487cbSHaibo Chen } 2765348487cbSHaibo Chen 27665d0d11c5SAdrian Hunter static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 27675d0d11c5SAdrian Hunter { 27685d0d11c5SAdrian Hunter if (host->data_cmd) { 27695d0d11c5SAdrian Hunter host->data_cmd->error = err; 27705d0d11c5SAdrian Hunter sdhci_finish_mrq(host, host->data_cmd->mrq); 27715d0d11c5SAdrian Hunter } 27725d0d11c5SAdrian Hunter 27735d0d11c5SAdrian Hunter if (host->cmd) { 27745d0d11c5SAdrian Hunter host->cmd->error = err; 27755d0d11c5SAdrian Hunter sdhci_finish_mrq(host, host->cmd->mrq); 27765d0d11c5SAdrian Hunter } 27775d0d11c5SAdrian Hunter } 27785d0d11c5SAdrian Hunter 277971e69211SGuennadi Liakhovetski static void sdhci_card_event(struct mmc_host *mmc) 27801c6a0718SPierre Ossman { 278171e69211SGuennadi Liakhovetski struct sdhci_host *host = mmc_priv(mmc); 27821c6a0718SPierre Ossman unsigned long flags; 27832836766aSKrzysztof Kozlowski int present; 27841c6a0718SPierre Ossman 2785722e1280SChristian Daudt /* First check if client has provided their own card event */ 2786722e1280SChristian Daudt if (host->ops->card_event) 2787722e1280SChristian Daudt host->ops->card_event(host); 2788722e1280SChristian Daudt 2789d3940f27SAdrian Hunter present = mmc->ops->get_cd(mmc); 27902836766aSKrzysztof Kozlowski 27911c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 27921c6a0718SPierre Ossman 27935d0d11c5SAdrian Hunter /* Check sdhci_has_requests() first in case we are runtime suspended */ 27945d0d11c5SAdrian Hunter if (sdhci_has_requests(host) && !present) { 2795a3c76eb9SGirish K S pr_err("%s: Card removed during transfer!\n", 27961c6a0718SPierre Ossman mmc_hostname(host->mmc)); 2797a3c76eb9SGirish K S pr_err("%s: Resetting controller.\n", 27981c6a0718SPierre Ossman mmc_hostname(host->mmc)); 27991c6a0718SPierre Ossman 280003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 280103231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 28021c6a0718SPierre Ossman 28035d0d11c5SAdrian Hunter sdhci_error_out_mrqs(host, -ENOMEDIUM); 28041c6a0718SPierre Ossman } 28051c6a0718SPierre Ossman 28061c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 280771e69211SGuennadi Liakhovetski } 280871e69211SGuennadi Liakhovetski 280971e69211SGuennadi Liakhovetski static const struct mmc_host_ops sdhci_ops = { 281071e69211SGuennadi Liakhovetski .request = sdhci_request, 2811348487cbSHaibo Chen .post_req = sdhci_post_req, 2812348487cbSHaibo Chen .pre_req = sdhci_pre_req, 281371e69211SGuennadi Liakhovetski .set_ios = sdhci_set_ios, 281494144a46SKevin Liu .get_cd = sdhci_get_cd, 281571e69211SGuennadi Liakhovetski .get_ro = sdhci_get_ro, 281671e69211SGuennadi Liakhovetski .hw_reset = sdhci_hw_reset, 281771e69211SGuennadi Liakhovetski .enable_sdio_irq = sdhci_enable_sdio_irq, 281889f3c365SAdrian Hunter .ack_sdio_irq = sdhci_ack_sdio_irq, 281971e69211SGuennadi Liakhovetski .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2820b5540ce1SAdrian Hunter .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 282171e69211SGuennadi Liakhovetski .execute_tuning = sdhci_execute_tuning, 282271e69211SGuennadi Liakhovetski .card_event = sdhci_card_event, 282320b92a30SKevin Liu .card_busy = sdhci_card_busy, 282471e69211SGuennadi Liakhovetski }; 282571e69211SGuennadi Liakhovetski 282671e69211SGuennadi Liakhovetski /*****************************************************************************\ 282771e69211SGuennadi Liakhovetski * * 2828c07a48c2SAdrian Hunter * Request done * 282971e69211SGuennadi Liakhovetski * * 283071e69211SGuennadi Liakhovetski \*****************************************************************************/ 283171e69211SGuennadi Liakhovetski 28324e9f8fe5SAdrian Hunter static bool sdhci_request_done(struct sdhci_host *host) 28331c6a0718SPierre Ossman { 28341c6a0718SPierre Ossman unsigned long flags; 28351c6a0718SPierre Ossman struct mmc_request *mrq; 28364e9f8fe5SAdrian Hunter int i; 28371c6a0718SPierre Ossman 283866fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 283966fd8ad5SAdrian Hunter 28404e9f8fe5SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 28414e9f8fe5SAdrian Hunter mrq = host->mrqs_done[i]; 28426ebebeabSAdrian Hunter if (mrq) 28434e9f8fe5SAdrian Hunter break; 28444e9f8fe5SAdrian Hunter } 28451c6a0718SPierre Ossman 28464e9f8fe5SAdrian Hunter if (!mrq) { 28474e9f8fe5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 28484e9f8fe5SAdrian Hunter return true; 28494e9f8fe5SAdrian Hunter } 28501c6a0718SPierre Ossman 28511c6a0718SPierre Ossman /* 2852054cedffSRussell King * Always unmap the data buffers if they were mapped by 2853054cedffSRussell King * sdhci_prepare_data() whenever we finish with a request. 2854054cedffSRussell King * This avoids leaking DMA mappings on error. 2855054cedffSRussell King */ 2856054cedffSRussell King if (host->flags & SDHCI_REQ_USE_DMA) { 2857054cedffSRussell King struct mmc_data *data = mrq->data; 2858054cedffSRussell King 285918e762e3SChunyan Zhang if (host->use_external_dma && data && 286018e762e3SChunyan Zhang (mrq->cmd->error || data->error)) { 286118e762e3SChunyan Zhang struct dma_chan *chan = sdhci_external_dma_channel(host, data); 286218e762e3SChunyan Zhang 286318e762e3SChunyan Zhang host->mrqs_done[i] = NULL; 286418e762e3SChunyan Zhang spin_unlock_irqrestore(&host->lock, flags); 286518e762e3SChunyan Zhang dmaengine_terminate_sync(chan); 286618e762e3SChunyan Zhang spin_lock_irqsave(&host->lock, flags); 286718e762e3SChunyan Zhang sdhci_set_mrq_done(host, mrq); 286818e762e3SChunyan Zhang } 286918e762e3SChunyan Zhang 2870054cedffSRussell King if (data && data->host_cookie == COOKIE_MAPPED) { 2871bd9b9027SLinus Walleij if (host->bounce_buffer) { 2872bd9b9027SLinus Walleij /* 2873bd9b9027SLinus Walleij * On reads, copy the bounced data into the 2874bd9b9027SLinus Walleij * sglist 2875bd9b9027SLinus Walleij */ 2876bd9b9027SLinus Walleij if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { 2877bd9b9027SLinus Walleij unsigned int length = data->bytes_xfered; 2878bd9b9027SLinus Walleij 2879bd9b9027SLinus Walleij if (length > host->bounce_buffer_size) { 2880bd9b9027SLinus Walleij pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", 2881bd9b9027SLinus Walleij mmc_hostname(host->mmc), 2882bd9b9027SLinus Walleij host->bounce_buffer_size, 2883bd9b9027SLinus Walleij data->bytes_xfered); 2884bd9b9027SLinus Walleij /* Cap it down and continue */ 2885bd9b9027SLinus Walleij length = host->bounce_buffer_size; 2886bd9b9027SLinus Walleij } 2887bd9b9027SLinus Walleij dma_sync_single_for_cpu( 2888bd9b9027SLinus Walleij host->mmc->parent, 2889bd9b9027SLinus Walleij host->bounce_addr, 2890bd9b9027SLinus Walleij host->bounce_buffer_size, 2891bd9b9027SLinus Walleij DMA_FROM_DEVICE); 2892bd9b9027SLinus Walleij sg_copy_from_buffer(data->sg, 2893bd9b9027SLinus Walleij data->sg_len, 2894bd9b9027SLinus Walleij host->bounce_buffer, 2895bd9b9027SLinus Walleij length); 2896bd9b9027SLinus Walleij } else { 2897bd9b9027SLinus Walleij /* No copying, just switch ownership */ 2898bd9b9027SLinus Walleij dma_sync_single_for_cpu( 2899bd9b9027SLinus Walleij host->mmc->parent, 2900bd9b9027SLinus Walleij host->bounce_addr, 2901bd9b9027SLinus Walleij host->bounce_buffer_size, 2902feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 2903bd9b9027SLinus Walleij } 2904bd9b9027SLinus Walleij } else { 2905bd9b9027SLinus Walleij /* Unmap the raw data */ 2906bd9b9027SLinus Walleij dma_unmap_sg(mmc_dev(host->mmc), data->sg, 2907bd9b9027SLinus Walleij data->sg_len, 2908bd9b9027SLinus Walleij mmc_get_dma_dir(data)); 2909bd9b9027SLinus Walleij } 2910054cedffSRussell King data->host_cookie = COOKIE_UNMAPPED; 2911054cedffSRussell King } 2912054cedffSRussell King } 2913054cedffSRussell King 2914054cedffSRussell King /* 29151c6a0718SPierre Ossman * The controller needs a reset of internal state machines 29161c6a0718SPierre Ossman * upon error conditions. 29171c6a0718SPierre Ossman */ 29180cc563ceSAdrian Hunter if (sdhci_needs_reset(host, mrq)) { 29196ebebeabSAdrian Hunter /* 29206ebebeabSAdrian Hunter * Do not finish until command and data lines are available for 29216ebebeabSAdrian Hunter * reset. Note there can only be one other mrq, so it cannot 29226ebebeabSAdrian Hunter * also be in mrqs_done, otherwise host->cmd and host->data_cmd 29236ebebeabSAdrian Hunter * would both be null. 29246ebebeabSAdrian Hunter */ 29256ebebeabSAdrian Hunter if (host->cmd || host->data_cmd) { 29266ebebeabSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 29276ebebeabSAdrian Hunter return true; 29286ebebeabSAdrian Hunter } 29296ebebeabSAdrian Hunter 29301c6a0718SPierre Ossman /* Some controllers need this kick or reset won't work here */ 29318213af3bSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 29321c6a0718SPierre Ossman /* This is to force an update */ 29331771059cSRussell King host->ops->set_clock(host, host->clock); 29341c6a0718SPierre Ossman 29351c6a0718SPierre Ossman /* Spec says we should do both at the same time, but Ricoh 29361c6a0718SPierre Ossman controllers do not like that. */ 293703231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 293803231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 2939ed1563deSAdrian Hunter 2940ed1563deSAdrian Hunter host->pending_reset = false; 29411c6a0718SPierre Ossman } 29421c6a0718SPierre Ossman 29436ebebeabSAdrian Hunter host->mrqs_done[i] = NULL; 29446ebebeabSAdrian Hunter 29451c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 29461c6a0718SPierre Ossman 29471c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 29484e9f8fe5SAdrian Hunter 29494e9f8fe5SAdrian Hunter return false; 29504e9f8fe5SAdrian Hunter } 29514e9f8fe5SAdrian Hunter 2952c07a48c2SAdrian Hunter static void sdhci_complete_work(struct work_struct *work) 29534e9f8fe5SAdrian Hunter { 2954c07a48c2SAdrian Hunter struct sdhci_host *host = container_of(work, struct sdhci_host, 2955c07a48c2SAdrian Hunter complete_work); 29564e9f8fe5SAdrian Hunter 29574e9f8fe5SAdrian Hunter while (!sdhci_request_done(host)) 29584e9f8fe5SAdrian Hunter ; 29591c6a0718SPierre Ossman } 29601c6a0718SPierre Ossman 29612ee4f620SKees Cook static void sdhci_timeout_timer(struct timer_list *t) 29621c6a0718SPierre Ossman { 29631c6a0718SPierre Ossman struct sdhci_host *host; 29641c6a0718SPierre Ossman unsigned long flags; 29651c6a0718SPierre Ossman 29662ee4f620SKees Cook host = from_timer(host, t, timer); 29671c6a0718SPierre Ossman 29681c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 29691c6a0718SPierre Ossman 2970d7422fb4SAdrian Hunter if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2971d7422fb4SAdrian Hunter pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2972d7422fb4SAdrian Hunter mmc_hostname(host->mmc)); 2973d7422fb4SAdrian Hunter sdhci_dumpregs(host); 2974d7422fb4SAdrian Hunter 2975d7422fb4SAdrian Hunter host->cmd->error = -ETIMEDOUT; 2976d7422fb4SAdrian Hunter sdhci_finish_mrq(host, host->cmd->mrq); 2977d7422fb4SAdrian Hunter } 2978d7422fb4SAdrian Hunter 2979d7422fb4SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 2980d7422fb4SAdrian Hunter } 2981d7422fb4SAdrian Hunter 29822ee4f620SKees Cook static void sdhci_timeout_data_timer(struct timer_list *t) 2983d7422fb4SAdrian Hunter { 2984d7422fb4SAdrian Hunter struct sdhci_host *host; 2985d7422fb4SAdrian Hunter unsigned long flags; 2986d7422fb4SAdrian Hunter 29872ee4f620SKees Cook host = from_timer(host, t, data_timer); 2988d7422fb4SAdrian Hunter 2989d7422fb4SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2990d7422fb4SAdrian Hunter 2991d7422fb4SAdrian Hunter if (host->data || host->data_cmd || 2992d7422fb4SAdrian Hunter (host->cmd && sdhci_data_line_cmd(host->cmd))) { 29932e4456f0SMarek Vasut pr_err("%s: Timeout waiting for hardware interrupt.\n", 29942e4456f0SMarek Vasut mmc_hostname(host->mmc)); 29951c6a0718SPierre Ossman sdhci_dumpregs(host); 29961c6a0718SPierre Ossman 29971c6a0718SPierre Ossman if (host->data) { 299817b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 29991c6a0718SPierre Ossman sdhci_finish_data(host); 3000c07a48c2SAdrian Hunter queue_work(host->complete_wq, &host->complete_work); 3001d7422fb4SAdrian Hunter } else if (host->data_cmd) { 3002d7422fb4SAdrian Hunter host->data_cmd->error = -ETIMEDOUT; 3003d7422fb4SAdrian Hunter sdhci_finish_mrq(host, host->data_cmd->mrq); 30041c6a0718SPierre Ossman } else { 300517b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 3006d7422fb4SAdrian Hunter sdhci_finish_mrq(host, host->cmd->mrq); 30071c6a0718SPierre Ossman } 30081c6a0718SPierre Ossman } 30091c6a0718SPierre Ossman 30101c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 30111c6a0718SPierre Ossman } 30121c6a0718SPierre Ossman 30131c6a0718SPierre Ossman /*****************************************************************************\ 30141c6a0718SPierre Ossman * * 30151c6a0718SPierre Ossman * Interrupt handling * 30161c6a0718SPierre Ossman * * 30171c6a0718SPierre Ossman \*****************************************************************************/ 30181c6a0718SPierre Ossman 30194bf78099SAdrian Hunter static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p) 30201c6a0718SPierre Ossman { 3021af849c86SAdrian Hunter /* Handle auto-CMD12 error */ 3022af849c86SAdrian Hunter if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) { 3023af849c86SAdrian Hunter struct mmc_request *mrq = host->data_cmd->mrq; 3024af849c86SAdrian Hunter u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); 3025af849c86SAdrian Hunter int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? 3026af849c86SAdrian Hunter SDHCI_INT_DATA_TIMEOUT : 3027af849c86SAdrian Hunter SDHCI_INT_DATA_CRC; 3028af849c86SAdrian Hunter 3029af849c86SAdrian Hunter /* Treat auto-CMD12 error the same as data error */ 3030af849c86SAdrian Hunter if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 3031af849c86SAdrian Hunter *intmask_p |= data_err_bit; 3032af849c86SAdrian Hunter return; 3033af849c86SAdrian Hunter } 3034af849c86SAdrian Hunter } 3035af849c86SAdrian Hunter 30361c6a0718SPierre Ossman if (!host->cmd) { 3037ed1563deSAdrian Hunter /* 3038ed1563deSAdrian Hunter * SDHCI recovers from errors by resetting the cmd and data 3039ed1563deSAdrian Hunter * circuits. Until that is done, there very well might be more 3040ed1563deSAdrian Hunter * interrupts, so ignore them in that case. 3041ed1563deSAdrian Hunter */ 3042ed1563deSAdrian Hunter if (host->pending_reset) 3043ed1563deSAdrian Hunter return; 30442e4456f0SMarek Vasut pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 3045b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 30461c6a0718SPierre Ossman sdhci_dumpregs(host); 30471c6a0718SPierre Ossman return; 30481c6a0718SPierre Ossman } 30491c6a0718SPierre Ossman 3050ec014cbaSRussell King if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 3051ec014cbaSRussell King SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 30521c6a0718SPierre Ossman if (intmask & SDHCI_INT_TIMEOUT) 305317b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 3054ec014cbaSRussell King else 305517b0429dSPierre Ossman host->cmd->error = -EILSEQ; 30561c6a0718SPierre Ossman 30574bf78099SAdrian Hunter /* Treat data command CRC error the same as data CRC error */ 305871fcbda0SRussell King if (host->cmd->data && 305971fcbda0SRussell King (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 306071fcbda0SRussell King SDHCI_INT_CRC) { 306171fcbda0SRussell King host->cmd = NULL; 30624bf78099SAdrian Hunter *intmask_p |= SDHCI_INT_DATA_CRC; 306371fcbda0SRussell King return; 306471fcbda0SRussell King } 306571fcbda0SRussell King 306619d2f695SAdrian Hunter __sdhci_finish_mrq(host, host->cmd->mrq); 3067e809517fSPierre Ossman return; 3068e809517fSPierre Ossman } 3069e809517fSPierre Ossman 3070af849c86SAdrian Hunter /* Handle auto-CMD23 error */ 3071af849c86SAdrian Hunter if (intmask & SDHCI_INT_AUTO_CMD_ERR) { 3072af849c86SAdrian Hunter struct mmc_request *mrq = host->cmd->mrq; 3073af849c86SAdrian Hunter u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); 3074af849c86SAdrian Hunter int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? 3075af849c86SAdrian Hunter -ETIMEDOUT : 3076af849c86SAdrian Hunter -EILSEQ; 3077af849c86SAdrian Hunter 3078af849c86SAdrian Hunter if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 3079af849c86SAdrian Hunter mrq->sbc->error = err; 308019d2f695SAdrian Hunter __sdhci_finish_mrq(host, mrq); 3081af849c86SAdrian Hunter return; 3082af849c86SAdrian Hunter } 3083af849c86SAdrian Hunter } 3084af849c86SAdrian Hunter 3085e809517fSPierre Ossman if (intmask & SDHCI_INT_RESPONSE) 308643b58b36SPierre Ossman sdhci_finish_command(host); 30871c6a0718SPierre Ossman } 30881c6a0718SPierre Ossman 308908621b18SAdrian Hunter static void sdhci_adma_show_error(struct sdhci_host *host) 30906882a8c0SBen Dooks { 30911c3d5f6dSAdrian Hunter void *desc = host->adma_table; 3092d1c536e3SRussell King dma_addr_t dma = host->adma_addr; 30936882a8c0SBen Dooks 30946882a8c0SBen Dooks sdhci_dumpregs(host); 30956882a8c0SBen Dooks 30966882a8c0SBen Dooks while (true) { 3097e57a5f61SAdrian Hunter struct sdhci_adma2_64_desc *dma_desc = desc; 30986882a8c0SBen Dooks 3099e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) 3100d1c536e3SRussell King SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 3101d1c536e3SRussell King (unsigned long long)dma, 3102d1c536e3SRussell King le32_to_cpu(dma_desc->addr_hi), 3103e57a5f61SAdrian Hunter le32_to_cpu(dma_desc->addr_lo), 3104e57a5f61SAdrian Hunter le16_to_cpu(dma_desc->len), 3105e57a5f61SAdrian Hunter le16_to_cpu(dma_desc->cmd)); 3106e57a5f61SAdrian Hunter else 3107d1c536e3SRussell King SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 3108d1c536e3SRussell King (unsigned long long)dma, 3109d1c536e3SRussell King le32_to_cpu(dma_desc->addr_lo), 31100545230fSAdrian Hunter le16_to_cpu(dma_desc->len), 31110545230fSAdrian Hunter le16_to_cpu(dma_desc->cmd)); 31126882a8c0SBen Dooks 311376fe379aSAdrian Hunter desc += host->desc_sz; 3114d1c536e3SRussell King dma += host->desc_sz; 31156882a8c0SBen Dooks 31160545230fSAdrian Hunter if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 31176882a8c0SBen Dooks break; 31186882a8c0SBen Dooks } 31196882a8c0SBen Dooks } 31206882a8c0SBen Dooks 31211c6a0718SPierre Ossman static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 31221c6a0718SPierre Ossman { 3123069c9f14SGirish K S u32 command; 31241c6a0718SPierre Ossman 3125b513ea25SArindam Nath /* CMD19 generates _only_ Buffer Read Ready interrupt */ 3126b513ea25SArindam Nath if (intmask & SDHCI_INT_DATA_AVAIL) { 3127069c9f14SGirish K S command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 3128069c9f14SGirish K S if (command == MMC_SEND_TUNING_BLOCK || 3129069c9f14SGirish K S command == MMC_SEND_TUNING_BLOCK_HS200) { 3130b513ea25SArindam Nath host->tuning_done = 1; 3131b513ea25SArindam Nath wake_up(&host->buf_ready_int); 3132b513ea25SArindam Nath return; 3133b513ea25SArindam Nath } 3134b513ea25SArindam Nath } 3135b513ea25SArindam Nath 31361c6a0718SPierre Ossman if (!host->data) { 31377c89a3d9SAdrian Hunter struct mmc_command *data_cmd = host->data_cmd; 31387c89a3d9SAdrian Hunter 31391c6a0718SPierre Ossman /* 3140e809517fSPierre Ossman * The "data complete" interrupt is also used to 3141e809517fSPierre Ossman * indicate that a busy state has ended. See comment 3142e809517fSPierre Ossman * above in sdhci_cmd_irq(). 31431c6a0718SPierre Ossman */ 31447c89a3d9SAdrian Hunter if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 3145c5abd5e8SMatthieu CASTET if (intmask & SDHCI_INT_DATA_TIMEOUT) { 314669b962a6SAdrian Hunter host->data_cmd = NULL; 31477c89a3d9SAdrian Hunter data_cmd->error = -ETIMEDOUT; 314819d2f695SAdrian Hunter __sdhci_finish_mrq(host, data_cmd->mrq); 3149c5abd5e8SMatthieu CASTET return; 3150c5abd5e8SMatthieu CASTET } 3151e809517fSPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 315269b962a6SAdrian Hunter host->data_cmd = NULL; 3153e99783a4SChanho Min /* 3154e99783a4SChanho Min * Some cards handle busy-end interrupt 3155e99783a4SChanho Min * before the command completed, so make 3156e99783a4SChanho Min * sure we do things in the proper order. 3157e99783a4SChanho Min */ 3158ea968023SAdrian Hunter if (host->cmd == data_cmd) 3159ea968023SAdrian Hunter return; 3160ea968023SAdrian Hunter 316119d2f695SAdrian Hunter __sdhci_finish_mrq(host, data_cmd->mrq); 31621c6a0718SPierre Ossman return; 3163e809517fSPierre Ossman } 3164e809517fSPierre Ossman } 31651c6a0718SPierre Ossman 3166ed1563deSAdrian Hunter /* 3167ed1563deSAdrian Hunter * SDHCI recovers from errors by resetting the cmd and data 3168ed1563deSAdrian Hunter * circuits. Until that is done, there very well might be more 3169ed1563deSAdrian Hunter * interrupts, so ignore them in that case. 3170ed1563deSAdrian Hunter */ 3171ed1563deSAdrian Hunter if (host->pending_reset) 3172ed1563deSAdrian Hunter return; 3173ed1563deSAdrian Hunter 31742e4456f0SMarek Vasut pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 3175b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 31761c6a0718SPierre Ossman sdhci_dumpregs(host); 31771c6a0718SPierre Ossman 31781c6a0718SPierre Ossman return; 31791c6a0718SPierre Ossman } 31801c6a0718SPierre Ossman 31811c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_TIMEOUT) 318217b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 318322113efdSAries Lee else if (intmask & SDHCI_INT_DATA_END_BIT) 318422113efdSAries Lee host->data->error = -EILSEQ; 318522113efdSAries Lee else if ((intmask & SDHCI_INT_DATA_CRC) && 318622113efdSAries Lee SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 318722113efdSAries Lee != MMC_BUS_TEST_R) 318817b0429dSPierre Ossman host->data->error = -EILSEQ; 31896882a8c0SBen Dooks else if (intmask & SDHCI_INT_ADMA_ERROR) { 3190d1c536e3SRussell King pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc), 3191d1c536e3SRussell King intmask); 319208621b18SAdrian Hunter sdhci_adma_show_error(host); 31932134a922SPierre Ossman host->data->error = -EIO; 3194a4071fbbSHaijun Zhang if (host->ops->adma_workaround) 3195a4071fbbSHaijun Zhang host->ops->adma_workaround(host, intmask); 31966882a8c0SBen Dooks } 31971c6a0718SPierre Ossman 319817b0429dSPierre Ossman if (host->data->error) 31991c6a0718SPierre Ossman sdhci_finish_data(host); 32001c6a0718SPierre Ossman else { 32011c6a0718SPierre Ossman if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 32021c6a0718SPierre Ossman sdhci_transfer_pio(host); 32031c6a0718SPierre Ossman 32046ba736a1SPierre Ossman /* 32056ba736a1SPierre Ossman * We currently don't do anything fancy with DMA 32066ba736a1SPierre Ossman * boundaries, but as we can't disable the feature 32076ba736a1SPierre Ossman * we need to at least restart the transfer. 3208f6a03cbfSMikko Vinni * 3209f6a03cbfSMikko Vinni * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 3210f6a03cbfSMikko Vinni * should return a valid address to continue from, but as 3211f6a03cbfSMikko Vinni * some controllers are faulty, don't trust them. 32126ba736a1SPierre Ossman */ 3213f6a03cbfSMikko Vinni if (intmask & SDHCI_INT_DMA_END) { 3214917a0c52SChunyan Zhang dma_addr_t dmastart, dmanow; 3215bd9b9027SLinus Walleij 3216bd9b9027SLinus Walleij dmastart = sdhci_sdma_address(host); 3217f6a03cbfSMikko Vinni dmanow = dmastart + host->data->bytes_xfered; 3218f6a03cbfSMikko Vinni /* 3219f6a03cbfSMikko Vinni * Force update to the next DMA block boundary. 3220f6a03cbfSMikko Vinni */ 3221f6a03cbfSMikko Vinni dmanow = (dmanow & 3222917a0c52SChunyan Zhang ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 3223f6a03cbfSMikko Vinni SDHCI_DEFAULT_BOUNDARY_SIZE; 3224f6a03cbfSMikko Vinni host->data->bytes_xfered = dmanow - dmastart; 3225917a0c52SChunyan Zhang DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", 3226917a0c52SChunyan Zhang &dmastart, host->data->bytes_xfered, &dmanow); 3227917a0c52SChunyan Zhang sdhci_set_sdma_addr(host, dmanow); 3228f6a03cbfSMikko Vinni } 32296ba736a1SPierre Ossman 3230e538fbe8SPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 32317c89a3d9SAdrian Hunter if (host->cmd == host->data_cmd) { 3232e538fbe8SPierre Ossman /* 3233e538fbe8SPierre Ossman * Data managed to finish before the 3234e538fbe8SPierre Ossman * command completed. Make sure we do 3235e538fbe8SPierre Ossman * things in the proper order. 3236e538fbe8SPierre Ossman */ 3237e538fbe8SPierre Ossman host->data_early = 1; 3238e538fbe8SPierre Ossman } else { 32391c6a0718SPierre Ossman sdhci_finish_data(host); 32401c6a0718SPierre Ossman } 32411c6a0718SPierre Ossman } 3242e538fbe8SPierre Ossman } 3243e538fbe8SPierre Ossman } 32441c6a0718SPierre Ossman 324519d2f695SAdrian Hunter static inline bool sdhci_defer_done(struct sdhci_host *host, 324619d2f695SAdrian Hunter struct mmc_request *mrq) 324719d2f695SAdrian Hunter { 324819d2f695SAdrian Hunter struct mmc_data *data = mrq->data; 324919d2f695SAdrian Hunter 325019d2f695SAdrian Hunter return host->pending_reset || 325119d2f695SAdrian Hunter ((host->flags & SDHCI_REQ_USE_DMA) && data && 325219d2f695SAdrian Hunter data->host_cookie == COOKIE_MAPPED); 325319d2f695SAdrian Hunter } 325419d2f695SAdrian Hunter 32551c6a0718SPierre Ossman static irqreturn_t sdhci_irq(int irq, void *dev_id) 32561c6a0718SPierre Ossman { 325719d2f695SAdrian Hunter struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0}; 3258781e989cSRussell King irqreturn_t result = IRQ_NONE; 32591c6a0718SPierre Ossman struct sdhci_host *host = dev_id; 326041005003SRussell King u32 intmask, mask, unexpected = 0; 3261781e989cSRussell King int max_loops = 16; 326219d2f695SAdrian Hunter int i; 32631c6a0718SPierre Ossman 32641c6a0718SPierre Ossman spin_lock(&host->lock); 32651c6a0718SPierre Ossman 3266af5d2b7bSUlf Hansson if (host->runtime_suspended) { 326766fd8ad5SAdrian Hunter spin_unlock(&host->lock); 3268655bca76SAdrian Hunter return IRQ_NONE; 326966fd8ad5SAdrian Hunter } 327066fd8ad5SAdrian Hunter 32714e4141a5SAnton Vorontsov intmask = sdhci_readl(host, SDHCI_INT_STATUS); 32721c6a0718SPierre Ossman if (!intmask || intmask == 0xffffffff) { 32731c6a0718SPierre Ossman result = IRQ_NONE; 32741c6a0718SPierre Ossman goto out; 32751c6a0718SPierre Ossman } 32761c6a0718SPierre Ossman 327741005003SRussell King do { 3278f12e39dbSAdrian Hunter DBG("IRQ status 0x%08x\n", intmask); 3279f12e39dbSAdrian Hunter 3280f12e39dbSAdrian Hunter if (host->ops->irq) { 3281f12e39dbSAdrian Hunter intmask = host->ops->irq(host, intmask); 3282f12e39dbSAdrian Hunter if (!intmask) 3283f12e39dbSAdrian Hunter goto cont; 3284f12e39dbSAdrian Hunter } 3285f12e39dbSAdrian Hunter 328641005003SRussell King /* Clear selected interrupts. */ 328741005003SRussell King mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 328841005003SRussell King SDHCI_INT_BUS_POWER); 328941005003SRussell King sdhci_writel(host, mask, SDHCI_INT_STATUS); 329041005003SRussell King 32911c6a0718SPierre Ossman if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 3292d25928d1SShawn Guo u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 3293d25928d1SShawn Guo SDHCI_CARD_PRESENT; 3294d25928d1SShawn Guo 3295d25928d1SShawn Guo /* 329641005003SRussell King * There is a observation on i.mx esdhc. INSERT 329741005003SRussell King * bit will be immediately set again when it gets 329841005003SRussell King * cleared, if a card is inserted. We have to mask 329941005003SRussell King * the irq to prevent interrupt storm which will 330041005003SRussell King * freeze the system. And the REMOVE gets the 330141005003SRussell King * same situation. 3302d25928d1SShawn Guo * 330341005003SRussell King * More testing are needed here to ensure it works 330441005003SRussell King * for other platforms though. 3305d25928d1SShawn Guo */ 3306b537f94cSRussell King host->ier &= ~(SDHCI_INT_CARD_INSERT | 3307d25928d1SShawn Guo SDHCI_INT_CARD_REMOVE); 3308b537f94cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 3309b537f94cSRussell King SDHCI_INT_CARD_INSERT; 3310b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3311b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3312d25928d1SShawn Guo 33134e4141a5SAnton Vorontsov sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 33144e4141a5SAnton Vorontsov SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 33153560db8eSRussell King 33163560db8eSRussell King host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 33173560db8eSRussell King SDHCI_INT_CARD_REMOVE); 33183560db8eSRussell King result = IRQ_WAKE_THREAD; 33191c6a0718SPierre Ossman } 33201c6a0718SPierre Ossman 332141005003SRussell King if (intmask & SDHCI_INT_CMD_MASK) 33224bf78099SAdrian Hunter sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask); 33231c6a0718SPierre Ossman 332441005003SRussell King if (intmask & SDHCI_INT_DATA_MASK) 33251c6a0718SPierre Ossman sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 33261c6a0718SPierre Ossman 332741005003SRussell King if (intmask & SDHCI_INT_BUS_POWER) 3328a3c76eb9SGirish K S pr_err("%s: Card is consuming too much power!\n", 33291c6a0718SPierre Ossman mmc_hostname(host->mmc)); 33301c6a0718SPierre Ossman 3331f37b20ebSDong Aisheng if (intmask & SDHCI_INT_RETUNE) 3332f37b20ebSDong Aisheng mmc_retune_needed(host->mmc); 3333f37b20ebSDong Aisheng 3334161e6d44SGabriel Krisman Bertazi if ((intmask & SDHCI_INT_CARD_INT) && 3335161e6d44SGabriel Krisman Bertazi (host->ier & SDHCI_INT_CARD_INT)) { 3336781e989cSRussell King sdhci_enable_sdio_irq_nolock(host, false); 333789f3c365SAdrian Hunter sdio_signal_irq(host->mmc); 3338781e989cSRussell King } 3339f75979b7SPierre Ossman 334041005003SRussell King intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 334141005003SRussell King SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 334241005003SRussell King SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 3343f37b20ebSDong Aisheng SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 3344f75979b7SPierre Ossman 33451c6a0718SPierre Ossman if (intmask) { 33466379b237SAlexander Stein unexpected |= intmask; 33474e4141a5SAnton Vorontsov sdhci_writel(host, intmask, SDHCI_INT_STATUS); 33481c6a0718SPierre Ossman } 3349f12e39dbSAdrian Hunter cont: 3350781e989cSRussell King if (result == IRQ_NONE) 33511c6a0718SPierre Ossman result = IRQ_HANDLED; 33521c6a0718SPierre Ossman 33536379b237SAlexander Stein intmask = sdhci_readl(host, SDHCI_INT_STATUS); 335441005003SRussell King } while (intmask && --max_loops); 335519d2f695SAdrian Hunter 335619d2f695SAdrian Hunter /* Determine if mrqs can be completed immediately */ 335719d2f695SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 335819d2f695SAdrian Hunter struct mmc_request *mrq = host->mrqs_done[i]; 335919d2f695SAdrian Hunter 336019d2f695SAdrian Hunter if (!mrq) 336119d2f695SAdrian Hunter continue; 336219d2f695SAdrian Hunter 336319d2f695SAdrian Hunter if (sdhci_defer_done(host, mrq)) { 3364c07a48c2SAdrian Hunter result = IRQ_WAKE_THREAD; 336519d2f695SAdrian Hunter } else { 336619d2f695SAdrian Hunter mrqs_done[i] = mrq; 336719d2f695SAdrian Hunter host->mrqs_done[i] = NULL; 336819d2f695SAdrian Hunter } 336919d2f695SAdrian Hunter } 33701c6a0718SPierre Ossman out: 33711c6a0718SPierre Ossman spin_unlock(&host->lock); 33721c6a0718SPierre Ossman 337319d2f695SAdrian Hunter /* Process mrqs ready for immediate completion */ 337419d2f695SAdrian Hunter for (i = 0; i < SDHCI_MAX_MRQS; i++) { 337519d2f695SAdrian Hunter if (mrqs_done[i]) 337619d2f695SAdrian Hunter mmc_request_done(host->mmc, mrqs_done[i]); 337719d2f695SAdrian Hunter } 337819d2f695SAdrian Hunter 33796379b237SAlexander Stein if (unexpected) { 33806379b237SAlexander Stein pr_err("%s: Unexpected interrupt 0x%08x.\n", 33816379b237SAlexander Stein mmc_hostname(host->mmc), unexpected); 33826379b237SAlexander Stein sdhci_dumpregs(host); 33836379b237SAlexander Stein } 3384f75979b7SPierre Ossman 33851c6a0718SPierre Ossman return result; 33861c6a0718SPierre Ossman } 33871c6a0718SPierre Ossman 3388781e989cSRussell King static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 3389781e989cSRussell King { 3390781e989cSRussell King struct sdhci_host *host = dev_id; 3391781e989cSRussell King unsigned long flags; 3392781e989cSRussell King u32 isr; 3393781e989cSRussell King 3394c07a48c2SAdrian Hunter while (!sdhci_request_done(host)) 3395c07a48c2SAdrian Hunter ; 3396c07a48c2SAdrian Hunter 3397781e989cSRussell King spin_lock_irqsave(&host->lock, flags); 3398781e989cSRussell King isr = host->thread_isr; 3399781e989cSRussell King host->thread_isr = 0; 3400781e989cSRussell King spin_unlock_irqrestore(&host->lock, flags); 3401781e989cSRussell King 34023560db8eSRussell King if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 3403d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 3404d3940f27SAdrian Hunter 3405d3940f27SAdrian Hunter mmc->ops->card_event(mmc); 3406d3940f27SAdrian Hunter mmc_detect_change(mmc, msecs_to_jiffies(200)); 34073560db8eSRussell King } 34083560db8eSRussell King 3409c07a48c2SAdrian Hunter return IRQ_HANDLED; 3410781e989cSRussell King } 3411781e989cSRussell King 34121c6a0718SPierre Ossman /*****************************************************************************\ 34131c6a0718SPierre Ossman * * 34141c6a0718SPierre Ossman * Suspend/resume * 34151c6a0718SPierre Ossman * * 34161c6a0718SPierre Ossman \*****************************************************************************/ 34171c6a0718SPierre Ossman 34181c6a0718SPierre Ossman #ifdef CONFIG_PM 34199c316b38SAdrian Hunter 34209c316b38SAdrian Hunter static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host) 34219c316b38SAdrian Hunter { 34229c316b38SAdrian Hunter return mmc_card_is_removable(host->mmc) && 34239c316b38SAdrian Hunter !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 34249c316b38SAdrian Hunter !mmc_can_gpio_cd(host->mmc); 34259c316b38SAdrian Hunter } 34269c316b38SAdrian Hunter 342784d62605SLudovic Desroches /* 342884d62605SLudovic Desroches * To enable wakeup events, the corresponding events have to be enabled in 342984d62605SLudovic Desroches * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 343084d62605SLudovic Desroches * Table' in the SD Host Controller Standard Specification. 343184d62605SLudovic Desroches * It is useless to restore SDHCI_INT_ENABLE state in 343284d62605SLudovic Desroches * sdhci_disable_irq_wakeups() since it will be set by 343384d62605SLudovic Desroches * sdhci_enable_card_detection() or sdhci_init(). 343484d62605SLudovic Desroches */ 343558e79b60SAdrian Hunter static bool sdhci_enable_irq_wakeups(struct sdhci_host *host) 3436ad080d79SKevin Liu { 343781b14543SAdrian Hunter u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | 343881b14543SAdrian Hunter SDHCI_WAKE_ON_INT; 343981b14543SAdrian Hunter u32 irq_val = 0; 344081b14543SAdrian Hunter u8 wake_val = 0; 3441ad080d79SKevin Liu u8 val; 344281b14543SAdrian Hunter 34439c316b38SAdrian Hunter if (sdhci_cd_irq_can_wakeup(host)) { 344481b14543SAdrian Hunter wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE; 344581b14543SAdrian Hunter irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE; 344681b14543SAdrian Hunter } 344781b14543SAdrian Hunter 3448d5d568faSAdrian Hunter if (mmc_card_wake_sdio_irq(host->mmc)) { 344981b14543SAdrian Hunter wake_val |= SDHCI_WAKE_ON_INT; 345081b14543SAdrian Hunter irq_val |= SDHCI_INT_CARD_INT; 3451d5d568faSAdrian Hunter } 3452d5d568faSAdrian Hunter 3453d5d568faSAdrian Hunter if (!irq_val) 3454d5d568faSAdrian Hunter return false; 3455ad080d79SKevin Liu 3456ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 345781b14543SAdrian Hunter val &= ~mask; 345881b14543SAdrian Hunter val |= wake_val; 3459ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 346081b14543SAdrian Hunter 346184d62605SLudovic Desroches sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 346258e79b60SAdrian Hunter 346358e79b60SAdrian Hunter host->irq_wake_enabled = !enable_irq_wake(host->irq); 346458e79b60SAdrian Hunter 346558e79b60SAdrian Hunter return host->irq_wake_enabled; 3466ad080d79SKevin Liu } 3467ad080d79SKevin Liu 34680b10f478SFabio Estevam static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 3469ad080d79SKevin Liu { 3470ad080d79SKevin Liu u8 val; 3471ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 3472ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 3473ad080d79SKevin Liu 3474ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 3475ad080d79SKevin Liu val &= ~mask; 3476ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 347758e79b60SAdrian Hunter 347858e79b60SAdrian Hunter disable_irq_wake(host->irq); 347958e79b60SAdrian Hunter 348058e79b60SAdrian Hunter host->irq_wake_enabled = false; 3481ad080d79SKevin Liu } 34821c6a0718SPierre Ossman 348329495aa0SManuel Lauss int sdhci_suspend_host(struct sdhci_host *host) 34841c6a0718SPierre Ossman { 34857260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 34867260cf5eSAnton Vorontsov 348766c39dfcSAdrian Hunter mmc_retune_timer_stop(host->mmc); 3488cf2b5eeaSArindam Nath 348958e79b60SAdrian Hunter if (!device_may_wakeup(mmc_dev(host->mmc)) || 349058e79b60SAdrian Hunter !sdhci_enable_irq_wakeups(host)) { 3491b537f94cSRussell King host->ier = 0; 3492b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3493b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3494b8c86fc5SPierre Ossman free_irq(host->irq, host); 3495ad080d79SKevin Liu } 349658e79b60SAdrian Hunter 34974ee14ec6SUlf Hansson return 0; 3498b8c86fc5SPierre Ossman } 3499b8c86fc5SPierre Ossman 3500b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_suspend_host); 3501b8c86fc5SPierre Ossman 3502b8c86fc5SPierre Ossman int sdhci_resume_host(struct sdhci_host *host) 3503b8c86fc5SPierre Ossman { 3504d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 35054ee14ec6SUlf Hansson int ret = 0; 3506b8c86fc5SPierre Ossman 3507a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3508b8c86fc5SPierre Ossman if (host->ops->enable_dma) 3509b8c86fc5SPierre Ossman host->ops->enable_dma(host); 3510b8c86fc5SPierre Ossman } 3511b8c86fc5SPierre Ossman 35126308d290SAdrian Hunter if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 35136308d290SAdrian Hunter (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 35146308d290SAdrian Hunter /* Card keeps power but host controller does not */ 35156308d290SAdrian Hunter sdhci_init(host, 0); 35166308d290SAdrian Hunter host->pwr = 0; 35176308d290SAdrian Hunter host->clock = 0; 3518d3940f27SAdrian Hunter mmc->ops->set_ios(mmc, &mmc->ios); 35196308d290SAdrian Hunter } else { 35202f4cbb3dSNicolas Pitre sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 35216308d290SAdrian Hunter } 3522b8c86fc5SPierre Ossman 352358e79b60SAdrian Hunter if (host->irq_wake_enabled) { 352458e79b60SAdrian Hunter sdhci_disable_irq_wakeups(host); 352558e79b60SAdrian Hunter } else { 352614a7b416SHaibo Chen ret = request_threaded_irq(host->irq, sdhci_irq, 352714a7b416SHaibo Chen sdhci_thread_irq, IRQF_SHARED, 352814a7b416SHaibo Chen mmc_hostname(host->mmc), host); 352914a7b416SHaibo Chen if (ret) 353014a7b416SHaibo Chen return ret; 353114a7b416SHaibo Chen } 353214a7b416SHaibo Chen 35337260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 35347260cf5eSAnton Vorontsov 35352f4cbb3dSNicolas Pitre return ret; 35361c6a0718SPierre Ossman } 35371c6a0718SPierre Ossman 3538b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_resume_host); 353966fd8ad5SAdrian Hunter 354066fd8ad5SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host) 354166fd8ad5SAdrian Hunter { 354266fd8ad5SAdrian Hunter unsigned long flags; 354366fd8ad5SAdrian Hunter 354466c39dfcSAdrian Hunter mmc_retune_timer_stop(host->mmc); 354566fd8ad5SAdrian Hunter 354666fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 3547b537f94cSRussell King host->ier &= SDHCI_INT_CARD_INT; 3548b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3549b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 355066fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 355166fd8ad5SAdrian Hunter 3552781e989cSRussell King synchronize_hardirq(host->irq); 355366fd8ad5SAdrian Hunter 355466fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 355566fd8ad5SAdrian Hunter host->runtime_suspended = true; 355666fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 355766fd8ad5SAdrian Hunter 35588a125badSMarkus Pargmann return 0; 355966fd8ad5SAdrian Hunter } 356066fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 356166fd8ad5SAdrian Hunter 3562c6303c5dSBaolin Wang int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset) 356366fd8ad5SAdrian Hunter { 3564d3940f27SAdrian Hunter struct mmc_host *mmc = host->mmc; 356566fd8ad5SAdrian Hunter unsigned long flags; 35668a125badSMarkus Pargmann int host_flags = host->flags; 356766fd8ad5SAdrian Hunter 356866fd8ad5SAdrian Hunter if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 356966fd8ad5SAdrian Hunter if (host->ops->enable_dma) 357066fd8ad5SAdrian Hunter host->ops->enable_dma(host); 357166fd8ad5SAdrian Hunter } 357266fd8ad5SAdrian Hunter 3573c6303c5dSBaolin Wang sdhci_init(host, soft_reset); 357466fd8ad5SAdrian Hunter 357570bc85adSZhoujie Wu if (mmc->ios.power_mode != MMC_POWER_UNDEFINED && 357670bc85adSZhoujie Wu mmc->ios.power_mode != MMC_POWER_OFF) { 357766fd8ad5SAdrian Hunter /* Force clock and power re-program */ 357866fd8ad5SAdrian Hunter host->pwr = 0; 357966fd8ad5SAdrian Hunter host->clock = 0; 3580d3940f27SAdrian Hunter mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 3581d3940f27SAdrian Hunter mmc->ops->set_ios(mmc, &mmc->ios); 358266fd8ad5SAdrian Hunter 358352983382SKevin Liu if ((host_flags & SDHCI_PV_ENABLED) && 358452983382SKevin Liu !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 358552983382SKevin Liu spin_lock_irqsave(&host->lock, flags); 358652983382SKevin Liu sdhci_enable_preset_value(host, true); 358752983382SKevin Liu spin_unlock_irqrestore(&host->lock, flags); 358852983382SKevin Liu } 358966fd8ad5SAdrian Hunter 3590086b0ddbSAdrian Hunter if ((mmc->caps2 & MMC_CAP2_HS400_ES) && 3591086b0ddbSAdrian Hunter mmc->ops->hs400_enhanced_strobe) 3592086b0ddbSAdrian Hunter mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); 359384ec048bSAdrian Hunter } 3594086b0ddbSAdrian Hunter 359566fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 359666fd8ad5SAdrian Hunter 359766fd8ad5SAdrian Hunter host->runtime_suspended = false; 359866fd8ad5SAdrian Hunter 359966fd8ad5SAdrian Hunter /* Enable SDIO IRQ */ 36000e62614bSUlf Hansson if (sdio_irq_claimed(mmc)) 360166fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 360266fd8ad5SAdrian Hunter 360366fd8ad5SAdrian Hunter /* Enable Card Detection */ 360466fd8ad5SAdrian Hunter sdhci_enable_card_detection(host); 360566fd8ad5SAdrian Hunter 360666fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 360766fd8ad5SAdrian Hunter 36088a125badSMarkus Pargmann return 0; 360966fd8ad5SAdrian Hunter } 361066fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 361166fd8ad5SAdrian Hunter 3612162d6f98SRafael J. Wysocki #endif /* CONFIG_PM */ 361366fd8ad5SAdrian Hunter 36141c6a0718SPierre Ossman /*****************************************************************************\ 36151c6a0718SPierre Ossman * * 3616f12e39dbSAdrian Hunter * Command Queue Engine (CQE) helpers * 3617f12e39dbSAdrian Hunter * * 3618f12e39dbSAdrian Hunter \*****************************************************************************/ 3619f12e39dbSAdrian Hunter 3620f12e39dbSAdrian Hunter void sdhci_cqe_enable(struct mmc_host *mmc) 3621f12e39dbSAdrian Hunter { 3622f12e39dbSAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 3623f12e39dbSAdrian Hunter unsigned long flags; 3624f12e39dbSAdrian Hunter u8 ctrl; 3625f12e39dbSAdrian Hunter 3626f12e39dbSAdrian Hunter spin_lock_irqsave(&host->lock, flags); 3627f12e39dbSAdrian Hunter 3628f12e39dbSAdrian Hunter ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3629f12e39dbSAdrian Hunter ctrl &= ~SDHCI_CTRL_DMA_MASK; 36304c4faff6SSowjanya Komatineni /* 36314c4faff6SSowjanya Komatineni * Host from V4.10 supports ADMA3 DMA type. 36324c4faff6SSowjanya Komatineni * ADMA3 performs integrated descriptor which is more suitable 36334c4faff6SSowjanya Komatineni * for cmd queuing to fetch both command and transfer descriptors. 36344c4faff6SSowjanya Komatineni */ 36354c4faff6SSowjanya Komatineni if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3)) 36364c4faff6SSowjanya Komatineni ctrl |= SDHCI_CTRL_ADMA3; 36374c4faff6SSowjanya Komatineni else if (host->flags & SDHCI_USE_64_BIT_DMA) 3638f12e39dbSAdrian Hunter ctrl |= SDHCI_CTRL_ADMA64; 3639f12e39dbSAdrian Hunter else 3640f12e39dbSAdrian Hunter ctrl |= SDHCI_CTRL_ADMA32; 3641f12e39dbSAdrian Hunter sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3642f12e39dbSAdrian Hunter 3643c846a00fSSrinivas Kandagatla sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512), 3644f12e39dbSAdrian Hunter SDHCI_BLOCK_SIZE); 3645f12e39dbSAdrian Hunter 3646f12e39dbSAdrian Hunter /* Set maximum timeout */ 3647401059dfSBOUGH CHEN sdhci_set_timeout(host, NULL); 3648f12e39dbSAdrian Hunter 3649f12e39dbSAdrian Hunter host->ier = host->cqe_ier; 3650f12e39dbSAdrian Hunter 3651f12e39dbSAdrian Hunter sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3652f12e39dbSAdrian Hunter sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3653f12e39dbSAdrian Hunter 3654f12e39dbSAdrian Hunter host->cqe_on = true; 3655f12e39dbSAdrian Hunter 3656f12e39dbSAdrian Hunter pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n", 3657f12e39dbSAdrian Hunter mmc_hostname(mmc), host->ier, 3658f12e39dbSAdrian Hunter sdhci_readl(host, SDHCI_INT_STATUS)); 3659f12e39dbSAdrian Hunter 3660f12e39dbSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 3661f12e39dbSAdrian Hunter } 3662f12e39dbSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cqe_enable); 3663f12e39dbSAdrian Hunter 3664f12e39dbSAdrian Hunter void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery) 3665f12e39dbSAdrian Hunter { 3666f12e39dbSAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 3667f12e39dbSAdrian Hunter unsigned long flags; 3668f12e39dbSAdrian Hunter 3669f12e39dbSAdrian Hunter spin_lock_irqsave(&host->lock, flags); 3670f12e39dbSAdrian Hunter 3671f12e39dbSAdrian Hunter sdhci_set_default_irqs(host); 3672f12e39dbSAdrian Hunter 3673f12e39dbSAdrian Hunter host->cqe_on = false; 3674f12e39dbSAdrian Hunter 3675f12e39dbSAdrian Hunter if (recovery) { 3676f12e39dbSAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_CMD); 3677f12e39dbSAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_DATA); 3678f12e39dbSAdrian Hunter } 3679f12e39dbSAdrian Hunter 3680f12e39dbSAdrian Hunter pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n", 3681f12e39dbSAdrian Hunter mmc_hostname(mmc), host->ier, 3682f12e39dbSAdrian Hunter sdhci_readl(host, SDHCI_INT_STATUS)); 3683f12e39dbSAdrian Hunter 3684f12e39dbSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 3685f12e39dbSAdrian Hunter } 3686f12e39dbSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cqe_disable); 3687f12e39dbSAdrian Hunter 3688f12e39dbSAdrian Hunter bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 3689f12e39dbSAdrian Hunter int *data_error) 3690f12e39dbSAdrian Hunter { 3691f12e39dbSAdrian Hunter u32 mask; 3692f12e39dbSAdrian Hunter 3693f12e39dbSAdrian Hunter if (!host->cqe_on) 3694f12e39dbSAdrian Hunter return false; 3695f12e39dbSAdrian Hunter 3696f12e39dbSAdrian Hunter if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) 3697f12e39dbSAdrian Hunter *cmd_error = -EILSEQ; 3698f12e39dbSAdrian Hunter else if (intmask & SDHCI_INT_TIMEOUT) 3699f12e39dbSAdrian Hunter *cmd_error = -ETIMEDOUT; 3700f12e39dbSAdrian Hunter else 3701f12e39dbSAdrian Hunter *cmd_error = 0; 3702f12e39dbSAdrian Hunter 3703f12e39dbSAdrian Hunter if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) 3704f12e39dbSAdrian Hunter *data_error = -EILSEQ; 3705f12e39dbSAdrian Hunter else if (intmask & SDHCI_INT_DATA_TIMEOUT) 3706f12e39dbSAdrian Hunter *data_error = -ETIMEDOUT; 3707f12e39dbSAdrian Hunter else if (intmask & SDHCI_INT_ADMA_ERROR) 3708f12e39dbSAdrian Hunter *data_error = -EIO; 3709f12e39dbSAdrian Hunter else 3710f12e39dbSAdrian Hunter *data_error = 0; 3711f12e39dbSAdrian Hunter 3712f12e39dbSAdrian Hunter /* Clear selected interrupts. */ 3713f12e39dbSAdrian Hunter mask = intmask & host->cqe_ier; 3714f12e39dbSAdrian Hunter sdhci_writel(host, mask, SDHCI_INT_STATUS); 3715f12e39dbSAdrian Hunter 3716f12e39dbSAdrian Hunter if (intmask & SDHCI_INT_BUS_POWER) 3717f12e39dbSAdrian Hunter pr_err("%s: Card is consuming too much power!\n", 3718f12e39dbSAdrian Hunter mmc_hostname(host->mmc)); 3719f12e39dbSAdrian Hunter 3720f12e39dbSAdrian Hunter intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR); 3721f12e39dbSAdrian Hunter if (intmask) { 3722f12e39dbSAdrian Hunter sdhci_writel(host, intmask, SDHCI_INT_STATUS); 3723f12e39dbSAdrian Hunter pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n", 3724f12e39dbSAdrian Hunter mmc_hostname(host->mmc), intmask); 3725f12e39dbSAdrian Hunter sdhci_dumpregs(host); 3726f12e39dbSAdrian Hunter } 3727f12e39dbSAdrian Hunter 3728f12e39dbSAdrian Hunter return true; 3729f12e39dbSAdrian Hunter } 3730f12e39dbSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cqe_irq); 3731f12e39dbSAdrian Hunter 3732f12e39dbSAdrian Hunter /*****************************************************************************\ 3733f12e39dbSAdrian Hunter * * 3734b8c86fc5SPierre Ossman * Device allocation/registration * 37351c6a0718SPierre Ossman * * 37361c6a0718SPierre Ossman \*****************************************************************************/ 37371c6a0718SPierre Ossman 3738b8c86fc5SPierre Ossman struct sdhci_host *sdhci_alloc_host(struct device *dev, 3739b8c86fc5SPierre Ossman size_t priv_size) 37401c6a0718SPierre Ossman { 37411c6a0718SPierre Ossman struct mmc_host *mmc; 37421c6a0718SPierre Ossman struct sdhci_host *host; 37431c6a0718SPierre Ossman 3744b8c86fc5SPierre Ossman WARN_ON(dev == NULL); 37451c6a0718SPierre Ossman 3746b8c86fc5SPierre Ossman mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 37471c6a0718SPierre Ossman if (!mmc) 3748b8c86fc5SPierre Ossman return ERR_PTR(-ENOMEM); 37491c6a0718SPierre Ossman 37501c6a0718SPierre Ossman host = mmc_priv(mmc); 37511c6a0718SPierre Ossman host->mmc = mmc; 3752bf60e592SAdrian Hunter host->mmc_host_ops = sdhci_ops; 3753bf60e592SAdrian Hunter mmc->ops = &host->mmc_host_ops; 37541c6a0718SPierre Ossman 37558cb851a4SAdrian Hunter host->flags = SDHCI_SIGNALING_330; 37568cb851a4SAdrian Hunter 3757f12e39dbSAdrian Hunter host->cqe_ier = SDHCI_CQE_INT_MASK; 3758f12e39dbSAdrian Hunter host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK; 3759f12e39dbSAdrian Hunter 376083b600b8SAdrian Hunter host->tuning_delay = -1; 37611d8cd065SSowjanya Komatineni host->tuning_loop_count = MAX_TUNING_LOOP; 376283b600b8SAdrian Hunter 3763c846a00fSSrinivas Kandagatla host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG; 3764c846a00fSSrinivas Kandagatla 3765e93be38aSJisheng Zhang /* 3766e93be38aSJisheng Zhang * The DMA table descriptor count is calculated as the maximum 3767e93be38aSJisheng Zhang * number of segments times 2, to allow for an alignment 3768e93be38aSJisheng Zhang * descriptor for each segment, plus 1 for a nop end descriptor. 3769e93be38aSJisheng Zhang */ 3770e93be38aSJisheng Zhang host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1; 3771e93be38aSJisheng Zhang 3772b8c86fc5SPierre Ossman return host; 37731c6a0718SPierre Ossman } 37741c6a0718SPierre Ossman 3775b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_alloc_host); 3776b8c86fc5SPierre Ossman 37777b91369bSAlexandre Courbot static int sdhci_set_dma_mask(struct sdhci_host *host) 37787b91369bSAlexandre Courbot { 37797b91369bSAlexandre Courbot struct mmc_host *mmc = host->mmc; 37807b91369bSAlexandre Courbot struct device *dev = mmc_dev(mmc); 37817b91369bSAlexandre Courbot int ret = -EINVAL; 37827b91369bSAlexandre Courbot 37837b91369bSAlexandre Courbot if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 37847b91369bSAlexandre Courbot host->flags &= ~SDHCI_USE_64_BIT_DMA; 37857b91369bSAlexandre Courbot 37867b91369bSAlexandre Courbot /* Try 64-bit mask if hardware is capable of it */ 37877b91369bSAlexandre Courbot if (host->flags & SDHCI_USE_64_BIT_DMA) { 37887b91369bSAlexandre Courbot ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 37897b91369bSAlexandre Courbot if (ret) { 37907b91369bSAlexandre Courbot pr_warn("%s: Failed to set 64-bit DMA mask.\n", 37917b91369bSAlexandre Courbot mmc_hostname(mmc)); 37927b91369bSAlexandre Courbot host->flags &= ~SDHCI_USE_64_BIT_DMA; 37937b91369bSAlexandre Courbot } 37947b91369bSAlexandre Courbot } 37957b91369bSAlexandre Courbot 37967b91369bSAlexandre Courbot /* 32-bit mask as default & fallback */ 37977b91369bSAlexandre Courbot if (ret) { 37987b91369bSAlexandre Courbot ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 37997b91369bSAlexandre Courbot if (ret) 38007b91369bSAlexandre Courbot pr_warn("%s: Failed to set 32-bit DMA mask.\n", 38017b91369bSAlexandre Courbot mmc_hostname(mmc)); 38027b91369bSAlexandre Courbot } 38037b91369bSAlexandre Courbot 38047b91369bSAlexandre Courbot return ret; 38057b91369bSAlexandre Courbot } 38067b91369bSAlexandre Courbot 38078784edc8SMasahiro Yamada void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 38088784edc8SMasahiro Yamada const u32 *caps, const u32 *caps1) 38096132a3bfSAdrian Hunter { 38106132a3bfSAdrian Hunter u16 v; 381192e0c44bSZach Brown u64 dt_caps_mask = 0; 381292e0c44bSZach Brown u64 dt_caps = 0; 38136132a3bfSAdrian Hunter 38146132a3bfSAdrian Hunter if (host->read_caps) 38156132a3bfSAdrian Hunter return; 38166132a3bfSAdrian Hunter 38176132a3bfSAdrian Hunter host->read_caps = true; 38186132a3bfSAdrian Hunter 38196132a3bfSAdrian Hunter if (debug_quirks) 38206132a3bfSAdrian Hunter host->quirks = debug_quirks; 38216132a3bfSAdrian Hunter 38226132a3bfSAdrian Hunter if (debug_quirks2) 38236132a3bfSAdrian Hunter host->quirks2 = debug_quirks2; 38246132a3bfSAdrian Hunter 38256132a3bfSAdrian Hunter sdhci_do_reset(host, SDHCI_RESET_ALL); 38266132a3bfSAdrian Hunter 3827b3f80b43SChunyan Zhang if (host->v4_mode) 3828b3f80b43SChunyan Zhang sdhci_do_enable_v4_mode(host); 3829b3f80b43SChunyan Zhang 383092e0c44bSZach Brown of_property_read_u64(mmc_dev(host->mmc)->of_node, 383192e0c44bSZach Brown "sdhci-caps-mask", &dt_caps_mask); 383292e0c44bSZach Brown of_property_read_u64(mmc_dev(host->mmc)->of_node, 383392e0c44bSZach Brown "sdhci-caps", &dt_caps); 383492e0c44bSZach Brown 38356132a3bfSAdrian Hunter v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 38366132a3bfSAdrian Hunter host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 38376132a3bfSAdrian Hunter 38386132a3bfSAdrian Hunter if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 38396132a3bfSAdrian Hunter return; 38406132a3bfSAdrian Hunter 384192e0c44bSZach Brown if (caps) { 384292e0c44bSZach Brown host->caps = *caps; 384392e0c44bSZach Brown } else { 384492e0c44bSZach Brown host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 384592e0c44bSZach Brown host->caps &= ~lower_32_bits(dt_caps_mask); 384692e0c44bSZach Brown host->caps |= lower_32_bits(dt_caps); 384792e0c44bSZach Brown } 38486132a3bfSAdrian Hunter 38496132a3bfSAdrian Hunter if (host->version < SDHCI_SPEC_300) 38506132a3bfSAdrian Hunter return; 38516132a3bfSAdrian Hunter 385292e0c44bSZach Brown if (caps1) { 385392e0c44bSZach Brown host->caps1 = *caps1; 385492e0c44bSZach Brown } else { 385592e0c44bSZach Brown host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 385692e0c44bSZach Brown host->caps1 &= ~upper_32_bits(dt_caps_mask); 385792e0c44bSZach Brown host->caps1 |= upper_32_bits(dt_caps); 385892e0c44bSZach Brown } 38596132a3bfSAdrian Hunter } 38606132a3bfSAdrian Hunter EXPORT_SYMBOL_GPL(__sdhci_read_caps); 38616132a3bfSAdrian Hunter 3862a68dd9a0SChunyan Zhang static void sdhci_allocate_bounce_buffer(struct sdhci_host *host) 3863bd9b9027SLinus Walleij { 3864bd9b9027SLinus Walleij struct mmc_host *mmc = host->mmc; 3865bd9b9027SLinus Walleij unsigned int max_blocks; 3866bd9b9027SLinus Walleij unsigned int bounce_size; 3867bd9b9027SLinus Walleij int ret; 3868bd9b9027SLinus Walleij 3869bd9b9027SLinus Walleij /* 3870bd9b9027SLinus Walleij * Cap the bounce buffer at 64KB. Using a bigger bounce buffer 3871bd9b9027SLinus Walleij * has diminishing returns, this is probably because SD/MMC 3872bd9b9027SLinus Walleij * cards are usually optimized to handle this size of requests. 3873bd9b9027SLinus Walleij */ 3874bd9b9027SLinus Walleij bounce_size = SZ_64K; 3875bd9b9027SLinus Walleij /* 3876bd9b9027SLinus Walleij * Adjust downwards to maximum request size if this is less 3877bd9b9027SLinus Walleij * than our segment size, else hammer down the maximum 3878bd9b9027SLinus Walleij * request size to the maximum buffer size. 3879bd9b9027SLinus Walleij */ 3880bd9b9027SLinus Walleij if (mmc->max_req_size < bounce_size) 3881bd9b9027SLinus Walleij bounce_size = mmc->max_req_size; 3882bd9b9027SLinus Walleij max_blocks = bounce_size / 512; 3883bd9b9027SLinus Walleij 3884bd9b9027SLinus Walleij /* 3885bd9b9027SLinus Walleij * When we just support one segment, we can get significant 3886bd9b9027SLinus Walleij * speedups by the help of a bounce buffer to group scattered 3887bd9b9027SLinus Walleij * reads/writes together. 3888bd9b9027SLinus Walleij */ 3889bd9b9027SLinus Walleij host->bounce_buffer = devm_kmalloc(mmc->parent, 3890bd9b9027SLinus Walleij bounce_size, 3891bd9b9027SLinus Walleij GFP_KERNEL); 3892bd9b9027SLinus Walleij if (!host->bounce_buffer) { 3893bd9b9027SLinus Walleij pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n", 3894bd9b9027SLinus Walleij mmc_hostname(mmc), 3895bd9b9027SLinus Walleij bounce_size); 3896bd9b9027SLinus Walleij /* 3897bd9b9027SLinus Walleij * Exiting with zero here makes sure we proceed with 3898bd9b9027SLinus Walleij * mmc->max_segs == 1. 3899bd9b9027SLinus Walleij */ 3900a68dd9a0SChunyan Zhang return; 3901bd9b9027SLinus Walleij } 3902bd9b9027SLinus Walleij 3903bd9b9027SLinus Walleij host->bounce_addr = dma_map_single(mmc->parent, 3904bd9b9027SLinus Walleij host->bounce_buffer, 3905bd9b9027SLinus Walleij bounce_size, 3906bd9b9027SLinus Walleij DMA_BIDIRECTIONAL); 3907bd9b9027SLinus Walleij ret = dma_mapping_error(mmc->parent, host->bounce_addr); 3908bd9b9027SLinus Walleij if (ret) 3909bd9b9027SLinus Walleij /* Again fall back to max_segs == 1 */ 3910a68dd9a0SChunyan Zhang return; 3911bd9b9027SLinus Walleij host->bounce_buffer_size = bounce_size; 3912bd9b9027SLinus Walleij 3913bd9b9027SLinus Walleij /* Lie about this since we're bouncing */ 3914bd9b9027SLinus Walleij mmc->max_segs = max_blocks; 3915bd9b9027SLinus Walleij mmc->max_seg_size = bounce_size; 3916bd9b9027SLinus Walleij mmc->max_req_size = bounce_size; 3917bd9b9027SLinus Walleij 3918bd9b9027SLinus Walleij pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n", 3919bd9b9027SLinus Walleij mmc_hostname(mmc), max_blocks, bounce_size); 3920bd9b9027SLinus Walleij } 3921bd9b9027SLinus Walleij 3922685e444bSChunyan Zhang static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) 3923685e444bSChunyan Zhang { 3924685e444bSChunyan Zhang /* 3925685e444bSChunyan Zhang * According to SD Host Controller spec v4.10, bit[27] added from 3926685e444bSChunyan Zhang * version 4.10 in Capabilities Register is used as 64-bit System 3927685e444bSChunyan Zhang * Address support for V4 mode. 3928685e444bSChunyan Zhang */ 3929685e444bSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && host->v4_mode) 3930685e444bSChunyan Zhang return host->caps & SDHCI_CAN_64BIT_V4; 3931685e444bSChunyan Zhang 3932685e444bSChunyan Zhang return host->caps & SDHCI_CAN_64BIT; 3933685e444bSChunyan Zhang } 3934685e444bSChunyan Zhang 393552f5336dSAdrian Hunter int sdhci_setup_host(struct sdhci_host *host) 3936b8c86fc5SPierre Ossman { 3937b8c86fc5SPierre Ossman struct mmc_host *mmc; 3938f2119df6SArindam Nath u32 max_current_caps; 3939f2119df6SArindam Nath unsigned int ocr_avail; 3940f5fa92e5SAdrian Hunter unsigned int override_timeout_clk; 394159241757SDong Aisheng u32 max_clk; 3942b8c86fc5SPierre Ossman int ret; 3943b8c86fc5SPierre Ossman 3944b8c86fc5SPierre Ossman WARN_ON(host == NULL); 3945b8c86fc5SPierre Ossman if (host == NULL) 3946b8c86fc5SPierre Ossman return -EINVAL; 3947b8c86fc5SPierre Ossman 3948b8c86fc5SPierre Ossman mmc = host->mmc; 3949b8c86fc5SPierre Ossman 3950efba142bSJon Hunter /* 3951efba142bSJon Hunter * If there are external regulators, get them. Note this must be done 3952efba142bSJon Hunter * early before resetting the host and reading the capabilities so that 3953efba142bSJon Hunter * the host can take the appropriate action if regulators are not 3954efba142bSJon Hunter * available. 3955efba142bSJon Hunter */ 3956efba142bSJon Hunter ret = mmc_regulator_get_supply(mmc); 39572a63303dSWolfram Sang if (ret) 3958efba142bSJon Hunter return ret; 3959efba142bSJon Hunter 396006ebc601SShawn Lin DBG("Version: 0x%08x | Present: 0x%08x\n", 396106ebc601SShawn Lin sdhci_readw(host, SDHCI_HOST_VERSION), 396206ebc601SShawn Lin sdhci_readl(host, SDHCI_PRESENT_STATE)); 396306ebc601SShawn Lin DBG("Caps: 0x%08x | Caps_1: 0x%08x\n", 396406ebc601SShawn Lin sdhci_readl(host, SDHCI_CAPABILITIES), 396506ebc601SShawn Lin sdhci_readl(host, SDHCI_CAPABILITIES_1)); 396606ebc601SShawn Lin 39676132a3bfSAdrian Hunter sdhci_read_caps(host); 3968b8c86fc5SPierre Ossman 3969f5fa92e5SAdrian Hunter override_timeout_clk = host->timeout_clk; 3970f5fa92e5SAdrian Hunter 397118da1990SChunyan Zhang if (host->version > SDHCI_SPEC_420) { 39722e4456f0SMarek Vasut pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 39732e4456f0SMarek Vasut mmc_hostname(mmc), host->version); 39741c6a0718SPierre Ossman } 39751c6a0718SPierre Ossman 397675d27ea1SAdrian Hunter if (host->quirks & SDHCI_QUIRK_BROKEN_CQE) 397775d27ea1SAdrian Hunter mmc->caps2 &= ~MMC_CAP2_CQE; 397875d27ea1SAdrian Hunter 3979b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3980a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 398128da3589SAdrian Hunter else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3982a13abc7bSRichard Röjfors DBG("Controller doesn't have SDMA capability\n"); 39831c6a0718SPierre Ossman else 3984a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 39851c6a0718SPierre Ossman 3986b8c86fc5SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3987a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA)) { 3988cee687ceSRolf Eike Beer DBG("Disabling DMA as it is marked broken\n"); 3989a13abc7bSRichard Röjfors host->flags &= ~SDHCI_USE_SDMA; 39907c168e3dSFeng Tang } 39917c168e3dSFeng Tang 3992f2119df6SArindam Nath if ((host->version >= SDHCI_SPEC_200) && 399328da3589SAdrian Hunter (host->caps & SDHCI_CAN_DO_ADMA2)) 39942134a922SPierre Ossman host->flags |= SDHCI_USE_ADMA; 39952134a922SPierre Ossman 39962134a922SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 39972134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) { 39982134a922SPierre Ossman DBG("Disabling ADMA as it is marked broken\n"); 39992134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 40002134a922SPierre Ossman } 40012134a922SPierre Ossman 4002685e444bSChunyan Zhang if (sdhci_can_64bit_dma(host)) 4003e57a5f61SAdrian Hunter host->flags |= SDHCI_USE_64_BIT_DMA; 4004e57a5f61SAdrian Hunter 400518e762e3SChunyan Zhang if (host->use_external_dma) { 400618e762e3SChunyan Zhang ret = sdhci_external_dma_init(host); 400718e762e3SChunyan Zhang if (ret == -EPROBE_DEFER) 400818e762e3SChunyan Zhang goto unreg; 400918e762e3SChunyan Zhang /* 401018e762e3SChunyan Zhang * Fall back to use the DMA/PIO integrated in standard SDHCI 401118e762e3SChunyan Zhang * instead of external DMA devices. 401218e762e3SChunyan Zhang */ 401318e762e3SChunyan Zhang else if (ret) 401418e762e3SChunyan Zhang sdhci_switch_external_dma(host, false); 401518e762e3SChunyan Zhang /* Disable internal DMA sources */ 401618e762e3SChunyan Zhang else 401718e762e3SChunyan Zhang host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 401818e762e3SChunyan Zhang } 401918e762e3SChunyan Zhang 4020a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 40214ee7dde4SAdrian Hunter if (host->ops->set_dma_mask) 40224ee7dde4SAdrian Hunter ret = host->ops->set_dma_mask(host); 40234ee7dde4SAdrian Hunter else 40247b91369bSAlexandre Courbot ret = sdhci_set_dma_mask(host); 40257b91369bSAlexandre Courbot 40267b91369bSAlexandre Courbot if (!ret && host->ops->enable_dma) 40277b91369bSAlexandre Courbot ret = host->ops->enable_dma(host); 40287b91369bSAlexandre Courbot 40297b91369bSAlexandre Courbot if (ret) { 40306606110dSJoe Perches pr_warn("%s: No suitable DMA available - falling back to PIO\n", 4031b8c86fc5SPierre Ossman mmc_hostname(mmc)); 40327b91369bSAlexandre Courbot host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 40337b91369bSAlexandre Courbot 40347b91369bSAlexandre Courbot ret = 0; 40351c6a0718SPierre Ossman } 4036b8c86fc5SPierre Ossman } 40371c6a0718SPierre Ossman 4038917a0c52SChunyan Zhang /* SDMA does not support 64-bit DMA if v4 mode not set */ 4039917a0c52SChunyan Zhang if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) 4040e57a5f61SAdrian Hunter host->flags &= ~SDHCI_USE_SDMA; 4041e57a5f61SAdrian Hunter 40422134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 4043e66e61cbSRussell King dma_addr_t dma; 4044e66e61cbSRussell King void *buf; 4045e66e61cbSRussell King 4046e57a5f61SAdrian Hunter if (host->flags & SDHCI_USE_64_BIT_DMA) { 4047e93be38aSJisheng Zhang host->adma_table_sz = host->adma_table_cnt * 4048685e444bSChunyan Zhang SDHCI_ADMA2_64_DESC_SZ(host); 4049685e444bSChunyan Zhang host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); 4050e57a5f61SAdrian Hunter } else { 4051e93be38aSJisheng Zhang host->adma_table_sz = host->adma_table_cnt * 4052739d46dcSAdrian Hunter SDHCI_ADMA2_32_DESC_SZ; 4053739d46dcSAdrian Hunter host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 4054e57a5f61SAdrian Hunter } 4055e66e61cbSRussell King 405604a5ae6fSAdrian Hunter host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 4057685e444bSChunyan Zhang /* 4058685e444bSChunyan Zhang * Use zalloc to zero the reserved high 32-bits of 128-bit 4059685e444bSChunyan Zhang * descriptors so that they never need to be written. 4060685e444bSChunyan Zhang */ 4061750afb08SLuis Chamberlain buf = dma_alloc_coherent(mmc_dev(mmc), 4062750afb08SLuis Chamberlain host->align_buffer_sz + host->adma_table_sz, 4063750afb08SLuis Chamberlain &dma, GFP_KERNEL); 4064e66e61cbSRussell King if (!buf) { 40656606110dSJoe Perches pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 40662134a922SPierre Ossman mmc_hostname(mmc)); 40672134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 4068e66e61cbSRussell King } else if ((dma + host->align_buffer_sz) & 4069e66e61cbSRussell King (SDHCI_ADMA2_DESC_ALIGN - 1)) { 40706606110dSJoe Perches pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 4071d1e49f77SRussell King mmc_hostname(mmc)); 4072d1e49f77SRussell King host->flags &= ~SDHCI_USE_ADMA; 4073e66e61cbSRussell King dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 4074e66e61cbSRussell King host->adma_table_sz, buf, dma); 4075e66e61cbSRussell King } else { 4076e66e61cbSRussell King host->align_buffer = buf; 4077e66e61cbSRussell King host->align_addr = dma; 4078edd63fccSRussell King 4079e66e61cbSRussell King host->adma_table = buf + host->align_buffer_sz; 4080e66e61cbSRussell King host->adma_addr = dma + host->align_buffer_sz; 4081e66e61cbSRussell King } 40822134a922SPierre Ossman } 40832134a922SPierre Ossman 40847659150cSPierre Ossman /* 40857659150cSPierre Ossman * If we use DMA, then it's up to the caller to set the DMA 40867659150cSPierre Ossman * mask, but PIO does not need the hw shim so we set a new 40877659150cSPierre Ossman * mask here in that case. 40887659150cSPierre Ossman */ 4089a13abc7bSRichard Röjfors if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 40907659150cSPierre Ossman host->dma_mask = DMA_BIT_MASK(64); 40914e743f1fSMarkus Mayer mmc_dev(mmc)->dma_mask = &host->dma_mask; 40927659150cSPierre Ossman } 40931c6a0718SPierre Ossman 4094c4687d5fSZhangfei Gao if (host->version >= SDHCI_SPEC_300) 409528da3589SAdrian Hunter host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 4096c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 4097c4687d5fSZhangfei Gao else 409828da3589SAdrian Hunter host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 4099c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 4100c4687d5fSZhangfei Gao 41014240ff0aSBen Dooks host->max_clk *= 1000000; 4102f27f47efSAnton Vorontsov if (host->max_clk == 0 || host->quirks & 4103f27f47efSAnton Vorontsov SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 41044240ff0aSBen Dooks if (!host->ops->get_max_clock) { 41052e4456f0SMarek Vasut pr_err("%s: Hardware doesn't specify base clock frequency.\n", 41062e4456f0SMarek Vasut mmc_hostname(mmc)); 4107eb5c20deSAdrian Hunter ret = -ENODEV; 4108eb5c20deSAdrian Hunter goto undma; 41091c6a0718SPierre Ossman } 41104240ff0aSBen Dooks host->max_clk = host->ops->get_max_clock(host); 41114240ff0aSBen Dooks } 41121c6a0718SPierre Ossman 41131c6a0718SPierre Ossman /* 4114c3ed3877SArindam Nath * In case of Host Controller v3.00, find out whether clock 4115c3ed3877SArindam Nath * multiplier is supported. 4116c3ed3877SArindam Nath */ 411728da3589SAdrian Hunter host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 4118c3ed3877SArindam Nath SDHCI_CLOCK_MUL_SHIFT; 4119c3ed3877SArindam Nath 4120c3ed3877SArindam Nath /* 4121c3ed3877SArindam Nath * In case the value in Clock Multiplier is 0, then programmable 4122c3ed3877SArindam Nath * clock mode is not supported, otherwise the actual clock 4123c3ed3877SArindam Nath * multiplier is one more than the value of Clock Multiplier 4124c3ed3877SArindam Nath * in the Capabilities Register. 4125c3ed3877SArindam Nath */ 4126c3ed3877SArindam Nath if (host->clk_mul) 4127c3ed3877SArindam Nath host->clk_mul += 1; 4128c3ed3877SArindam Nath 4129c3ed3877SArindam Nath /* 41301c6a0718SPierre Ossman * Set host parameters. 41311c6a0718SPierre Ossman */ 413259241757SDong Aisheng max_clk = host->max_clk; 413359241757SDong Aisheng 4134ce5f036bSMarek Szyprowski if (host->ops->get_min_clock) 4135a9e58f25SAnton Vorontsov mmc->f_min = host->ops->get_min_clock(host); 4136c3ed3877SArindam Nath else if (host->version >= SDHCI_SPEC_300) { 41372a187d03SMichał Mirosław if (host->clk_mul) 413859241757SDong Aisheng max_clk = host->max_clk * host->clk_mul; 41392a187d03SMichał Mirosław /* 41402a187d03SMichał Mirosław * Divided Clock Mode minimum clock rate is always less than 41412a187d03SMichał Mirosław * Programmable Clock Mode minimum clock rate. 41422a187d03SMichał Mirosław */ 41430397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 4144c3ed3877SArindam Nath } else 41450397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 414615ec4461SPhilip Rakity 4147d310ae49SAdrian Hunter if (!mmc->f_max || mmc->f_max > max_clk) 414859241757SDong Aisheng mmc->f_max = max_clk; 414959241757SDong Aisheng 415028aab053SAisheng Dong if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 415128da3589SAdrian Hunter host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 415228aab053SAisheng Dong SDHCI_TIMEOUT_CLK_SHIFT; 41538cc35289SShawn Lin 41548cc35289SShawn Lin if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 41558cc35289SShawn Lin host->timeout_clk *= 1000; 41568cc35289SShawn Lin 4157272308caSAndy Shevchenko if (host->timeout_clk == 0) { 41588cc35289SShawn Lin if (!host->ops->get_timeout_clock) { 415928aab053SAisheng Dong pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 416028aab053SAisheng Dong mmc_hostname(mmc)); 4161eb5c20deSAdrian Hunter ret = -ENODEV; 4162eb5c20deSAdrian Hunter goto undma; 4163272308caSAndy Shevchenko } 416428aab053SAisheng Dong 41658cc35289SShawn Lin host->timeout_clk = 41668cc35289SShawn Lin DIV_ROUND_UP(host->ops->get_timeout_clock(host), 41678cc35289SShawn Lin 1000); 41688cc35289SShawn Lin } 4169272308caSAndy Shevchenko 417099513624SAdrian Hunter if (override_timeout_clk) 417199513624SAdrian Hunter host->timeout_clk = override_timeout_clk; 417299513624SAdrian Hunter 4173a6ff5aebSAisheng Dong mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 4174a6ff5aebSAisheng Dong host->ops->get_max_timeout_count(host) : 1 << 27; 4175a6ff5aebSAisheng Dong mmc->max_busy_timeout /= host->timeout_clk; 417628aab053SAisheng Dong } 417758d1246dSAdrian Hunter 4178a999fd93SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && 4179a999fd93SAdrian Hunter !host->ops->get_max_timeout_count) 4180a999fd93SAdrian Hunter mmc->max_busy_timeout = 0; 4181a999fd93SAdrian Hunter 4182e89d456fSAndrei Warkentin mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 4183781e989cSRussell King mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 4184e89d456fSAndrei Warkentin 4185e89d456fSAndrei Warkentin if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 4186e89d456fSAndrei Warkentin host->flags |= SDHCI_AUTO_CMD12; 41875fe23c7fSAnton Vorontsov 41887ed71a9dSChunyan Zhang /* 41897ed71a9dSChunyan Zhang * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO. 41907ed71a9dSChunyan Zhang * For v4 mode, SDMA may use Auto-CMD23 as well. 41917ed71a9dSChunyan Zhang */ 41924f3d3e9bSAndrei Warkentin if ((host->version >= SDHCI_SPEC_300) && 41938edf6371SAndrei Warkentin ((host->flags & SDHCI_USE_ADMA) || 41947ed71a9dSChunyan Zhang !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) && 41953bfa6f03SScott Branden !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 41968edf6371SAndrei Warkentin host->flags |= SDHCI_AUTO_CMD23; 4197f421865dSAdrian Hunter DBG("Auto-CMD23 available\n"); 41988edf6371SAndrei Warkentin } else { 4199f421865dSAdrian Hunter DBG("Auto-CMD23 unavailable\n"); 42008edf6371SAndrei Warkentin } 42018edf6371SAndrei Warkentin 420215ec4461SPhilip Rakity /* 420315ec4461SPhilip Rakity * A controller may support 8-bit width, but the board itself 420415ec4461SPhilip Rakity * might not have the pins brought out. Boards that support 420515ec4461SPhilip Rakity * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 420615ec4461SPhilip Rakity * their platform code before calling sdhci_add_host(), and we 420715ec4461SPhilip Rakity * won't assume 8-bit width for hosts without that CAP. 420815ec4461SPhilip Rakity */ 42095fe23c7fSAnton Vorontsov if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 421015ec4461SPhilip Rakity mmc->caps |= MMC_CAP_4_BIT_DATA; 42111c6a0718SPierre Ossman 421263ef5d8cSJerry Huang if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 421363ef5d8cSJerry Huang mmc->caps &= ~MMC_CAP_CMD23; 421463ef5d8cSJerry Huang 421528da3589SAdrian Hunter if (host->caps & SDHCI_CAN_DO_HISPD) 4216a29e7e18SZhangfei Gao mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 42171c6a0718SPierre Ossman 4218176d1ed4SJaehoon Chung if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 4219860951c5SJaehoon Chung mmc_card_is_removable(mmc) && 4220287980e4SArnd Bergmann mmc_gpio_get_cd(host->mmc) < 0) 422168d1fb7eSAnton Vorontsov mmc->caps |= MMC_CAP_NEEDS_POLL; 422268d1fb7eSAnton Vorontsov 42233a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 42243a48edc4STim Kryger ret = regulator_enable(mmc->supply.vqmmc); 42251b5190c2SStefan Agner 42261b5190c2SStefan Agner /* If vqmmc provides no 1.8V signalling, then there's no UHS */ 42273a48edc4STim Kryger if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 4228cec2e216SKevin Liu 1950000)) 422928da3589SAdrian Hunter host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 42308363c374SKevin Liu SDHCI_SUPPORT_SDR50 | 42316231f3deSPhilip Rakity SDHCI_SUPPORT_DDR50); 42321b5190c2SStefan Agner 42331b5190c2SStefan Agner /* In eMMC case vqmmc might be a fixed 1.8V regulator */ 42341b5190c2SStefan Agner if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, 42351b5190c2SStefan Agner 3600000)) 42361b5190c2SStefan Agner host->flags &= ~SDHCI_SIGNALING_330; 42371b5190c2SStefan Agner 4238a3361abaSChris Ball if (ret) { 4239a3361abaSChris Ball pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 4240a3361abaSChris Ball mmc_hostname(mmc), ret); 42414bb74313SAdrian Hunter mmc->supply.vqmmc = ERR_PTR(-EINVAL); 4242a3361abaSChris Ball } 42438363c374SKevin Liu } 42446231f3deSPhilip Rakity 424528da3589SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 424628da3589SAdrian Hunter host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 42476a66180aSDaniel Drake SDHCI_SUPPORT_DDR50); 4248c16bc9a7SKishon Vijay Abraham I /* 4249c16bc9a7SKishon Vijay Abraham I * The SDHCI controller in a SoC might support HS200/HS400 4250c16bc9a7SKishon Vijay Abraham I * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property), 4251c16bc9a7SKishon Vijay Abraham I * but if the board is modeled such that the IO lines are not 4252c16bc9a7SKishon Vijay Abraham I * connected to 1.8v then HS200/HS400 cannot be supported. 4253c16bc9a7SKishon Vijay Abraham I * Disable HS200/HS400 if the board does not have 1.8v connected 4254c16bc9a7SKishon Vijay Abraham I * to the IO lines. (Applicable for other modes in 1.8v) 4255c16bc9a7SKishon Vijay Abraham I */ 4256c16bc9a7SKishon Vijay Abraham I mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES); 4257c16bc9a7SKishon Vijay Abraham I mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS); 425828da3589SAdrian Hunter } 42596a66180aSDaniel Drake 42604188bba0SAl Cooper /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 426128da3589SAdrian Hunter if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 42624188bba0SAl Cooper SDHCI_SUPPORT_DDR50)) 4263f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 4264f2119df6SArindam Nath 4265f2119df6SArindam Nath /* SDR104 supports also implies SDR50 support */ 426628da3589SAdrian Hunter if (host->caps1 & SDHCI_SUPPORT_SDR104) { 4267f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 4268156e14b1SGiuseppe CAVALLARO /* SD3.0: SDR104 is supported so (for eMMC) the caps2 4269156e14b1SGiuseppe CAVALLARO * field can be promoted to support HS200. 4270156e14b1SGiuseppe CAVALLARO */ 4271549c0b18SAdrian Hunter if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 4272156e14b1SGiuseppe CAVALLARO mmc->caps2 |= MMC_CAP2_HS200; 427328da3589SAdrian Hunter } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 4274f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR50; 427528da3589SAdrian Hunter } 4276f2119df6SArindam Nath 4277e9fb05d5SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 427828da3589SAdrian Hunter (host->caps1 & SDHCI_SUPPORT_HS400)) 4279e9fb05d5SAdrian Hunter mmc->caps2 |= MMC_CAP2_HS400; 4280e9fb05d5SAdrian Hunter 4281549c0b18SAdrian Hunter if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 4282549c0b18SAdrian Hunter (IS_ERR(mmc->supply.vqmmc) || 4283549c0b18SAdrian Hunter !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 4284549c0b18SAdrian Hunter 1300000))) 4285549c0b18SAdrian Hunter mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 4286549c0b18SAdrian Hunter 428728da3589SAdrian Hunter if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 42889107ebbfSMicky Ching !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 4289f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_DDR50; 4290f2119df6SArindam Nath 4291069c9f14SGirish K S /* Does the host need tuning for SDR50? */ 429228da3589SAdrian Hunter if (host->caps1 & SDHCI_USE_SDR50_TUNING) 4293b513ea25SArindam Nath host->flags |= SDHCI_SDR50_NEEDS_TUNING; 4294b513ea25SArindam Nath 4295d6d50a15SArindam Nath /* Driver Type(s) (A, C, D) supported by the host */ 429628da3589SAdrian Hunter if (host->caps1 & SDHCI_DRIVER_TYPE_A) 4297d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 429828da3589SAdrian Hunter if (host->caps1 & SDHCI_DRIVER_TYPE_C) 4299d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 430028da3589SAdrian Hunter if (host->caps1 & SDHCI_DRIVER_TYPE_D) 4301d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 4302d6d50a15SArindam Nath 4303cf2b5eeaSArindam Nath /* Initial value for re-tuning timer count */ 430428da3589SAdrian Hunter host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 4305cf2b5eeaSArindam Nath SDHCI_RETUNING_TIMER_COUNT_SHIFT; 4306cf2b5eeaSArindam Nath 4307cf2b5eeaSArindam Nath /* 4308cf2b5eeaSArindam Nath * In case Re-tuning Timer is not disabled, the actual value of 4309cf2b5eeaSArindam Nath * re-tuning timer will be 2 ^ (n - 1). 4310cf2b5eeaSArindam Nath */ 4311cf2b5eeaSArindam Nath if (host->tuning_count) 4312cf2b5eeaSArindam Nath host->tuning_count = 1 << (host->tuning_count - 1); 4313cf2b5eeaSArindam Nath 4314cf2b5eeaSArindam Nath /* Re-tuning mode supported by the Host Controller */ 431528da3589SAdrian Hunter host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 4316cf2b5eeaSArindam Nath SDHCI_RETUNING_MODE_SHIFT; 4317cf2b5eeaSArindam Nath 43188f230f45STakashi Iwai ocr_avail = 0; 4319bad37e1aSPhilip Rakity 4320f2119df6SArindam Nath /* 4321f2119df6SArindam Nath * According to SD Host Controller spec v3.00, if the Host System 4322f2119df6SArindam Nath * can afford more than 150mA, Host Driver should set XPC to 1. Also 4323f2119df6SArindam Nath * the value is meaningful only if Voltage Support in the Capabilities 4324f2119df6SArindam Nath * register is set. The actual current value is 4 times the register 4325f2119df6SArindam Nath * value. 4326f2119df6SArindam Nath */ 4327f2119df6SArindam Nath max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 43283a48edc4STim Kryger if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 4329ae906037SChuanxiao.Dong int curr = regulator_get_current_limit(mmc->supply.vmmc); 4330bad37e1aSPhilip Rakity if (curr > 0) { 4331bad37e1aSPhilip Rakity 4332bad37e1aSPhilip Rakity /* convert to SDHCI_MAX_CURRENT format */ 4333bad37e1aSPhilip Rakity curr = curr/1000; /* convert to mA */ 4334bad37e1aSPhilip Rakity curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 4335bad37e1aSPhilip Rakity 4336bad37e1aSPhilip Rakity curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 4337bad37e1aSPhilip Rakity max_current_caps = 4338bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 4339bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 4340bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_180_SHIFT); 4341bad37e1aSPhilip Rakity } 4342bad37e1aSPhilip Rakity } 4343f2119df6SArindam Nath 434428da3589SAdrian Hunter if (host->caps & SDHCI_CAN_VDD_330) { 43458f230f45STakashi Iwai ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 4346f2119df6SArindam Nath 434755c4665eSAaron Lu mmc->max_current_330 = ((max_current_caps & 4348f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_MASK) >> 4349f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_SHIFT) * 4350f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 4351f2119df6SArindam Nath } 435228da3589SAdrian Hunter if (host->caps & SDHCI_CAN_VDD_300) { 43538f230f45STakashi Iwai ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 4354f2119df6SArindam Nath 435555c4665eSAaron Lu mmc->max_current_300 = ((max_current_caps & 4356f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_MASK) >> 4357f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_SHIFT) * 4358f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 4359f2119df6SArindam Nath } 436028da3589SAdrian Hunter if (host->caps & SDHCI_CAN_VDD_180) { 43618f230f45STakashi Iwai ocr_avail |= MMC_VDD_165_195; 43628f230f45STakashi Iwai 436355c4665eSAaron Lu mmc->max_current_180 = ((max_current_caps & 4364f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_MASK) >> 4365f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_SHIFT) * 4366f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 4367f2119df6SArindam Nath } 4368f2119df6SArindam Nath 43695fd26c7eSUlf Hansson /* If OCR set by host, use it instead. */ 43705fd26c7eSUlf Hansson if (host->ocr_mask) 43715fd26c7eSUlf Hansson ocr_avail = host->ocr_mask; 43725fd26c7eSUlf Hansson 43735fd26c7eSUlf Hansson /* If OCR set by external regulators, give it highest prio. */ 43743a48edc4STim Kryger if (mmc->ocr_avail) 437552221610STim Kryger ocr_avail = mmc->ocr_avail; 43763a48edc4STim Kryger 43778f230f45STakashi Iwai mmc->ocr_avail = ocr_avail; 43788f230f45STakashi Iwai mmc->ocr_avail_sdio = ocr_avail; 43798f230f45STakashi Iwai if (host->ocr_avail_sdio) 43808f230f45STakashi Iwai mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 43818f230f45STakashi Iwai mmc->ocr_avail_sd = ocr_avail; 43828f230f45STakashi Iwai if (host->ocr_avail_sd) 43838f230f45STakashi Iwai mmc->ocr_avail_sd &= host->ocr_avail_sd; 43848f230f45STakashi Iwai else /* normal SD controllers don't support 1.8V */ 43858f230f45STakashi Iwai mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 43868f230f45STakashi Iwai mmc->ocr_avail_mmc = ocr_avail; 43878f230f45STakashi Iwai if (host->ocr_avail_mmc) 43888f230f45STakashi Iwai mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 43891c6a0718SPierre Ossman 43901c6a0718SPierre Ossman if (mmc->ocr_avail == 0) { 43912e4456f0SMarek Vasut pr_err("%s: Hardware doesn't report any support voltages.\n", 43922e4456f0SMarek Vasut mmc_hostname(mmc)); 4393eb5c20deSAdrian Hunter ret = -ENODEV; 4394eb5c20deSAdrian Hunter goto unreg; 43951c6a0718SPierre Ossman } 43961c6a0718SPierre Ossman 43978cb851a4SAdrian Hunter if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 43988cb851a4SAdrian Hunter MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 43998cb851a4SAdrian Hunter MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 44008cb851a4SAdrian Hunter (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 44018cb851a4SAdrian Hunter host->flags |= SDHCI_SIGNALING_180; 44028cb851a4SAdrian Hunter 44038cb851a4SAdrian Hunter if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 44048cb851a4SAdrian Hunter host->flags |= SDHCI_SIGNALING_120; 44058cb851a4SAdrian Hunter 44061c6a0718SPierre Ossman spin_lock_init(&host->lock); 44071c6a0718SPierre Ossman 44081c6a0718SPierre Ossman /* 4409ac00531dSAdrian Hunter * Maximum number of sectors in one transfer. Limited by SDMA boundary 4410ac00531dSAdrian Hunter * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 4411ac00531dSAdrian Hunter * is less anyway. 44121c6a0718SPierre Ossman */ 44131c6a0718SPierre Ossman mmc->max_req_size = 524288; 44141c6a0718SPierre Ossman 44151c6a0718SPierre Ossman /* 4416250dcd11SUlf Hansson * Maximum number of segments. Depends on if the hardware 4417250dcd11SUlf Hansson * can do scatter/gather or not. 4418250dcd11SUlf Hansson */ 4419250dcd11SUlf Hansson if (host->flags & SDHCI_USE_ADMA) { 4420250dcd11SUlf Hansson mmc->max_segs = SDHCI_MAX_SEGS; 4421250dcd11SUlf Hansson } else if (host->flags & SDHCI_USE_SDMA) { 4422250dcd11SUlf Hansson mmc->max_segs = 1; 4423250dcd11SUlf Hansson if (swiotlb_max_segment()) { 4424250dcd11SUlf Hansson unsigned int max_req_size = (1 << IO_TLB_SHIFT) * 4425250dcd11SUlf Hansson IO_TLB_SEGSIZE; 4426250dcd11SUlf Hansson mmc->max_req_size = min(mmc->max_req_size, 4427250dcd11SUlf Hansson max_req_size); 4428250dcd11SUlf Hansson } 4429250dcd11SUlf Hansson } else { /* PIO */ 4430250dcd11SUlf Hansson mmc->max_segs = SDHCI_MAX_SEGS; 4431250dcd11SUlf Hansson } 4432250dcd11SUlf Hansson 4433250dcd11SUlf Hansson /* 44341c6a0718SPierre Ossman * Maximum segment size. Could be one segment with the maximum number 44352134a922SPierre Ossman * of bytes. When doing hardware scatter/gather, each entry cannot 44362134a922SPierre Ossman * be larger than 64 KiB though. 44371c6a0718SPierre Ossman */ 443830652aa3SOlof Johansson if (host->flags & SDHCI_USE_ADMA) { 443930652aa3SOlof Johansson if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 444030652aa3SOlof Johansson mmc->max_seg_size = 65535; 44412134a922SPierre Ossman else 444230652aa3SOlof Johansson mmc->max_seg_size = 65536; 444330652aa3SOlof Johansson } else { 44441c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 444530652aa3SOlof Johansson } 44461c6a0718SPierre Ossman 44471c6a0718SPierre Ossman /* 44481c6a0718SPierre Ossman * Maximum block size. This varies from controller to controller and 44491c6a0718SPierre Ossman * is specified in the capabilities register. 44501c6a0718SPierre Ossman */ 44510633f654SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 44520633f654SAnton Vorontsov mmc->max_blk_size = 2; 44530633f654SAnton Vorontsov } else { 445428da3589SAdrian Hunter mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 44550633f654SAnton Vorontsov SDHCI_MAX_BLOCK_SHIFT; 44561c6a0718SPierre Ossman if (mmc->max_blk_size >= 3) { 44576606110dSJoe Perches pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 44586606110dSJoe Perches mmc_hostname(mmc)); 44590633f654SAnton Vorontsov mmc->max_blk_size = 0; 44600633f654SAnton Vorontsov } 44610633f654SAnton Vorontsov } 44620633f654SAnton Vorontsov 44631c6a0718SPierre Ossman mmc->max_blk_size = 512 << mmc->max_blk_size; 44641c6a0718SPierre Ossman 44651c6a0718SPierre Ossman /* 44661c6a0718SPierre Ossman * Maximum block count. 44671c6a0718SPierre Ossman */ 44681388eefdSBen Dooks mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 44691c6a0718SPierre Ossman 4470a68dd9a0SChunyan Zhang if (mmc->max_segs == 1) 4471bd9b9027SLinus Walleij /* This may alter mmc->*_blk_* parameters */ 4472a68dd9a0SChunyan Zhang sdhci_allocate_bounce_buffer(host); 4473bd9b9027SLinus Walleij 447452f5336dSAdrian Hunter return 0; 447552f5336dSAdrian Hunter 447652f5336dSAdrian Hunter unreg: 447752f5336dSAdrian Hunter if (!IS_ERR(mmc->supply.vqmmc)) 447852f5336dSAdrian Hunter regulator_disable(mmc->supply.vqmmc); 447952f5336dSAdrian Hunter undma: 448052f5336dSAdrian Hunter if (host->align_buffer) 448152f5336dSAdrian Hunter dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 448252f5336dSAdrian Hunter host->adma_table_sz, host->align_buffer, 448352f5336dSAdrian Hunter host->align_addr); 448452f5336dSAdrian Hunter host->adma_table = NULL; 448552f5336dSAdrian Hunter host->align_buffer = NULL; 448652f5336dSAdrian Hunter 448752f5336dSAdrian Hunter return ret; 448852f5336dSAdrian Hunter } 448952f5336dSAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_setup_host); 449052f5336dSAdrian Hunter 44914180ffa8SAdrian Hunter void sdhci_cleanup_host(struct sdhci_host *host) 44924180ffa8SAdrian Hunter { 44934180ffa8SAdrian Hunter struct mmc_host *mmc = host->mmc; 44944180ffa8SAdrian Hunter 44954180ffa8SAdrian Hunter if (!IS_ERR(mmc->supply.vqmmc)) 44964180ffa8SAdrian Hunter regulator_disable(mmc->supply.vqmmc); 44974180ffa8SAdrian Hunter 44984180ffa8SAdrian Hunter if (host->align_buffer) 44994180ffa8SAdrian Hunter dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 45004180ffa8SAdrian Hunter host->adma_table_sz, host->align_buffer, 45014180ffa8SAdrian Hunter host->align_addr); 450218e762e3SChunyan Zhang 450318e762e3SChunyan Zhang if (host->use_external_dma) 450418e762e3SChunyan Zhang sdhci_external_dma_release(host); 450518e762e3SChunyan Zhang 45064180ffa8SAdrian Hunter host->adma_table = NULL; 45074180ffa8SAdrian Hunter host->align_buffer = NULL; 45084180ffa8SAdrian Hunter } 45094180ffa8SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_cleanup_host); 45104180ffa8SAdrian Hunter 451152f5336dSAdrian Hunter int __sdhci_add_host(struct sdhci_host *host) 451252f5336dSAdrian Hunter { 4513c07a48c2SAdrian Hunter unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI; 451452f5336dSAdrian Hunter struct mmc_host *mmc = host->mmc; 451552f5336dSAdrian Hunter int ret; 451652f5336dSAdrian Hunter 4517c07a48c2SAdrian Hunter host->complete_wq = alloc_workqueue("sdhci", flags, 0); 4518c07a48c2SAdrian Hunter if (!host->complete_wq) 4519c07a48c2SAdrian Hunter return -ENOMEM; 4520c07a48c2SAdrian Hunter 4521c07a48c2SAdrian Hunter INIT_WORK(&host->complete_work, sdhci_complete_work); 45221c6a0718SPierre Ossman 45232ee4f620SKees Cook timer_setup(&host->timer, sdhci_timeout_timer, 0); 45242ee4f620SKees Cook timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); 45251c6a0718SPierre Ossman 4526b513ea25SArindam Nath init_waitqueue_head(&host->buf_ready_int); 4527b513ea25SArindam Nath 45282af502caSShawn Guo sdhci_init(host, 0); 45292af502caSShawn Guo 4530781e989cSRussell King ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 4531781e989cSRussell King IRQF_SHARED, mmc_hostname(mmc), host); 45320fc81ee3SMark Brown if (ret) { 45330fc81ee3SMark Brown pr_err("%s: Failed to request IRQ %d: %d\n", 45340fc81ee3SMark Brown mmc_hostname(mmc), host->irq, ret); 4535c07a48c2SAdrian Hunter goto unwq; 45360fc81ee3SMark Brown } 45371c6a0718SPierre Ossman 4538061d17a6SAdrian Hunter ret = sdhci_led_register(host); 45390fc81ee3SMark Brown if (ret) { 45400fc81ee3SMark Brown pr_err("%s: Failed to register LED device: %d\n", 45410fc81ee3SMark Brown mmc_hostname(mmc), ret); 4542eb5c20deSAdrian Hunter goto unirq; 45430fc81ee3SMark Brown } 45442f730fecSPierre Ossman 4545eb5c20deSAdrian Hunter ret = mmc_add_host(mmc); 4546eb5c20deSAdrian Hunter if (ret) 4547eb5c20deSAdrian Hunter goto unled; 45481c6a0718SPierre Ossman 4549a3c76eb9SGirish K S pr_info("%s: SDHCI controller on %s [%s] using %s\n", 4550d1b26863SKay Sievers mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 455118e762e3SChunyan Zhang host->use_external_dma ? "External DMA" : 4552e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_ADMA) ? 4553e57a5f61SAdrian Hunter (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 4554a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 45551c6a0718SPierre Ossman 45567260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 45577260cf5eSAnton Vorontsov 45581c6a0718SPierre Ossman return 0; 45591c6a0718SPierre Ossman 4560eb5c20deSAdrian Hunter unled: 4561061d17a6SAdrian Hunter sdhci_led_unregister(host); 4562eb5c20deSAdrian Hunter unirq: 456303231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 4564b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 4565b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 45662f730fecSPierre Ossman free_irq(host->irq, host); 4567c07a48c2SAdrian Hunter unwq: 4568c07a48c2SAdrian Hunter destroy_workqueue(host->complete_wq); 456952f5336dSAdrian Hunter 45701c6a0718SPierre Ossman return ret; 45711c6a0718SPierre Ossman } 457252f5336dSAdrian Hunter EXPORT_SYMBOL_GPL(__sdhci_add_host); 45731c6a0718SPierre Ossman 457452f5336dSAdrian Hunter int sdhci_add_host(struct sdhci_host *host) 457552f5336dSAdrian Hunter { 457652f5336dSAdrian Hunter int ret; 457752f5336dSAdrian Hunter 457852f5336dSAdrian Hunter ret = sdhci_setup_host(host); 457952f5336dSAdrian Hunter if (ret) 458052f5336dSAdrian Hunter return ret; 458152f5336dSAdrian Hunter 45824180ffa8SAdrian Hunter ret = __sdhci_add_host(host); 45834180ffa8SAdrian Hunter if (ret) 45844180ffa8SAdrian Hunter goto cleanup; 45854180ffa8SAdrian Hunter 45864180ffa8SAdrian Hunter return 0; 45874180ffa8SAdrian Hunter 45884180ffa8SAdrian Hunter cleanup: 45894180ffa8SAdrian Hunter sdhci_cleanup_host(host); 45904180ffa8SAdrian Hunter 45914180ffa8SAdrian Hunter return ret; 459252f5336dSAdrian Hunter } 4593b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_add_host); 4594b8c86fc5SPierre Ossman 45951e72859eSPierre Ossman void sdhci_remove_host(struct sdhci_host *host, int dead) 45961c6a0718SPierre Ossman { 45973a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 45981e72859eSPierre Ossman unsigned long flags; 45991e72859eSPierre Ossman 46001e72859eSPierre Ossman if (dead) { 46011e72859eSPierre Ossman spin_lock_irqsave(&host->lock, flags); 46021e72859eSPierre Ossman 46031e72859eSPierre Ossman host->flags |= SDHCI_DEVICE_DEAD; 46041e72859eSPierre Ossman 46055d0d11c5SAdrian Hunter if (sdhci_has_requests(host)) { 4606a3c76eb9SGirish K S pr_err("%s: Controller removed during " 46074e743f1fSMarkus Mayer " transfer!\n", mmc_hostname(mmc)); 46085d0d11c5SAdrian Hunter sdhci_error_out_mrqs(host, -ENOMEDIUM); 46091e72859eSPierre Ossman } 46101e72859eSPierre Ossman 46111e72859eSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 46121e72859eSPierre Ossman } 46131e72859eSPierre Ossman 46147260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 46157260cf5eSAnton Vorontsov 46164e743f1fSMarkus Mayer mmc_remove_host(mmc); 46171c6a0718SPierre Ossman 4618061d17a6SAdrian Hunter sdhci_led_unregister(host); 46192f730fecSPierre Ossman 46201e72859eSPierre Ossman if (!dead) 462103231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 46221c6a0718SPierre Ossman 4623b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 4624b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 46251c6a0718SPierre Ossman free_irq(host->irq, host); 46261c6a0718SPierre Ossman 46271c6a0718SPierre Ossman del_timer_sync(&host->timer); 4628d7422fb4SAdrian Hunter del_timer_sync(&host->data_timer); 46291c6a0718SPierre Ossman 4630c07a48c2SAdrian Hunter destroy_workqueue(host->complete_wq); 46312134a922SPierre Ossman 46323a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) 46333a48edc4STim Kryger regulator_disable(mmc->supply.vqmmc); 46346231f3deSPhilip Rakity 4635edd63fccSRussell King if (host->align_buffer) 4636e66e61cbSRussell King dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 4637e66e61cbSRussell King host->adma_table_sz, host->align_buffer, 4638e66e61cbSRussell King host->align_addr); 46392134a922SPierre Ossman 464018e762e3SChunyan Zhang if (host->use_external_dma) 464118e762e3SChunyan Zhang sdhci_external_dma_release(host); 464218e762e3SChunyan Zhang 46434efaa6fbSAdrian Hunter host->adma_table = NULL; 46442134a922SPierre Ossman host->align_buffer = NULL; 46451c6a0718SPierre Ossman } 46461c6a0718SPierre Ossman 4647b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_remove_host); 4648b8c86fc5SPierre Ossman 4649b8c86fc5SPierre Ossman void sdhci_free_host(struct sdhci_host *host) 46501c6a0718SPierre Ossman { 4651b8c86fc5SPierre Ossman mmc_free_host(host->mmc); 46521c6a0718SPierre Ossman } 46531c6a0718SPierre Ossman 4654b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_free_host); 46551c6a0718SPierre Ossman 46561c6a0718SPierre Ossman /*****************************************************************************\ 46571c6a0718SPierre Ossman * * 46581c6a0718SPierre Ossman * Driver init/exit * 46591c6a0718SPierre Ossman * * 46601c6a0718SPierre Ossman \*****************************************************************************/ 46611c6a0718SPierre Ossman 46621c6a0718SPierre Ossman static int __init sdhci_drv_init(void) 46631c6a0718SPierre Ossman { 4664a3c76eb9SGirish K S pr_info(DRIVER_NAME 46651c6a0718SPierre Ossman ": Secure Digital Host Controller Interface driver\n"); 4666a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 46671c6a0718SPierre Ossman 4668b8c86fc5SPierre Ossman return 0; 46691c6a0718SPierre Ossman } 46701c6a0718SPierre Ossman 46711c6a0718SPierre Ossman static void __exit sdhci_drv_exit(void) 46721c6a0718SPierre Ossman { 46731c6a0718SPierre Ossman } 46741c6a0718SPierre Ossman 46751c6a0718SPierre Ossman module_init(sdhci_drv_init); 46761c6a0718SPierre Ossman module_exit(sdhci_drv_exit); 46771c6a0718SPierre Ossman 46781c6a0718SPierre Ossman module_param(debug_quirks, uint, 0444); 467966fd8ad5SAdrian Hunter module_param(debug_quirks2, uint, 0444); 46801c6a0718SPierre Ossman 468132710e8fSPierre Ossman MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 4682b8c86fc5SPierre Ossman MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 46831c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 46841c6a0718SPierre Ossman 46851c6a0718SPierre Ossman MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 468666fd8ad5SAdrian Hunter MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 4687