11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 31c6a0718SPierre Ossman * 4b69c9058SPierre Ossman * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License as published by 81c6a0718SPierre Ossman * the Free Software Foundation; either version 2 of the License, or (at 91c6a0718SPierre Ossman * your option) any later version. 1084c46a53SPierre Ossman * 1184c46a53SPierre Ossman * Thanks to the following companies for their support: 1284c46a53SPierre Ossman * 1384c46a53SPierre Ossman * - JMicron (hardware and technical support) 141c6a0718SPierre Ossman */ 151c6a0718SPierre Ossman 161c6a0718SPierre Ossman #include <linux/delay.h> 171c6a0718SPierre Ossman #include <linux/highmem.h> 18b8c86fc5SPierre Ossman #include <linux/io.h> 1988b47679SPaul Gortmaker #include <linux/module.h> 201c6a0718SPierre Ossman #include <linux/dma-mapping.h> 215a0e3ad6STejun Heo #include <linux/slab.h> 2211763609SRalf Baechle #include <linux/scatterlist.h> 239bea3c85SMarek Szyprowski #include <linux/regulator/consumer.h> 2466fd8ad5SAdrian Hunter #include <linux/pm_runtime.h> 251c6a0718SPierre Ossman 262f730fecSPierre Ossman #include <linux/leds.h> 272f730fecSPierre Ossman 2822113efdSAries Lee #include <linux/mmc/mmc.h> 291c6a0718SPierre Ossman #include <linux/mmc/host.h> 30473b095aSAaron Lu #include <linux/mmc/card.h> 31bec9d4e5SGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 321c6a0718SPierre Ossman 331c6a0718SPierre Ossman #include "sdhci.h" 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define DRIVER_NAME "sdhci" 361c6a0718SPierre Ossman 371c6a0718SPierre Ossman #define DBG(f, x...) \ 381c6a0718SPierre Ossman pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 391c6a0718SPierre Ossman 40f9134319SPierre Ossman #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41f9134319SPierre Ossman defined(CONFIG_MMC_SDHCI_MODULE)) 42f9134319SPierre Ossman #define SDHCI_USE_LEDS_CLASS 43f9134319SPierre Ossman #endif 44f9134319SPierre Ossman 45b513ea25SArindam Nath #define MAX_TUNING_LOOP 40 46b513ea25SArindam Nath 47d1e49f77SRussell King #define ADMA_SIZE ((128 * 2 + 1) * 4) 48d1e49f77SRussell King 491c6a0718SPierre Ossman static unsigned int debug_quirks = 0; 5066fd8ad5SAdrian Hunter static unsigned int debug_quirks2; 511c6a0718SPierre Ossman 521c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *); 531c6a0718SPierre Ossman 541c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *); 55069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 56cf2b5eeaSArindam Nath static void sdhci_tuning_timer(unsigned long data); 5752983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 581c6a0718SPierre Ossman 5966fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 6066fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host); 6166fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host); 62f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 63f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 6466fd8ad5SAdrian Hunter #else 6566fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 6666fd8ad5SAdrian Hunter { 6766fd8ad5SAdrian Hunter return 0; 6866fd8ad5SAdrian Hunter } 6966fd8ad5SAdrian Hunter static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 7066fd8ad5SAdrian Hunter { 7166fd8ad5SAdrian Hunter return 0; 7266fd8ad5SAdrian Hunter } 73f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 74f0710a55SAdrian Hunter { 75f0710a55SAdrian Hunter } 76f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 77f0710a55SAdrian Hunter { 78f0710a55SAdrian Hunter } 7966fd8ad5SAdrian Hunter #endif 8066fd8ad5SAdrian Hunter 811c6a0718SPierre Ossman static void sdhci_dumpregs(struct sdhci_host *host) 821c6a0718SPierre Ossman { 83a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 84412ab659SPhilip Rakity mmc_hostname(host->mmc)); 851c6a0718SPierre Ossman 86a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 874e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_DMA_ADDRESS), 884e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_HOST_VERSION)); 89a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 904e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_SIZE), 914e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_BLOCK_COUNT)); 92a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 934e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_ARGUMENT), 944e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_TRANSFER_MODE)); 95a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 964e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_PRESENT_STATE), 974e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_HOST_CONTROL)); 98a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 994e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_POWER_CONTROL), 1004e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 101a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 1024e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 1034e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 104a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 1054e4141a5SAnton Vorontsov sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 1064e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_STATUS)); 107a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 1084e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_INT_ENABLE), 1094e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 110a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 1114e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_ACMD12_ERR), 1124e4141a5SAnton Vorontsov sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 113a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 1144e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_CAPABILITIES), 115e8120ad1SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1)); 116a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 117e8120ad1SPhilip Rakity sdhci_readw(host, SDHCI_COMMAND), 1184e4141a5SAnton Vorontsov sdhci_readl(host, SDHCI_MAX_CURRENT)); 119a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 120f2119df6SArindam Nath sdhci_readw(host, SDHCI_HOST_CONTROL2)); 1211c6a0718SPierre Ossman 122be3f4ae0SBen Dooks if (host->flags & SDHCI_USE_ADMA) 123a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 124be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ERROR), 125be3f4ae0SBen Dooks readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 126be3f4ae0SBen Dooks 127a3c76eb9SGirish K S pr_debug(DRIVER_NAME ": ===========================================\n"); 1281c6a0718SPierre Ossman } 1291c6a0718SPierre Ossman 1301c6a0718SPierre Ossman /*****************************************************************************\ 1311c6a0718SPierre Ossman * * 1321c6a0718SPierre Ossman * Low level functions * 1331c6a0718SPierre Ossman * * 1341c6a0718SPierre Ossman \*****************************************************************************/ 1351c6a0718SPierre Ossman 1367260cf5eSAnton Vorontsov static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 1377260cf5eSAnton Vorontsov { 1385b4f1f6cSRussell King u32 present; 1397260cf5eSAnton Vorontsov 140c79396c1SAdrian Hunter if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 14187b87a3fSDaniel Drake (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 14266fd8ad5SAdrian Hunter return; 14366fd8ad5SAdrian Hunter 1445b4f1f6cSRussell King if (enable) { 145d25928d1SShawn Guo present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 146d25928d1SShawn Guo SDHCI_CARD_PRESENT; 147d25928d1SShawn Guo 1485b4f1f6cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 1495b4f1f6cSRussell King SDHCI_INT_CARD_INSERT; 1505b4f1f6cSRussell King } else { 1515b4f1f6cSRussell King host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 1525b4f1f6cSRussell King } 153b537f94cSRussell King 154b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 155b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1567260cf5eSAnton Vorontsov } 1577260cf5eSAnton Vorontsov 1587260cf5eSAnton Vorontsov static void sdhci_enable_card_detection(struct sdhci_host *host) 1597260cf5eSAnton Vorontsov { 1607260cf5eSAnton Vorontsov sdhci_set_card_detection(host, true); 1617260cf5eSAnton Vorontsov } 1627260cf5eSAnton Vorontsov 1637260cf5eSAnton Vorontsov static void sdhci_disable_card_detection(struct sdhci_host *host) 1647260cf5eSAnton Vorontsov { 1657260cf5eSAnton Vorontsov sdhci_set_card_detection(host, false); 1667260cf5eSAnton Vorontsov } 1677260cf5eSAnton Vorontsov 16803231f9bSRussell King void sdhci_reset(struct sdhci_host *host, u8 mask) 1691c6a0718SPierre Ossman { 1701c6a0718SPierre Ossman unsigned long timeout; 171393c1a34SPhilip Rakity 1724e4141a5SAnton Vorontsov sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1731c6a0718SPierre Ossman 174f0710a55SAdrian Hunter if (mask & SDHCI_RESET_ALL) { 1751c6a0718SPierre Ossman host->clock = 0; 176f0710a55SAdrian Hunter /* Reset-all turns off SD Bus Power */ 177f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 178f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 179f0710a55SAdrian Hunter } 1801c6a0718SPierre Ossman 1811c6a0718SPierre Ossman /* Wait max 100 ms */ 1821c6a0718SPierre Ossman timeout = 100; 1831c6a0718SPierre Ossman 1841c6a0718SPierre Ossman /* hw clears the bit when it's done */ 1854e4141a5SAnton Vorontsov while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 1861c6a0718SPierre Ossman if (timeout == 0) { 187a3c76eb9SGirish K S pr_err("%s: Reset 0x%x never completed.\n", 1881c6a0718SPierre Ossman mmc_hostname(host->mmc), (int)mask); 1891c6a0718SPierre Ossman sdhci_dumpregs(host); 1901c6a0718SPierre Ossman return; 1911c6a0718SPierre Ossman } 1921c6a0718SPierre Ossman timeout--; 1931c6a0718SPierre Ossman mdelay(1); 1941c6a0718SPierre Ossman } 19503231f9bSRussell King } 19603231f9bSRussell King EXPORT_SYMBOL_GPL(sdhci_reset); 197063a9dbbSAnton Vorontsov 19803231f9bSRussell King static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 19903231f9bSRussell King { 20003231f9bSRussell King if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 20103231f9bSRussell King if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 20203231f9bSRussell King SDHCI_CARD_PRESENT)) 20303231f9bSRussell King return; 20403231f9bSRussell King } 20503231f9bSRussell King 20603231f9bSRussell King host->ops->reset(host, mask); 207393c1a34SPhilip Rakity 208da91a8f9SRussell King if (mask & SDHCI_RESET_ALL) { 2093abc1e80SShaohui Xie if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 210da91a8f9SRussell King if (host->ops->enable_dma) 2113abc1e80SShaohui Xie host->ops->enable_dma(host); 2123abc1e80SShaohui Xie } 213da91a8f9SRussell King 214da91a8f9SRussell King /* Resetting the controller clears many */ 215da91a8f9SRussell King host->preset_enabled = false; 216da91a8f9SRussell King } 2171c6a0718SPierre Ossman } 2181c6a0718SPierre Ossman 2192f4cbb3dSNicolas Pitre static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 2202f4cbb3dSNicolas Pitre 2212f4cbb3dSNicolas Pitre static void sdhci_init(struct sdhci_host *host, int soft) 2221c6a0718SPierre Ossman { 2232f4cbb3dSNicolas Pitre if (soft) 22403231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 2252f4cbb3dSNicolas Pitre else 22603231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 2271c6a0718SPierre Ossman 228b537f94cSRussell King host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 229b537f94cSRussell King SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 230b537f94cSRussell King SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 231b537f94cSRussell King SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 232b537f94cSRussell King SDHCI_INT_RESPONSE; 233b537f94cSRussell King 234b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 235b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2362f4cbb3dSNicolas Pitre 2372f4cbb3dSNicolas Pitre if (soft) { 2382f4cbb3dSNicolas Pitre /* force clock reconfiguration */ 2392f4cbb3dSNicolas Pitre host->clock = 0; 2402f4cbb3dSNicolas Pitre sdhci_set_ios(host->mmc, &host->mmc->ios); 2412f4cbb3dSNicolas Pitre } 2427260cf5eSAnton Vorontsov } 2431c6a0718SPierre Ossman 2447260cf5eSAnton Vorontsov static void sdhci_reinit(struct sdhci_host *host) 2457260cf5eSAnton Vorontsov { 2462f4cbb3dSNicolas Pitre sdhci_init(host, 0); 247b67c6b41SAaron Lu /* 248b67c6b41SAaron Lu * Retuning stuffs are affected by different cards inserted and only 249b67c6b41SAaron Lu * applicable to UHS-I cards. So reset these fields to their initial 250b67c6b41SAaron Lu * value when card is removed. 251b67c6b41SAaron Lu */ 252973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 253973905feSAaron Lu host->flags &= ~SDHCI_USING_RETUNING_TIMER; 254973905feSAaron Lu 255b67c6b41SAaron Lu del_timer_sync(&host->tuning_timer); 256b67c6b41SAaron Lu host->flags &= ~SDHCI_NEEDS_RETUNING; 257b67c6b41SAaron Lu host->mmc->max_blk_count = 258b67c6b41SAaron Lu (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 259b67c6b41SAaron Lu } 2607260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 2611c6a0718SPierre Ossman } 2621c6a0718SPierre Ossman 2631c6a0718SPierre Ossman static void sdhci_activate_led(struct sdhci_host *host) 2641c6a0718SPierre Ossman { 2651c6a0718SPierre Ossman u8 ctrl; 2661c6a0718SPierre Ossman 2674e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2681c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_LED; 2694e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2701c6a0718SPierre Ossman } 2711c6a0718SPierre Ossman 2721c6a0718SPierre Ossman static void sdhci_deactivate_led(struct sdhci_host *host) 2731c6a0718SPierre Ossman { 2741c6a0718SPierre Ossman u8 ctrl; 2751c6a0718SPierre Ossman 2764e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 2771c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_LED; 2784e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2791c6a0718SPierre Ossman } 2801c6a0718SPierre Ossman 281f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 2822f730fecSPierre Ossman static void sdhci_led_control(struct led_classdev *led, 2832f730fecSPierre Ossman enum led_brightness brightness) 2842f730fecSPierre Ossman { 2852f730fecSPierre Ossman struct sdhci_host *host = container_of(led, struct sdhci_host, led); 2862f730fecSPierre Ossman unsigned long flags; 2872f730fecSPierre Ossman 2882f730fecSPierre Ossman spin_lock_irqsave(&host->lock, flags); 2892f730fecSPierre Ossman 29066fd8ad5SAdrian Hunter if (host->runtime_suspended) 29166fd8ad5SAdrian Hunter goto out; 29266fd8ad5SAdrian Hunter 2932f730fecSPierre Ossman if (brightness == LED_OFF) 2942f730fecSPierre Ossman sdhci_deactivate_led(host); 2952f730fecSPierre Ossman else 2962f730fecSPierre Ossman sdhci_activate_led(host); 29766fd8ad5SAdrian Hunter out: 2982f730fecSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 2992f730fecSPierre Ossman } 3002f730fecSPierre Ossman #endif 3012f730fecSPierre Ossman 3021c6a0718SPierre Ossman /*****************************************************************************\ 3031c6a0718SPierre Ossman * * 3041c6a0718SPierre Ossman * Core functions * 3051c6a0718SPierre Ossman * * 3061c6a0718SPierre Ossman \*****************************************************************************/ 3071c6a0718SPierre Ossman 3081c6a0718SPierre Ossman static void sdhci_read_block_pio(struct sdhci_host *host) 3091c6a0718SPierre Ossman { 3107659150cSPierre Ossman unsigned long flags; 3117659150cSPierre Ossman size_t blksize, len, chunk; 3127244b85bSSteven Noonan u32 uninitialized_var(scratch); 3137659150cSPierre Ossman u8 *buf; 3141c6a0718SPierre Ossman 3151c6a0718SPierre Ossman DBG("PIO reading\n"); 3161c6a0718SPierre Ossman 3171c6a0718SPierre Ossman blksize = host->data->blksz; 3187659150cSPierre Ossman chunk = 0; 3191c6a0718SPierre Ossman 3207659150cSPierre Ossman local_irq_save(flags); 3211c6a0718SPierre Ossman 3221c6a0718SPierre Ossman while (blksize) { 3237659150cSPierre Ossman if (!sg_miter_next(&host->sg_miter)) 3247659150cSPierre Ossman BUG(); 3257659150cSPierre Ossman 3267659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3277659150cSPierre Ossman 3287659150cSPierre Ossman blksize -= len; 3297659150cSPierre Ossman host->sg_miter.consumed = len; 3307659150cSPierre Ossman 3317659150cSPierre Ossman buf = host->sg_miter.addr; 3327659150cSPierre Ossman 3337659150cSPierre Ossman while (len) { 3347659150cSPierre Ossman if (chunk == 0) { 3354e4141a5SAnton Vorontsov scratch = sdhci_readl(host, SDHCI_BUFFER); 3367659150cSPierre Ossman chunk = 4; 3371c6a0718SPierre Ossman } 3381c6a0718SPierre Ossman 3397659150cSPierre Ossman *buf = scratch & 0xFF; 3401c6a0718SPierre Ossman 3417659150cSPierre Ossman buf++; 3427659150cSPierre Ossman scratch >>= 8; 3437659150cSPierre Ossman chunk--; 3447659150cSPierre Ossman len--; 3457659150cSPierre Ossman } 3461c6a0718SPierre Ossman } 3471c6a0718SPierre Ossman 3487659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3497659150cSPierre Ossman 3507659150cSPierre Ossman local_irq_restore(flags); 3511c6a0718SPierre Ossman } 3521c6a0718SPierre Ossman 3531c6a0718SPierre Ossman static void sdhci_write_block_pio(struct sdhci_host *host) 3541c6a0718SPierre Ossman { 3557659150cSPierre Ossman unsigned long flags; 3567659150cSPierre Ossman size_t blksize, len, chunk; 3577659150cSPierre Ossman u32 scratch; 3587659150cSPierre Ossman u8 *buf; 3591c6a0718SPierre Ossman 3601c6a0718SPierre Ossman DBG("PIO writing\n"); 3611c6a0718SPierre Ossman 3621c6a0718SPierre Ossman blksize = host->data->blksz; 3637659150cSPierre Ossman chunk = 0; 3647659150cSPierre Ossman scratch = 0; 3651c6a0718SPierre Ossman 3667659150cSPierre Ossman local_irq_save(flags); 3671c6a0718SPierre Ossman 3681c6a0718SPierre Ossman while (blksize) { 3697659150cSPierre Ossman if (!sg_miter_next(&host->sg_miter)) 3707659150cSPierre Ossman BUG(); 3711c6a0718SPierre Ossman 3727659150cSPierre Ossman len = min(host->sg_miter.length, blksize); 3731c6a0718SPierre Ossman 3747659150cSPierre Ossman blksize -= len; 3757659150cSPierre Ossman host->sg_miter.consumed = len; 3767659150cSPierre Ossman 3777659150cSPierre Ossman buf = host->sg_miter.addr; 3787659150cSPierre Ossman 3797659150cSPierre Ossman while (len) { 3807659150cSPierre Ossman scratch |= (u32)*buf << (chunk * 8); 3817659150cSPierre Ossman 3827659150cSPierre Ossman buf++; 3837659150cSPierre Ossman chunk++; 3847659150cSPierre Ossman len--; 3857659150cSPierre Ossman 3867659150cSPierre Ossman if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 3874e4141a5SAnton Vorontsov sdhci_writel(host, scratch, SDHCI_BUFFER); 3887659150cSPierre Ossman chunk = 0; 3897659150cSPierre Ossman scratch = 0; 3907659150cSPierre Ossman } 3917659150cSPierre Ossman } 3921c6a0718SPierre Ossman } 3931c6a0718SPierre Ossman 3947659150cSPierre Ossman sg_miter_stop(&host->sg_miter); 3951c6a0718SPierre Ossman 3967659150cSPierre Ossman local_irq_restore(flags); 3971c6a0718SPierre Ossman } 3981c6a0718SPierre Ossman 3991c6a0718SPierre Ossman static void sdhci_transfer_pio(struct sdhci_host *host) 4001c6a0718SPierre Ossman { 4011c6a0718SPierre Ossman u32 mask; 4021c6a0718SPierre Ossman 4031c6a0718SPierre Ossman BUG_ON(!host->data); 4041c6a0718SPierre Ossman 4057659150cSPierre Ossman if (host->blocks == 0) 4061c6a0718SPierre Ossman return; 4071c6a0718SPierre Ossman 4081c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4091c6a0718SPierre Ossman mask = SDHCI_DATA_AVAILABLE; 4101c6a0718SPierre Ossman else 4111c6a0718SPierre Ossman mask = SDHCI_SPACE_AVAILABLE; 4121c6a0718SPierre Ossman 4134a3cba32SPierre Ossman /* 4144a3cba32SPierre Ossman * Some controllers (JMicron JMB38x) mess up the buffer bits 4154a3cba32SPierre Ossman * for transfers < 4 bytes. As long as it is just one block, 4164a3cba32SPierre Ossman * we can ignore the bits. 4174a3cba32SPierre Ossman */ 4184a3cba32SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 4194a3cba32SPierre Ossman (host->data->blocks == 1)) 4204a3cba32SPierre Ossman mask = ~0; 4214a3cba32SPierre Ossman 4224e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 4233e3bf207SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 4243e3bf207SAnton Vorontsov udelay(100); 4253e3bf207SAnton Vorontsov 4261c6a0718SPierre Ossman if (host->data->flags & MMC_DATA_READ) 4271c6a0718SPierre Ossman sdhci_read_block_pio(host); 4281c6a0718SPierre Ossman else 4291c6a0718SPierre Ossman sdhci_write_block_pio(host); 4301c6a0718SPierre Ossman 4317659150cSPierre Ossman host->blocks--; 4327659150cSPierre Ossman if (host->blocks == 0) 4331c6a0718SPierre Ossman break; 4341c6a0718SPierre Ossman } 4351c6a0718SPierre Ossman 4361c6a0718SPierre Ossman DBG("PIO transfer complete.\n"); 4371c6a0718SPierre Ossman } 4381c6a0718SPierre Ossman 4392134a922SPierre Ossman static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 4402134a922SPierre Ossman { 4412134a922SPierre Ossman local_irq_save(*flags); 442482fce99SCong Wang return kmap_atomic(sg_page(sg)) + sg->offset; 4432134a922SPierre Ossman } 4442134a922SPierre Ossman 4452134a922SPierre Ossman static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 4462134a922SPierre Ossman { 447482fce99SCong Wang kunmap_atomic(buffer); 4482134a922SPierre Ossman local_irq_restore(*flags); 4492134a922SPierre Ossman } 4502134a922SPierre Ossman 451118cd17dSBen Dooks static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 452118cd17dSBen Dooks { 4539e506f35SBen Dooks __le32 *dataddr = (__le32 __force *)(desc + 4); 4549e506f35SBen Dooks __le16 *cmdlen = (__le16 __force *)desc; 455118cd17dSBen Dooks 4569e506f35SBen Dooks /* SDHCI specification says ADMA descriptors should be 4 byte 4579e506f35SBen Dooks * aligned, so using 16 or 32bit operations should be safe. */ 458118cd17dSBen Dooks 4599e506f35SBen Dooks cmdlen[0] = cpu_to_le16(cmd); 4609e506f35SBen Dooks cmdlen[1] = cpu_to_le16(len); 4619e506f35SBen Dooks 4629e506f35SBen Dooks dataddr[0] = cpu_to_le32(addr); 463118cd17dSBen Dooks } 464118cd17dSBen Dooks 4658f1934ceSPierre Ossman static int sdhci_adma_table_pre(struct sdhci_host *host, 4662134a922SPierre Ossman struct mmc_data *data) 4672134a922SPierre Ossman { 4682134a922SPierre Ossman int direction; 4692134a922SPierre Ossman 4702134a922SPierre Ossman u8 *desc; 4712134a922SPierre Ossman u8 *align; 4722134a922SPierre Ossman dma_addr_t addr; 4732134a922SPierre Ossman dma_addr_t align_addr; 4742134a922SPierre Ossman int len, offset; 4752134a922SPierre Ossman 4762134a922SPierre Ossman struct scatterlist *sg; 4772134a922SPierre Ossman int i; 4782134a922SPierre Ossman char *buffer; 4792134a922SPierre Ossman unsigned long flags; 4802134a922SPierre Ossman 4812134a922SPierre Ossman /* 4822134a922SPierre Ossman * The spec does not specify endianness of descriptor table. 4832134a922SPierre Ossman * We currently guess that it is LE. 4842134a922SPierre Ossman */ 4852134a922SPierre Ossman 4862134a922SPierre Ossman if (data->flags & MMC_DATA_READ) 4872134a922SPierre Ossman direction = DMA_FROM_DEVICE; 4882134a922SPierre Ossman else 4892134a922SPierre Ossman direction = DMA_TO_DEVICE; 4902134a922SPierre Ossman 4912134a922SPierre Ossman host->align_addr = dma_map_single(mmc_dev(host->mmc), 4922134a922SPierre Ossman host->align_buffer, 128 * 4, direction); 4938d8bb39bSFUJITA Tomonori if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 4948f1934ceSPierre Ossman goto fail; 4952134a922SPierre Ossman BUG_ON(host->align_addr & 0x3); 4962134a922SPierre Ossman 4972134a922SPierre Ossman host->sg_count = dma_map_sg(mmc_dev(host->mmc), 4982134a922SPierre Ossman data->sg, data->sg_len, direction); 4998f1934ceSPierre Ossman if (host->sg_count == 0) 5008f1934ceSPierre Ossman goto unmap_align; 5012134a922SPierre Ossman 5022134a922SPierre Ossman desc = host->adma_desc; 5032134a922SPierre Ossman align = host->align_buffer; 5042134a922SPierre Ossman 5052134a922SPierre Ossman align_addr = host->align_addr; 5062134a922SPierre Ossman 5072134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 5082134a922SPierre Ossman addr = sg_dma_address(sg); 5092134a922SPierre Ossman len = sg_dma_len(sg); 5102134a922SPierre Ossman 5112134a922SPierre Ossman /* 5122134a922SPierre Ossman * The SDHCI specification states that ADMA 5132134a922SPierre Ossman * addresses must be 32-bit aligned. If they 5142134a922SPierre Ossman * aren't, then we use a bounce buffer for 5152134a922SPierre Ossman * the (up to three) bytes that screw up the 5162134a922SPierre Ossman * alignment. 5172134a922SPierre Ossman */ 5182134a922SPierre Ossman offset = (4 - (addr & 0x3)) & 0x3; 5192134a922SPierre Ossman if (offset) { 5202134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5212134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 5226cefd05fSPierre Ossman WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 5232134a922SPierre Ossman memcpy(align, buffer, offset); 5242134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 5252134a922SPierre Ossman } 5262134a922SPierre Ossman 527118cd17dSBen Dooks /* tran, valid */ 528118cd17dSBen Dooks sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 5292134a922SPierre Ossman 5302134a922SPierre Ossman BUG_ON(offset > 65536); 5312134a922SPierre Ossman 5322134a922SPierre Ossman align += 4; 5332134a922SPierre Ossman align_addr += 4; 5342134a922SPierre Ossman 5352134a922SPierre Ossman desc += 8; 5362134a922SPierre Ossman 5372134a922SPierre Ossman addr += offset; 5382134a922SPierre Ossman len -= offset; 5392134a922SPierre Ossman } 5402134a922SPierre Ossman 5412134a922SPierre Ossman BUG_ON(len > 65536); 5422134a922SPierre Ossman 543118cd17dSBen Dooks /* tran, valid */ 544118cd17dSBen Dooks sdhci_set_adma_desc(desc, addr, len, 0x21); 5452134a922SPierre Ossman desc += 8; 5462134a922SPierre Ossman 5472134a922SPierre Ossman /* 5482134a922SPierre Ossman * If this triggers then we have a calculation bug 5492134a922SPierre Ossman * somewhere. :/ 5502134a922SPierre Ossman */ 551d1e49f77SRussell King WARN_ON((desc - host->adma_desc) > ADMA_SIZE); 5522134a922SPierre Ossman } 5532134a922SPierre Ossman 55470764a90SThomas Abraham if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 55570764a90SThomas Abraham /* 55670764a90SThomas Abraham * Mark the last descriptor as the terminating descriptor 55770764a90SThomas Abraham */ 55870764a90SThomas Abraham if (desc != host->adma_desc) { 55970764a90SThomas Abraham desc -= 8; 56070764a90SThomas Abraham desc[0] |= 0x2; /* end */ 56170764a90SThomas Abraham } 56270764a90SThomas Abraham } else { 5632134a922SPierre Ossman /* 5642134a922SPierre Ossman * Add a terminating entry. 5652134a922SPierre Ossman */ 5662134a922SPierre Ossman 567118cd17dSBen Dooks /* nop, end, valid */ 568118cd17dSBen Dooks sdhci_set_adma_desc(desc, 0, 0, 0x3); 56970764a90SThomas Abraham } 5702134a922SPierre Ossman 5712134a922SPierre Ossman /* 5722134a922SPierre Ossman * Resync align buffer as we might have changed it. 5732134a922SPierre Ossman */ 5742134a922SPierre Ossman if (data->flags & MMC_DATA_WRITE) { 5752134a922SPierre Ossman dma_sync_single_for_device(mmc_dev(host->mmc), 5762134a922SPierre Ossman host->align_addr, 128 * 4, direction); 5772134a922SPierre Ossman } 5782134a922SPierre Ossman 5798f1934ceSPierre Ossman return 0; 5808f1934ceSPierre Ossman 5818f1934ceSPierre Ossman unmap_align: 5828f1934ceSPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 5838f1934ceSPierre Ossman 128 * 4, direction); 5848f1934ceSPierre Ossman fail: 5858f1934ceSPierre Ossman return -EINVAL; 5862134a922SPierre Ossman } 5872134a922SPierre Ossman 5882134a922SPierre Ossman static void sdhci_adma_table_post(struct sdhci_host *host, 5892134a922SPierre Ossman struct mmc_data *data) 5902134a922SPierre Ossman { 5912134a922SPierre Ossman int direction; 5922134a922SPierre Ossman 5932134a922SPierre Ossman struct scatterlist *sg; 5942134a922SPierre Ossman int i, size; 5952134a922SPierre Ossman u8 *align; 5962134a922SPierre Ossman char *buffer; 5972134a922SPierre Ossman unsigned long flags; 598de0b65a7SRussell King bool has_unaligned; 5992134a922SPierre Ossman 6002134a922SPierre Ossman if (data->flags & MMC_DATA_READ) 6012134a922SPierre Ossman direction = DMA_FROM_DEVICE; 6022134a922SPierre Ossman else 6032134a922SPierre Ossman direction = DMA_TO_DEVICE; 6042134a922SPierre Ossman 6052134a922SPierre Ossman dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 6062134a922SPierre Ossman 128 * 4, direction); 6072134a922SPierre Ossman 608de0b65a7SRussell King /* Do a quick scan of the SG list for any unaligned mappings */ 609de0b65a7SRussell King has_unaligned = false; 610de0b65a7SRussell King for_each_sg(data->sg, sg, host->sg_count, i) 611de0b65a7SRussell King if (sg_dma_address(sg) & 3) { 612de0b65a7SRussell King has_unaligned = true; 613de0b65a7SRussell King break; 614de0b65a7SRussell King } 615de0b65a7SRussell King 616de0b65a7SRussell King if (has_unaligned && data->flags & MMC_DATA_READ) { 6172134a922SPierre Ossman dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 6182134a922SPierre Ossman data->sg_len, direction); 6192134a922SPierre Ossman 6202134a922SPierre Ossman align = host->align_buffer; 6212134a922SPierre Ossman 6222134a922SPierre Ossman for_each_sg(data->sg, sg, host->sg_count, i) { 6232134a922SPierre Ossman if (sg_dma_address(sg) & 0x3) { 6242134a922SPierre Ossman size = 4 - (sg_dma_address(sg) & 0x3); 6252134a922SPierre Ossman 6262134a922SPierre Ossman buffer = sdhci_kmap_atomic(sg, &flags); 6276cefd05fSPierre Ossman WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 6282134a922SPierre Ossman memcpy(buffer, align, size); 6292134a922SPierre Ossman sdhci_kunmap_atomic(buffer, &flags); 6302134a922SPierre Ossman 6312134a922SPierre Ossman align += 4; 6322134a922SPierre Ossman } 6332134a922SPierre Ossman } 6342134a922SPierre Ossman } 6352134a922SPierre Ossman 6362134a922SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 6372134a922SPierre Ossman data->sg_len, direction); 6382134a922SPierre Ossman } 6392134a922SPierre Ossman 640a3c7778fSAndrei Warkentin static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 6411c6a0718SPierre Ossman { 6421c6a0718SPierre Ossman u8 count; 643a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 6441c6a0718SPierre Ossman unsigned target_timeout, current_timeout; 6451c6a0718SPierre Ossman 646ee53ab5dSPierre Ossman /* 647ee53ab5dSPierre Ossman * If the host controller provides us with an incorrect timeout 648ee53ab5dSPierre Ossman * value, just skip the check and use 0xE. The hardware may take 649ee53ab5dSPierre Ossman * longer to time out, but that's much better than having a too-short 650ee53ab5dSPierre Ossman * timeout value. 651ee53ab5dSPierre Ossman */ 65211a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 653ee53ab5dSPierre Ossman return 0xE; 654e538fbe8SPierre Ossman 655a3c7778fSAndrei Warkentin /* Unspecified timeout, assume max */ 6561d4d7744SUlf Hansson if (!data && !cmd->busy_timeout) 657a3c7778fSAndrei Warkentin return 0xE; 658a3c7778fSAndrei Warkentin 6591c6a0718SPierre Ossman /* timeout in us */ 660a3c7778fSAndrei Warkentin if (!data) 6611d4d7744SUlf Hansson target_timeout = cmd->busy_timeout * 1000; 66278a2ca27SAndy Shevchenko else { 66378a2ca27SAndy Shevchenko target_timeout = data->timeout_ns / 1000; 66478a2ca27SAndy Shevchenko if (host->clock) 66578a2ca27SAndy Shevchenko target_timeout += data->timeout_clks / host->clock; 66678a2ca27SAndy Shevchenko } 6671c6a0718SPierre Ossman 6681c6a0718SPierre Ossman /* 6691c6a0718SPierre Ossman * Figure out needed cycles. 6701c6a0718SPierre Ossman * We do this in steps in order to fit inside a 32 bit int. 6711c6a0718SPierre Ossman * The first step is the minimum timeout, which will have a 6721c6a0718SPierre Ossman * minimum resolution of 6 bits: 6731c6a0718SPierre Ossman * (1) 2^13*1000 > 2^22, 6741c6a0718SPierre Ossman * (2) host->timeout_clk < 2^16 6751c6a0718SPierre Ossman * => 6761c6a0718SPierre Ossman * (1) / (2) > 2^6 6771c6a0718SPierre Ossman */ 6781c6a0718SPierre Ossman count = 0; 6791c6a0718SPierre Ossman current_timeout = (1 << 13) * 1000 / host->timeout_clk; 6801c6a0718SPierre Ossman while (current_timeout < target_timeout) { 6811c6a0718SPierre Ossman count++; 6821c6a0718SPierre Ossman current_timeout <<= 1; 6831c6a0718SPierre Ossman if (count >= 0xF) 6841c6a0718SPierre Ossman break; 6851c6a0718SPierre Ossman } 6861c6a0718SPierre Ossman 6871c6a0718SPierre Ossman if (count >= 0xF) { 68809eeff52SChris Ball DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 68902145977SMark Brown mmc_hostname(host->mmc), count, cmd->opcode); 6901c6a0718SPierre Ossman count = 0xE; 6911c6a0718SPierre Ossman } 6921c6a0718SPierre Ossman 693ee53ab5dSPierre Ossman return count; 694ee53ab5dSPierre Ossman } 695ee53ab5dSPierre Ossman 6966aa943abSAnton Vorontsov static void sdhci_set_transfer_irqs(struct sdhci_host *host) 6976aa943abSAnton Vorontsov { 6986aa943abSAnton Vorontsov u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 6996aa943abSAnton Vorontsov u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 7006aa943abSAnton Vorontsov 7016aa943abSAnton Vorontsov if (host->flags & SDHCI_REQ_USE_DMA) 702b537f94cSRussell King host->ier = (host->ier & ~pio_irqs) | dma_irqs; 7036aa943abSAnton Vorontsov else 704b537f94cSRussell King host->ier = (host->ier & ~dma_irqs) | pio_irqs; 705b537f94cSRussell King 706b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 707b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 7086aa943abSAnton Vorontsov } 7096aa943abSAnton Vorontsov 710b45e668aSAisheng Dong static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 711ee53ab5dSPierre Ossman { 712ee53ab5dSPierre Ossman u8 count; 713b45e668aSAisheng Dong 714b45e668aSAisheng Dong if (host->ops->set_timeout) { 715b45e668aSAisheng Dong host->ops->set_timeout(host, cmd); 716b45e668aSAisheng Dong } else { 717b45e668aSAisheng Dong count = sdhci_calc_timeout(host, cmd); 718b45e668aSAisheng Dong sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 719b45e668aSAisheng Dong } 720b45e668aSAisheng Dong } 721b45e668aSAisheng Dong 722b45e668aSAisheng Dong static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 723b45e668aSAisheng Dong { 7242134a922SPierre Ossman u8 ctrl; 725a3c7778fSAndrei Warkentin struct mmc_data *data = cmd->data; 7268f1934ceSPierre Ossman int ret; 727ee53ab5dSPierre Ossman 728ee53ab5dSPierre Ossman WARN_ON(host->data); 729ee53ab5dSPierre Ossman 730b45e668aSAisheng Dong if (data || (cmd->flags & MMC_RSP_BUSY)) 731b45e668aSAisheng Dong sdhci_set_timeout(host, cmd); 732a3c7778fSAndrei Warkentin 733a3c7778fSAndrei Warkentin if (!data) 734ee53ab5dSPierre Ossman return; 735ee53ab5dSPierre Ossman 736ee53ab5dSPierre Ossman /* Sanity checks */ 737ee53ab5dSPierre Ossman BUG_ON(data->blksz * data->blocks > 524288); 738ee53ab5dSPierre Ossman BUG_ON(data->blksz > host->mmc->max_blk_size); 739ee53ab5dSPierre Ossman BUG_ON(data->blocks > 65535); 740ee53ab5dSPierre Ossman 741ee53ab5dSPierre Ossman host->data = data; 742ee53ab5dSPierre Ossman host->data_early = 0; 743f6a03cbfSMikko Vinni host->data->bytes_xfered = 0; 744ee53ab5dSPierre Ossman 745a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 746c9fddbc4SPierre Ossman host->flags |= SDHCI_REQ_USE_DMA; 747c9fddbc4SPierre Ossman 7482134a922SPierre Ossman /* 7492134a922SPierre Ossman * FIXME: This doesn't account for merging when mapping the 7502134a922SPierre Ossman * scatterlist. 7512134a922SPierre Ossman */ 7522134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7532134a922SPierre Ossman int broken, i; 7542134a922SPierre Ossman struct scatterlist *sg; 7552134a922SPierre Ossman 7562134a922SPierre Ossman broken = 0; 7572134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7582134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7592134a922SPierre Ossman broken = 1; 7602134a922SPierre Ossman } else { 7612134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 7622134a922SPierre Ossman broken = 1; 7632134a922SPierre Ossman } 7642134a922SPierre Ossman 7652134a922SPierre Ossman if (unlikely(broken)) { 7662134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 7672134a922SPierre Ossman if (sg->length & 0x3) { 7682134a922SPierre Ossman DBG("Reverting to PIO because of " 7692134a922SPierre Ossman "transfer size (%d)\n", 7702134a922SPierre Ossman sg->length); 771c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 7722134a922SPierre Ossman break; 7732134a922SPierre Ossman } 7742134a922SPierre Ossman } 7752134a922SPierre Ossman } 776c9fddbc4SPierre Ossman } 777c9fddbc4SPierre Ossman 778c9fddbc4SPierre Ossman /* 779c9fddbc4SPierre Ossman * The assumption here being that alignment is the same after 780c9fddbc4SPierre Ossman * translation to device address space. 781c9fddbc4SPierre Ossman */ 7822134a922SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 7832134a922SPierre Ossman int broken, i; 7842134a922SPierre Ossman struct scatterlist *sg; 7852134a922SPierre Ossman 7862134a922SPierre Ossman broken = 0; 7872134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 7882134a922SPierre Ossman /* 7892134a922SPierre Ossman * As we use 3 byte chunks to work around 7902134a922SPierre Ossman * alignment problems, we need to check this 7912134a922SPierre Ossman * quirk. 7922134a922SPierre Ossman */ 7932134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 7942134a922SPierre Ossman broken = 1; 7952134a922SPierre Ossman } else { 7962134a922SPierre Ossman if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 7972134a922SPierre Ossman broken = 1; 7982134a922SPierre Ossman } 7992134a922SPierre Ossman 8002134a922SPierre Ossman if (unlikely(broken)) { 8012134a922SPierre Ossman for_each_sg(data->sg, sg, data->sg_len, i) { 8022134a922SPierre Ossman if (sg->offset & 0x3) { 8032134a922SPierre Ossman DBG("Reverting to PIO because of " 8042134a922SPierre Ossman "bad alignment\n"); 805c9fddbc4SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8062134a922SPierre Ossman break; 8072134a922SPierre Ossman } 8082134a922SPierre Ossman } 8092134a922SPierre Ossman } 8102134a922SPierre Ossman } 8112134a922SPierre Ossman 8128f1934ceSPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 8138f1934ceSPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 8148f1934ceSPierre Ossman ret = sdhci_adma_table_pre(host, data); 8158f1934ceSPierre Ossman if (ret) { 8168f1934ceSPierre Ossman /* 8178f1934ceSPierre Ossman * This only happens when someone fed 8188f1934ceSPierre Ossman * us an invalid request. 8198f1934ceSPierre Ossman */ 8208f1934ceSPierre Ossman WARN_ON(1); 821ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8228f1934ceSPierre Ossman } else { 8234e4141a5SAnton Vorontsov sdhci_writel(host, host->adma_addr, 8244e4141a5SAnton Vorontsov SDHCI_ADMA_ADDRESS); 8258f1934ceSPierre Ossman } 8268f1934ceSPierre Ossman } else { 827c8b3e02eSTomas Winkler int sg_cnt; 8288f1934ceSPierre Ossman 829c8b3e02eSTomas Winkler sg_cnt = dma_map_sg(mmc_dev(host->mmc), 8308f1934ceSPierre Ossman data->sg, data->sg_len, 8318f1934ceSPierre Ossman (data->flags & MMC_DATA_READ) ? 8328f1934ceSPierre Ossman DMA_FROM_DEVICE : 8338f1934ceSPierre Ossman DMA_TO_DEVICE); 834c8b3e02eSTomas Winkler if (sg_cnt == 0) { 8358f1934ceSPierre Ossman /* 8368f1934ceSPierre Ossman * This only happens when someone fed 8378f1934ceSPierre Ossman * us an invalid request. 8388f1934ceSPierre Ossman */ 8398f1934ceSPierre Ossman WARN_ON(1); 840ebd6d357SPierre Ossman host->flags &= ~SDHCI_REQ_USE_DMA; 8418f1934ceSPierre Ossman } else { 842719a61b4SPierre Ossman WARN_ON(sg_cnt != 1); 8434e4141a5SAnton Vorontsov sdhci_writel(host, sg_dma_address(data->sg), 8444e4141a5SAnton Vorontsov SDHCI_DMA_ADDRESS); 8458f1934ceSPierre Ossman } 8468f1934ceSPierre Ossman } 8478f1934ceSPierre Ossman } 8488f1934ceSPierre Ossman 8492134a922SPierre Ossman /* 8502134a922SPierre Ossman * Always adjust the DMA selection as some controllers 8512134a922SPierre Ossman * (e.g. JMicron) can't do PIO properly when the selection 8522134a922SPierre Ossman * is ADMA. 8532134a922SPierre Ossman */ 8542134a922SPierre Ossman if (host->version >= SDHCI_SPEC_200) { 8554e4141a5SAnton Vorontsov ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 8562134a922SPierre Ossman ctrl &= ~SDHCI_CTRL_DMA_MASK; 8572134a922SPierre Ossman if ((host->flags & SDHCI_REQ_USE_DMA) && 8582134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) 8592134a922SPierre Ossman ctrl |= SDHCI_CTRL_ADMA32; 8602134a922SPierre Ossman else 8612134a922SPierre Ossman ctrl |= SDHCI_CTRL_SDMA; 8624e4141a5SAnton Vorontsov sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 863c9fddbc4SPierre Ossman } 864c9fddbc4SPierre Ossman 8658f1934ceSPierre Ossman if (!(host->flags & SDHCI_REQ_USE_DMA)) { 866da60a91dSSebastian Andrzej Siewior int flags; 867da60a91dSSebastian Andrzej Siewior 868da60a91dSSebastian Andrzej Siewior flags = SG_MITER_ATOMIC; 869da60a91dSSebastian Andrzej Siewior if (host->data->flags & MMC_DATA_READ) 870da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_TO_SG; 871da60a91dSSebastian Andrzej Siewior else 872da60a91dSSebastian Andrzej Siewior flags |= SG_MITER_FROM_SG; 873da60a91dSSebastian Andrzej Siewior sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 8747659150cSPierre Ossman host->blocks = data->blocks; 8751c6a0718SPierre Ossman } 8761c6a0718SPierre Ossman 8776aa943abSAnton Vorontsov sdhci_set_transfer_irqs(host); 8786aa943abSAnton Vorontsov 879f6a03cbfSMikko Vinni /* Set the DMA boundary value and block size */ 880f6a03cbfSMikko Vinni sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 881f6a03cbfSMikko Vinni data->blksz), SDHCI_BLOCK_SIZE); 8824e4141a5SAnton Vorontsov sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 8831c6a0718SPierre Ossman } 8841c6a0718SPierre Ossman 8851c6a0718SPierre Ossman static void sdhci_set_transfer_mode(struct sdhci_host *host, 886e89d456fSAndrei Warkentin struct mmc_command *cmd) 8871c6a0718SPierre Ossman { 8881c6a0718SPierre Ossman u16 mode; 889e89d456fSAndrei Warkentin struct mmc_data *data = cmd->data; 8901c6a0718SPierre Ossman 8912b558c13SDong Aisheng if (data == NULL) { 8922b558c13SDong Aisheng /* clear Auto CMD settings for no data CMDs */ 8932b558c13SDong Aisheng mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 8942b558c13SDong Aisheng sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 8952b558c13SDong Aisheng SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 8961c6a0718SPierre Ossman return; 8972b558c13SDong Aisheng } 8981c6a0718SPierre Ossman 899e538fbe8SPierre Ossman WARN_ON(!host->data); 900e538fbe8SPierre Ossman 9011c6a0718SPierre Ossman mode = SDHCI_TRNS_BLK_CNT_EN; 902e89d456fSAndrei Warkentin if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 9031c6a0718SPierre Ossman mode |= SDHCI_TRNS_MULTI; 904e89d456fSAndrei Warkentin /* 905e89d456fSAndrei Warkentin * If we are sending CMD23, CMD12 never gets sent 906e89d456fSAndrei Warkentin * on successful completion (so no Auto-CMD12). 907e89d456fSAndrei Warkentin */ 908e89d456fSAndrei Warkentin if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 909e89d456fSAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD12; 9108edf6371SAndrei Warkentin else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 9118edf6371SAndrei Warkentin mode |= SDHCI_TRNS_AUTO_CMD23; 9128edf6371SAndrei Warkentin sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 913c4512f79SJerry Huang } 9148edf6371SAndrei Warkentin } 9158edf6371SAndrei Warkentin 9161c6a0718SPierre Ossman if (data->flags & MMC_DATA_READ) 9171c6a0718SPierre Ossman mode |= SDHCI_TRNS_READ; 918c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) 9191c6a0718SPierre Ossman mode |= SDHCI_TRNS_DMA; 9201c6a0718SPierre Ossman 9214e4141a5SAnton Vorontsov sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 9221c6a0718SPierre Ossman } 9231c6a0718SPierre Ossman 9241c6a0718SPierre Ossman static void sdhci_finish_data(struct sdhci_host *host) 9251c6a0718SPierre Ossman { 9261c6a0718SPierre Ossman struct mmc_data *data; 9271c6a0718SPierre Ossman 9281c6a0718SPierre Ossman BUG_ON(!host->data); 9291c6a0718SPierre Ossman 9301c6a0718SPierre Ossman data = host->data; 9311c6a0718SPierre Ossman host->data = NULL; 9321c6a0718SPierre Ossman 933c9fddbc4SPierre Ossman if (host->flags & SDHCI_REQ_USE_DMA) { 9342134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 9352134a922SPierre Ossman sdhci_adma_table_post(host, data); 9362134a922SPierre Ossman else { 9372134a922SPierre Ossman dma_unmap_sg(mmc_dev(host->mmc), data->sg, 9382134a922SPierre Ossman data->sg_len, (data->flags & MMC_DATA_READ) ? 939b8c86fc5SPierre Ossman DMA_FROM_DEVICE : DMA_TO_DEVICE); 9401c6a0718SPierre Ossman } 9412134a922SPierre Ossman } 9421c6a0718SPierre Ossman 9431c6a0718SPierre Ossman /* 944c9b74c5bSPierre Ossman * The specification states that the block count register must 945c9b74c5bSPierre Ossman * be updated, but it does not specify at what point in the 946c9b74c5bSPierre Ossman * data flow. That makes the register entirely useless to read 947c9b74c5bSPierre Ossman * back so we have to assume that nothing made it to the card 948c9b74c5bSPierre Ossman * in the event of an error. 9491c6a0718SPierre Ossman */ 950c9b74c5bSPierre Ossman if (data->error) 951c9b74c5bSPierre Ossman data->bytes_xfered = 0; 9521c6a0718SPierre Ossman else 953c9b74c5bSPierre Ossman data->bytes_xfered = data->blksz * data->blocks; 9541c6a0718SPierre Ossman 955e89d456fSAndrei Warkentin /* 956e89d456fSAndrei Warkentin * Need to send CMD12 if - 957e89d456fSAndrei Warkentin * a) open-ended multiblock transfer (no CMD23) 958e89d456fSAndrei Warkentin * b) error in multiblock transfer 959e89d456fSAndrei Warkentin */ 960e89d456fSAndrei Warkentin if (data->stop && 961e89d456fSAndrei Warkentin (data->error || 962e89d456fSAndrei Warkentin !host->mrq->sbc)) { 963e89d456fSAndrei Warkentin 9641c6a0718SPierre Ossman /* 9651c6a0718SPierre Ossman * The controller needs a reset of internal state machines 9661c6a0718SPierre Ossman * upon error conditions. 9671c6a0718SPierre Ossman */ 96817b0429dSPierre Ossman if (data->error) { 96903231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 97003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 9711c6a0718SPierre Ossman } 9721c6a0718SPierre Ossman 9731c6a0718SPierre Ossman sdhci_send_command(host, data->stop); 9741c6a0718SPierre Ossman } else 9751c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 9761c6a0718SPierre Ossman } 9771c6a0718SPierre Ossman 978c0e55129SDong Aisheng void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 9791c6a0718SPierre Ossman { 9801c6a0718SPierre Ossman int flags; 9811c6a0718SPierre Ossman u32 mask; 9821c6a0718SPierre Ossman unsigned long timeout; 9831c6a0718SPierre Ossman 9841c6a0718SPierre Ossman WARN_ON(host->cmd); 9851c6a0718SPierre Ossman 9861c6a0718SPierre Ossman /* Wait max 10 ms */ 9871c6a0718SPierre Ossman timeout = 10; 9881c6a0718SPierre Ossman 9891c6a0718SPierre Ossman mask = SDHCI_CMD_INHIBIT; 9901c6a0718SPierre Ossman if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 9911c6a0718SPierre Ossman mask |= SDHCI_DATA_INHIBIT; 9921c6a0718SPierre Ossman 9931c6a0718SPierre Ossman /* We shouldn't wait for data inihibit for stop commands, even 9941c6a0718SPierre Ossman though they might use busy signaling */ 9951c6a0718SPierre Ossman if (host->mrq->data && (cmd == host->mrq->data->stop)) 9961c6a0718SPierre Ossman mask &= ~SDHCI_DATA_INHIBIT; 9971c6a0718SPierre Ossman 9984e4141a5SAnton Vorontsov while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 9991c6a0718SPierre Ossman if (timeout == 0) { 1000a3c76eb9SGirish K S pr_err("%s: Controller never released " 10011c6a0718SPierre Ossman "inhibit bit(s).\n", mmc_hostname(host->mmc)); 10021c6a0718SPierre Ossman sdhci_dumpregs(host); 100317b0429dSPierre Ossman cmd->error = -EIO; 10041c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10051c6a0718SPierre Ossman return; 10061c6a0718SPierre Ossman } 10071c6a0718SPierre Ossman timeout--; 10081c6a0718SPierre Ossman mdelay(1); 10091c6a0718SPierre Ossman } 10101c6a0718SPierre Ossman 10113e1a6892SAdrian Hunter timeout = jiffies; 10121d4d7744SUlf Hansson if (!cmd->data && cmd->busy_timeout > 9000) 10131d4d7744SUlf Hansson timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 10143e1a6892SAdrian Hunter else 10153e1a6892SAdrian Hunter timeout += 10 * HZ; 10163e1a6892SAdrian Hunter mod_timer(&host->timer, timeout); 10171c6a0718SPierre Ossman 10181c6a0718SPierre Ossman host->cmd = cmd; 10191c6a0718SPierre Ossman 1020a3c7778fSAndrei Warkentin sdhci_prepare_data(host, cmd); 10211c6a0718SPierre Ossman 10224e4141a5SAnton Vorontsov sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 10231c6a0718SPierre Ossman 1024e89d456fSAndrei Warkentin sdhci_set_transfer_mode(host, cmd); 10251c6a0718SPierre Ossman 10261c6a0718SPierre Ossman if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1027a3c76eb9SGirish K S pr_err("%s: Unsupported response type!\n", 10281c6a0718SPierre Ossman mmc_hostname(host->mmc)); 102917b0429dSPierre Ossman cmd->error = -EINVAL; 10301c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10311c6a0718SPierre Ossman return; 10321c6a0718SPierre Ossman } 10331c6a0718SPierre Ossman 10341c6a0718SPierre Ossman if (!(cmd->flags & MMC_RSP_PRESENT)) 10351c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_NONE; 10361c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_136) 10371c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_LONG; 10381c6a0718SPierre Ossman else if (cmd->flags & MMC_RSP_BUSY) 10391c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT_BUSY; 10401c6a0718SPierre Ossman else 10411c6a0718SPierre Ossman flags = SDHCI_CMD_RESP_SHORT; 10421c6a0718SPierre Ossman 10431c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_CRC) 10441c6a0718SPierre Ossman flags |= SDHCI_CMD_CRC; 10451c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_OPCODE) 10461c6a0718SPierre Ossman flags |= SDHCI_CMD_INDEX; 1047b513ea25SArindam Nath 1048b513ea25SArindam Nath /* CMD19 is special in that the Data Present Select should be set */ 1049069c9f14SGirish K S if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1050069c9f14SGirish K S cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 10511c6a0718SPierre Ossman flags |= SDHCI_CMD_DATA; 10521c6a0718SPierre Ossman 10534e4141a5SAnton Vorontsov sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 10541c6a0718SPierre Ossman } 1055c0e55129SDong Aisheng EXPORT_SYMBOL_GPL(sdhci_send_command); 10561c6a0718SPierre Ossman 10571c6a0718SPierre Ossman static void sdhci_finish_command(struct sdhci_host *host) 10581c6a0718SPierre Ossman { 10591c6a0718SPierre Ossman int i; 10601c6a0718SPierre Ossman 10611c6a0718SPierre Ossman BUG_ON(host->cmd == NULL); 10621c6a0718SPierre Ossman 10631c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_PRESENT) { 10641c6a0718SPierre Ossman if (host->cmd->flags & MMC_RSP_136) { 10651c6a0718SPierre Ossman /* CRC is stripped so we need to do some shifting. */ 10661c6a0718SPierre Ossman for (i = 0;i < 4;i++) { 10674e4141a5SAnton Vorontsov host->cmd->resp[i] = sdhci_readl(host, 10681c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4) << 8; 10691c6a0718SPierre Ossman if (i != 3) 10701c6a0718SPierre Ossman host->cmd->resp[i] |= 10714e4141a5SAnton Vorontsov sdhci_readb(host, 10721c6a0718SPierre Ossman SDHCI_RESPONSE + (3-i)*4-1); 10731c6a0718SPierre Ossman } 10741c6a0718SPierre Ossman } else { 10754e4141a5SAnton Vorontsov host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 10761c6a0718SPierre Ossman } 10771c6a0718SPierre Ossman } 10781c6a0718SPierre Ossman 107917b0429dSPierre Ossman host->cmd->error = 0; 10801c6a0718SPierre Ossman 1081e89d456fSAndrei Warkentin /* Finished CMD23, now send actual command. */ 1082e89d456fSAndrei Warkentin if (host->cmd == host->mrq->sbc) { 1083e89d456fSAndrei Warkentin host->cmd = NULL; 1084e89d456fSAndrei Warkentin sdhci_send_command(host, host->mrq->cmd); 1085e89d456fSAndrei Warkentin } else { 1086e89d456fSAndrei Warkentin 1087e89d456fSAndrei Warkentin /* Processed actual command. */ 1088e538fbe8SPierre Ossman if (host->data && host->data_early) 1089e538fbe8SPierre Ossman sdhci_finish_data(host); 1090e538fbe8SPierre Ossman 1091e538fbe8SPierre Ossman if (!host->cmd->data) 10921c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 10931c6a0718SPierre Ossman 10941c6a0718SPierre Ossman host->cmd = NULL; 10951c6a0718SPierre Ossman } 1096e89d456fSAndrei Warkentin } 10971c6a0718SPierre Ossman 109852983382SKevin Liu static u16 sdhci_get_preset_value(struct sdhci_host *host) 109952983382SKevin Liu { 1100d975f121SRussell King u16 preset = 0; 110152983382SKevin Liu 1102d975f121SRussell King switch (host->timing) { 1103d975f121SRussell King case MMC_TIMING_UHS_SDR12: 110452983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 110552983382SKevin Liu break; 1106d975f121SRussell King case MMC_TIMING_UHS_SDR25: 110752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 110852983382SKevin Liu break; 1109d975f121SRussell King case MMC_TIMING_UHS_SDR50: 111052983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 111152983382SKevin Liu break; 1112d975f121SRussell King case MMC_TIMING_UHS_SDR104: 1113d975f121SRussell King case MMC_TIMING_MMC_HS200: 111452983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 111552983382SKevin Liu break; 1116d975f121SRussell King case MMC_TIMING_UHS_DDR50: 111752983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 111852983382SKevin Liu break; 111952983382SKevin Liu default: 112052983382SKevin Liu pr_warn("%s: Invalid UHS-I mode selected\n", 112152983382SKevin Liu mmc_hostname(host->mmc)); 112252983382SKevin Liu preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 112352983382SKevin Liu break; 112452983382SKevin Liu } 112552983382SKevin Liu return preset; 112652983382SKevin Liu } 112752983382SKevin Liu 11281771059cSRussell King void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 11291c6a0718SPierre Ossman { 1130c3ed3877SArindam Nath int div = 0; /* Initialized for compiler warning */ 1131df16219fSGiuseppe CAVALLARO int real_div = div, clk_mul = 1; 1132c3ed3877SArindam Nath u16 clk = 0; 11331c6a0718SPierre Ossman unsigned long timeout; 11341c6a0718SPierre Ossman 11351650d0c7SRussell King host->mmc->actual_clock = 0; 11361650d0c7SRussell King 11374e4141a5SAnton Vorontsov sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 11381c6a0718SPierre Ossman 11391c6a0718SPierre Ossman if (clock == 0) 1140373073efSRussell King return; 11411c6a0718SPierre Ossman 114285105c53SZhangfei Gao if (host->version >= SDHCI_SPEC_300) { 1143da91a8f9SRussell King if (host->preset_enabled) { 114452983382SKevin Liu u16 pre_val; 114552983382SKevin Liu 114652983382SKevin Liu clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 114752983382SKevin Liu pre_val = sdhci_get_preset_value(host); 114852983382SKevin Liu div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 114952983382SKevin Liu >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 115052983382SKevin Liu if (host->clk_mul && 115152983382SKevin Liu (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 115252983382SKevin Liu clk = SDHCI_PROG_CLOCK_MODE; 115352983382SKevin Liu real_div = div + 1; 115452983382SKevin Liu clk_mul = host->clk_mul; 115552983382SKevin Liu } else { 115652983382SKevin Liu real_div = max_t(int, 1, div << 1); 115752983382SKevin Liu } 115852983382SKevin Liu goto clock_set; 115952983382SKevin Liu } 116052983382SKevin Liu 1161c3ed3877SArindam Nath /* 1162c3ed3877SArindam Nath * Check if the Host Controller supports Programmable Clock 1163c3ed3877SArindam Nath * Mode. 1164c3ed3877SArindam Nath */ 1165c3ed3877SArindam Nath if (host->clk_mul) { 1166c3ed3877SArindam Nath for (div = 1; div <= 1024; div++) { 116752983382SKevin Liu if ((host->max_clk * host->clk_mul / div) 116852983382SKevin Liu <= clock) 1169c3ed3877SArindam Nath break; 1170c3ed3877SArindam Nath } 1171c3ed3877SArindam Nath /* 1172c3ed3877SArindam Nath * Set Programmable Clock Mode in the Clock 1173c3ed3877SArindam Nath * Control register. 1174c3ed3877SArindam Nath */ 1175c3ed3877SArindam Nath clk = SDHCI_PROG_CLOCK_MODE; 1176df16219fSGiuseppe CAVALLARO real_div = div; 1177df16219fSGiuseppe CAVALLARO clk_mul = host->clk_mul; 1178c3ed3877SArindam Nath div--; 1179c3ed3877SArindam Nath } else { 118085105c53SZhangfei Gao /* Version 3.00 divisors must be a multiple of 2. */ 118185105c53SZhangfei Gao if (host->max_clk <= clock) 118285105c53SZhangfei Gao div = 1; 118385105c53SZhangfei Gao else { 1184c3ed3877SArindam Nath for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1185c3ed3877SArindam Nath div += 2) { 118685105c53SZhangfei Gao if ((host->max_clk / div) <= clock) 118785105c53SZhangfei Gao break; 118885105c53SZhangfei Gao } 118985105c53SZhangfei Gao } 1190df16219fSGiuseppe CAVALLARO real_div = div; 1191c3ed3877SArindam Nath div >>= 1; 1192c3ed3877SArindam Nath } 119385105c53SZhangfei Gao } else { 119485105c53SZhangfei Gao /* Version 2.00 divisors must be a power of 2. */ 11950397526dSZhangfei Gao for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 11961c6a0718SPierre Ossman if ((host->max_clk / div) <= clock) 11971c6a0718SPierre Ossman break; 11981c6a0718SPierre Ossman } 1199df16219fSGiuseppe CAVALLARO real_div = div; 12001c6a0718SPierre Ossman div >>= 1; 1201c3ed3877SArindam Nath } 12021c6a0718SPierre Ossman 120352983382SKevin Liu clock_set: 120403d6f5ffSAisheng Dong if (real_div) 1205df16219fSGiuseppe CAVALLARO host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1206c3ed3877SArindam Nath clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 120785105c53SZhangfei Gao clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 120885105c53SZhangfei Gao << SDHCI_DIVIDER_HI_SHIFT; 12091c6a0718SPierre Ossman clk |= SDHCI_CLOCK_INT_EN; 12104e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12111c6a0718SPierre Ossman 121227f6cb16SChris Ball /* Wait max 20 ms */ 121327f6cb16SChris Ball timeout = 20; 12144e4141a5SAnton Vorontsov while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 12151c6a0718SPierre Ossman & SDHCI_CLOCK_INT_STABLE)) { 12161c6a0718SPierre Ossman if (timeout == 0) { 1217a3c76eb9SGirish K S pr_err("%s: Internal clock never " 12181c6a0718SPierre Ossman "stabilised.\n", mmc_hostname(host->mmc)); 12191c6a0718SPierre Ossman sdhci_dumpregs(host); 12201c6a0718SPierre Ossman return; 12211c6a0718SPierre Ossman } 12221c6a0718SPierre Ossman timeout--; 12231c6a0718SPierre Ossman mdelay(1); 12241c6a0718SPierre Ossman } 12251c6a0718SPierre Ossman 12261c6a0718SPierre Ossman clk |= SDHCI_CLOCK_CARD_EN; 12274e4141a5SAnton Vorontsov sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 12281c6a0718SPierre Ossman } 12291771059cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_clock); 12301c6a0718SPierre Ossman 123124fbb3caSRussell King static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 123224fbb3caSRussell King unsigned short vdd) 12331c6a0718SPierre Ossman { 12343a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 12358364248aSGiuseppe Cavallaro u8 pwr = 0; 12361c6a0718SPierre Ossman 123752221610STim Kryger if (!IS_ERR(mmc->supply.vmmc)) { 123852221610STim Kryger spin_unlock_irq(&host->lock); 12394e743f1fSMarkus Mayer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 124052221610STim Kryger spin_lock_irq(&host->lock); 124152221610STim Kryger return; 124252221610STim Kryger } 124352221610STim Kryger 124424fbb3caSRussell King if (mode != MMC_POWER_OFF) { 124524fbb3caSRussell King switch (1 << vdd) { 1246ae628903SPierre Ossman case MMC_VDD_165_195: 1247ae628903SPierre Ossman pwr = SDHCI_POWER_180; 1248ae628903SPierre Ossman break; 1249ae628903SPierre Ossman case MMC_VDD_29_30: 1250ae628903SPierre Ossman case MMC_VDD_30_31: 1251ae628903SPierre Ossman pwr = SDHCI_POWER_300; 1252ae628903SPierre Ossman break; 1253ae628903SPierre Ossman case MMC_VDD_32_33: 1254ae628903SPierre Ossman case MMC_VDD_33_34: 1255ae628903SPierre Ossman pwr = SDHCI_POWER_330; 1256ae628903SPierre Ossman break; 1257ae628903SPierre Ossman default: 1258ae628903SPierre Ossman BUG(); 1259ae628903SPierre Ossman } 1260ae628903SPierre Ossman } 1261ae628903SPierre Ossman 1262ae628903SPierre Ossman if (host->pwr == pwr) 1263e921a8b6SRussell King return; 12641c6a0718SPierre Ossman 1265ae628903SPierre Ossman host->pwr = pwr; 1266ae628903SPierre Ossman 1267ae628903SPierre Ossman if (pwr == 0) { 12684e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1269f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1270f0710a55SAdrian Hunter sdhci_runtime_pm_bus_off(host); 127124fbb3caSRussell King vdd = 0; 1272e921a8b6SRussell King } else { 12731c6a0718SPierre Ossman /* 12741c6a0718SPierre Ossman * Spec says that we should clear the power reg before setting 12751c6a0718SPierre Ossman * a new value. Some controllers don't seem to like this though. 12761c6a0718SPierre Ossman */ 1277b8c86fc5SPierre Ossman if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 12784e4141a5SAnton Vorontsov sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 12791c6a0718SPierre Ossman 1280e08c1694SAndres Salomon /* 1281e921a8b6SRussell King * At least the Marvell CaFe chip gets confused if we set the 1282e921a8b6SRussell King * voltage and set turn on power at the same time, so set the 1283e921a8b6SRussell King * voltage first. 1284e08c1694SAndres Salomon */ 128511a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 12864e4141a5SAnton Vorontsov sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 12871c6a0718SPierre Ossman 1288ae628903SPierre Ossman pwr |= SDHCI_POWER_ON; 1289ae628903SPierre Ossman 1290ae628903SPierre Ossman sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1291557b0697SHarald Welte 1292f0710a55SAdrian Hunter if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1293f0710a55SAdrian Hunter sdhci_runtime_pm_bus_on(host); 1294f0710a55SAdrian Hunter 1295557b0697SHarald Welte /* 1296e921a8b6SRussell King * Some controllers need an extra 10ms delay of 10ms before 1297e921a8b6SRussell King * they can apply clock after applying power 1298557b0697SHarald Welte */ 129911a2f1b7SPierre Ossman if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1300557b0697SHarald Welte mdelay(10); 1301e921a8b6SRussell King } 13021c6a0718SPierre Ossman } 13031c6a0718SPierre Ossman 13041c6a0718SPierre Ossman /*****************************************************************************\ 13051c6a0718SPierre Ossman * * 13061c6a0718SPierre Ossman * MMC callbacks * 13071c6a0718SPierre Ossman * * 13081c6a0718SPierre Ossman \*****************************************************************************/ 13091c6a0718SPierre Ossman 13101c6a0718SPierre Ossman static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 13111c6a0718SPierre Ossman { 13121c6a0718SPierre Ossman struct sdhci_host *host; 1313505a8680SShawn Guo int present; 13141c6a0718SPierre Ossman unsigned long flags; 1315473b095aSAaron Lu u32 tuning_opcode; 13161c6a0718SPierre Ossman 13171c6a0718SPierre Ossman host = mmc_priv(mmc); 13181c6a0718SPierre Ossman 131966fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 132066fd8ad5SAdrian Hunter 13211c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 13221c6a0718SPierre Ossman 13231c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 13241c6a0718SPierre Ossman 1325f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 13261c6a0718SPierre Ossman sdhci_activate_led(host); 13272f730fecSPierre Ossman #endif 1328e89d456fSAndrei Warkentin 1329e89d456fSAndrei Warkentin /* 1330e89d456fSAndrei Warkentin * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1331e89d456fSAndrei Warkentin * requests if Auto-CMD12 is enabled. 1332e89d456fSAndrei Warkentin */ 1333e89d456fSAndrei Warkentin if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1334c4512f79SJerry Huang if (mrq->stop) { 1335c4512f79SJerry Huang mrq->data->stop = NULL; 1336c4512f79SJerry Huang mrq->stop = NULL; 1337c4512f79SJerry Huang } 1338c4512f79SJerry Huang } 13391c6a0718SPierre Ossman 13401c6a0718SPierre Ossman host->mrq = mrq; 13411c6a0718SPierre Ossman 1342505a8680SShawn Guo /* 1343505a8680SShawn Guo * Firstly check card presence from cd-gpio. The return could 1344505a8680SShawn Guo * be one of the following possibilities: 1345505a8680SShawn Guo * negative: cd-gpio is not available 1346505a8680SShawn Guo * zero: cd-gpio is used, and card is removed 1347505a8680SShawn Guo * one: cd-gpio is used, and card is present 1348505a8680SShawn Guo */ 1349505a8680SShawn Guo present = mmc_gpio_get_cd(host->mmc); 1350505a8680SShawn Guo if (present < 0) { 135168d1fb7eSAnton Vorontsov /* If polling, assume that the card is always present. */ 135268d1fb7eSAnton Vorontsov if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1353505a8680SShawn Guo present = 1; 135468d1fb7eSAnton Vorontsov else 135568d1fb7eSAnton Vorontsov present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 135668d1fb7eSAnton Vorontsov SDHCI_CARD_PRESENT; 1357bec9d4e5SGuennadi Liakhovetski } 1358bec9d4e5SGuennadi Liakhovetski 135968d1fb7eSAnton Vorontsov if (!present || host->flags & SDHCI_DEVICE_DEAD) { 136017b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 13611c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 1362cf2b5eeaSArindam Nath } else { 1363cf2b5eeaSArindam Nath u32 present_state; 1364cf2b5eeaSArindam Nath 1365cf2b5eeaSArindam Nath present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1366cf2b5eeaSArindam Nath /* 1367cf2b5eeaSArindam Nath * Check if the re-tuning timer has already expired and there 1368cf2b5eeaSArindam Nath * is no on-going data transfer. If so, we need to execute 1369cf2b5eeaSArindam Nath * tuning procedure before sending command. 1370cf2b5eeaSArindam Nath */ 1371cf2b5eeaSArindam Nath if ((host->flags & SDHCI_NEEDS_RETUNING) && 1372cf2b5eeaSArindam Nath !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 137314efd957SChris Ball if (mmc->card) { 137414efd957SChris Ball /* eMMC uses cmd21 but sd and sdio use cmd19 */ 137514efd957SChris Ball tuning_opcode = 137614efd957SChris Ball mmc->card->type == MMC_TYPE_MMC ? 1377473b095aSAaron Lu MMC_SEND_TUNING_BLOCK_HS200 : 1378473b095aSAaron Lu MMC_SEND_TUNING_BLOCK; 137963c21180SChuansheng Liu 138063c21180SChuansheng Liu /* Here we need to set the host->mrq to NULL, 138163c21180SChuansheng Liu * in case the pending finish_tasklet 138263c21180SChuansheng Liu * finishes it incorrectly. 138363c21180SChuansheng Liu */ 138463c21180SChuansheng Liu host->mrq = NULL; 138563c21180SChuansheng Liu 1386cf2b5eeaSArindam Nath spin_unlock_irqrestore(&host->lock, flags); 1387473b095aSAaron Lu sdhci_execute_tuning(mmc, tuning_opcode); 1388cf2b5eeaSArindam Nath spin_lock_irqsave(&host->lock, flags); 1389cf2b5eeaSArindam Nath 1390cf2b5eeaSArindam Nath /* Restore original mmc_request structure */ 1391cf2b5eeaSArindam Nath host->mrq = mrq; 1392cf2b5eeaSArindam Nath } 139314efd957SChris Ball } 1394cf2b5eeaSArindam Nath 13958edf6371SAndrei Warkentin if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1396e89d456fSAndrei Warkentin sdhci_send_command(host, mrq->sbc); 1397e89d456fSAndrei Warkentin else 13981c6a0718SPierre Ossman sdhci_send_command(host, mrq->cmd); 1399cf2b5eeaSArindam Nath } 14001c6a0718SPierre Ossman 14011c6a0718SPierre Ossman mmiowb(); 14021c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 14031c6a0718SPierre Ossman } 14041c6a0718SPierre Ossman 14052317f56cSRussell King void sdhci_set_bus_width(struct sdhci_host *host, int width) 14062317f56cSRussell King { 14072317f56cSRussell King u8 ctrl; 14082317f56cSRussell King 14092317f56cSRussell King ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 14102317f56cSRussell King if (width == MMC_BUS_WIDTH_8) { 14112317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 14122317f56cSRussell King if (host->version >= SDHCI_SPEC_300) 14132317f56cSRussell King ctrl |= SDHCI_CTRL_8BITBUS; 14142317f56cSRussell King } else { 14152317f56cSRussell King if (host->version >= SDHCI_SPEC_300) 14162317f56cSRussell King ctrl &= ~SDHCI_CTRL_8BITBUS; 14172317f56cSRussell King if (width == MMC_BUS_WIDTH_4) 14182317f56cSRussell King ctrl |= SDHCI_CTRL_4BITBUS; 14192317f56cSRussell King else 14202317f56cSRussell King ctrl &= ~SDHCI_CTRL_4BITBUS; 14212317f56cSRussell King } 14222317f56cSRussell King sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 14232317f56cSRussell King } 14242317f56cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 14252317f56cSRussell King 142696d7b78cSRussell King void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 142796d7b78cSRussell King { 142896d7b78cSRussell King u16 ctrl_2; 142996d7b78cSRussell King 143096d7b78cSRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 143196d7b78cSRussell King /* Select Bus Speed Mode for host */ 143296d7b78cSRussell King ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 143396d7b78cSRussell King if ((timing == MMC_TIMING_MMC_HS200) || 143496d7b78cSRussell King (timing == MMC_TIMING_UHS_SDR104)) 143596d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 143696d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR12) 143796d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 143896d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR25) 143996d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 144096d7b78cSRussell King else if (timing == MMC_TIMING_UHS_SDR50) 144196d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 144296d7b78cSRussell King else if ((timing == MMC_TIMING_UHS_DDR50) || 144396d7b78cSRussell King (timing == MMC_TIMING_MMC_DDR52)) 144496d7b78cSRussell King ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 144596d7b78cSRussell King sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 144696d7b78cSRussell King } 144796d7b78cSRussell King EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 144896d7b78cSRussell King 144966fd8ad5SAdrian Hunter static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 14501c6a0718SPierre Ossman { 14511c6a0718SPierre Ossman unsigned long flags; 14521c6a0718SPierre Ossman u8 ctrl; 14533a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 14541c6a0718SPierre Ossman 14551c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 14561c6a0718SPierre Ossman 1457ceb6143bSAdrian Hunter if (host->flags & SDHCI_DEVICE_DEAD) { 1458ceb6143bSAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 14593a48edc4STim Kryger if (!IS_ERR(mmc->supply.vmmc) && 14603a48edc4STim Kryger ios->power_mode == MMC_POWER_OFF) 14614e743f1fSMarkus Mayer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1462ceb6143bSAdrian Hunter return; 1463ceb6143bSAdrian Hunter } 14641e72859eSPierre Ossman 14651c6a0718SPierre Ossman /* 14661c6a0718SPierre Ossman * Reset the chip on each power off. 14671c6a0718SPierre Ossman * Should clear out any weird states. 14681c6a0718SPierre Ossman */ 14691c6a0718SPierre Ossman if (ios->power_mode == MMC_POWER_OFF) { 14704e4141a5SAnton Vorontsov sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 14717260cf5eSAnton Vorontsov sdhci_reinit(host); 14721c6a0718SPierre Ossman } 14731c6a0718SPierre Ossman 147452983382SKevin Liu if (host->version >= SDHCI_SPEC_300 && 1475372c4634SDong Aisheng (ios->power_mode == MMC_POWER_UP) && 1476372c4634SDong Aisheng !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 147752983382SKevin Liu sdhci_enable_preset_value(host, false); 147852983382SKevin Liu 1479373073efSRussell King if (!ios->clock || ios->clock != host->clock) { 14801771059cSRussell King host->ops->set_clock(host, ios->clock); 1481373073efSRussell King host->clock = ios->clock; 148203d6f5ffSAisheng Dong 148303d6f5ffSAisheng Dong if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 148403d6f5ffSAisheng Dong host->clock) { 148503d6f5ffSAisheng Dong host->timeout_clk = host->mmc->actual_clock ? 148603d6f5ffSAisheng Dong host->mmc->actual_clock / 1000 : 148703d6f5ffSAisheng Dong host->clock / 1000; 148803d6f5ffSAisheng Dong host->mmc->max_busy_timeout = 148903d6f5ffSAisheng Dong host->ops->get_max_timeout_count ? 149003d6f5ffSAisheng Dong host->ops->get_max_timeout_count(host) : 149103d6f5ffSAisheng Dong 1 << 27; 149203d6f5ffSAisheng Dong host->mmc->max_busy_timeout /= host->timeout_clk; 149303d6f5ffSAisheng Dong } 1494373073efSRussell King } 14951c6a0718SPierre Ossman 149624fbb3caSRussell King sdhci_set_power(host, ios->power_mode, ios->vdd); 14971c6a0718SPierre Ossman 1498643a81ffSPhilip Rakity if (host->ops->platform_send_init_74_clocks) 1499643a81ffSPhilip Rakity host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1500643a81ffSPhilip Rakity 15012317f56cSRussell King host->ops->set_bus_width(host, ios->bus_width); 150215ec4461SPhilip Rakity 150315ec4461SPhilip Rakity ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 15041c6a0718SPierre Ossman 15053ab9c8daSPhilip Rakity if ((ios->timing == MMC_TIMING_SD_HS || 15063ab9c8daSPhilip Rakity ios->timing == MMC_TIMING_MMC_HS) 15073ab9c8daSPhilip Rakity && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 15081c6a0718SPierre Ossman ctrl |= SDHCI_CTRL_HISPD; 15091c6a0718SPierre Ossman else 15101c6a0718SPierre Ossman ctrl &= ~SDHCI_CTRL_HISPD; 15111c6a0718SPierre Ossman 1512d6d50a15SArindam Nath if (host->version >= SDHCI_SPEC_300) { 151349c468fcSArindam Nath u16 clk, ctrl_2; 151449c468fcSArindam Nath 151549c468fcSArindam Nath /* In case of UHS-I modes, set High Speed Enable */ 1516069c9f14SGirish K S if ((ios->timing == MMC_TIMING_MMC_HS200) || 1517bb8175a8SSeungwon Jeon (ios->timing == MMC_TIMING_MMC_DDR52) || 1518069c9f14SGirish K S (ios->timing == MMC_TIMING_UHS_SDR50) || 151949c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_SDR104) || 152049c468fcSArindam Nath (ios->timing == MMC_TIMING_UHS_DDR50) || 1521dd8df17fSAlexander Elbs (ios->timing == MMC_TIMING_UHS_SDR25)) 152249c468fcSArindam Nath ctrl |= SDHCI_CTRL_HISPD; 1523d6d50a15SArindam Nath 1524da91a8f9SRussell King if (!host->preset_enabled) { 1525758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1526d6d50a15SArindam Nath /* 1527d6d50a15SArindam Nath * We only need to set Driver Strength if the 1528d6d50a15SArindam Nath * preset value enable is not set. 1529d6d50a15SArindam Nath */ 1530da91a8f9SRussell King ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1531d6d50a15SArindam Nath ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1532d6d50a15SArindam Nath if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1533d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1534d6d50a15SArindam Nath else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1535d6d50a15SArindam Nath ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1536d6d50a15SArindam Nath 1537d6d50a15SArindam Nath sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1538758535c4SArindam Nath } else { 1539758535c4SArindam Nath /* 1540758535c4SArindam Nath * According to SDHC Spec v3.00, if the Preset Value 1541758535c4SArindam Nath * Enable in the Host Control 2 register is set, we 1542758535c4SArindam Nath * need to reset SD Clock Enable before changing High 1543758535c4SArindam Nath * Speed Enable to avoid generating clock gliches. 1544758535c4SArindam Nath */ 1545758535c4SArindam Nath 1546758535c4SArindam Nath /* Reset SD Clock Enable */ 1547758535c4SArindam Nath clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1548758535c4SArindam Nath clk &= ~SDHCI_CLOCK_CARD_EN; 1549758535c4SArindam Nath sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1550758535c4SArindam Nath 1551758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1552758535c4SArindam Nath 1553758535c4SArindam Nath /* Re-enable SD Clock */ 15541771059cSRussell King host->ops->set_clock(host, host->clock); 1555d6d50a15SArindam Nath } 155649c468fcSArindam Nath 15576322cdd0SPhilip Rakity /* Reset SD Clock Enable */ 15586322cdd0SPhilip Rakity clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 15596322cdd0SPhilip Rakity clk &= ~SDHCI_CLOCK_CARD_EN; 15606322cdd0SPhilip Rakity sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 15616322cdd0SPhilip Rakity 15626322cdd0SPhilip Rakity host->ops->set_uhs_signaling(host, ios->timing); 1563d975f121SRussell King host->timing = ios->timing; 156449c468fcSArindam Nath 156552983382SKevin Liu if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 156652983382SKevin Liu ((ios->timing == MMC_TIMING_UHS_SDR12) || 156752983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR25) || 156852983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR50) || 156952983382SKevin Liu (ios->timing == MMC_TIMING_UHS_SDR104) || 157052983382SKevin Liu (ios->timing == MMC_TIMING_UHS_DDR50))) { 157152983382SKevin Liu u16 preset; 157252983382SKevin Liu 157352983382SKevin Liu sdhci_enable_preset_value(host, true); 157452983382SKevin Liu preset = sdhci_get_preset_value(host); 157552983382SKevin Liu ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 157652983382SKevin Liu >> SDHCI_PRESET_DRV_SHIFT; 157752983382SKevin Liu } 157852983382SKevin Liu 157949c468fcSArindam Nath /* Re-enable SD Clock */ 15801771059cSRussell King host->ops->set_clock(host, host->clock); 1581758535c4SArindam Nath } else 1582758535c4SArindam Nath sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1583d6d50a15SArindam Nath 1584b8352260SLeandro Dorileo /* 1585b8352260SLeandro Dorileo * Some (ENE) controllers go apeshit on some ios operation, 1586b8352260SLeandro Dorileo * signalling timeout and CRC errors even on CMD0. Resetting 1587b8352260SLeandro Dorileo * it on each ios seems to solve the problem. 1588b8352260SLeandro Dorileo */ 1589b8c86fc5SPierre Ossman if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 159003231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1591b8352260SLeandro Dorileo 15921c6a0718SPierre Ossman mmiowb(); 15931c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 15941c6a0718SPierre Ossman } 15951c6a0718SPierre Ossman 159666fd8ad5SAdrian Hunter static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 159766fd8ad5SAdrian Hunter { 159866fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 159966fd8ad5SAdrian Hunter 160066fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 160166fd8ad5SAdrian Hunter sdhci_do_set_ios(host, ios); 160266fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 160366fd8ad5SAdrian Hunter } 160466fd8ad5SAdrian Hunter 160594144a46SKevin Liu static int sdhci_do_get_cd(struct sdhci_host *host) 160694144a46SKevin Liu { 160794144a46SKevin Liu int gpio_cd = mmc_gpio_get_cd(host->mmc); 160894144a46SKevin Liu 160994144a46SKevin Liu if (host->flags & SDHCI_DEVICE_DEAD) 161094144a46SKevin Liu return 0; 161194144a46SKevin Liu 161294144a46SKevin Liu /* If polling/nonremovable, assume that the card is always present. */ 161394144a46SKevin Liu if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 161494144a46SKevin Liu (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 161594144a46SKevin Liu return 1; 161694144a46SKevin Liu 161794144a46SKevin Liu /* Try slot gpio detect */ 161894144a46SKevin Liu if (!IS_ERR_VALUE(gpio_cd)) 161994144a46SKevin Liu return !!gpio_cd; 162094144a46SKevin Liu 162194144a46SKevin Liu /* Host native card detect */ 162294144a46SKevin Liu return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 162394144a46SKevin Liu } 162494144a46SKevin Liu 162594144a46SKevin Liu static int sdhci_get_cd(struct mmc_host *mmc) 162694144a46SKevin Liu { 162794144a46SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 162894144a46SKevin Liu int ret; 162994144a46SKevin Liu 163094144a46SKevin Liu sdhci_runtime_pm_get(host); 163194144a46SKevin Liu ret = sdhci_do_get_cd(host); 163294144a46SKevin Liu sdhci_runtime_pm_put(host); 163394144a46SKevin Liu return ret; 163494144a46SKevin Liu } 163594144a46SKevin Liu 163666fd8ad5SAdrian Hunter static int sdhci_check_ro(struct sdhci_host *host) 16371c6a0718SPierre Ossman { 16381c6a0718SPierre Ossman unsigned long flags; 16392dfb579cSWolfram Sang int is_readonly; 16401c6a0718SPierre Ossman 16411c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 16421c6a0718SPierre Ossman 16431e72859eSPierre Ossman if (host->flags & SDHCI_DEVICE_DEAD) 16442dfb579cSWolfram Sang is_readonly = 0; 16452dfb579cSWolfram Sang else if (host->ops->get_ro) 16462dfb579cSWolfram Sang is_readonly = host->ops->get_ro(host); 16471e72859eSPierre Ossman else 16482dfb579cSWolfram Sang is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 16492dfb579cSWolfram Sang & SDHCI_WRITE_PROTECT); 16501c6a0718SPierre Ossman 16511c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 16521c6a0718SPierre Ossman 16532dfb579cSWolfram Sang /* This quirk needs to be replaced by a callback-function later */ 16542dfb579cSWolfram Sang return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 16552dfb579cSWolfram Sang !is_readonly : is_readonly; 16561c6a0718SPierre Ossman } 16571c6a0718SPierre Ossman 165882b0e23aSTakashi Iwai #define SAMPLE_COUNT 5 165982b0e23aSTakashi Iwai 166066fd8ad5SAdrian Hunter static int sdhci_do_get_ro(struct sdhci_host *host) 166182b0e23aSTakashi Iwai { 166282b0e23aSTakashi Iwai int i, ro_count; 166382b0e23aSTakashi Iwai 166482b0e23aSTakashi Iwai if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 166566fd8ad5SAdrian Hunter return sdhci_check_ro(host); 166682b0e23aSTakashi Iwai 166782b0e23aSTakashi Iwai ro_count = 0; 166882b0e23aSTakashi Iwai for (i = 0; i < SAMPLE_COUNT; i++) { 166966fd8ad5SAdrian Hunter if (sdhci_check_ro(host)) { 167082b0e23aSTakashi Iwai if (++ro_count > SAMPLE_COUNT / 2) 167182b0e23aSTakashi Iwai return 1; 167282b0e23aSTakashi Iwai } 167382b0e23aSTakashi Iwai msleep(30); 167482b0e23aSTakashi Iwai } 167582b0e23aSTakashi Iwai return 0; 167682b0e23aSTakashi Iwai } 167782b0e23aSTakashi Iwai 167820758b66SAdrian Hunter static void sdhci_hw_reset(struct mmc_host *mmc) 167920758b66SAdrian Hunter { 168020758b66SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 168120758b66SAdrian Hunter 168220758b66SAdrian Hunter if (host->ops && host->ops->hw_reset) 168320758b66SAdrian Hunter host->ops->hw_reset(host); 168420758b66SAdrian Hunter } 168520758b66SAdrian Hunter 168666fd8ad5SAdrian Hunter static int sdhci_get_ro(struct mmc_host *mmc) 1687f75979b7SPierre Ossman { 168866fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 168966fd8ad5SAdrian Hunter int ret; 1690f75979b7SPierre Ossman 169166fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 169266fd8ad5SAdrian Hunter ret = sdhci_do_get_ro(host); 169366fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 169466fd8ad5SAdrian Hunter return ret; 169566fd8ad5SAdrian Hunter } 1696f75979b7SPierre Ossman 169766fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 169866fd8ad5SAdrian Hunter { 1699be138554SRussell King if (!(host->flags & SDHCI_DEVICE_DEAD)) { 170066fd8ad5SAdrian Hunter if (enable) 1701b537f94cSRussell King host->ier |= SDHCI_INT_CARD_INT; 17027260cf5eSAnton Vorontsov else 1703b537f94cSRussell King host->ier &= ~SDHCI_INT_CARD_INT; 1704b537f94cSRussell King 1705b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1706b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1707f75979b7SPierre Ossman mmiowb(); 170866fd8ad5SAdrian Hunter } 1709ef104333SRussell King } 1710f75979b7SPierre Ossman 171166fd8ad5SAdrian Hunter static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 171266fd8ad5SAdrian Hunter { 171366fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 171466fd8ad5SAdrian Hunter unsigned long flags; 171566fd8ad5SAdrian Hunter 1716ef104333SRussell King sdhci_runtime_pm_get(host); 1717ef104333SRussell King 171866fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 1719ef104333SRussell King if (enable) 1720ef104333SRussell King host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1721ef104333SRussell King else 1722ef104333SRussell King host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1723ef104333SRussell King 172466fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, enable); 1725f75979b7SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 1726ef104333SRussell King 1727ef104333SRussell King sdhci_runtime_pm_put(host); 1728f75979b7SPierre Ossman } 1729f75979b7SPierre Ossman 173020b92a30SKevin Liu static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 173121f5998fSFabio Estevam struct mmc_ios *ios) 1732f2119df6SArindam Nath { 17333a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 173420b92a30SKevin Liu u16 ctrl; 17356231f3deSPhilip Rakity int ret; 1736f2119df6SArindam Nath 173720b92a30SKevin Liu /* 173820b92a30SKevin Liu * Signal Voltage Switching is only applicable for Host Controllers 173920b92a30SKevin Liu * v3.00 and above. 174020b92a30SKevin Liu */ 174120b92a30SKevin Liu if (host->version < SDHCI_SPEC_300) 174220b92a30SKevin Liu return 0; 174320b92a30SKevin Liu 174420b92a30SKevin Liu ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 174520b92a30SKevin Liu 174621f5998fSFabio Estevam switch (ios->signal_voltage) { 174720b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_330: 1748f2119df6SArindam Nath /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1749f2119df6SArindam Nath ctrl &= ~SDHCI_CTRL_VDD_180; 1750f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1751f2119df6SArindam Nath 17523a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 17533a48edc4STim Kryger ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, 17543a48edc4STim Kryger 3600000); 17556231f3deSPhilip Rakity if (ret) { 17566231f3deSPhilip Rakity pr_warning("%s: Switching to 3.3V signalling voltage " 17574e743f1fSMarkus Mayer " failed\n", mmc_hostname(mmc)); 17586231f3deSPhilip Rakity return -EIO; 17596231f3deSPhilip Rakity } 17606231f3deSPhilip Rakity } 1761f2119df6SArindam Nath /* Wait for 5ms */ 1762f2119df6SArindam Nath usleep_range(5000, 5500); 1763f2119df6SArindam Nath 1764f2119df6SArindam Nath /* 3.3V regulator output should be stable within 5 ms */ 1765f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1766f2119df6SArindam Nath if (!(ctrl & SDHCI_CTRL_VDD_180)) 1767f2119df6SArindam Nath return 0; 17686231f3deSPhilip Rakity 17696231f3deSPhilip Rakity pr_warning("%s: 3.3V regulator output did not became stable\n", 17704e743f1fSMarkus Mayer mmc_hostname(mmc)); 17716231f3deSPhilip Rakity 177220b92a30SKevin Liu return -EAGAIN; 177320b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_180: 17743a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 17753a48edc4STim Kryger ret = regulator_set_voltage(mmc->supply.vqmmc, 177620b92a30SKevin Liu 1700000, 1950000); 177720b92a30SKevin Liu if (ret) { 177820b92a30SKevin Liu pr_warning("%s: Switching to 1.8V signalling voltage " 17794e743f1fSMarkus Mayer " failed\n", mmc_hostname(mmc)); 1780f2119df6SArindam Nath return -EIO; 1781f2119df6SArindam Nath } 178220b92a30SKevin Liu } 17836231f3deSPhilip Rakity 1784f2119df6SArindam Nath /* 1785f2119df6SArindam Nath * Enable 1.8V Signal Enable in the Host Control2 1786f2119df6SArindam Nath * register 1787f2119df6SArindam Nath */ 1788f2119df6SArindam Nath ctrl |= SDHCI_CTRL_VDD_180; 1789f2119df6SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1790f2119df6SArindam Nath 179120b92a30SKevin Liu /* 1.8V regulator output should be stable within 5 ms */ 1792f2119df6SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 179320b92a30SKevin Liu if (ctrl & SDHCI_CTRL_VDD_180) 1794f2119df6SArindam Nath return 0; 1795f2119df6SArindam Nath 179620b92a30SKevin Liu pr_warning("%s: 1.8V regulator output did not became stable\n", 17974e743f1fSMarkus Mayer mmc_hostname(mmc)); 17986231f3deSPhilip Rakity 1799f2119df6SArindam Nath return -EAGAIN; 180020b92a30SKevin Liu case MMC_SIGNAL_VOLTAGE_120: 18013a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 18023a48edc4STim Kryger ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, 18033a48edc4STim Kryger 1300000); 180420b92a30SKevin Liu if (ret) { 180520b92a30SKevin Liu pr_warning("%s: Switching to 1.2V signalling voltage " 18064e743f1fSMarkus Mayer " failed\n", mmc_hostname(mmc)); 180720b92a30SKevin Liu return -EIO; 18086231f3deSPhilip Rakity } 180920b92a30SKevin Liu } 18106231f3deSPhilip Rakity return 0; 181120b92a30SKevin Liu default: 1812f2119df6SArindam Nath /* No signal voltage switch required */ 1813f2119df6SArindam Nath return 0; 1814f2119df6SArindam Nath } 181520b92a30SKevin Liu } 1816f2119df6SArindam Nath 181766fd8ad5SAdrian Hunter static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 181821f5998fSFabio Estevam struct mmc_ios *ios) 181966fd8ad5SAdrian Hunter { 182066fd8ad5SAdrian Hunter struct sdhci_host *host = mmc_priv(mmc); 182166fd8ad5SAdrian Hunter int err; 182266fd8ad5SAdrian Hunter 182366fd8ad5SAdrian Hunter if (host->version < SDHCI_SPEC_300) 182466fd8ad5SAdrian Hunter return 0; 182566fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 182621f5998fSFabio Estevam err = sdhci_do_start_signal_voltage_switch(host, ios); 182766fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 182866fd8ad5SAdrian Hunter return err; 182966fd8ad5SAdrian Hunter } 183066fd8ad5SAdrian Hunter 183120b92a30SKevin Liu static int sdhci_card_busy(struct mmc_host *mmc) 183220b92a30SKevin Liu { 183320b92a30SKevin Liu struct sdhci_host *host = mmc_priv(mmc); 183420b92a30SKevin Liu u32 present_state; 183520b92a30SKevin Liu 183620b92a30SKevin Liu sdhci_runtime_pm_get(host); 183720b92a30SKevin Liu /* Check whether DAT[3:0] is 0000 */ 183820b92a30SKevin Liu present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 183920b92a30SKevin Liu sdhci_runtime_pm_put(host); 184020b92a30SKevin Liu 184120b92a30SKevin Liu return !(present_state & SDHCI_DATA_LVL_MASK); 184220b92a30SKevin Liu } 184320b92a30SKevin Liu 1844069c9f14SGirish K S static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1845b513ea25SArindam Nath { 18464b6f37d3SRussell King struct sdhci_host *host = mmc_priv(mmc); 1847b513ea25SArindam Nath u16 ctrl; 1848b513ea25SArindam Nath int tuning_loop_counter = MAX_TUNING_LOOP; 1849b513ea25SArindam Nath int err = 0; 18502b35bd83SAisheng Dong unsigned long flags; 1851b513ea25SArindam Nath 185266fd8ad5SAdrian Hunter sdhci_runtime_pm_get(host); 18532b35bd83SAisheng Dong spin_lock_irqsave(&host->lock, flags); 1854b513ea25SArindam Nath 1855b513ea25SArindam Nath /* 1856069c9f14SGirish K S * The Host Controller needs tuning only in case of SDR104 mode 1857069c9f14SGirish K S * and for SDR50 mode when Use Tuning for SDR50 is set in the 1858b513ea25SArindam Nath * Capabilities register. 1859069c9f14SGirish K S * If the Host Controller supports the HS200 mode then the 1860069c9f14SGirish K S * tuning function has to be executed. 1861b513ea25SArindam Nath */ 18624b6f37d3SRussell King switch (host->timing) { 18634b6f37d3SRussell King case MMC_TIMING_MMC_HS200: 18644b6f37d3SRussell King case MMC_TIMING_UHS_SDR104: 18654b6f37d3SRussell King break; 1866069c9f14SGirish K S 18674b6f37d3SRussell King case MMC_TIMING_UHS_SDR50: 18684b6f37d3SRussell King if (host->flags & SDHCI_SDR50_NEEDS_TUNING || 18694b6f37d3SRussell King host->flags & SDHCI_SDR104_NEEDS_TUNING) 18704b6f37d3SRussell King break; 18714b6f37d3SRussell King /* FALLTHROUGH */ 18724b6f37d3SRussell King 18734b6f37d3SRussell King default: 18742b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 187566fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 1876b513ea25SArindam Nath return 0; 1877b513ea25SArindam Nath } 1878b513ea25SArindam Nath 187945251812SDong Aisheng if (host->ops->platform_execute_tuning) { 18802b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 188145251812SDong Aisheng err = host->ops->platform_execute_tuning(host, opcode); 188245251812SDong Aisheng sdhci_runtime_pm_put(host); 188345251812SDong Aisheng return err; 188445251812SDong Aisheng } 188545251812SDong Aisheng 18864b6f37d3SRussell King ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 18874b6f37d3SRussell King ctrl |= SDHCI_CTRL_EXEC_TUNING; 1888b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1889b513ea25SArindam Nath 1890b513ea25SArindam Nath /* 1891b513ea25SArindam Nath * As per the Host Controller spec v3.00, tuning command 1892b513ea25SArindam Nath * generates Buffer Read Ready interrupt, so enable that. 1893b513ea25SArindam Nath * 1894b513ea25SArindam Nath * Note: The spec clearly says that when tuning sequence 1895b513ea25SArindam Nath * is being performed, the controller does not generate 1896b513ea25SArindam Nath * interrupts other than Buffer Read Ready interrupt. But 1897b513ea25SArindam Nath * to make sure we don't hit a controller bug, we _only_ 1898b513ea25SArindam Nath * enable Buffer Read Ready interrupt here. 1899b513ea25SArindam Nath */ 1900b537f94cSRussell King sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1901b537f94cSRussell King sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1902b513ea25SArindam Nath 1903b513ea25SArindam Nath /* 1904b513ea25SArindam Nath * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1905b513ea25SArindam Nath * of loops reaches 40 times or a timeout of 150ms occurs. 1906b513ea25SArindam Nath */ 1907b513ea25SArindam Nath do { 1908b513ea25SArindam Nath struct mmc_command cmd = {0}; 190966fd8ad5SAdrian Hunter struct mmc_request mrq = {NULL}; 1910b513ea25SArindam Nath 1911069c9f14SGirish K S cmd.opcode = opcode; 1912b513ea25SArindam Nath cmd.arg = 0; 1913b513ea25SArindam Nath cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1914b513ea25SArindam Nath cmd.retries = 0; 1915b513ea25SArindam Nath cmd.data = NULL; 1916b513ea25SArindam Nath cmd.error = 0; 1917b513ea25SArindam Nath 19187ce45e95SAl Cooper if (tuning_loop_counter-- == 0) 19197ce45e95SAl Cooper break; 19207ce45e95SAl Cooper 1921b513ea25SArindam Nath mrq.cmd = &cmd; 1922b513ea25SArindam Nath host->mrq = &mrq; 1923b513ea25SArindam Nath 1924b513ea25SArindam Nath /* 1925b513ea25SArindam Nath * In response to CMD19, the card sends 64 bytes of tuning 1926b513ea25SArindam Nath * block to the Host Controller. So we set the block size 1927b513ea25SArindam Nath * to 64 here. 1928b513ea25SArindam Nath */ 1929069c9f14SGirish K S if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1930069c9f14SGirish K S if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1931069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1932069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1933069c9f14SGirish K S else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1934069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1935069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1936069c9f14SGirish K S } else { 1937069c9f14SGirish K S sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1938069c9f14SGirish K S SDHCI_BLOCK_SIZE); 1939069c9f14SGirish K S } 1940b513ea25SArindam Nath 1941b513ea25SArindam Nath /* 1942b513ea25SArindam Nath * The tuning block is sent by the card to the host controller. 1943b513ea25SArindam Nath * So we set the TRNS_READ bit in the Transfer Mode register. 1944b513ea25SArindam Nath * This also takes care of setting DMA Enable and Multi Block 1945b513ea25SArindam Nath * Select in the same register to 0. 1946b513ea25SArindam Nath */ 1947b513ea25SArindam Nath sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1948b513ea25SArindam Nath 1949b513ea25SArindam Nath sdhci_send_command(host, &cmd); 1950b513ea25SArindam Nath 1951b513ea25SArindam Nath host->cmd = NULL; 1952b513ea25SArindam Nath host->mrq = NULL; 1953b513ea25SArindam Nath 19542b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 1955b513ea25SArindam Nath /* Wait for Buffer Read Ready interrupt */ 1956b513ea25SArindam Nath wait_event_interruptible_timeout(host->buf_ready_int, 1957b513ea25SArindam Nath (host->tuning_done == 1), 1958b513ea25SArindam Nath msecs_to_jiffies(50)); 19592b35bd83SAisheng Dong spin_lock_irqsave(&host->lock, flags); 1960b513ea25SArindam Nath 1961b513ea25SArindam Nath if (!host->tuning_done) { 1962a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Timeout waiting for " 1963b513ea25SArindam Nath "Buffer Read Ready interrupt during tuning " 1964b513ea25SArindam Nath "procedure, falling back to fixed sampling " 1965b513ea25SArindam Nath "clock\n"); 1966b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1967b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1968b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1969b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1970b513ea25SArindam Nath 1971b513ea25SArindam Nath err = -EIO; 1972b513ea25SArindam Nath goto out; 1973b513ea25SArindam Nath } 1974b513ea25SArindam Nath 1975b513ea25SArindam Nath host->tuning_done = 0; 1976b513ea25SArindam Nath 1977b513ea25SArindam Nath ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1978197160d5SNick Sanders 1979197160d5SNick Sanders /* eMMC spec does not require a delay between tuning cycles */ 1980197160d5SNick Sanders if (opcode == MMC_SEND_TUNING_BLOCK) 1981b513ea25SArindam Nath mdelay(1); 1982b513ea25SArindam Nath } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1983b513ea25SArindam Nath 1984b513ea25SArindam Nath /* 1985b513ea25SArindam Nath * The Host Driver has exhausted the maximum number of loops allowed, 1986b513ea25SArindam Nath * so use fixed sampling frequency. 1987b513ea25SArindam Nath */ 19887ce45e95SAl Cooper if (tuning_loop_counter < 0) { 1989b513ea25SArindam Nath ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1990b513ea25SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 19917ce45e95SAl Cooper } 1992b513ea25SArindam Nath if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1993a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Tuning procedure" 1994b513ea25SArindam Nath " failed, falling back to fixed sampling" 1995b513ea25SArindam Nath " clock\n"); 1996b513ea25SArindam Nath err = -EIO; 1997b513ea25SArindam Nath } 1998b513ea25SArindam Nath 1999b513ea25SArindam Nath out: 2000cf2b5eeaSArindam Nath /* 2001cf2b5eeaSArindam Nath * If this is the very first time we are here, we start the retuning 2002cf2b5eeaSArindam Nath * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 2003cf2b5eeaSArindam Nath * flag won't be set, we check this condition before actually starting 2004cf2b5eeaSArindam Nath * the timer. 2005cf2b5eeaSArindam Nath */ 2006cf2b5eeaSArindam Nath if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 2007cf2b5eeaSArindam Nath (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 2008973905feSAaron Lu host->flags |= SDHCI_USING_RETUNING_TIMER; 2009cf2b5eeaSArindam Nath mod_timer(&host->tuning_timer, jiffies + 2010cf2b5eeaSArindam Nath host->tuning_count * HZ); 2011cf2b5eeaSArindam Nath /* Tuning mode 1 limits the maximum data length to 4MB */ 2012cf2b5eeaSArindam Nath mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 20132bc02485SArend van Spriel } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2014cf2b5eeaSArindam Nath host->flags &= ~SDHCI_NEEDS_RETUNING; 2015cf2b5eeaSArindam Nath /* Reload the new initial value for timer */ 2016cf2b5eeaSArindam Nath mod_timer(&host->tuning_timer, jiffies + 2017cf2b5eeaSArindam Nath host->tuning_count * HZ); 2018cf2b5eeaSArindam Nath } 2019cf2b5eeaSArindam Nath 2020cf2b5eeaSArindam Nath /* 2021cf2b5eeaSArindam Nath * In case tuning fails, host controllers which support re-tuning can 2022cf2b5eeaSArindam Nath * try tuning again at a later time, when the re-tuning timer expires. 2023cf2b5eeaSArindam Nath * So for these controllers, we return 0. Since there might be other 2024cf2b5eeaSArindam Nath * controllers who do not have this capability, we return error for 2025973905feSAaron Lu * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2026973905feSAaron Lu * a retuning timer to do the retuning for the card. 2027cf2b5eeaSArindam Nath */ 2028973905feSAaron Lu if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2029cf2b5eeaSArindam Nath err = 0; 2030cf2b5eeaSArindam Nath 2031b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2032b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 20332b35bd83SAisheng Dong spin_unlock_irqrestore(&host->lock, flags); 203466fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 2035b513ea25SArindam Nath 2036b513ea25SArindam Nath return err; 2037b513ea25SArindam Nath } 2038b513ea25SArindam Nath 203952983382SKevin Liu 204052983382SKevin Liu static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 20414d55c5a1SArindam Nath { 20424d55c5a1SArindam Nath /* Host Controller v3.00 defines preset value registers */ 20434d55c5a1SArindam Nath if (host->version < SDHCI_SPEC_300) 20444d55c5a1SArindam Nath return; 20454d55c5a1SArindam Nath 20464d55c5a1SArindam Nath /* 20474d55c5a1SArindam Nath * We only enable or disable Preset Value if they are not already 20484d55c5a1SArindam Nath * enabled or disabled respectively. Otherwise, we bail out. 20494d55c5a1SArindam Nath */ 2050da91a8f9SRussell King if (host->preset_enabled != enable) { 2051da91a8f9SRussell King u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2052da91a8f9SRussell King 2053da91a8f9SRussell King if (enable) 20544d55c5a1SArindam Nath ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2055da91a8f9SRussell King else 20564d55c5a1SArindam Nath ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2057da91a8f9SRussell King 20584d55c5a1SArindam Nath sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2059da91a8f9SRussell King 2060da91a8f9SRussell King if (enable) 2061da91a8f9SRussell King host->flags |= SDHCI_PV_ENABLED; 2062da91a8f9SRussell King else 206366fd8ad5SAdrian Hunter host->flags &= ~SDHCI_PV_ENABLED; 2064da91a8f9SRussell King 2065da91a8f9SRussell King host->preset_enabled = enable; 20664d55c5a1SArindam Nath } 206766fd8ad5SAdrian Hunter } 206866fd8ad5SAdrian Hunter 206971e69211SGuennadi Liakhovetski static void sdhci_card_event(struct mmc_host *mmc) 20701c6a0718SPierre Ossman { 207171e69211SGuennadi Liakhovetski struct sdhci_host *host = mmc_priv(mmc); 20721c6a0718SPierre Ossman unsigned long flags; 20731c6a0718SPierre Ossman 2074722e1280SChristian Daudt /* First check if client has provided their own card event */ 2075722e1280SChristian Daudt if (host->ops->card_event) 2076722e1280SChristian Daudt host->ops->card_event(host); 2077722e1280SChristian Daudt 20781c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 20791c6a0718SPierre Ossman 208066fd8ad5SAdrian Hunter /* Check host->mrq first in case we are runtime suspended */ 20819668d765SShawn Guo if (host->mrq && !sdhci_do_get_cd(host)) { 2082a3c76eb9SGirish K S pr_err("%s: Card removed during transfer!\n", 20831c6a0718SPierre Ossman mmc_hostname(host->mmc)); 2084a3c76eb9SGirish K S pr_err("%s: Resetting controller.\n", 20851c6a0718SPierre Ossman mmc_hostname(host->mmc)); 20861c6a0718SPierre Ossman 208703231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 208803231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 20891c6a0718SPierre Ossman 209017b0429dSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 20911c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 20921c6a0718SPierre Ossman } 20931c6a0718SPierre Ossman 20941c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 209571e69211SGuennadi Liakhovetski } 209671e69211SGuennadi Liakhovetski 209771e69211SGuennadi Liakhovetski static const struct mmc_host_ops sdhci_ops = { 209871e69211SGuennadi Liakhovetski .request = sdhci_request, 209971e69211SGuennadi Liakhovetski .set_ios = sdhci_set_ios, 210094144a46SKevin Liu .get_cd = sdhci_get_cd, 210171e69211SGuennadi Liakhovetski .get_ro = sdhci_get_ro, 210271e69211SGuennadi Liakhovetski .hw_reset = sdhci_hw_reset, 210371e69211SGuennadi Liakhovetski .enable_sdio_irq = sdhci_enable_sdio_irq, 210471e69211SGuennadi Liakhovetski .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 210571e69211SGuennadi Liakhovetski .execute_tuning = sdhci_execute_tuning, 210671e69211SGuennadi Liakhovetski .card_event = sdhci_card_event, 210720b92a30SKevin Liu .card_busy = sdhci_card_busy, 210871e69211SGuennadi Liakhovetski }; 210971e69211SGuennadi Liakhovetski 211071e69211SGuennadi Liakhovetski /*****************************************************************************\ 211171e69211SGuennadi Liakhovetski * * 211271e69211SGuennadi Liakhovetski * Tasklets * 211371e69211SGuennadi Liakhovetski * * 211471e69211SGuennadi Liakhovetski \*****************************************************************************/ 211571e69211SGuennadi Liakhovetski 21161c6a0718SPierre Ossman static void sdhci_tasklet_finish(unsigned long param) 21171c6a0718SPierre Ossman { 21181c6a0718SPierre Ossman struct sdhci_host *host; 21191c6a0718SPierre Ossman unsigned long flags; 21201c6a0718SPierre Ossman struct mmc_request *mrq; 21211c6a0718SPierre Ossman 21221c6a0718SPierre Ossman host = (struct sdhci_host*)param; 21231c6a0718SPierre Ossman 212466fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 212566fd8ad5SAdrian Hunter 21260c9c99a7SChris Ball /* 21270c9c99a7SChris Ball * If this tasklet gets rescheduled while running, it will 21280c9c99a7SChris Ball * be run again afterwards but without any active request. 21290c9c99a7SChris Ball */ 213066fd8ad5SAdrian Hunter if (!host->mrq) { 213166fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 21320c9c99a7SChris Ball return; 213366fd8ad5SAdrian Hunter } 21341c6a0718SPierre Ossman 21351c6a0718SPierre Ossman del_timer(&host->timer); 21361c6a0718SPierre Ossman 21371c6a0718SPierre Ossman mrq = host->mrq; 21381c6a0718SPierre Ossman 21391c6a0718SPierre Ossman /* 21401c6a0718SPierre Ossman * The controller needs a reset of internal state machines 21411c6a0718SPierre Ossman * upon error conditions. 21421c6a0718SPierre Ossman */ 21431e72859eSPierre Ossman if (!(host->flags & SDHCI_DEVICE_DEAD) && 2144b7b4d342SBen Dooks ((mrq->cmd && mrq->cmd->error) || 214517b0429dSPierre Ossman (mrq->data && (mrq->data->error || 214684c46a53SPierre Ossman (mrq->data->stop && mrq->data->stop->error))) || 21471e72859eSPierre Ossman (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 21481c6a0718SPierre Ossman 21491c6a0718SPierre Ossman /* Some controllers need this kick or reset won't work here */ 21508213af3bSAndy Shevchenko if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 21511c6a0718SPierre Ossman /* This is to force an update */ 21521771059cSRussell King host->ops->set_clock(host, host->clock); 21531c6a0718SPierre Ossman 21541c6a0718SPierre Ossman /* Spec says we should do both at the same time, but Ricoh 21551c6a0718SPierre Ossman controllers do not like that. */ 215603231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_CMD); 215703231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_DATA); 21581c6a0718SPierre Ossman } 21591c6a0718SPierre Ossman 21601c6a0718SPierre Ossman host->mrq = NULL; 21611c6a0718SPierre Ossman host->cmd = NULL; 21621c6a0718SPierre Ossman host->data = NULL; 21631c6a0718SPierre Ossman 2164f9134319SPierre Ossman #ifndef SDHCI_USE_LEDS_CLASS 21651c6a0718SPierre Ossman sdhci_deactivate_led(host); 21662f730fecSPierre Ossman #endif 21671c6a0718SPierre Ossman 21681c6a0718SPierre Ossman mmiowb(); 21691c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 21701c6a0718SPierre Ossman 21711c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 217266fd8ad5SAdrian Hunter sdhci_runtime_pm_put(host); 21731c6a0718SPierre Ossman } 21741c6a0718SPierre Ossman 21751c6a0718SPierre Ossman static void sdhci_timeout_timer(unsigned long data) 21761c6a0718SPierre Ossman { 21771c6a0718SPierre Ossman struct sdhci_host *host; 21781c6a0718SPierre Ossman unsigned long flags; 21791c6a0718SPierre Ossman 21801c6a0718SPierre Ossman host = (struct sdhci_host*)data; 21811c6a0718SPierre Ossman 21821c6a0718SPierre Ossman spin_lock_irqsave(&host->lock, flags); 21831c6a0718SPierre Ossman 21841c6a0718SPierre Ossman if (host->mrq) { 2185a3c76eb9SGirish K S pr_err("%s: Timeout waiting for hardware " 21861c6a0718SPierre Ossman "interrupt.\n", mmc_hostname(host->mmc)); 21871c6a0718SPierre Ossman sdhci_dumpregs(host); 21881c6a0718SPierre Ossman 21891c6a0718SPierre Ossman if (host->data) { 219017b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 21911c6a0718SPierre Ossman sdhci_finish_data(host); 21921c6a0718SPierre Ossman } else { 21931c6a0718SPierre Ossman if (host->cmd) 219417b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 21951c6a0718SPierre Ossman else 219617b0429dSPierre Ossman host->mrq->cmd->error = -ETIMEDOUT; 21971c6a0718SPierre Ossman 21981c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 21991c6a0718SPierre Ossman } 22001c6a0718SPierre Ossman } 22011c6a0718SPierre Ossman 22021c6a0718SPierre Ossman mmiowb(); 22031c6a0718SPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 22041c6a0718SPierre Ossman } 22051c6a0718SPierre Ossman 2206cf2b5eeaSArindam Nath static void sdhci_tuning_timer(unsigned long data) 2207cf2b5eeaSArindam Nath { 2208cf2b5eeaSArindam Nath struct sdhci_host *host; 2209cf2b5eeaSArindam Nath unsigned long flags; 2210cf2b5eeaSArindam Nath 2211cf2b5eeaSArindam Nath host = (struct sdhci_host *)data; 2212cf2b5eeaSArindam Nath 2213cf2b5eeaSArindam Nath spin_lock_irqsave(&host->lock, flags); 2214cf2b5eeaSArindam Nath 2215cf2b5eeaSArindam Nath host->flags |= SDHCI_NEEDS_RETUNING; 2216cf2b5eeaSArindam Nath 2217cf2b5eeaSArindam Nath spin_unlock_irqrestore(&host->lock, flags); 2218cf2b5eeaSArindam Nath } 2219cf2b5eeaSArindam Nath 22201c6a0718SPierre Ossman /*****************************************************************************\ 22211c6a0718SPierre Ossman * * 22221c6a0718SPierre Ossman * Interrupt handling * 22231c6a0718SPierre Ossman * * 22241c6a0718SPierre Ossman \*****************************************************************************/ 22251c6a0718SPierre Ossman 22261c6a0718SPierre Ossman static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 22271c6a0718SPierre Ossman { 22281c6a0718SPierre Ossman BUG_ON(intmask == 0); 22291c6a0718SPierre Ossman 22301c6a0718SPierre Ossman if (!host->cmd) { 2231a3c76eb9SGirish K S pr_err("%s: Got command interrupt 0x%08x even " 2232b67ac3f3SPierre Ossman "though no command operation was in progress.\n", 2233b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 22341c6a0718SPierre Ossman sdhci_dumpregs(host); 22351c6a0718SPierre Ossman return; 22361c6a0718SPierre Ossman } 22371c6a0718SPierre Ossman 22381c6a0718SPierre Ossman if (intmask & SDHCI_INT_TIMEOUT) 223917b0429dSPierre Ossman host->cmd->error = -ETIMEDOUT; 224017b0429dSPierre Ossman else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 224117b0429dSPierre Ossman SDHCI_INT_INDEX)) 224217b0429dSPierre Ossman host->cmd->error = -EILSEQ; 22431c6a0718SPierre Ossman 2244e809517fSPierre Ossman if (host->cmd->error) { 22451c6a0718SPierre Ossman tasklet_schedule(&host->finish_tasklet); 2246e809517fSPierre Ossman return; 2247e809517fSPierre Ossman } 2248e809517fSPierre Ossman 2249e809517fSPierre Ossman /* 2250e809517fSPierre Ossman * The host can send and interrupt when the busy state has 2251e809517fSPierre Ossman * ended, allowing us to wait without wasting CPU cycles. 2252e809517fSPierre Ossman * Unfortunately this is overloaded on the "data complete" 2253e809517fSPierre Ossman * interrupt, so we need to take some care when handling 2254e809517fSPierre Ossman * it. 2255e809517fSPierre Ossman * 2256e809517fSPierre Ossman * Note: The 1.0 specification is a bit ambiguous about this 2257e809517fSPierre Ossman * feature so there might be some problems with older 2258e809517fSPierre Ossman * controllers. 2259e809517fSPierre Ossman */ 2260e809517fSPierre Ossman if (host->cmd->flags & MMC_RSP_BUSY) { 2261e809517fSPierre Ossman if (host->cmd->data) 2262e809517fSPierre Ossman DBG("Cannot wait for busy signal when also " 2263e809517fSPierre Ossman "doing a data transfer"); 2264f945405cSBen Dooks else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2265e809517fSPierre Ossman return; 2266f945405cSBen Dooks 2267f945405cSBen Dooks /* The controller does not support the end-of-busy IRQ, 2268f945405cSBen Dooks * fall through and take the SDHCI_INT_RESPONSE */ 2269e809517fSPierre Ossman } 2270e809517fSPierre Ossman 2271e809517fSPierre Ossman if (intmask & SDHCI_INT_RESPONSE) 227243b58b36SPierre Ossman sdhci_finish_command(host); 22731c6a0718SPierre Ossman } 22741c6a0718SPierre Ossman 22750957c333SGeorge G. Davis #ifdef CONFIG_MMC_DEBUG 22766882a8c0SBen Dooks static void sdhci_show_adma_error(struct sdhci_host *host) 22776882a8c0SBen Dooks { 22786882a8c0SBen Dooks const char *name = mmc_hostname(host->mmc); 22796882a8c0SBen Dooks u8 *desc = host->adma_desc; 22806882a8c0SBen Dooks __le32 *dma; 22816882a8c0SBen Dooks __le16 *len; 22826882a8c0SBen Dooks u8 attr; 22836882a8c0SBen Dooks 22846882a8c0SBen Dooks sdhci_dumpregs(host); 22856882a8c0SBen Dooks 22866882a8c0SBen Dooks while (true) { 22876882a8c0SBen Dooks dma = (__le32 *)(desc + 4); 22886882a8c0SBen Dooks len = (__le16 *)(desc + 2); 22896882a8c0SBen Dooks attr = *desc; 22906882a8c0SBen Dooks 22916882a8c0SBen Dooks DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 22926882a8c0SBen Dooks name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 22936882a8c0SBen Dooks 22946882a8c0SBen Dooks desc += 8; 22956882a8c0SBen Dooks 22966882a8c0SBen Dooks if (attr & 2) 22976882a8c0SBen Dooks break; 22986882a8c0SBen Dooks } 22996882a8c0SBen Dooks } 23006882a8c0SBen Dooks #else 23016882a8c0SBen Dooks static void sdhci_show_adma_error(struct sdhci_host *host) { } 23026882a8c0SBen Dooks #endif 23036882a8c0SBen Dooks 23041c6a0718SPierre Ossman static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 23051c6a0718SPierre Ossman { 2306069c9f14SGirish K S u32 command; 23071c6a0718SPierre Ossman BUG_ON(intmask == 0); 23081c6a0718SPierre Ossman 2309b513ea25SArindam Nath /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2310b513ea25SArindam Nath if (intmask & SDHCI_INT_DATA_AVAIL) { 2311069c9f14SGirish K S command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2312069c9f14SGirish K S if (command == MMC_SEND_TUNING_BLOCK || 2313069c9f14SGirish K S command == MMC_SEND_TUNING_BLOCK_HS200) { 2314b513ea25SArindam Nath host->tuning_done = 1; 2315b513ea25SArindam Nath wake_up(&host->buf_ready_int); 2316b513ea25SArindam Nath return; 2317b513ea25SArindam Nath } 2318b513ea25SArindam Nath } 2319b513ea25SArindam Nath 23201c6a0718SPierre Ossman if (!host->data) { 23211c6a0718SPierre Ossman /* 2322e809517fSPierre Ossman * The "data complete" interrupt is also used to 2323e809517fSPierre Ossman * indicate that a busy state has ended. See comment 2324e809517fSPierre Ossman * above in sdhci_cmd_irq(). 23251c6a0718SPierre Ossman */ 2326e809517fSPierre Ossman if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2327c5abd5e8SMatthieu CASTET if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2328c5abd5e8SMatthieu CASTET host->cmd->error = -ETIMEDOUT; 2329c5abd5e8SMatthieu CASTET tasklet_schedule(&host->finish_tasklet); 2330c5abd5e8SMatthieu CASTET return; 2331c5abd5e8SMatthieu CASTET } 2332e809517fSPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2333e809517fSPierre Ossman sdhci_finish_command(host); 23341c6a0718SPierre Ossman return; 2335e809517fSPierre Ossman } 2336e809517fSPierre Ossman } 23371c6a0718SPierre Ossman 2338a3c76eb9SGirish K S pr_err("%s: Got data interrupt 0x%08x even " 2339b67ac3f3SPierre Ossman "though no data operation was in progress.\n", 2340b67ac3f3SPierre Ossman mmc_hostname(host->mmc), (unsigned)intmask); 23411c6a0718SPierre Ossman sdhci_dumpregs(host); 23421c6a0718SPierre Ossman 23431c6a0718SPierre Ossman return; 23441c6a0718SPierre Ossman } 23451c6a0718SPierre Ossman 23461c6a0718SPierre Ossman if (intmask & SDHCI_INT_DATA_TIMEOUT) 234717b0429dSPierre Ossman host->data->error = -ETIMEDOUT; 234822113efdSAries Lee else if (intmask & SDHCI_INT_DATA_END_BIT) 234922113efdSAries Lee host->data->error = -EILSEQ; 235022113efdSAries Lee else if ((intmask & SDHCI_INT_DATA_CRC) && 235122113efdSAries Lee SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 235222113efdSAries Lee != MMC_BUS_TEST_R) 235317b0429dSPierre Ossman host->data->error = -EILSEQ; 23546882a8c0SBen Dooks else if (intmask & SDHCI_INT_ADMA_ERROR) { 2355a3c76eb9SGirish K S pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 23566882a8c0SBen Dooks sdhci_show_adma_error(host); 23572134a922SPierre Ossman host->data->error = -EIO; 2358a4071fbbSHaijun Zhang if (host->ops->adma_workaround) 2359a4071fbbSHaijun Zhang host->ops->adma_workaround(host, intmask); 23606882a8c0SBen Dooks } 23611c6a0718SPierre Ossman 236217b0429dSPierre Ossman if (host->data->error) 23631c6a0718SPierre Ossman sdhci_finish_data(host); 23641c6a0718SPierre Ossman else { 23651c6a0718SPierre Ossman if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 23661c6a0718SPierre Ossman sdhci_transfer_pio(host); 23671c6a0718SPierre Ossman 23686ba736a1SPierre Ossman /* 23696ba736a1SPierre Ossman * We currently don't do anything fancy with DMA 23706ba736a1SPierre Ossman * boundaries, but as we can't disable the feature 23716ba736a1SPierre Ossman * we need to at least restart the transfer. 2372f6a03cbfSMikko Vinni * 2373f6a03cbfSMikko Vinni * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2374f6a03cbfSMikko Vinni * should return a valid address to continue from, but as 2375f6a03cbfSMikko Vinni * some controllers are faulty, don't trust them. 23766ba736a1SPierre Ossman */ 2377f6a03cbfSMikko Vinni if (intmask & SDHCI_INT_DMA_END) { 2378f6a03cbfSMikko Vinni u32 dmastart, dmanow; 2379f6a03cbfSMikko Vinni dmastart = sg_dma_address(host->data->sg); 2380f6a03cbfSMikko Vinni dmanow = dmastart + host->data->bytes_xfered; 2381f6a03cbfSMikko Vinni /* 2382f6a03cbfSMikko Vinni * Force update to the next DMA block boundary. 2383f6a03cbfSMikko Vinni */ 2384f6a03cbfSMikko Vinni dmanow = (dmanow & 2385f6a03cbfSMikko Vinni ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2386f6a03cbfSMikko Vinni SDHCI_DEFAULT_BOUNDARY_SIZE; 2387f6a03cbfSMikko Vinni host->data->bytes_xfered = dmanow - dmastart; 2388f6a03cbfSMikko Vinni DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2389f6a03cbfSMikko Vinni " next 0x%08x\n", 2390f6a03cbfSMikko Vinni mmc_hostname(host->mmc), dmastart, 2391f6a03cbfSMikko Vinni host->data->bytes_xfered, dmanow); 2392f6a03cbfSMikko Vinni sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2393f6a03cbfSMikko Vinni } 23946ba736a1SPierre Ossman 2395e538fbe8SPierre Ossman if (intmask & SDHCI_INT_DATA_END) { 2396e538fbe8SPierre Ossman if (host->cmd) { 2397e538fbe8SPierre Ossman /* 2398e538fbe8SPierre Ossman * Data managed to finish before the 2399e538fbe8SPierre Ossman * command completed. Make sure we do 2400e538fbe8SPierre Ossman * things in the proper order. 2401e538fbe8SPierre Ossman */ 2402e538fbe8SPierre Ossman host->data_early = 1; 2403e538fbe8SPierre Ossman } else { 24041c6a0718SPierre Ossman sdhci_finish_data(host); 24051c6a0718SPierre Ossman } 24061c6a0718SPierre Ossman } 2407e538fbe8SPierre Ossman } 2408e538fbe8SPierre Ossman } 24091c6a0718SPierre Ossman 24101c6a0718SPierre Ossman static irqreturn_t sdhci_irq(int irq, void *dev_id) 24111c6a0718SPierre Ossman { 2412781e989cSRussell King irqreturn_t result = IRQ_NONE; 24131c6a0718SPierre Ossman struct sdhci_host *host = dev_id; 241441005003SRussell King u32 intmask, mask, unexpected = 0; 2415781e989cSRussell King int max_loops = 16; 24161c6a0718SPierre Ossman 24171c6a0718SPierre Ossman spin_lock(&host->lock); 24181c6a0718SPierre Ossman 2419be138554SRussell King if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 242066fd8ad5SAdrian Hunter spin_unlock(&host->lock); 2421655bca76SAdrian Hunter return IRQ_NONE; 242266fd8ad5SAdrian Hunter } 242366fd8ad5SAdrian Hunter 24244e4141a5SAnton Vorontsov intmask = sdhci_readl(host, SDHCI_INT_STATUS); 24251c6a0718SPierre Ossman if (!intmask || intmask == 0xffffffff) { 24261c6a0718SPierre Ossman result = IRQ_NONE; 24271c6a0718SPierre Ossman goto out; 24281c6a0718SPierre Ossman } 24291c6a0718SPierre Ossman 243041005003SRussell King do { 243141005003SRussell King /* Clear selected interrupts. */ 243241005003SRussell King mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 243341005003SRussell King SDHCI_INT_BUS_POWER); 243441005003SRussell King sdhci_writel(host, mask, SDHCI_INT_STATUS); 243541005003SRussell King 2436b69c9058SPierre Ossman DBG("*** %s got interrupt: 0x%08x\n", 2437b69c9058SPierre Ossman mmc_hostname(host->mmc), intmask); 24381c6a0718SPierre Ossman 24391c6a0718SPierre Ossman if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2440d25928d1SShawn Guo u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2441d25928d1SShawn Guo SDHCI_CARD_PRESENT; 2442d25928d1SShawn Guo 2443d25928d1SShawn Guo /* 244441005003SRussell King * There is a observation on i.mx esdhc. INSERT 244541005003SRussell King * bit will be immediately set again when it gets 244641005003SRussell King * cleared, if a card is inserted. We have to mask 244741005003SRussell King * the irq to prevent interrupt storm which will 244841005003SRussell King * freeze the system. And the REMOVE gets the 244941005003SRussell King * same situation. 2450d25928d1SShawn Guo * 245141005003SRussell King * More testing are needed here to ensure it works 245241005003SRussell King * for other platforms though. 2453d25928d1SShawn Guo */ 2454b537f94cSRussell King host->ier &= ~(SDHCI_INT_CARD_INSERT | 2455d25928d1SShawn Guo SDHCI_INT_CARD_REMOVE); 2456b537f94cSRussell King host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2457b537f94cSRussell King SDHCI_INT_CARD_INSERT; 2458b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2459b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2460d25928d1SShawn Guo 24614e4141a5SAnton Vorontsov sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 24624e4141a5SAnton Vorontsov SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 24633560db8eSRussell King 24643560db8eSRussell King host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 24653560db8eSRussell King SDHCI_INT_CARD_REMOVE); 24663560db8eSRussell King result = IRQ_WAKE_THREAD; 24671c6a0718SPierre Ossman } 24681c6a0718SPierre Ossman 246941005003SRussell King if (intmask & SDHCI_INT_CMD_MASK) 24701c6a0718SPierre Ossman sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 24711c6a0718SPierre Ossman 247241005003SRussell King if (intmask & SDHCI_INT_DATA_MASK) 24731c6a0718SPierre Ossman sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 24741c6a0718SPierre Ossman 247541005003SRussell King if (intmask & SDHCI_INT_BUS_POWER) 2476a3c76eb9SGirish K S pr_err("%s: Card is consuming too much power!\n", 24771c6a0718SPierre Ossman mmc_hostname(host->mmc)); 24781c6a0718SPierre Ossman 2479781e989cSRussell King if (intmask & SDHCI_INT_CARD_INT) { 2480781e989cSRussell King sdhci_enable_sdio_irq_nolock(host, false); 2481781e989cSRussell King host->thread_isr |= SDHCI_INT_CARD_INT; 2482781e989cSRussell King result = IRQ_WAKE_THREAD; 2483781e989cSRussell King } 2484f75979b7SPierre Ossman 248541005003SRussell King intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 248641005003SRussell King SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 248741005003SRussell King SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 248841005003SRussell King SDHCI_INT_CARD_INT); 2489f75979b7SPierre Ossman 24901c6a0718SPierre Ossman if (intmask) { 24916379b237SAlexander Stein unexpected |= intmask; 24924e4141a5SAnton Vorontsov sdhci_writel(host, intmask, SDHCI_INT_STATUS); 24931c6a0718SPierre Ossman } 24941c6a0718SPierre Ossman 2495781e989cSRussell King if (result == IRQ_NONE) 24961c6a0718SPierre Ossman result = IRQ_HANDLED; 24971c6a0718SPierre Ossman 24986379b237SAlexander Stein intmask = sdhci_readl(host, SDHCI_INT_STATUS); 249941005003SRussell King } while (intmask && --max_loops); 25001c6a0718SPierre Ossman out: 25011c6a0718SPierre Ossman spin_unlock(&host->lock); 25021c6a0718SPierre Ossman 25036379b237SAlexander Stein if (unexpected) { 25046379b237SAlexander Stein pr_err("%s: Unexpected interrupt 0x%08x.\n", 25056379b237SAlexander Stein mmc_hostname(host->mmc), unexpected); 25066379b237SAlexander Stein sdhci_dumpregs(host); 25076379b237SAlexander Stein } 2508f75979b7SPierre Ossman 25091c6a0718SPierre Ossman return result; 25101c6a0718SPierre Ossman } 25111c6a0718SPierre Ossman 2512781e989cSRussell King static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2513781e989cSRussell King { 2514781e989cSRussell King struct sdhci_host *host = dev_id; 2515781e989cSRussell King unsigned long flags; 2516781e989cSRussell King u32 isr; 2517781e989cSRussell King 2518781e989cSRussell King spin_lock_irqsave(&host->lock, flags); 2519781e989cSRussell King isr = host->thread_isr; 2520781e989cSRussell King host->thread_isr = 0; 2521781e989cSRussell King spin_unlock_irqrestore(&host->lock, flags); 2522781e989cSRussell King 25233560db8eSRussell King if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 25243560db8eSRussell King sdhci_card_event(host->mmc); 25253560db8eSRussell King mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 25263560db8eSRussell King } 25273560db8eSRussell King 2528781e989cSRussell King if (isr & SDHCI_INT_CARD_INT) { 2529781e989cSRussell King sdio_run_irqs(host->mmc); 2530781e989cSRussell King 2531781e989cSRussell King spin_lock_irqsave(&host->lock, flags); 2532781e989cSRussell King if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2533781e989cSRussell King sdhci_enable_sdio_irq_nolock(host, true); 2534781e989cSRussell King spin_unlock_irqrestore(&host->lock, flags); 2535781e989cSRussell King } 2536781e989cSRussell King 2537781e989cSRussell King return isr ? IRQ_HANDLED : IRQ_NONE; 2538781e989cSRussell King } 2539781e989cSRussell King 25401c6a0718SPierre Ossman /*****************************************************************************\ 25411c6a0718SPierre Ossman * * 25421c6a0718SPierre Ossman * Suspend/resume * 25431c6a0718SPierre Ossman * * 25441c6a0718SPierre Ossman \*****************************************************************************/ 25451c6a0718SPierre Ossman 25461c6a0718SPierre Ossman #ifdef CONFIG_PM 2547ad080d79SKevin Liu void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2548ad080d79SKevin Liu { 2549ad080d79SKevin Liu u8 val; 2550ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2551ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2552ad080d79SKevin Liu 2553ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2554ad080d79SKevin Liu val |= mask ; 2555ad080d79SKevin Liu /* Avoid fake wake up */ 2556ad080d79SKevin Liu if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2557ad080d79SKevin Liu val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2558ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2559ad080d79SKevin Liu } 2560ad080d79SKevin Liu EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2561ad080d79SKevin Liu 25620b10f478SFabio Estevam static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2563ad080d79SKevin Liu { 2564ad080d79SKevin Liu u8 val; 2565ad080d79SKevin Liu u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2566ad080d79SKevin Liu | SDHCI_WAKE_ON_INT; 2567ad080d79SKevin Liu 2568ad080d79SKevin Liu val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2569ad080d79SKevin Liu val &= ~mask; 2570ad080d79SKevin Liu sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2571ad080d79SKevin Liu } 25721c6a0718SPierre Ossman 257329495aa0SManuel Lauss int sdhci_suspend_host(struct sdhci_host *host) 25741c6a0718SPierre Ossman { 25757260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 25767260cf5eSAnton Vorontsov 2577cf2b5eeaSArindam Nath /* Disable tuning since we are suspending */ 2578973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2579c6ced0dbSAaron Lu del_timer_sync(&host->tuning_timer); 2580cf2b5eeaSArindam Nath host->flags &= ~SDHCI_NEEDS_RETUNING; 2581cf2b5eeaSArindam Nath } 2582cf2b5eeaSArindam Nath 2583ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2584b537f94cSRussell King host->ier = 0; 2585b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2586b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2587b8c86fc5SPierre Ossman free_irq(host->irq, host); 2588ad080d79SKevin Liu } else { 2589ad080d79SKevin Liu sdhci_enable_irq_wakeups(host); 2590ad080d79SKevin Liu enable_irq_wake(host->irq); 2591ad080d79SKevin Liu } 25924ee14ec6SUlf Hansson return 0; 2593b8c86fc5SPierre Ossman } 2594b8c86fc5SPierre Ossman 2595b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2596b8c86fc5SPierre Ossman 2597b8c86fc5SPierre Ossman int sdhci_resume_host(struct sdhci_host *host) 2598b8c86fc5SPierre Ossman { 25994ee14ec6SUlf Hansson int ret = 0; 2600b8c86fc5SPierre Ossman 2601a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2602b8c86fc5SPierre Ossman if (host->ops->enable_dma) 2603b8c86fc5SPierre Ossman host->ops->enable_dma(host); 2604b8c86fc5SPierre Ossman } 2605b8c86fc5SPierre Ossman 2606ad080d79SKevin Liu if (!device_may_wakeup(mmc_dev(host->mmc))) { 2607781e989cSRussell King ret = request_threaded_irq(host->irq, sdhci_irq, 2608781e989cSRussell King sdhci_thread_irq, IRQF_SHARED, 2609b8c86fc5SPierre Ossman mmc_hostname(host->mmc), host); 26101c6a0718SPierre Ossman if (ret) 26111c6a0718SPierre Ossman return ret; 2612ad080d79SKevin Liu } else { 2613ad080d79SKevin Liu sdhci_disable_irq_wakeups(host); 2614ad080d79SKevin Liu disable_irq_wake(host->irq); 2615ad080d79SKevin Liu } 2616b8c86fc5SPierre Ossman 26176308d290SAdrian Hunter if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 26186308d290SAdrian Hunter (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 26196308d290SAdrian Hunter /* Card keeps power but host controller does not */ 26206308d290SAdrian Hunter sdhci_init(host, 0); 26216308d290SAdrian Hunter host->pwr = 0; 26226308d290SAdrian Hunter host->clock = 0; 26236308d290SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 26246308d290SAdrian Hunter } else { 26252f4cbb3dSNicolas Pitre sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 26261c6a0718SPierre Ossman mmiowb(); 26276308d290SAdrian Hunter } 2628b8c86fc5SPierre Ossman 26297260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 26307260cf5eSAnton Vorontsov 2631cf2b5eeaSArindam Nath /* Set the re-tuning expiration flag */ 2632973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) 2633cf2b5eeaSArindam Nath host->flags |= SDHCI_NEEDS_RETUNING; 2634cf2b5eeaSArindam Nath 26352f4cbb3dSNicolas Pitre return ret; 26361c6a0718SPierre Ossman } 26371c6a0718SPierre Ossman 2638b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_resume_host); 26391c6a0718SPierre Ossman #endif /* CONFIG_PM */ 26401c6a0718SPierre Ossman 264166fd8ad5SAdrian Hunter #ifdef CONFIG_PM_RUNTIME 264266fd8ad5SAdrian Hunter 264366fd8ad5SAdrian Hunter static int sdhci_runtime_pm_get(struct sdhci_host *host) 264466fd8ad5SAdrian Hunter { 264566fd8ad5SAdrian Hunter return pm_runtime_get_sync(host->mmc->parent); 264666fd8ad5SAdrian Hunter } 264766fd8ad5SAdrian Hunter 264866fd8ad5SAdrian Hunter static int sdhci_runtime_pm_put(struct sdhci_host *host) 264966fd8ad5SAdrian Hunter { 265066fd8ad5SAdrian Hunter pm_runtime_mark_last_busy(host->mmc->parent); 265166fd8ad5SAdrian Hunter return pm_runtime_put_autosuspend(host->mmc->parent); 265266fd8ad5SAdrian Hunter } 265366fd8ad5SAdrian Hunter 2654f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2655f0710a55SAdrian Hunter { 2656f0710a55SAdrian Hunter if (host->runtime_suspended || host->bus_on) 2657f0710a55SAdrian Hunter return; 2658f0710a55SAdrian Hunter host->bus_on = true; 2659f0710a55SAdrian Hunter pm_runtime_get_noresume(host->mmc->parent); 2660f0710a55SAdrian Hunter } 2661f0710a55SAdrian Hunter 2662f0710a55SAdrian Hunter static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2663f0710a55SAdrian Hunter { 2664f0710a55SAdrian Hunter if (host->runtime_suspended || !host->bus_on) 2665f0710a55SAdrian Hunter return; 2666f0710a55SAdrian Hunter host->bus_on = false; 2667f0710a55SAdrian Hunter pm_runtime_put_noidle(host->mmc->parent); 2668f0710a55SAdrian Hunter } 2669f0710a55SAdrian Hunter 267066fd8ad5SAdrian Hunter int sdhci_runtime_suspend_host(struct sdhci_host *host) 267166fd8ad5SAdrian Hunter { 267266fd8ad5SAdrian Hunter unsigned long flags; 267366fd8ad5SAdrian Hunter 267466fd8ad5SAdrian Hunter /* Disable tuning since we are suspending */ 2675973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) { 267666fd8ad5SAdrian Hunter del_timer_sync(&host->tuning_timer); 267766fd8ad5SAdrian Hunter host->flags &= ~SDHCI_NEEDS_RETUNING; 267866fd8ad5SAdrian Hunter } 267966fd8ad5SAdrian Hunter 268066fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 2681b537f94cSRussell King host->ier &= SDHCI_INT_CARD_INT; 2682b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2683b537f94cSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 268466fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 268566fd8ad5SAdrian Hunter 2686781e989cSRussell King synchronize_hardirq(host->irq); 268766fd8ad5SAdrian Hunter 268866fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 268966fd8ad5SAdrian Hunter host->runtime_suspended = true; 269066fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 269166fd8ad5SAdrian Hunter 26928a125badSMarkus Pargmann return 0; 269366fd8ad5SAdrian Hunter } 269466fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 269566fd8ad5SAdrian Hunter 269666fd8ad5SAdrian Hunter int sdhci_runtime_resume_host(struct sdhci_host *host) 269766fd8ad5SAdrian Hunter { 269866fd8ad5SAdrian Hunter unsigned long flags; 26998a125badSMarkus Pargmann int host_flags = host->flags; 270066fd8ad5SAdrian Hunter 270166fd8ad5SAdrian Hunter if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 270266fd8ad5SAdrian Hunter if (host->ops->enable_dma) 270366fd8ad5SAdrian Hunter host->ops->enable_dma(host); 270466fd8ad5SAdrian Hunter } 270566fd8ad5SAdrian Hunter 270666fd8ad5SAdrian Hunter sdhci_init(host, 0); 270766fd8ad5SAdrian Hunter 270866fd8ad5SAdrian Hunter /* Force clock and power re-program */ 270966fd8ad5SAdrian Hunter host->pwr = 0; 271066fd8ad5SAdrian Hunter host->clock = 0; 271166fd8ad5SAdrian Hunter sdhci_do_set_ios(host, &host->mmc->ios); 271266fd8ad5SAdrian Hunter 271366fd8ad5SAdrian Hunter sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 271452983382SKevin Liu if ((host_flags & SDHCI_PV_ENABLED) && 271552983382SKevin Liu !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 271652983382SKevin Liu spin_lock_irqsave(&host->lock, flags); 271752983382SKevin Liu sdhci_enable_preset_value(host, true); 271852983382SKevin Liu spin_unlock_irqrestore(&host->lock, flags); 271952983382SKevin Liu } 272066fd8ad5SAdrian Hunter 272166fd8ad5SAdrian Hunter /* Set the re-tuning expiration flag */ 2722973905feSAaron Lu if (host->flags & SDHCI_USING_RETUNING_TIMER) 272366fd8ad5SAdrian Hunter host->flags |= SDHCI_NEEDS_RETUNING; 272466fd8ad5SAdrian Hunter 272566fd8ad5SAdrian Hunter spin_lock_irqsave(&host->lock, flags); 272666fd8ad5SAdrian Hunter 272766fd8ad5SAdrian Hunter host->runtime_suspended = false; 272866fd8ad5SAdrian Hunter 272966fd8ad5SAdrian Hunter /* Enable SDIO IRQ */ 2730ef104333SRussell King if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 273166fd8ad5SAdrian Hunter sdhci_enable_sdio_irq_nolock(host, true); 273266fd8ad5SAdrian Hunter 273366fd8ad5SAdrian Hunter /* Enable Card Detection */ 273466fd8ad5SAdrian Hunter sdhci_enable_card_detection(host); 273566fd8ad5SAdrian Hunter 273666fd8ad5SAdrian Hunter spin_unlock_irqrestore(&host->lock, flags); 273766fd8ad5SAdrian Hunter 27388a125badSMarkus Pargmann return 0; 273966fd8ad5SAdrian Hunter } 274066fd8ad5SAdrian Hunter EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 274166fd8ad5SAdrian Hunter 274266fd8ad5SAdrian Hunter #endif 274366fd8ad5SAdrian Hunter 27441c6a0718SPierre Ossman /*****************************************************************************\ 27451c6a0718SPierre Ossman * * 2746b8c86fc5SPierre Ossman * Device allocation/registration * 27471c6a0718SPierre Ossman * * 27481c6a0718SPierre Ossman \*****************************************************************************/ 27491c6a0718SPierre Ossman 2750b8c86fc5SPierre Ossman struct sdhci_host *sdhci_alloc_host(struct device *dev, 2751b8c86fc5SPierre Ossman size_t priv_size) 27521c6a0718SPierre Ossman { 27531c6a0718SPierre Ossman struct mmc_host *mmc; 27541c6a0718SPierre Ossman struct sdhci_host *host; 27551c6a0718SPierre Ossman 2756b8c86fc5SPierre Ossman WARN_ON(dev == NULL); 27571c6a0718SPierre Ossman 2758b8c86fc5SPierre Ossman mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 27591c6a0718SPierre Ossman if (!mmc) 2760b8c86fc5SPierre Ossman return ERR_PTR(-ENOMEM); 27611c6a0718SPierre Ossman 27621c6a0718SPierre Ossman host = mmc_priv(mmc); 27631c6a0718SPierre Ossman host->mmc = mmc; 27641c6a0718SPierre Ossman 2765b8c86fc5SPierre Ossman return host; 27661c6a0718SPierre Ossman } 27671c6a0718SPierre Ossman 2768b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2769b8c86fc5SPierre Ossman 2770b8c86fc5SPierre Ossman int sdhci_add_host(struct sdhci_host *host) 2771b8c86fc5SPierre Ossman { 2772b8c86fc5SPierre Ossman struct mmc_host *mmc; 2773bd6a8c30SPhilip Rakity u32 caps[2] = {0, 0}; 2774f2119df6SArindam Nath u32 max_current_caps; 2775f2119df6SArindam Nath unsigned int ocr_avail; 2776b8c86fc5SPierre Ossman int ret; 2777b8c86fc5SPierre Ossman 2778b8c86fc5SPierre Ossman WARN_ON(host == NULL); 2779b8c86fc5SPierre Ossman if (host == NULL) 2780b8c86fc5SPierre Ossman return -EINVAL; 2781b8c86fc5SPierre Ossman 2782b8c86fc5SPierre Ossman mmc = host->mmc; 2783b8c86fc5SPierre Ossman 2784b8c86fc5SPierre Ossman if (debug_quirks) 2785b8c86fc5SPierre Ossman host->quirks = debug_quirks; 278666fd8ad5SAdrian Hunter if (debug_quirks2) 278766fd8ad5SAdrian Hunter host->quirks2 = debug_quirks2; 2788b8c86fc5SPierre Ossman 278903231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 27901c6a0718SPierre Ossman 27914e4141a5SAnton Vorontsov host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 27922134a922SPierre Ossman host->version = (host->version & SDHCI_SPEC_VER_MASK) 27932134a922SPierre Ossman >> SDHCI_SPEC_VER_SHIFT; 279485105c53SZhangfei Gao if (host->version > SDHCI_SPEC_300) { 2795a3c76eb9SGirish K S pr_err("%s: Unknown controller version (%d). " 2796b69c9058SPierre Ossman "You may experience problems.\n", mmc_hostname(mmc), 27972134a922SPierre Ossman host->version); 27981c6a0718SPierre Ossman } 27991c6a0718SPierre Ossman 2800f2119df6SArindam Nath caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2801ccc92c23SMaxim Levitsky sdhci_readl(host, SDHCI_CAPABILITIES); 28021c6a0718SPierre Ossman 2803bd6a8c30SPhilip Rakity if (host->version >= SDHCI_SPEC_300) 2804bd6a8c30SPhilip Rakity caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2805bd6a8c30SPhilip Rakity host->caps1 : 2806bd6a8c30SPhilip Rakity sdhci_readl(host, SDHCI_CAPABILITIES_1); 2807f2119df6SArindam Nath 2808b8c86fc5SPierre Ossman if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2809a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 2810f2119df6SArindam Nath else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2811a13abc7bSRichard Röjfors DBG("Controller doesn't have SDMA capability\n"); 28121c6a0718SPierre Ossman else 2813a13abc7bSRichard Röjfors host->flags |= SDHCI_USE_SDMA; 28141c6a0718SPierre Ossman 2815b8c86fc5SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2816a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA)) { 2817cee687ceSRolf Eike Beer DBG("Disabling DMA as it is marked broken\n"); 2818a13abc7bSRichard Röjfors host->flags &= ~SDHCI_USE_SDMA; 28197c168e3dSFeng Tang } 28207c168e3dSFeng Tang 2821f2119df6SArindam Nath if ((host->version >= SDHCI_SPEC_200) && 2822f2119df6SArindam Nath (caps[0] & SDHCI_CAN_DO_ADMA2)) 28232134a922SPierre Ossman host->flags |= SDHCI_USE_ADMA; 28242134a922SPierre Ossman 28252134a922SPierre Ossman if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 28262134a922SPierre Ossman (host->flags & SDHCI_USE_ADMA)) { 28272134a922SPierre Ossman DBG("Disabling ADMA as it is marked broken\n"); 28282134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 28292134a922SPierre Ossman } 28302134a922SPierre Ossman 2831a13abc7bSRichard Röjfors if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2832b8c86fc5SPierre Ossman if (host->ops->enable_dma) { 2833b8c86fc5SPierre Ossman if (host->ops->enable_dma(host)) { 2834a3c76eb9SGirish K S pr_warning("%s: No suitable DMA " 2835b8c86fc5SPierre Ossman "available. Falling back to PIO.\n", 2836b8c86fc5SPierre Ossman mmc_hostname(mmc)); 2837a13abc7bSRichard Röjfors host->flags &= 2838a13abc7bSRichard Röjfors ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 28391c6a0718SPierre Ossman } 28401c6a0718SPierre Ossman } 2841b8c86fc5SPierre Ossman } 28421c6a0718SPierre Ossman 28432134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) { 28442134a922SPierre Ossman /* 28452134a922SPierre Ossman * We need to allocate descriptors for all sg entries 28462134a922SPierre Ossman * (128) and potentially one alignment transfer for 28472134a922SPierre Ossman * each of those entries. 28482134a922SPierre Ossman */ 28494e743f1fSMarkus Mayer host->adma_desc = dma_alloc_coherent(mmc_dev(mmc), 2850d1e49f77SRussell King ADMA_SIZE, &host->adma_addr, 2851d1e49f77SRussell King GFP_KERNEL); 28522134a922SPierre Ossman host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 28532134a922SPierre Ossman if (!host->adma_desc || !host->align_buffer) { 28544e743f1fSMarkus Mayer dma_free_coherent(mmc_dev(mmc), ADMA_SIZE, 2855d1e49f77SRussell King host->adma_desc, host->adma_addr); 28562134a922SPierre Ossman kfree(host->align_buffer); 2857a3c76eb9SGirish K S pr_warning("%s: Unable to allocate ADMA " 28582134a922SPierre Ossman "buffers. Falling back to standard DMA.\n", 28592134a922SPierre Ossman mmc_hostname(mmc)); 28602134a922SPierre Ossman host->flags &= ~SDHCI_USE_ADMA; 2861d1e49f77SRussell King host->adma_desc = NULL; 2862d1e49f77SRussell King host->align_buffer = NULL; 2863d1e49f77SRussell King } else if (host->adma_addr & 3) { 2864d1e49f77SRussell King pr_warning("%s: unable to allocate aligned ADMA descriptor\n", 2865d1e49f77SRussell King mmc_hostname(mmc)); 2866d1e49f77SRussell King host->flags &= ~SDHCI_USE_ADMA; 28674e743f1fSMarkus Mayer dma_free_coherent(mmc_dev(mmc), ADMA_SIZE, 2868d1e49f77SRussell King host->adma_desc, host->adma_addr); 2869d1e49f77SRussell King kfree(host->align_buffer); 2870d1e49f77SRussell King host->adma_desc = NULL; 2871d1e49f77SRussell King host->align_buffer = NULL; 28722134a922SPierre Ossman } 28732134a922SPierre Ossman } 28742134a922SPierre Ossman 28757659150cSPierre Ossman /* 28767659150cSPierre Ossman * If we use DMA, then it's up to the caller to set the DMA 28777659150cSPierre Ossman * mask, but PIO does not need the hw shim so we set a new 28787659150cSPierre Ossman * mask here in that case. 28797659150cSPierre Ossman */ 2880a13abc7bSRichard Röjfors if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 28817659150cSPierre Ossman host->dma_mask = DMA_BIT_MASK(64); 28824e743f1fSMarkus Mayer mmc_dev(mmc)->dma_mask = &host->dma_mask; 28837659150cSPierre Ossman } 28841c6a0718SPierre Ossman 2885c4687d5fSZhangfei Gao if (host->version >= SDHCI_SPEC_300) 2886f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2887c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2888c4687d5fSZhangfei Gao else 2889f2119df6SArindam Nath host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2890c4687d5fSZhangfei Gao >> SDHCI_CLOCK_BASE_SHIFT; 2891c4687d5fSZhangfei Gao 28924240ff0aSBen Dooks host->max_clk *= 1000000; 2893f27f47efSAnton Vorontsov if (host->max_clk == 0 || host->quirks & 2894f27f47efSAnton Vorontsov SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 28954240ff0aSBen Dooks if (!host->ops->get_max_clock) { 2896a3c76eb9SGirish K S pr_err("%s: Hardware doesn't specify base clock " 2897b69c9058SPierre Ossman "frequency.\n", mmc_hostname(mmc)); 2898b8c86fc5SPierre Ossman return -ENODEV; 28991c6a0718SPierre Ossman } 29004240ff0aSBen Dooks host->max_clk = host->ops->get_max_clock(host); 29014240ff0aSBen Dooks } 29021c6a0718SPierre Ossman 29031c6a0718SPierre Ossman /* 2904c3ed3877SArindam Nath * In case of Host Controller v3.00, find out whether clock 2905c3ed3877SArindam Nath * multiplier is supported. 2906c3ed3877SArindam Nath */ 2907c3ed3877SArindam Nath host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2908c3ed3877SArindam Nath SDHCI_CLOCK_MUL_SHIFT; 2909c3ed3877SArindam Nath 2910c3ed3877SArindam Nath /* 2911c3ed3877SArindam Nath * In case the value in Clock Multiplier is 0, then programmable 2912c3ed3877SArindam Nath * clock mode is not supported, otherwise the actual clock 2913c3ed3877SArindam Nath * multiplier is one more than the value of Clock Multiplier 2914c3ed3877SArindam Nath * in the Capabilities Register. 2915c3ed3877SArindam Nath */ 2916c3ed3877SArindam Nath if (host->clk_mul) 2917c3ed3877SArindam Nath host->clk_mul += 1; 2918c3ed3877SArindam Nath 2919c3ed3877SArindam Nath /* 29201c6a0718SPierre Ossman * Set host parameters. 29211c6a0718SPierre Ossman */ 29221c6a0718SPierre Ossman mmc->ops = &sdhci_ops; 2923c3ed3877SArindam Nath mmc->f_max = host->max_clk; 2924ce5f036bSMarek Szyprowski if (host->ops->get_min_clock) 2925a9e58f25SAnton Vorontsov mmc->f_min = host->ops->get_min_clock(host); 2926c3ed3877SArindam Nath else if (host->version >= SDHCI_SPEC_300) { 2927c3ed3877SArindam Nath if (host->clk_mul) { 2928c3ed3877SArindam Nath mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2929c3ed3877SArindam Nath mmc->f_max = host->max_clk * host->clk_mul; 2930c3ed3877SArindam Nath } else 29310397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2932c3ed3877SArindam Nath } else 29330397526dSZhangfei Gao mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 293415ec4461SPhilip Rakity 293528aab053SAisheng Dong if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 293628aab053SAisheng Dong host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> 293728aab053SAisheng Dong SDHCI_TIMEOUT_CLK_SHIFT; 2938272308caSAndy Shevchenko if (host->timeout_clk == 0) { 2939272308caSAndy Shevchenko if (host->ops->get_timeout_clock) { 294028aab053SAisheng Dong host->timeout_clk = 294128aab053SAisheng Dong host->ops->get_timeout_clock(host); 294228aab053SAisheng Dong } else { 294328aab053SAisheng Dong pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 294428aab053SAisheng Dong mmc_hostname(mmc)); 2945272308caSAndy Shevchenko return -ENODEV; 2946272308caSAndy Shevchenko } 2947272308caSAndy Shevchenko } 294828aab053SAisheng Dong 2949272308caSAndy Shevchenko if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2950272308caSAndy Shevchenko host->timeout_clk *= 1000; 2951272308caSAndy Shevchenko 2952a6ff5aebSAisheng Dong mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 2953a6ff5aebSAisheng Dong host->ops->get_max_timeout_count(host) : 1 << 27; 2954a6ff5aebSAisheng Dong mmc->max_busy_timeout /= host->timeout_clk; 295528aab053SAisheng Dong } 295658d1246dSAdrian Hunter 2957e89d456fSAndrei Warkentin mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2958781e989cSRussell King mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2959e89d456fSAndrei Warkentin 2960e89d456fSAndrei Warkentin if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2961e89d456fSAndrei Warkentin host->flags |= SDHCI_AUTO_CMD12; 29625fe23c7fSAnton Vorontsov 29638edf6371SAndrei Warkentin /* Auto-CMD23 stuff only works in ADMA or PIO. */ 29644f3d3e9bSAndrei Warkentin if ((host->version >= SDHCI_SPEC_300) && 29658edf6371SAndrei Warkentin ((host->flags & SDHCI_USE_ADMA) || 29664f3d3e9bSAndrei Warkentin !(host->flags & SDHCI_USE_SDMA))) { 29678edf6371SAndrei Warkentin host->flags |= SDHCI_AUTO_CMD23; 29688edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 29698edf6371SAndrei Warkentin } else { 29708edf6371SAndrei Warkentin DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 29718edf6371SAndrei Warkentin } 29728edf6371SAndrei Warkentin 297315ec4461SPhilip Rakity /* 297415ec4461SPhilip Rakity * A controller may support 8-bit width, but the board itself 297515ec4461SPhilip Rakity * might not have the pins brought out. Boards that support 297615ec4461SPhilip Rakity * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 297715ec4461SPhilip Rakity * their platform code before calling sdhci_add_host(), and we 297815ec4461SPhilip Rakity * won't assume 8-bit width for hosts without that CAP. 297915ec4461SPhilip Rakity */ 29805fe23c7fSAnton Vorontsov if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 298115ec4461SPhilip Rakity mmc->caps |= MMC_CAP_4_BIT_DATA; 29821c6a0718SPierre Ossman 298363ef5d8cSJerry Huang if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 298463ef5d8cSJerry Huang mmc->caps &= ~MMC_CAP_CMD23; 298563ef5d8cSJerry Huang 2986f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_DO_HISPD) 2987a29e7e18SZhangfei Gao mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 29881c6a0718SPierre Ossman 2989176d1ed4SJaehoon Chung if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 29904e743f1fSMarkus Mayer !(mmc->caps & MMC_CAP_NONREMOVABLE)) 299168d1fb7eSAnton Vorontsov mmc->caps |= MMC_CAP_NEEDS_POLL; 299268d1fb7eSAnton Vorontsov 29933a48edc4STim Kryger /* If there are external regulators, get them */ 29943a48edc4STim Kryger if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) 29953a48edc4STim Kryger return -EPROBE_DEFER; 29963a48edc4STim Kryger 29976231f3deSPhilip Rakity /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 29983a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) { 29993a48edc4STim Kryger ret = regulator_enable(mmc->supply.vqmmc); 30003a48edc4STim Kryger if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3001cec2e216SKevin Liu 1950000)) 30028363c374SKevin Liu caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 30038363c374SKevin Liu SDHCI_SUPPORT_SDR50 | 30046231f3deSPhilip Rakity SDHCI_SUPPORT_DDR50); 3005a3361abaSChris Ball if (ret) { 3006a3361abaSChris Ball pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3007a3361abaSChris Ball mmc_hostname(mmc), ret); 30083a48edc4STim Kryger mmc->supply.vqmmc = NULL; 3009a3361abaSChris Ball } 30108363c374SKevin Liu } 30116231f3deSPhilip Rakity 30126a66180aSDaniel Drake if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 30136a66180aSDaniel Drake caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 30146a66180aSDaniel Drake SDHCI_SUPPORT_DDR50); 30156a66180aSDaniel Drake 30164188bba0SAl Cooper /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 30174188bba0SAl Cooper if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 30184188bba0SAl Cooper SDHCI_SUPPORT_DDR50)) 3019f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3020f2119df6SArindam Nath 3021f2119df6SArindam Nath /* SDR104 supports also implies SDR50 support */ 3022156e14b1SGiuseppe CAVALLARO if (caps[1] & SDHCI_SUPPORT_SDR104) { 3023f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3024156e14b1SGiuseppe CAVALLARO /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3025156e14b1SGiuseppe CAVALLARO * field can be promoted to support HS200. 3026156e14b1SGiuseppe CAVALLARO */ 302713868bf2SDavid Cohen if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3028156e14b1SGiuseppe CAVALLARO mmc->caps2 |= MMC_CAP2_HS200; 3029156e14b1SGiuseppe CAVALLARO } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3030f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_SDR50; 3031f2119df6SArindam Nath 30329107ebbfSMicky Ching if ((caps[1] & SDHCI_SUPPORT_DDR50) && 30339107ebbfSMicky Ching !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3034f2119df6SArindam Nath mmc->caps |= MMC_CAP_UHS_DDR50; 3035f2119df6SArindam Nath 3036069c9f14SGirish K S /* Does the host need tuning for SDR50? */ 3037b513ea25SArindam Nath if (caps[1] & SDHCI_USE_SDR50_TUNING) 3038b513ea25SArindam Nath host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3039b513ea25SArindam Nath 3040156e14b1SGiuseppe CAVALLARO /* Does the host need tuning for SDR104 / HS200? */ 3041069c9f14SGirish K S if (mmc->caps2 & MMC_CAP2_HS200) 3042156e14b1SGiuseppe CAVALLARO host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3043069c9f14SGirish K S 3044d6d50a15SArindam Nath /* Driver Type(s) (A, C, D) supported by the host */ 3045d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_A) 3046d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3047d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_C) 3048d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3049d6d50a15SArindam Nath if (caps[1] & SDHCI_DRIVER_TYPE_D) 3050d6d50a15SArindam Nath mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3051d6d50a15SArindam Nath 3052cf2b5eeaSArindam Nath /* Initial value for re-tuning timer count */ 3053cf2b5eeaSArindam Nath host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3054cf2b5eeaSArindam Nath SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3055cf2b5eeaSArindam Nath 3056cf2b5eeaSArindam Nath /* 3057cf2b5eeaSArindam Nath * In case Re-tuning Timer is not disabled, the actual value of 3058cf2b5eeaSArindam Nath * re-tuning timer will be 2 ^ (n - 1). 3059cf2b5eeaSArindam Nath */ 3060cf2b5eeaSArindam Nath if (host->tuning_count) 3061cf2b5eeaSArindam Nath host->tuning_count = 1 << (host->tuning_count - 1); 3062cf2b5eeaSArindam Nath 3063cf2b5eeaSArindam Nath /* Re-tuning mode supported by the Host Controller */ 3064cf2b5eeaSArindam Nath host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3065cf2b5eeaSArindam Nath SDHCI_RETUNING_MODE_SHIFT; 3066cf2b5eeaSArindam Nath 30678f230f45STakashi Iwai ocr_avail = 0; 3068bad37e1aSPhilip Rakity 3069f2119df6SArindam Nath /* 3070f2119df6SArindam Nath * According to SD Host Controller spec v3.00, if the Host System 3071f2119df6SArindam Nath * can afford more than 150mA, Host Driver should set XPC to 1. Also 3072f2119df6SArindam Nath * the value is meaningful only if Voltage Support in the Capabilities 3073f2119df6SArindam Nath * register is set. The actual current value is 4 times the register 3074f2119df6SArindam Nath * value. 3075f2119df6SArindam Nath */ 3076f2119df6SArindam Nath max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 30773a48edc4STim Kryger if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3078ae906037SChuanxiao.Dong int curr = regulator_get_current_limit(mmc->supply.vmmc); 3079bad37e1aSPhilip Rakity if (curr > 0) { 3080bad37e1aSPhilip Rakity 3081bad37e1aSPhilip Rakity /* convert to SDHCI_MAX_CURRENT format */ 3082bad37e1aSPhilip Rakity curr = curr/1000; /* convert to mA */ 3083bad37e1aSPhilip Rakity curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3084bad37e1aSPhilip Rakity 3085bad37e1aSPhilip Rakity curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3086bad37e1aSPhilip Rakity max_current_caps = 3087bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3088bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3089bad37e1aSPhilip Rakity (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3090bad37e1aSPhilip Rakity } 3091bad37e1aSPhilip Rakity } 3092f2119df6SArindam Nath 3093f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_330) { 30948f230f45STakashi Iwai ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3095f2119df6SArindam Nath 309655c4665eSAaron Lu mmc->max_current_330 = ((max_current_caps & 3097f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_MASK) >> 3098f2119df6SArindam Nath SDHCI_MAX_CURRENT_330_SHIFT) * 3099f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3100f2119df6SArindam Nath } 3101f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_300) { 31028f230f45STakashi Iwai ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3103f2119df6SArindam Nath 310455c4665eSAaron Lu mmc->max_current_300 = ((max_current_caps & 3105f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_MASK) >> 3106f2119df6SArindam Nath SDHCI_MAX_CURRENT_300_SHIFT) * 3107f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3108f2119df6SArindam Nath } 3109f2119df6SArindam Nath if (caps[0] & SDHCI_CAN_VDD_180) { 31108f230f45STakashi Iwai ocr_avail |= MMC_VDD_165_195; 31118f230f45STakashi Iwai 311255c4665eSAaron Lu mmc->max_current_180 = ((max_current_caps & 3113f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_MASK) >> 3114f2119df6SArindam Nath SDHCI_MAX_CURRENT_180_SHIFT) * 3115f2119df6SArindam Nath SDHCI_MAX_CURRENT_MULTIPLIER; 3116f2119df6SArindam Nath } 3117f2119df6SArindam Nath 311852221610STim Kryger /* If OCR set by external regulators, use it instead */ 31193a48edc4STim Kryger if (mmc->ocr_avail) 312052221610STim Kryger ocr_avail = mmc->ocr_avail; 31213a48edc4STim Kryger 3122c0b887b6SHaijun Zhang if (host->ocr_mask) 31233a48edc4STim Kryger ocr_avail &= host->ocr_mask; 3124c0b887b6SHaijun Zhang 31258f230f45STakashi Iwai mmc->ocr_avail = ocr_avail; 31268f230f45STakashi Iwai mmc->ocr_avail_sdio = ocr_avail; 31278f230f45STakashi Iwai if (host->ocr_avail_sdio) 31288f230f45STakashi Iwai mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 31298f230f45STakashi Iwai mmc->ocr_avail_sd = ocr_avail; 31308f230f45STakashi Iwai if (host->ocr_avail_sd) 31318f230f45STakashi Iwai mmc->ocr_avail_sd &= host->ocr_avail_sd; 31328f230f45STakashi Iwai else /* normal SD controllers don't support 1.8V */ 31338f230f45STakashi Iwai mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 31348f230f45STakashi Iwai mmc->ocr_avail_mmc = ocr_avail; 31358f230f45STakashi Iwai if (host->ocr_avail_mmc) 31368f230f45STakashi Iwai mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 31371c6a0718SPierre Ossman 31381c6a0718SPierre Ossman if (mmc->ocr_avail == 0) { 3139a3c76eb9SGirish K S pr_err("%s: Hardware doesn't report any " 3140b69c9058SPierre Ossman "support voltages.\n", mmc_hostname(mmc)); 3141b8c86fc5SPierre Ossman return -ENODEV; 31421c6a0718SPierre Ossman } 31431c6a0718SPierre Ossman 31441c6a0718SPierre Ossman spin_lock_init(&host->lock); 31451c6a0718SPierre Ossman 31461c6a0718SPierre Ossman /* 31472134a922SPierre Ossman * Maximum number of segments. Depends on if the hardware 31482134a922SPierre Ossman * can do scatter/gather or not. 31491c6a0718SPierre Ossman */ 31502134a922SPierre Ossman if (host->flags & SDHCI_USE_ADMA) 3151a36274e0SMartin K. Petersen mmc->max_segs = 128; 3152a13abc7bSRichard Röjfors else if (host->flags & SDHCI_USE_SDMA) 3153a36274e0SMartin K. Petersen mmc->max_segs = 1; 31542134a922SPierre Ossman else /* PIO */ 3155a36274e0SMartin K. Petersen mmc->max_segs = 128; 31561c6a0718SPierre Ossman 31571c6a0718SPierre Ossman /* 31581c6a0718SPierre Ossman * Maximum number of sectors in one transfer. Limited by DMA boundary 31591c6a0718SPierre Ossman * size (512KiB). 31601c6a0718SPierre Ossman */ 31611c6a0718SPierre Ossman mmc->max_req_size = 524288; 31621c6a0718SPierre Ossman 31631c6a0718SPierre Ossman /* 31641c6a0718SPierre Ossman * Maximum segment size. Could be one segment with the maximum number 31652134a922SPierre Ossman * of bytes. When doing hardware scatter/gather, each entry cannot 31662134a922SPierre Ossman * be larger than 64 KiB though. 31671c6a0718SPierre Ossman */ 316830652aa3SOlof Johansson if (host->flags & SDHCI_USE_ADMA) { 316930652aa3SOlof Johansson if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 317030652aa3SOlof Johansson mmc->max_seg_size = 65535; 31712134a922SPierre Ossman else 317230652aa3SOlof Johansson mmc->max_seg_size = 65536; 317330652aa3SOlof Johansson } else { 31741c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 317530652aa3SOlof Johansson } 31761c6a0718SPierre Ossman 31771c6a0718SPierre Ossman /* 31781c6a0718SPierre Ossman * Maximum block size. This varies from controller to controller and 31791c6a0718SPierre Ossman * is specified in the capabilities register. 31801c6a0718SPierre Ossman */ 31810633f654SAnton Vorontsov if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 31820633f654SAnton Vorontsov mmc->max_blk_size = 2; 31830633f654SAnton Vorontsov } else { 3184f2119df6SArindam Nath mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 31850633f654SAnton Vorontsov SDHCI_MAX_BLOCK_SHIFT; 31861c6a0718SPierre Ossman if (mmc->max_blk_size >= 3) { 3187a3c76eb9SGirish K S pr_warning("%s: Invalid maximum block size, " 3188b69c9058SPierre Ossman "assuming 512 bytes\n", mmc_hostname(mmc)); 31890633f654SAnton Vorontsov mmc->max_blk_size = 0; 31900633f654SAnton Vorontsov } 31910633f654SAnton Vorontsov } 31920633f654SAnton Vorontsov 31931c6a0718SPierre Ossman mmc->max_blk_size = 512 << mmc->max_blk_size; 31941c6a0718SPierre Ossman 31951c6a0718SPierre Ossman /* 31961c6a0718SPierre Ossman * Maximum block count. 31971c6a0718SPierre Ossman */ 31981388eefdSBen Dooks mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 31991c6a0718SPierre Ossman 32001c6a0718SPierre Ossman /* 32011c6a0718SPierre Ossman * Init tasklets. 32021c6a0718SPierre Ossman */ 32031c6a0718SPierre Ossman tasklet_init(&host->finish_tasklet, 32041c6a0718SPierre Ossman sdhci_tasklet_finish, (unsigned long)host); 32051c6a0718SPierre Ossman 32061c6a0718SPierre Ossman setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 32071c6a0718SPierre Ossman 3208cf2b5eeaSArindam Nath if (host->version >= SDHCI_SPEC_300) { 3209b513ea25SArindam Nath init_waitqueue_head(&host->buf_ready_int); 3210b513ea25SArindam Nath 3211cf2b5eeaSArindam Nath /* Initialize re-tuning timer */ 3212cf2b5eeaSArindam Nath init_timer(&host->tuning_timer); 3213cf2b5eeaSArindam Nath host->tuning_timer.data = (unsigned long)host; 3214cf2b5eeaSArindam Nath host->tuning_timer.function = sdhci_tuning_timer; 3215cf2b5eeaSArindam Nath } 3216cf2b5eeaSArindam Nath 32172af502caSShawn Guo sdhci_init(host, 0); 32182af502caSShawn Guo 3219781e989cSRussell King ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3220781e989cSRussell King IRQF_SHARED, mmc_hostname(mmc), host); 32210fc81ee3SMark Brown if (ret) { 32220fc81ee3SMark Brown pr_err("%s: Failed to request IRQ %d: %d\n", 32230fc81ee3SMark Brown mmc_hostname(mmc), host->irq, ret); 32241c6a0718SPierre Ossman goto untasklet; 32250fc81ee3SMark Brown } 32261c6a0718SPierre Ossman 32271c6a0718SPierre Ossman #ifdef CONFIG_MMC_DEBUG 32281c6a0718SPierre Ossman sdhci_dumpregs(host); 32291c6a0718SPierre Ossman #endif 32301c6a0718SPierre Ossman 3231f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 32325dbace0cSHelmut Schaa snprintf(host->led_name, sizeof(host->led_name), 32335dbace0cSHelmut Schaa "%s::", mmc_hostname(mmc)); 32345dbace0cSHelmut Schaa host->led.name = host->led_name; 32352f730fecSPierre Ossman host->led.brightness = LED_OFF; 32362f730fecSPierre Ossman host->led.default_trigger = mmc_hostname(mmc); 32372f730fecSPierre Ossman host->led.brightness_set = sdhci_led_control; 32382f730fecSPierre Ossman 3239b8c86fc5SPierre Ossman ret = led_classdev_register(mmc_dev(mmc), &host->led); 32400fc81ee3SMark Brown if (ret) { 32410fc81ee3SMark Brown pr_err("%s: Failed to register LED device: %d\n", 32420fc81ee3SMark Brown mmc_hostname(mmc), ret); 32432f730fecSPierre Ossman goto reset; 32440fc81ee3SMark Brown } 32452f730fecSPierre Ossman #endif 32462f730fecSPierre Ossman 32471c6a0718SPierre Ossman mmiowb(); 32481c6a0718SPierre Ossman 32491c6a0718SPierre Ossman mmc_add_host(mmc); 32501c6a0718SPierre Ossman 3251a3c76eb9SGirish K S pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3252d1b26863SKay Sievers mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3253a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3254a13abc7bSRichard Röjfors (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 32551c6a0718SPierre Ossman 32567260cf5eSAnton Vorontsov sdhci_enable_card_detection(host); 32577260cf5eSAnton Vorontsov 32581c6a0718SPierre Ossman return 0; 32591c6a0718SPierre Ossman 3260f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 32612f730fecSPierre Ossman reset: 326203231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 3263b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3264b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 32652f730fecSPierre Ossman free_irq(host->irq, host); 32662f730fecSPierre Ossman #endif 32671c6a0718SPierre Ossman untasklet: 32681c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 32691c6a0718SPierre Ossman 32701c6a0718SPierre Ossman return ret; 32711c6a0718SPierre Ossman } 32721c6a0718SPierre Ossman 3273b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_add_host); 3274b8c86fc5SPierre Ossman 32751e72859eSPierre Ossman void sdhci_remove_host(struct sdhci_host *host, int dead) 32761c6a0718SPierre Ossman { 32773a48edc4STim Kryger struct mmc_host *mmc = host->mmc; 32781e72859eSPierre Ossman unsigned long flags; 32791e72859eSPierre Ossman 32801e72859eSPierre Ossman if (dead) { 32811e72859eSPierre Ossman spin_lock_irqsave(&host->lock, flags); 32821e72859eSPierre Ossman 32831e72859eSPierre Ossman host->flags |= SDHCI_DEVICE_DEAD; 32841e72859eSPierre Ossman 32851e72859eSPierre Ossman if (host->mrq) { 3286a3c76eb9SGirish K S pr_err("%s: Controller removed during " 32874e743f1fSMarkus Mayer " transfer!\n", mmc_hostname(mmc)); 32881e72859eSPierre Ossman 32891e72859eSPierre Ossman host->mrq->cmd->error = -ENOMEDIUM; 32901e72859eSPierre Ossman tasklet_schedule(&host->finish_tasklet); 32911e72859eSPierre Ossman } 32921e72859eSPierre Ossman 32931e72859eSPierre Ossman spin_unlock_irqrestore(&host->lock, flags); 32941e72859eSPierre Ossman } 32951e72859eSPierre Ossman 32967260cf5eSAnton Vorontsov sdhci_disable_card_detection(host); 32977260cf5eSAnton Vorontsov 32984e743f1fSMarkus Mayer mmc_remove_host(mmc); 32991c6a0718SPierre Ossman 3300f9134319SPierre Ossman #ifdef SDHCI_USE_LEDS_CLASS 33012f730fecSPierre Ossman led_classdev_unregister(&host->led); 33022f730fecSPierre Ossman #endif 33032f730fecSPierre Ossman 33041e72859eSPierre Ossman if (!dead) 330503231f9bSRussell King sdhci_do_reset(host, SDHCI_RESET_ALL); 33061c6a0718SPierre Ossman 3307b537f94cSRussell King sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3308b537f94cSRussell King sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 33091c6a0718SPierre Ossman free_irq(host->irq, host); 33101c6a0718SPierre Ossman 33111c6a0718SPierre Ossman del_timer_sync(&host->timer); 33121c6a0718SPierre Ossman 33131c6a0718SPierre Ossman tasklet_kill(&host->finish_tasklet); 33142134a922SPierre Ossman 33153a48edc4STim Kryger if (!IS_ERR(mmc->supply.vmmc)) 33163a48edc4STim Kryger regulator_disable(mmc->supply.vmmc); 33179bea3c85SMarek Szyprowski 33183a48edc4STim Kryger if (!IS_ERR(mmc->supply.vqmmc)) 33193a48edc4STim Kryger regulator_disable(mmc->supply.vqmmc); 33206231f3deSPhilip Rakity 3321d1e49f77SRussell King if (host->adma_desc) 33224e743f1fSMarkus Mayer dma_free_coherent(mmc_dev(mmc), ADMA_SIZE, 3323d1e49f77SRussell King host->adma_desc, host->adma_addr); 33242134a922SPierre Ossman kfree(host->align_buffer); 33252134a922SPierre Ossman 33262134a922SPierre Ossman host->adma_desc = NULL; 33272134a922SPierre Ossman host->align_buffer = NULL; 33281c6a0718SPierre Ossman } 33291c6a0718SPierre Ossman 3330b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_remove_host); 3331b8c86fc5SPierre Ossman 3332b8c86fc5SPierre Ossman void sdhci_free_host(struct sdhci_host *host) 33331c6a0718SPierre Ossman { 3334b8c86fc5SPierre Ossman mmc_free_host(host->mmc); 33351c6a0718SPierre Ossman } 33361c6a0718SPierre Ossman 3337b8c86fc5SPierre Ossman EXPORT_SYMBOL_GPL(sdhci_free_host); 33381c6a0718SPierre Ossman 33391c6a0718SPierre Ossman /*****************************************************************************\ 33401c6a0718SPierre Ossman * * 33411c6a0718SPierre Ossman * Driver init/exit * 33421c6a0718SPierre Ossman * * 33431c6a0718SPierre Ossman \*****************************************************************************/ 33441c6a0718SPierre Ossman 33451c6a0718SPierre Ossman static int __init sdhci_drv_init(void) 33461c6a0718SPierre Ossman { 3347a3c76eb9SGirish K S pr_info(DRIVER_NAME 33481c6a0718SPierre Ossman ": Secure Digital Host Controller Interface driver\n"); 3349a3c76eb9SGirish K S pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 33501c6a0718SPierre Ossman 3351b8c86fc5SPierre Ossman return 0; 33521c6a0718SPierre Ossman } 33531c6a0718SPierre Ossman 33541c6a0718SPierre Ossman static void __exit sdhci_drv_exit(void) 33551c6a0718SPierre Ossman { 33561c6a0718SPierre Ossman } 33571c6a0718SPierre Ossman 33581c6a0718SPierre Ossman module_init(sdhci_drv_init); 33591c6a0718SPierre Ossman module_exit(sdhci_drv_exit); 33601c6a0718SPierre Ossman 33611c6a0718SPierre Ossman module_param(debug_quirks, uint, 0444); 336266fd8ad5SAdrian Hunter module_param(debug_quirks2, uint, 0444); 33631c6a0718SPierre Ossman 336432710e8fSPierre Ossman MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3365b8c86fc5SPierre Ossman MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 33661c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 33671c6a0718SPierre Ossman 33681c6a0718SPierre Ossman MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 336966fd8ad5SAdrian Hunter MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 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