13a3748dbSHu Ziji /* 23a3748dbSHu Ziji * Copyright (C) 2016 Marvell, All Rights Reserved. 33a3748dbSHu Ziji * 43a3748dbSHu Ziji * Author: Hu Ziji <huziji@marvell.com> 53a3748dbSHu Ziji * Date: 2016-8-24 63a3748dbSHu Ziji * 73a3748dbSHu Ziji * This program is free software; you can redistribute it and/or 83a3748dbSHu Ziji * modify it under the terms of the GNU General Public License as 93a3748dbSHu Ziji * published by the Free Software Foundation version 2. 103a3748dbSHu Ziji */ 113a3748dbSHu Ziji #ifndef SDHCI_XENON_H_ 123a3748dbSHu Ziji #define SDHCI_XENON_H_ 133a3748dbSHu Ziji 143a3748dbSHu Ziji /* Register Offset of Xenon SDHC self-defined register */ 153a3748dbSHu Ziji #define XENON_SYS_CFG_INFO 0x0104 163a3748dbSHu Ziji #define XENON_SLOT_TYPE_SDIO_SHIFT 24 173a3748dbSHu Ziji #define XENON_NR_SUPPORTED_SLOT_MASK 0x7 183a3748dbSHu Ziji 193a3748dbSHu Ziji #define XENON_SYS_OP_CTRL 0x0108 203a3748dbSHu Ziji #define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20) 213a3748dbSHu Ziji #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8 223a3748dbSHu Ziji #define XENON_SLOT_ENABLE_SHIFT 0 233a3748dbSHu Ziji 243a3748dbSHu Ziji #define XENON_SYS_EXT_OP_CTRL 0x010C 253a3748dbSHu Ziji #define XENON_MASK_CMD_CONFLICT_ERR BIT(8) 263a3748dbSHu Ziji 2706c8b667SHu Ziji #define XENON_SLOT_OP_STATUS_CTRL 0x0128 2806c8b667SHu Ziji #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16 2906c8b667SHu Ziji #define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7 3006c8b667SHu Ziji #define XENON_TUN_CONSECUTIVE_TIMES 0x4 3106c8b667SHu Ziji #define XENON_TUNING_STEP_SHIFT 12 3206c8b667SHu Ziji #define XENON_TUNING_STEP_MASK 0xF 3306c8b667SHu Ziji #define XENON_TUNING_STEP_DIVIDER BIT(6) 3406c8b667SHu Ziji 3506c8b667SHu Ziji #define XENON_SLOT_EMMC_CTRL 0x0130 3606c8b667SHu Ziji #define XENON_ENABLE_DATA_STROBE BIT(24) 3706c8b667SHu Ziji 383a3748dbSHu Ziji #define XENON_SLOT_RETUNING_REQ_CTRL 0x0144 393a3748dbSHu Ziji /* retuning compatible */ 403a3748dbSHu Ziji #define XENON_RETUNING_COMPATIBLE 0x1 413a3748dbSHu Ziji 4206c8b667SHu Ziji #define XENON_SLOT_EXT_PRESENT_STATE 0x014C 4306c8b667SHu Ziji #define XENON_DLL_LOCK_STATE 0x1 4406c8b667SHu Ziji 4506c8b667SHu Ziji #define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150 4606c8b667SHu Ziji 473a3748dbSHu Ziji /* Tuning Parameter */ 483a3748dbSHu Ziji #define XENON_TMR_RETUN_NO_PRESENT 0xF 493a3748dbSHu Ziji #define XENON_DEF_TUNING_COUNT 0x9 503a3748dbSHu Ziji 513a3748dbSHu Ziji #define XENON_DEFAULT_SDCLK_FREQ 400000 5206c8b667SHu Ziji #define XENON_LOWEST_SDCLK_FREQ 100000 533a3748dbSHu Ziji 543a3748dbSHu Ziji /* Xenon specific Mode Select value */ 553a3748dbSHu Ziji #define XENON_CTRL_HS200 0x5 563a3748dbSHu Ziji #define XENON_CTRL_HS400 0x6 573a3748dbSHu Ziji 583a3748dbSHu Ziji struct xenon_priv { 593a3748dbSHu Ziji unsigned char tuning_count; 603a3748dbSHu Ziji /* idx of SDHC */ 613a3748dbSHu Ziji u8 sdhc_id; 623a3748dbSHu Ziji 633a3748dbSHu Ziji /* 643a3748dbSHu Ziji * eMMC/SD/SDIO require different register settings. 653a3748dbSHu Ziji * Xenon driver has to recognize card type 663a3748dbSHu Ziji * before mmc_host->card is not available. 673a3748dbSHu Ziji * This field records the card type during init. 683a3748dbSHu Ziji * It is updated in xenon_init_card(). 693a3748dbSHu Ziji * 703a3748dbSHu Ziji * It is only valid during initialization after it is updated. 713a3748dbSHu Ziji * Do not access this variable in normal transfers after 723a3748dbSHu Ziji * initialization completes. 733a3748dbSHu Ziji */ 743a3748dbSHu Ziji unsigned int init_card_type; 7506c8b667SHu Ziji 7606c8b667SHu Ziji /* 7706c8b667SHu Ziji * The bus_width, timing, and clock fields in below 7806c8b667SHu Ziji * record the current ios setting of Xenon SDHC. 7906c8b667SHu Ziji * Driver will adjust PHY setting if any change to 8006c8b667SHu Ziji * ios affects PHY timing. 8106c8b667SHu Ziji */ 8206c8b667SHu Ziji unsigned char bus_width; 8306c8b667SHu Ziji unsigned char timing; 8406c8b667SHu Ziji unsigned int clock; 8506c8b667SHu Ziji 8606c8b667SHu Ziji int phy_type; 8706c8b667SHu Ziji /* 8806c8b667SHu Ziji * Contains board-specific PHY parameters 8906c8b667SHu Ziji * passed from device tree. 9006c8b667SHu Ziji */ 9106c8b667SHu Ziji void *phy_params; 9206c8b667SHu Ziji struct xenon_emmc_phy_regs *emmc_phy_regs; 933a3748dbSHu Ziji }; 943a3748dbSHu Ziji 9506c8b667SHu Ziji int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios); 9606c8b667SHu Ziji void xenon_clean_phy(struct sdhci_host *host); 9706c8b667SHu Ziji int xenon_phy_parse_dt(struct device_node *np, 9806c8b667SHu Ziji struct sdhci_host *host); 993a3748dbSHu Ziji #endif 100