1a10e763bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 23a3748dbSHu Ziji /* 33a3748dbSHu Ziji * Copyright (C) 2016 Marvell, All Rights Reserved. 43a3748dbSHu Ziji * 53a3748dbSHu Ziji * Author: Hu Ziji <huziji@marvell.com> 63a3748dbSHu Ziji * Date: 2016-8-24 73a3748dbSHu Ziji */ 83a3748dbSHu Ziji #ifndef SDHCI_XENON_H_ 93a3748dbSHu Ziji #define SDHCI_XENON_H_ 103a3748dbSHu Ziji 113a3748dbSHu Ziji /* Register Offset of Xenon SDHC self-defined register */ 123a3748dbSHu Ziji #define XENON_SYS_CFG_INFO 0x0104 133a3748dbSHu Ziji #define XENON_SLOT_TYPE_SDIO_SHIFT 24 143a3748dbSHu Ziji #define XENON_NR_SUPPORTED_SLOT_MASK 0x7 153a3748dbSHu Ziji 163a3748dbSHu Ziji #define XENON_SYS_OP_CTRL 0x0108 173a3748dbSHu Ziji #define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20) 183a3748dbSHu Ziji #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8 193a3748dbSHu Ziji #define XENON_SLOT_ENABLE_SHIFT 0 203a3748dbSHu Ziji 213a3748dbSHu Ziji #define XENON_SYS_EXT_OP_CTRL 0x010C 223a3748dbSHu Ziji #define XENON_MASK_CMD_CONFLICT_ERR BIT(8) 233a3748dbSHu Ziji 2406c8b667SHu Ziji #define XENON_SLOT_OP_STATUS_CTRL 0x0128 2506c8b667SHu Ziji #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16 2606c8b667SHu Ziji #define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7 2706c8b667SHu Ziji #define XENON_TUN_CONSECUTIVE_TIMES 0x4 2806c8b667SHu Ziji #define XENON_TUNING_STEP_SHIFT 12 2906c8b667SHu Ziji #define XENON_TUNING_STEP_MASK 0xF 3006c8b667SHu Ziji #define XENON_TUNING_STEP_DIVIDER BIT(6) 3106c8b667SHu Ziji 3206c8b667SHu Ziji #define XENON_SLOT_EMMC_CTRL 0x0130 33aab6e25aSHu Ziji #define XENON_ENABLE_RESP_STROBE BIT(25) 3406c8b667SHu Ziji #define XENON_ENABLE_DATA_STROBE BIT(24) 3506c8b667SHu Ziji 363a3748dbSHu Ziji #define XENON_SLOT_RETUNING_REQ_CTRL 0x0144 373a3748dbSHu Ziji /* retuning compatible */ 383a3748dbSHu Ziji #define XENON_RETUNING_COMPATIBLE 0x1 393a3748dbSHu Ziji 4006c8b667SHu Ziji #define XENON_SLOT_EXT_PRESENT_STATE 0x014C 4106c8b667SHu Ziji #define XENON_DLL_LOCK_STATE 0x1 4206c8b667SHu Ziji 4306c8b667SHu Ziji #define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150 4406c8b667SHu Ziji 453a3748dbSHu Ziji /* Tuning Parameter */ 463a3748dbSHu Ziji #define XENON_TMR_RETUN_NO_PRESENT 0xF 473a3748dbSHu Ziji #define XENON_DEF_TUNING_COUNT 0x9 483a3748dbSHu Ziji 493a3748dbSHu Ziji #define XENON_DEFAULT_SDCLK_FREQ 400000 5006c8b667SHu Ziji #define XENON_LOWEST_SDCLK_FREQ 100000 513a3748dbSHu Ziji 523a3748dbSHu Ziji /* Xenon specific Mode Select value */ 533a3748dbSHu Ziji #define XENON_CTRL_HS200 0x5 543a3748dbSHu Ziji #define XENON_CTRL_HS400 0x6 553a3748dbSHu Ziji 56f75fda37SMarcin Wojtas enum xenon_variant { 57f75fda37SMarcin Wojtas XENON_A3700, 58f75fda37SMarcin Wojtas XENON_AP806, 59f75fda37SMarcin Wojtas XENON_AP807, 60f75fda37SMarcin Wojtas XENON_CP110 61f75fda37SMarcin Wojtas }; 62f75fda37SMarcin Wojtas 633a3748dbSHu Ziji struct xenon_priv { 643a3748dbSHu Ziji unsigned char tuning_count; 653a3748dbSHu Ziji /* idx of SDHC */ 663a3748dbSHu Ziji u8 sdhc_id; 673a3748dbSHu Ziji 683a3748dbSHu Ziji /* 693a3748dbSHu Ziji * eMMC/SD/SDIO require different register settings. 703a3748dbSHu Ziji * Xenon driver has to recognize card type 713a3748dbSHu Ziji * before mmc_host->card is not available. 723a3748dbSHu Ziji * This field records the card type during init. 733a3748dbSHu Ziji * It is updated in xenon_init_card(). 743a3748dbSHu Ziji * 753a3748dbSHu Ziji * It is only valid during initialization after it is updated. 763a3748dbSHu Ziji * Do not access this variable in normal transfers after 773a3748dbSHu Ziji * initialization completes. 783a3748dbSHu Ziji */ 793a3748dbSHu Ziji unsigned int init_card_type; 8006c8b667SHu Ziji 8106c8b667SHu Ziji /* 8206c8b667SHu Ziji * The bus_width, timing, and clock fields in below 8306c8b667SHu Ziji * record the current ios setting of Xenon SDHC. 8406c8b667SHu Ziji * Driver will adjust PHY setting if any change to 8506c8b667SHu Ziji * ios affects PHY timing. 8606c8b667SHu Ziji */ 8706c8b667SHu Ziji unsigned char bus_width; 8806c8b667SHu Ziji unsigned char timing; 8906c8b667SHu Ziji unsigned int clock; 90bb16ea17SGregory CLEMENT struct clk *axi_clk; 9106c8b667SHu Ziji 9206c8b667SHu Ziji int phy_type; 9306c8b667SHu Ziji /* 9406c8b667SHu Ziji * Contains board-specific PHY parameters 9506c8b667SHu Ziji * passed from device tree. 9606c8b667SHu Ziji */ 9706c8b667SHu Ziji void *phy_params; 9806c8b667SHu Ziji struct xenon_emmc_phy_regs *emmc_phy_regs; 99a027b2c5SZhoujie Wu bool restore_needed; 100f75fda37SMarcin Wojtas enum xenon_variant hw_version; 1013a3748dbSHu Ziji }; 1023a3748dbSHu Ziji 10306c8b667SHu Ziji int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios); 104*f29bf660SMarcin Wojtas int xenon_phy_parse_params(struct device *dev, 10506c8b667SHu Ziji struct sdhci_host *host); 106298269c6SHu Ziji void xenon_soc_pad_ctrl(struct sdhci_host *host, 107298269c6SHu Ziji unsigned char signal_voltage); 1083a3748dbSHu Ziji #endif 109