1 /* 2 * PHY support for Xenon SDHC 3 * 4 * Copyright (C) 2016 Marvell, All Rights Reserved. 5 * 6 * Author: Hu Ziji <huziji@marvell.com> 7 * Date: 2016-8-24 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 */ 13 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/ktime.h> 17 #include <linux/of_address.h> 18 19 #include "sdhci-pltfm.h" 20 #include "sdhci-xenon.h" 21 22 /* Register base for eMMC PHY 5.0 Version */ 23 #define XENON_EMMC_5_0_PHY_REG_BASE 0x0160 24 /* Register base for eMMC PHY 5.1 Version */ 25 #define XENON_EMMC_PHY_REG_BASE 0x0170 26 27 #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE 28 #define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE 29 #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29) 30 #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28) 31 #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18) 32 #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 33 #define XENON_PHY_INITIALIZAION BIT(31) 34 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF 35 #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12 36 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF 37 #define XENON_FC_SYNC_EN_DURATION_SHIFT 8 38 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF 39 #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4 40 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF 41 #define XENON_FC_SYNC_RST_DURATION_SHIFT 0 42 43 #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4) 44 #define XENON_EMMC_5_0_PHY_FUNC_CONTROL \ 45 (XENON_EMMC_5_0_PHY_REG_BASE + 0x4) 46 #define XENON_ASYNC_DDRMODE_MASK BIT(23) 47 #define XENON_ASYNC_DDRMODE_SHIFT 23 48 #define XENON_CMD_DDR_MODE BIT(16) 49 #define XENON_DQ_DDR_MODE_SHIFT 8 50 #define XENON_DQ_DDR_MODE_MASK 0xFF 51 #define XENON_DQ_ASYNC_MODE BIT(4) 52 53 #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8) 54 #define XENON_EMMC_5_0_PHY_PAD_CONTROL \ 55 (XENON_EMMC_5_0_PHY_REG_BASE + 0x8) 56 #define XENON_REC_EN_SHIFT 24 57 #define XENON_REC_EN_MASK 0xF 58 #define XENON_FC_DQ_RECEN BIT(24) 59 #define XENON_FC_CMD_RECEN BIT(25) 60 #define XENON_FC_QSP_RECEN BIT(26) 61 #define XENON_FC_QSN_RECEN BIT(27) 62 #define XENON_OEN_QSN BIT(28) 63 #define XENON_AUTO_RECEN_CTRL BIT(30) 64 #define XENON_FC_ALL_CMOS_RECEIVER 0xF000 65 66 #define XENON_EMMC5_FC_QSP_PD BIT(18) 67 #define XENON_EMMC5_FC_QSP_PU BIT(22) 68 #define XENON_EMMC5_FC_CMD_PD BIT(17) 69 #define XENON_EMMC5_FC_CMD_PU BIT(21) 70 #define XENON_EMMC5_FC_DQ_PD BIT(16) 71 #define XENON_EMMC5_FC_DQ_PU BIT(20) 72 73 #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC) 74 #define XENON_EMMC5_1_FC_QSP_PD BIT(9) 75 #define XENON_EMMC5_1_FC_QSP_PU BIT(25) 76 #define XENON_EMMC5_1_FC_CMD_PD BIT(8) 77 #define XENON_EMMC5_1_FC_CMD_PU BIT(24) 78 #define XENON_EMMC5_1_FC_DQ_PD 0xFF 79 #define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16) 80 81 #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10) 82 #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \ 83 (XENON_EMMC_5_0_PHY_REG_BASE + 0xC) 84 #define XENON_ZNR_MASK 0x1F 85 #define XENON_ZNR_SHIFT 8 86 #define XENON_ZPR_MASK 0x1F 87 /* Preferred ZNR and ZPR value vary between different boards. 88 * The specific ZNR and ZPR value should be defined here 89 * according to board actual timing. 90 */ 91 #define XENON_ZNR_DEF_VALUE 0xF 92 #define XENON_ZPR_DEF_VALUE 0xF 93 94 #define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14) 95 #define XENON_EMMC_5_0_PHY_DLL_CONTROL \ 96 (XENON_EMMC_5_0_PHY_REG_BASE + 0x10) 97 #define XENON_DLL_ENABLE BIT(31) 98 #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30) 99 #define XENON_DLL_REFCLK_SEL BIT(30) 100 #define XENON_DLL_UPDATE BIT(23) 101 #define XENON_DLL_PHSEL1_SHIFT 24 102 #define XENON_DLL_PHSEL0_SHIFT 16 103 #define XENON_DLL_PHASE_MASK 0x3F 104 #define XENON_DLL_PHASE_90_DEGREE 0x1F 105 #define XENON_DLL_FAST_LOCK BIT(5) 106 #define XENON_DLL_GAIN2X BIT(3) 107 #define XENON_DLL_BYPASS_EN BIT(0) 108 109 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \ 110 (XENON_EMMC_5_0_PHY_REG_BASE + 0x14) 111 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54 112 #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) 113 #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 114 115 /* 116 * List offset of PHY registers and some special register values 117 * in eMMC PHY 5.0 or eMMC PHY 5.1 118 */ 119 struct xenon_emmc_phy_regs { 120 /* Offset of Timing Adjust register */ 121 u16 timing_adj; 122 /* Offset of Func Control register */ 123 u16 func_ctrl; 124 /* Offset of Pad Control register */ 125 u16 pad_ctrl; 126 /* Offset of Pad Control register 2 */ 127 u16 pad_ctrl2; 128 /* Offset of DLL Control register */ 129 u16 dll_ctrl; 130 /* Offset of Logic Timing Adjust register */ 131 u16 logic_timing_adj; 132 /* DLL Update Enable bit */ 133 u32 dll_update; 134 /* value in Logic Timing Adjustment register */ 135 u32 logic_timing_val; 136 }; 137 138 static const char * const phy_types[] = { 139 "emmc 5.0 phy", 140 "emmc 5.1 phy" 141 }; 142 143 enum xenon_phy_type_enum { 144 EMMC_5_0_PHY, 145 EMMC_5_1_PHY, 146 NR_PHY_TYPES 147 }; 148 149 enum soc_pad_ctrl_type { 150 SOC_PAD_SD, 151 SOC_PAD_FIXED_1_8V, 152 }; 153 154 struct soc_pad_ctrl { 155 /* Register address of SoC PHY PAD ctrl */ 156 void __iomem *reg; 157 /* SoC PHY PAD ctrl type */ 158 enum soc_pad_ctrl_type pad_type; 159 /* SoC specific operation to set SoC PHY PAD */ 160 void (*set_soc_pad)(struct sdhci_host *host, 161 unsigned char signal_voltage); 162 }; 163 164 static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = { 165 .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST, 166 .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL, 167 .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL, 168 .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2, 169 .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL, 170 .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST, 171 .dll_update = XENON_DLL_UPDATE_STROBE_5_0, 172 .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE, 173 }; 174 175 static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = { 176 .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST, 177 .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL, 178 .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL, 179 .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2, 180 .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL, 181 .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 182 .dll_update = XENON_DLL_UPDATE, 183 .logic_timing_val = XENON_LOGIC_TIMING_VALUE, 184 }; 185 186 /* 187 * eMMC PHY configuration and operations 188 */ 189 struct xenon_emmc_phy_params { 190 bool slow_mode; 191 192 u8 znr; 193 u8 zpr; 194 195 /* Nr of consecutive Sampling Points of a Valid Sampling Window */ 196 u8 nr_tun_times; 197 /* Divider for calculating Tuning Step */ 198 u8 tun_step_divider; 199 200 struct soc_pad_ctrl pad_ctrl; 201 }; 202 203 static int xenon_alloc_emmc_phy(struct sdhci_host *host) 204 { 205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 206 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 207 struct xenon_emmc_phy_params *params; 208 209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); 210 if (!params) 211 return -ENOMEM; 212 213 priv->phy_params = params; 214 if (priv->phy_type == EMMC_5_0_PHY) 215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; 216 else 217 priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs; 218 219 return 0; 220 } 221 222 /* 223 * eMMC 5.0/5.1 PHY init/re-init. 224 * eMMC PHY init should be executed after: 225 * 1. SDCLK frequency changes. 226 * 2. SDCLK is stopped and re-enabled. 227 * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl 228 * are changed 229 */ 230 static int xenon_emmc_phy_init(struct sdhci_host *host) 231 { 232 u32 reg; 233 u32 wait, clock; 234 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 235 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 236 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 237 238 reg = sdhci_readl(host, phy_regs->timing_adj); 239 reg |= XENON_PHY_INITIALIZAION; 240 sdhci_writel(host, reg, phy_regs->timing_adj); 241 242 /* Add duration of FC_SYNC_RST */ 243 wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) & 244 XENON_FC_SYNC_RST_DURATION_MASK); 245 /* Add interval between FC_SYNC_EN and FC_SYNC_RST */ 246 wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) & 247 XENON_FC_SYNC_RST_EN_DURATION_MASK); 248 /* Add duration of asserting FC_SYNC_EN */ 249 wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) & 250 XENON_FC_SYNC_EN_DURATION_MASK); 251 /* Add duration of waiting for PHY */ 252 wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) & 253 XENON_WAIT_CYCLE_BEFORE_USING_MASK); 254 /* 4 additional bus clock and 4 AXI bus clock are required */ 255 wait += 8; 256 wait <<= 20; 257 258 clock = host->clock; 259 if (!clock) 260 /* Use the possibly slowest bus frequency value */ 261 clock = XENON_LOWEST_SDCLK_FREQ; 262 /* get the wait time */ 263 wait /= clock; 264 wait++; 265 /* wait for host eMMC PHY init completes */ 266 udelay(wait); 267 268 reg = sdhci_readl(host, phy_regs->timing_adj); 269 reg &= XENON_PHY_INITIALIZAION; 270 if (reg) { 271 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", 272 wait); 273 return -ETIMEDOUT; 274 } 275 276 return 0; 277 } 278 279 #define ARMADA_3700_SOC_PAD_1_8V 0x1 280 #define ARMADA_3700_SOC_PAD_3_3V 0x0 281 282 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host, 283 unsigned char signal_voltage) 284 { 285 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 286 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 287 struct xenon_emmc_phy_params *params = priv->phy_params; 288 289 if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) { 290 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); 291 } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) { 292 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) 293 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); 294 else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 295 writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); 296 } 297 } 298 299 /* 300 * Set SoC PHY voltage PAD control register, 301 * according to the operation voltage on PAD. 302 * The detailed operation depends on SoC implementation. 303 */ 304 static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host, 305 unsigned char signal_voltage) 306 { 307 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 308 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 309 struct xenon_emmc_phy_params *params = priv->phy_params; 310 311 if (!params->pad_ctrl.reg) 312 return; 313 314 if (params->pad_ctrl.set_soc_pad) 315 params->pad_ctrl.set_soc_pad(host, signal_voltage); 316 } 317 318 /* 319 * Enable eMMC PHY HW DLL 320 * DLL should be enabled and stable before HS200/SDR104 tuning, 321 * and before HS400 data strobe setting. 322 */ 323 static int xenon_emmc_phy_enable_dll(struct sdhci_host *host) 324 { 325 u32 reg; 326 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 327 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 328 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 329 ktime_t timeout; 330 331 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR)) 332 return -EINVAL; 333 334 reg = sdhci_readl(host, phy_regs->dll_ctrl); 335 if (reg & XENON_DLL_ENABLE) 336 return 0; 337 338 /* Enable DLL */ 339 reg = sdhci_readl(host, phy_regs->dll_ctrl); 340 reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK); 341 342 /* 343 * Set Phase as 90 degree, which is most common value. 344 * Might set another value if necessary. 345 * The granularity is 1 degree. 346 */ 347 reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) | 348 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT)); 349 reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) | 350 (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT)); 351 352 reg &= ~XENON_DLL_BYPASS_EN; 353 reg |= phy_regs->dll_update; 354 if (priv->phy_type == EMMC_5_1_PHY) 355 reg &= ~XENON_DLL_REFCLK_SEL; 356 sdhci_writel(host, reg, phy_regs->dll_ctrl); 357 358 /* Wait max 32 ms */ 359 timeout = ktime_add_ms(ktime_get(), 32); 360 while (1) { 361 bool timedout = ktime_after(ktime_get(), timeout); 362 363 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & 364 XENON_DLL_LOCK_STATE) 365 break; 366 if (timedout) { 367 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); 368 return -ETIMEDOUT; 369 } 370 udelay(100); 371 } 372 return 0; 373 } 374 375 /* 376 * Config to eMMC PHY to prepare for tuning. 377 * Enable HW DLL and set the TUNING_STEP 378 */ 379 static int xenon_emmc_phy_config_tuning(struct sdhci_host *host) 380 { 381 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 382 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 383 struct xenon_emmc_phy_params *params = priv->phy_params; 384 u32 reg, tuning_step; 385 int ret; 386 387 if (host->clock <= MMC_HIGH_52_MAX_DTR) 388 return -EINVAL; 389 390 ret = xenon_emmc_phy_enable_dll(host); 391 if (ret) 392 return ret; 393 394 /* Achieve TUNING_STEP with HW DLL help */ 395 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); 396 tuning_step = reg / params->tun_step_divider; 397 if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) { 398 dev_warn(mmc_dev(host->mmc), 399 "HS200 TUNING_STEP %d is larger than MAX value\n", 400 tuning_step); 401 tuning_step = XENON_TUNING_STEP_MASK; 402 } 403 404 /* Set TUNING_STEP for later tuning */ 405 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); 406 reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK << 407 XENON_TUN_CONSECUTIVE_TIMES_SHIFT); 408 reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT); 409 reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT); 410 reg |= (tuning_step << XENON_TUNING_STEP_SHIFT); 411 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); 412 413 return 0; 414 } 415 416 static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host) 417 { 418 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 419 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 420 u32 reg; 421 422 /* Disable both SDHC Data Strobe and Enhanced Strobe */ 423 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); 424 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); 425 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); 426 427 /* Clear Strobe line Pull down or Pull up */ 428 if (priv->phy_type == EMMC_5_0_PHY) { 429 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 430 reg &= ~(XENON_EMMC5_FC_QSP_PD | XENON_EMMC5_FC_QSP_PU); 431 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 432 } else { 433 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 434 reg &= ~(XENON_EMMC5_1_FC_QSP_PD | XENON_EMMC5_1_FC_QSP_PU); 435 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 436 } 437 } 438 439 /* Set HS400 Data Strobe and Enhanced Strobe */ 440 static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host) 441 { 442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 443 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 444 u32 reg; 445 446 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400)) 447 return; 448 449 if (host->clock <= MMC_HIGH_52_MAX_DTR) 450 return; 451 452 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); 453 454 xenon_emmc_phy_enable_dll(host); 455 456 /* Enable SDHC Data Strobe */ 457 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); 458 reg |= XENON_ENABLE_DATA_STROBE; 459 /* 460 * Enable SDHC Enhanced Strobe if supported 461 * Xenon Enhanced Strobe should be enabled only when 462 * 1. card is in HS400 mode and 463 * 2. SDCLK is higher than 52MHz 464 * 3. DLL is enabled 465 */ 466 if (host->mmc->ios.enhanced_strobe) 467 reg |= XENON_ENABLE_RESP_STROBE; 468 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); 469 470 /* Set Data Strobe Pull down */ 471 if (priv->phy_type == EMMC_5_0_PHY) { 472 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 473 reg |= XENON_EMMC5_FC_QSP_PD; 474 reg &= ~XENON_EMMC5_FC_QSP_PU; 475 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 476 } else { 477 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 478 reg |= XENON_EMMC5_1_FC_QSP_PD; 479 reg &= ~XENON_EMMC5_1_FC_QSP_PU; 480 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 481 } 482 } 483 484 /* 485 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz) 486 * in SDR mode, enable Slow Mode to bypass eMMC PHY. 487 * SDIO slower SDR mode also requires Slow Mode. 488 * 489 * If Slow Mode is enabled, return true. 490 * Otherwise, return false. 491 */ 492 static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host, 493 unsigned char timing) 494 { 495 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 496 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 497 struct xenon_emmc_phy_params *params = priv->phy_params; 498 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 499 u32 reg; 500 int ret; 501 502 if (host->clock > MMC_HIGH_52_MAX_DTR) 503 return false; 504 505 reg = sdhci_readl(host, phy_regs->timing_adj); 506 /* When in slower SDR mode, enable Slow Mode for SDIO 507 * or when Slow Mode flag is set 508 */ 509 switch (timing) { 510 case MMC_TIMING_LEGACY: 511 /* 512 * If Slow Mode is required, enable Slow Mode by default 513 * in early init phase to avoid any potential issue. 514 */ 515 if (params->slow_mode) { 516 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 517 ret = true; 518 } else { 519 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 520 ret = false; 521 } 522 break; 523 case MMC_TIMING_UHS_SDR25: 524 case MMC_TIMING_UHS_SDR12: 525 case MMC_TIMING_SD_HS: 526 case MMC_TIMING_MMC_HS: 527 if ((priv->init_card_type == MMC_TYPE_SDIO) || 528 params->slow_mode) { 529 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 530 ret = true; 531 break; 532 } 533 /* else: fall through */ 534 default: 535 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 536 ret = false; 537 } 538 539 sdhci_writel(host, reg, phy_regs->timing_adj); 540 return ret; 541 } 542 543 /* 544 * Set-up eMMC 5.0/5.1 PHY. 545 * Specific configuration depends on the current speed mode in use. 546 */ 547 static void xenon_emmc_phy_set(struct sdhci_host *host, 548 unsigned char timing) 549 { 550 u32 reg; 551 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 552 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 553 struct xenon_emmc_phy_params *params = priv->phy_params; 554 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 555 556 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n"); 557 558 /* Setup pad, set bit[28] and bits[26:24] */ 559 reg = sdhci_readl(host, phy_regs->pad_ctrl); 560 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 561 XENON_FC_QSP_RECEN | XENON_OEN_QSN); 562 /* All FC_XX_RECEIVCE should be set as CMOS Type */ 563 reg |= XENON_FC_ALL_CMOS_RECEIVER; 564 sdhci_writel(host, reg, phy_regs->pad_ctrl); 565 566 /* Set CMD and DQ Pull Up */ 567 if (priv->phy_type == EMMC_5_0_PHY) { 568 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 569 reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU); 570 reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD); 571 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 572 } else { 573 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 574 reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU); 575 reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD); 576 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 577 } 578 579 if (timing == MMC_TIMING_LEGACY) { 580 xenon_emmc_phy_slow_mode(host, timing); 581 goto phy_init; 582 } 583 584 /* 585 * If SDIO card, set SDIO Mode 586 * Otherwise, clear SDIO Mode 587 */ 588 reg = sdhci_readl(host, phy_regs->timing_adj); 589 if (priv->init_card_type == MMC_TYPE_SDIO) 590 reg |= XENON_TIMING_ADJUST_SDIO_MODE; 591 else 592 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 593 sdhci_writel(host, reg, phy_regs->timing_adj); 594 595 if (xenon_emmc_phy_slow_mode(host, timing)) 596 goto phy_init; 597 598 /* 599 * Set preferred ZNR and ZPR value 600 * The ZNR and ZPR value vary between different boards. 601 * Define them both in sdhci-xenon-emmc-phy.h. 602 */ 603 reg = sdhci_readl(host, phy_regs->pad_ctrl2); 604 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 605 reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr); 606 sdhci_writel(host, reg, phy_regs->pad_ctrl2); 607 608 /* 609 * When setting EMMC_PHY_FUNC_CONTROL register, 610 * SD clock should be disabled 611 */ 612 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 613 reg &= ~SDHCI_CLOCK_CARD_EN; 614 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 615 616 reg = sdhci_readl(host, phy_regs->func_ctrl); 617 switch (timing) { 618 case MMC_TIMING_MMC_HS400: 619 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 620 XENON_CMD_DDR_MODE; 621 reg &= ~XENON_DQ_ASYNC_MODE; 622 break; 623 case MMC_TIMING_UHS_DDR50: 624 case MMC_TIMING_MMC_DDR52: 625 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 626 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 627 break; 628 default: 629 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 630 XENON_CMD_DDR_MODE); 631 reg |= XENON_DQ_ASYNC_MODE; 632 } 633 sdhci_writel(host, reg, phy_regs->func_ctrl); 634 635 /* Enable bus clock */ 636 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 637 reg |= SDHCI_CLOCK_CARD_EN; 638 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 639 640 if (timing == MMC_TIMING_MMC_HS400) 641 /* Hardware team recommend a value for HS400 */ 642 sdhci_writel(host, phy_regs->logic_timing_val, 643 phy_regs->logic_timing_adj); 644 else 645 xenon_emmc_phy_disable_strobe(host); 646 647 phy_init: 648 xenon_emmc_phy_init(host); 649 650 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n"); 651 } 652 653 static int get_dt_pad_ctrl_data(struct sdhci_host *host, 654 struct device_node *np, 655 struct xenon_emmc_phy_params *params) 656 { 657 int ret = 0; 658 const char *name; 659 struct resource iomem; 660 661 if (of_device_is_compatible(np, "marvell,armada-3700-sdhci")) 662 params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set; 663 else 664 return 0; 665 666 if (of_address_to_resource(np, 1, &iomem)) { 667 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %pOFn\n", 668 np); 669 return -EINVAL; 670 } 671 672 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), 673 &iomem); 674 if (IS_ERR(params->pad_ctrl.reg)) 675 return PTR_ERR(params->pad_ctrl.reg); 676 677 ret = of_property_read_string(np, "marvell,pad-type", &name); 678 if (ret) { 679 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n"); 680 return ret; 681 } 682 if (!strcmp(name, "sd")) { 683 params->pad_ctrl.pad_type = SOC_PAD_SD; 684 } else if (!strcmp(name, "fixed-1-8v")) { 685 params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V; 686 } else { 687 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n", 688 name); 689 return -EINVAL; 690 } 691 692 return ret; 693 } 694 695 static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host, 696 struct device_node *np, 697 struct xenon_emmc_phy_params *params) 698 { 699 u32 value; 700 701 params->slow_mode = false; 702 if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode")) 703 params->slow_mode = true; 704 705 params->znr = XENON_ZNR_DEF_VALUE; 706 if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value)) 707 params->znr = value & XENON_ZNR_MASK; 708 709 params->zpr = XENON_ZPR_DEF_VALUE; 710 if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value)) 711 params->zpr = value & XENON_ZPR_MASK; 712 713 params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES; 714 if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun", 715 &value)) 716 params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK; 717 718 params->tun_step_divider = XENON_TUNING_STEP_DIVIDER; 719 if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider", 720 &value)) 721 params->tun_step_divider = value & 0xFF; 722 723 return get_dt_pad_ctrl_data(host, np, params); 724 } 725 726 /* Set SoC PHY Voltage PAD */ 727 void xenon_soc_pad_ctrl(struct sdhci_host *host, 728 unsigned char signal_voltage) 729 { 730 xenon_emmc_phy_set_soc_pad(host, signal_voltage); 731 } 732 733 /* 734 * Setting PHY when card is working in High Speed Mode. 735 * HS400 set Data Strobe and Enhanced Strobe if it is supported. 736 * HS200/SDR104 set tuning config to prepare for tuning. 737 */ 738 static int xenon_hs_delay_adj(struct sdhci_host *host) 739 { 740 int ret = 0; 741 742 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ)) 743 return -EINVAL; 744 745 switch (host->timing) { 746 case MMC_TIMING_MMC_HS400: 747 xenon_emmc_phy_strobe_delay_adj(host); 748 return 0; 749 case MMC_TIMING_MMC_HS200: 750 case MMC_TIMING_UHS_SDR104: 751 return xenon_emmc_phy_config_tuning(host); 752 case MMC_TIMING_MMC_DDR52: 753 case MMC_TIMING_UHS_DDR50: 754 /* 755 * DDR Mode requires driver to scan Sampling Fixed Delay Line, 756 * to find out a perfect operation sampling point. 757 * It is hard to implement such a scan in host driver 758 * since initiating commands by host driver is not safe. 759 * Thus so far just keep PHY Sampling Fixed Delay in 760 * default value of DDR mode. 761 * 762 * If any timing issue occurs in DDR mode on Marvell products, 763 * please contact maintainer for internal support in Marvell. 764 */ 765 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n"); 766 return 0; 767 } 768 769 return ret; 770 } 771 772 /* 773 * Adjust PHY setting. 774 * PHY setting should be adjusted when SDCLK frequency, Bus Width 775 * or Speed Mode is changed. 776 * Additional config are required when card is working in High Speed mode, 777 * after leaving Legacy Mode. 778 */ 779 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios) 780 { 781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 782 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 783 int ret = 0; 784 785 if (!host->clock) { 786 priv->clock = 0; 787 return 0; 788 } 789 790 /* 791 * The timing, frequency or bus width is changed, 792 * better to set eMMC PHY based on current setting 793 * and adjust Xenon SDHC delay. 794 */ 795 if ((host->clock == priv->clock) && 796 (ios->bus_width == priv->bus_width) && 797 (ios->timing == priv->timing)) 798 return 0; 799 800 xenon_emmc_phy_set(host, ios->timing); 801 802 /* Update the record */ 803 priv->bus_width = ios->bus_width; 804 805 priv->timing = ios->timing; 806 priv->clock = host->clock; 807 808 /* Legacy mode is a special case */ 809 if (ios->timing == MMC_TIMING_LEGACY) 810 return 0; 811 812 if (host->clock > XENON_DEFAULT_SDCLK_FREQ) 813 ret = xenon_hs_delay_adj(host); 814 return ret; 815 } 816 817 static int xenon_add_phy(struct device_node *np, struct sdhci_host *host, 818 const char *phy_name) 819 { 820 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 821 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 822 int ret; 823 824 priv->phy_type = match_string(phy_types, NR_PHY_TYPES, phy_name); 825 if (priv->phy_type < 0) { 826 dev_err(mmc_dev(host->mmc), 827 "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n", 828 phy_name); 829 priv->phy_type = EMMC_5_1_PHY; 830 } 831 832 ret = xenon_alloc_emmc_phy(host); 833 if (ret) 834 return ret; 835 836 return xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params); 837 } 838 839 int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host) 840 { 841 const char *phy_type = NULL; 842 843 if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type)) 844 return xenon_add_phy(np, host, phy_type); 845 846 return xenon_add_phy(np, host, "emmc 5.1 phy"); 847 } 848