106c8b667SHu Ziji /* 206c8b667SHu Ziji * PHY support for Xenon SDHC 306c8b667SHu Ziji * 406c8b667SHu Ziji * Copyright (C) 2016 Marvell, All Rights Reserved. 506c8b667SHu Ziji * 606c8b667SHu Ziji * Author: Hu Ziji <huziji@marvell.com> 706c8b667SHu Ziji * Date: 2016-8-24 806c8b667SHu Ziji * 906c8b667SHu Ziji * This program is free software; you can redistribute it and/or 1006c8b667SHu Ziji * modify it under the terms of the GNU General Public License as 1106c8b667SHu Ziji * published by the Free Software Foundation version 2. 1206c8b667SHu Ziji */ 1306c8b667SHu Ziji 1406c8b667SHu Ziji #include <linux/slab.h> 1506c8b667SHu Ziji #include <linux/delay.h> 1606c8b667SHu Ziji #include <linux/ktime.h> 1706c8b667SHu Ziji #include <linux/of_address.h> 1806c8b667SHu Ziji 1906c8b667SHu Ziji #include "sdhci-pltfm.h" 2006c8b667SHu Ziji #include "sdhci-xenon.h" 2106c8b667SHu Ziji 2206c8b667SHu Ziji /* Register base for eMMC PHY 5.0 Version */ 2306c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_REG_BASE 0x0160 2406c8b667SHu Ziji /* Register base for eMMC PHY 5.1 Version */ 2506c8b667SHu Ziji #define XENON_EMMC_PHY_REG_BASE 0x0170 2606c8b667SHu Ziji 2706c8b667SHu Ziji #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE 2806c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE 2906c8b667SHu Ziji #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29) 3006c8b667SHu Ziji #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28) 3106c8b667SHu Ziji #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18) 3206c8b667SHu Ziji #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 3306c8b667SHu Ziji #define XENON_PHY_INITIALIZAION BIT(31) 3406c8b667SHu Ziji #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF 3506c8b667SHu Ziji #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12 3606c8b667SHu Ziji #define XENON_FC_SYNC_EN_DURATION_MASK 0xF 3706c8b667SHu Ziji #define XENON_FC_SYNC_EN_DURATION_SHIFT 8 3806c8b667SHu Ziji #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF 3906c8b667SHu Ziji #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4 4006c8b667SHu Ziji #define XENON_FC_SYNC_RST_DURATION_MASK 0xF 4106c8b667SHu Ziji #define XENON_FC_SYNC_RST_DURATION_SHIFT 0 4206c8b667SHu Ziji 4306c8b667SHu Ziji #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4) 4406c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_FUNC_CONTROL \ 4506c8b667SHu Ziji (XENON_EMMC_5_0_PHY_REG_BASE + 0x4) 4606c8b667SHu Ziji #define XENON_ASYNC_DDRMODE_MASK BIT(23) 4706c8b667SHu Ziji #define XENON_ASYNC_DDRMODE_SHIFT 23 4806c8b667SHu Ziji #define XENON_CMD_DDR_MODE BIT(16) 4906c8b667SHu Ziji #define XENON_DQ_DDR_MODE_SHIFT 8 5006c8b667SHu Ziji #define XENON_DQ_DDR_MODE_MASK 0xFF 5106c8b667SHu Ziji #define XENON_DQ_ASYNC_MODE BIT(4) 5206c8b667SHu Ziji 5306c8b667SHu Ziji #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8) 5406c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_PAD_CONTROL \ 5506c8b667SHu Ziji (XENON_EMMC_5_0_PHY_REG_BASE + 0x8) 5606c8b667SHu Ziji #define XENON_REC_EN_SHIFT 24 5706c8b667SHu Ziji #define XENON_REC_EN_MASK 0xF 5806c8b667SHu Ziji #define XENON_FC_DQ_RECEN BIT(24) 5906c8b667SHu Ziji #define XENON_FC_CMD_RECEN BIT(25) 6006c8b667SHu Ziji #define XENON_FC_QSP_RECEN BIT(26) 6106c8b667SHu Ziji #define XENON_FC_QSN_RECEN BIT(27) 6206c8b667SHu Ziji #define XENON_OEN_QSN BIT(28) 6306c8b667SHu Ziji #define XENON_AUTO_RECEN_CTRL BIT(30) 6406c8b667SHu Ziji #define XENON_FC_ALL_CMOS_RECEIVER 0xF000 6506c8b667SHu Ziji 6606c8b667SHu Ziji #define XENON_EMMC5_FC_QSP_PD BIT(18) 6706c8b667SHu Ziji #define XENON_EMMC5_FC_QSP_PU BIT(22) 6806c8b667SHu Ziji #define XENON_EMMC5_FC_CMD_PD BIT(17) 6906c8b667SHu Ziji #define XENON_EMMC5_FC_CMD_PU BIT(21) 7006c8b667SHu Ziji #define XENON_EMMC5_FC_DQ_PD BIT(16) 7106c8b667SHu Ziji #define XENON_EMMC5_FC_DQ_PU BIT(20) 7206c8b667SHu Ziji 7306c8b667SHu Ziji #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC) 7406c8b667SHu Ziji #define XENON_EMMC5_1_FC_QSP_PD BIT(9) 7506c8b667SHu Ziji #define XENON_EMMC5_1_FC_QSP_PU BIT(25) 7606c8b667SHu Ziji #define XENON_EMMC5_1_FC_CMD_PD BIT(8) 7706c8b667SHu Ziji #define XENON_EMMC5_1_FC_CMD_PU BIT(24) 7806c8b667SHu Ziji #define XENON_EMMC5_1_FC_DQ_PD 0xFF 7906c8b667SHu Ziji #define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16) 8006c8b667SHu Ziji 8106c8b667SHu Ziji #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10) 8206c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \ 8306c8b667SHu Ziji (XENON_EMMC_5_0_PHY_REG_BASE + 0xC) 8406c8b667SHu Ziji #define XENON_ZNR_MASK 0x1F 8506c8b667SHu Ziji #define XENON_ZNR_SHIFT 8 8606c8b667SHu Ziji #define XENON_ZPR_MASK 0x1F 8706c8b667SHu Ziji /* Preferred ZNR and ZPR value vary between different boards. 8806c8b667SHu Ziji * The specific ZNR and ZPR value should be defined here 8906c8b667SHu Ziji * according to board actual timing. 9006c8b667SHu Ziji */ 9106c8b667SHu Ziji #define XENON_ZNR_DEF_VALUE 0xF 9206c8b667SHu Ziji #define XENON_ZPR_DEF_VALUE 0xF 9306c8b667SHu Ziji 9406c8b667SHu Ziji #define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14) 9506c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_DLL_CONTROL \ 9606c8b667SHu Ziji (XENON_EMMC_5_0_PHY_REG_BASE + 0x10) 9706c8b667SHu Ziji #define XENON_DLL_ENABLE BIT(31) 9806c8b667SHu Ziji #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30) 9906c8b667SHu Ziji #define XENON_DLL_REFCLK_SEL BIT(30) 10006c8b667SHu Ziji #define XENON_DLL_UPDATE BIT(23) 10106c8b667SHu Ziji #define XENON_DLL_PHSEL1_SHIFT 24 10206c8b667SHu Ziji #define XENON_DLL_PHSEL0_SHIFT 16 10306c8b667SHu Ziji #define XENON_DLL_PHASE_MASK 0x3F 10406c8b667SHu Ziji #define XENON_DLL_PHASE_90_DEGREE 0x1F 10506c8b667SHu Ziji #define XENON_DLL_FAST_LOCK BIT(5) 10606c8b667SHu Ziji #define XENON_DLL_GAIN2X BIT(3) 10706c8b667SHu Ziji #define XENON_DLL_BYPASS_EN BIT(0) 10806c8b667SHu Ziji 10906c8b667SHu Ziji #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \ 11006c8b667SHu Ziji (XENON_EMMC_5_0_PHY_REG_BASE + 0x14) 111a04b9b47SHu Ziji #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54 11206c8b667SHu Ziji #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) 11306c8b667SHu Ziji #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 11406c8b667SHu Ziji 11506c8b667SHu Ziji /* 11606c8b667SHu Ziji * List offset of PHY registers and some special register values 11706c8b667SHu Ziji * in eMMC PHY 5.0 or eMMC PHY 5.1 11806c8b667SHu Ziji */ 11906c8b667SHu Ziji struct xenon_emmc_phy_regs { 12006c8b667SHu Ziji /* Offset of Timing Adjust register */ 12106c8b667SHu Ziji u16 timing_adj; 12206c8b667SHu Ziji /* Offset of Func Control register */ 12306c8b667SHu Ziji u16 func_ctrl; 12406c8b667SHu Ziji /* Offset of Pad Control register */ 12506c8b667SHu Ziji u16 pad_ctrl; 12606c8b667SHu Ziji /* Offset of Pad Control register 2 */ 12706c8b667SHu Ziji u16 pad_ctrl2; 12806c8b667SHu Ziji /* Offset of DLL Control register */ 12906c8b667SHu Ziji u16 dll_ctrl; 13006c8b667SHu Ziji /* Offset of Logic Timing Adjust register */ 13106c8b667SHu Ziji u16 logic_timing_adj; 13206c8b667SHu Ziji /* DLL Update Enable bit */ 13306c8b667SHu Ziji u32 dll_update; 134a04b9b47SHu Ziji /* value in Logic Timing Adjustment register */ 135a04b9b47SHu Ziji u32 logic_timing_val; 13606c8b667SHu Ziji }; 13706c8b667SHu Ziji 13806c8b667SHu Ziji static const char * const phy_types[] = { 13906c8b667SHu Ziji "emmc 5.0 phy", 14006c8b667SHu Ziji "emmc 5.1 phy" 14106c8b667SHu Ziji }; 14206c8b667SHu Ziji 14306c8b667SHu Ziji enum xenon_phy_type_enum { 14406c8b667SHu Ziji EMMC_5_0_PHY, 14506c8b667SHu Ziji EMMC_5_1_PHY, 14606c8b667SHu Ziji NR_PHY_TYPES 14706c8b667SHu Ziji }; 14806c8b667SHu Ziji 149298269c6SHu Ziji enum soc_pad_ctrl_type { 150298269c6SHu Ziji SOC_PAD_SD, 151298269c6SHu Ziji SOC_PAD_FIXED_1_8V, 152298269c6SHu Ziji }; 153298269c6SHu Ziji 154298269c6SHu Ziji struct soc_pad_ctrl { 155298269c6SHu Ziji /* Register address of SoC PHY PAD ctrl */ 156298269c6SHu Ziji void __iomem *reg; 157298269c6SHu Ziji /* SoC PHY PAD ctrl type */ 158298269c6SHu Ziji enum soc_pad_ctrl_type pad_type; 159298269c6SHu Ziji /* SoC specific operation to set SoC PHY PAD */ 160298269c6SHu Ziji void (*set_soc_pad)(struct sdhci_host *host, 161298269c6SHu Ziji unsigned char signal_voltage); 162298269c6SHu Ziji }; 163298269c6SHu Ziji 16406c8b667SHu Ziji static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = { 16506c8b667SHu Ziji .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST, 16606c8b667SHu Ziji .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL, 16706c8b667SHu Ziji .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL, 16806c8b667SHu Ziji .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2, 16906c8b667SHu Ziji .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL, 17006c8b667SHu Ziji .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST, 17106c8b667SHu Ziji .dll_update = XENON_DLL_UPDATE_STROBE_5_0, 172a04b9b47SHu Ziji .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE, 17306c8b667SHu Ziji }; 17406c8b667SHu Ziji 17506c8b667SHu Ziji static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = { 17606c8b667SHu Ziji .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST, 17706c8b667SHu Ziji .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL, 17806c8b667SHu Ziji .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL, 17906c8b667SHu Ziji .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2, 18006c8b667SHu Ziji .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL, 18106c8b667SHu Ziji .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 18206c8b667SHu Ziji .dll_update = XENON_DLL_UPDATE, 183a04b9b47SHu Ziji .logic_timing_val = XENON_LOGIC_TIMING_VALUE, 18406c8b667SHu Ziji }; 18506c8b667SHu Ziji 18606c8b667SHu Ziji /* 18706c8b667SHu Ziji * eMMC PHY configuration and operations 18806c8b667SHu Ziji */ 18906c8b667SHu Ziji struct xenon_emmc_phy_params { 19006c8b667SHu Ziji bool slow_mode; 19106c8b667SHu Ziji 19206c8b667SHu Ziji u8 znr; 19306c8b667SHu Ziji u8 zpr; 19406c8b667SHu Ziji 19506c8b667SHu Ziji /* Nr of consecutive Sampling Points of a Valid Sampling Window */ 19606c8b667SHu Ziji u8 nr_tun_times; 19706c8b667SHu Ziji /* Divider for calculating Tuning Step */ 19806c8b667SHu Ziji u8 tun_step_divider; 199298269c6SHu Ziji 200298269c6SHu Ziji struct soc_pad_ctrl pad_ctrl; 20106c8b667SHu Ziji }; 20206c8b667SHu Ziji 20306c8b667SHu Ziji static int xenon_alloc_emmc_phy(struct sdhci_host *host) 20406c8b667SHu Ziji { 20506c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 20606c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 20706c8b667SHu Ziji struct xenon_emmc_phy_params *params; 20806c8b667SHu Ziji 20906c8b667SHu Ziji params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); 21006c8b667SHu Ziji if (!params) 21106c8b667SHu Ziji return -ENOMEM; 21206c8b667SHu Ziji 21306c8b667SHu Ziji priv->phy_params = params; 21406c8b667SHu Ziji if (priv->phy_type == EMMC_5_0_PHY) 21506c8b667SHu Ziji priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; 21606c8b667SHu Ziji else 21706c8b667SHu Ziji priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs; 21806c8b667SHu Ziji 21906c8b667SHu Ziji return 0; 22006c8b667SHu Ziji } 22106c8b667SHu Ziji 22206c8b667SHu Ziji /* 22306c8b667SHu Ziji * eMMC 5.0/5.1 PHY init/re-init. 22406c8b667SHu Ziji * eMMC PHY init should be executed after: 22506c8b667SHu Ziji * 1. SDCLK frequency changes. 22606c8b667SHu Ziji * 2. SDCLK is stopped and re-enabled. 22706c8b667SHu Ziji * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl 22806c8b667SHu Ziji * are changed 22906c8b667SHu Ziji */ 23006c8b667SHu Ziji static int xenon_emmc_phy_init(struct sdhci_host *host) 23106c8b667SHu Ziji { 23206c8b667SHu Ziji u32 reg; 23306c8b667SHu Ziji u32 wait, clock; 23406c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 23506c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 23606c8b667SHu Ziji struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 23706c8b667SHu Ziji 23806c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->timing_adj); 23906c8b667SHu Ziji reg |= XENON_PHY_INITIALIZAION; 24006c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->timing_adj); 24106c8b667SHu Ziji 24206c8b667SHu Ziji /* Add duration of FC_SYNC_RST */ 24306c8b667SHu Ziji wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) & 24406c8b667SHu Ziji XENON_FC_SYNC_RST_DURATION_MASK); 24506c8b667SHu Ziji /* Add interval between FC_SYNC_EN and FC_SYNC_RST */ 24606c8b667SHu Ziji wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) & 24706c8b667SHu Ziji XENON_FC_SYNC_RST_EN_DURATION_MASK); 24806c8b667SHu Ziji /* Add duration of asserting FC_SYNC_EN */ 24906c8b667SHu Ziji wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) & 25006c8b667SHu Ziji XENON_FC_SYNC_EN_DURATION_MASK); 25106c8b667SHu Ziji /* Add duration of waiting for PHY */ 25206c8b667SHu Ziji wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) & 25306c8b667SHu Ziji XENON_WAIT_CYCLE_BEFORE_USING_MASK); 25406c8b667SHu Ziji /* 4 additional bus clock and 4 AXI bus clock are required */ 25506c8b667SHu Ziji wait += 8; 25606c8b667SHu Ziji wait <<= 20; 25706c8b667SHu Ziji 25806c8b667SHu Ziji clock = host->clock; 25906c8b667SHu Ziji if (!clock) 26006c8b667SHu Ziji /* Use the possibly slowest bus frequency value */ 26106c8b667SHu Ziji clock = XENON_LOWEST_SDCLK_FREQ; 26206c8b667SHu Ziji /* get the wait time */ 26306c8b667SHu Ziji wait /= clock; 26406c8b667SHu Ziji wait++; 26506c8b667SHu Ziji /* wait for host eMMC PHY init completes */ 26606c8b667SHu Ziji udelay(wait); 26706c8b667SHu Ziji 26806c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->timing_adj); 26906c8b667SHu Ziji reg &= XENON_PHY_INITIALIZAION; 27006c8b667SHu Ziji if (reg) { 27106c8b667SHu Ziji dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", 27206c8b667SHu Ziji wait); 27306c8b667SHu Ziji return -ETIMEDOUT; 27406c8b667SHu Ziji } 27506c8b667SHu Ziji 27606c8b667SHu Ziji return 0; 27706c8b667SHu Ziji } 27806c8b667SHu Ziji 279298269c6SHu Ziji #define ARMADA_3700_SOC_PAD_1_8V 0x1 280298269c6SHu Ziji #define ARMADA_3700_SOC_PAD_3_3V 0x0 281298269c6SHu Ziji 282298269c6SHu Ziji static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host, 283298269c6SHu Ziji unsigned char signal_voltage) 284298269c6SHu Ziji { 285298269c6SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 286298269c6SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 287298269c6SHu Ziji struct xenon_emmc_phy_params *params = priv->phy_params; 288298269c6SHu Ziji 289298269c6SHu Ziji if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) { 290298269c6SHu Ziji writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); 291298269c6SHu Ziji } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) { 292298269c6SHu Ziji if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) 293298269c6SHu Ziji writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); 294298269c6SHu Ziji else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 295298269c6SHu Ziji writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); 296298269c6SHu Ziji } 297298269c6SHu Ziji } 298298269c6SHu Ziji 299298269c6SHu Ziji /* 300298269c6SHu Ziji * Set SoC PHY voltage PAD control register, 301298269c6SHu Ziji * according to the operation voltage on PAD. 302298269c6SHu Ziji * The detailed operation depends on SoC implementation. 303298269c6SHu Ziji */ 304298269c6SHu Ziji static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host, 305298269c6SHu Ziji unsigned char signal_voltage) 306298269c6SHu Ziji { 307298269c6SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 308298269c6SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 309298269c6SHu Ziji struct xenon_emmc_phy_params *params = priv->phy_params; 310298269c6SHu Ziji 311298269c6SHu Ziji if (!params->pad_ctrl.reg) 312298269c6SHu Ziji return; 313298269c6SHu Ziji 314298269c6SHu Ziji if (params->pad_ctrl.set_soc_pad) 315298269c6SHu Ziji params->pad_ctrl.set_soc_pad(host, signal_voltage); 316298269c6SHu Ziji } 317298269c6SHu Ziji 31806c8b667SHu Ziji /* 31906c8b667SHu Ziji * Enable eMMC PHY HW DLL 32006c8b667SHu Ziji * DLL should be enabled and stable before HS200/SDR104 tuning, 32106c8b667SHu Ziji * and before HS400 data strobe setting. 32206c8b667SHu Ziji */ 32306c8b667SHu Ziji static int xenon_emmc_phy_enable_dll(struct sdhci_host *host) 32406c8b667SHu Ziji { 32506c8b667SHu Ziji u32 reg; 32606c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 32706c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 32806c8b667SHu Ziji struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 32906c8b667SHu Ziji ktime_t timeout; 33006c8b667SHu Ziji 33106c8b667SHu Ziji if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR)) 33206c8b667SHu Ziji return -EINVAL; 33306c8b667SHu Ziji 33406c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->dll_ctrl); 33506c8b667SHu Ziji if (reg & XENON_DLL_ENABLE) 33606c8b667SHu Ziji return 0; 33706c8b667SHu Ziji 33806c8b667SHu Ziji /* Enable DLL */ 33906c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->dll_ctrl); 34006c8b667SHu Ziji reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK); 34106c8b667SHu Ziji 34206c8b667SHu Ziji /* 34306c8b667SHu Ziji * Set Phase as 90 degree, which is most common value. 34406c8b667SHu Ziji * Might set another value if necessary. 34506c8b667SHu Ziji * The granularity is 1 degree. 34606c8b667SHu Ziji */ 34706c8b667SHu Ziji reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) | 34806c8b667SHu Ziji (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT)); 34906c8b667SHu Ziji reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) | 35006c8b667SHu Ziji (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT)); 35106c8b667SHu Ziji 35206c8b667SHu Ziji reg &= ~XENON_DLL_BYPASS_EN; 35306c8b667SHu Ziji reg |= phy_regs->dll_update; 35406c8b667SHu Ziji if (priv->phy_type == EMMC_5_1_PHY) 35506c8b667SHu Ziji reg &= ~XENON_DLL_REFCLK_SEL; 35606c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->dll_ctrl); 35706c8b667SHu Ziji 35806c8b667SHu Ziji /* Wait max 32 ms */ 35906c8b667SHu Ziji timeout = ktime_add_ms(ktime_get(), 32); 36006c8b667SHu Ziji while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & 36106c8b667SHu Ziji XENON_DLL_LOCK_STATE)) { 36206c8b667SHu Ziji if (ktime_after(ktime_get(), timeout)) { 36306c8b667SHu Ziji dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); 36406c8b667SHu Ziji return -ETIMEDOUT; 36506c8b667SHu Ziji } 36606c8b667SHu Ziji udelay(100); 36706c8b667SHu Ziji } 36806c8b667SHu Ziji return 0; 36906c8b667SHu Ziji } 37006c8b667SHu Ziji 37106c8b667SHu Ziji /* 37206c8b667SHu Ziji * Config to eMMC PHY to prepare for tuning. 37306c8b667SHu Ziji * Enable HW DLL and set the TUNING_STEP 37406c8b667SHu Ziji */ 37506c8b667SHu Ziji static int xenon_emmc_phy_config_tuning(struct sdhci_host *host) 37606c8b667SHu Ziji { 37706c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 37806c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 37906c8b667SHu Ziji struct xenon_emmc_phy_params *params = priv->phy_params; 38006c8b667SHu Ziji u32 reg, tuning_step; 38106c8b667SHu Ziji int ret; 38206c8b667SHu Ziji 38306c8b667SHu Ziji if (host->clock <= MMC_HIGH_52_MAX_DTR) 38406c8b667SHu Ziji return -EINVAL; 38506c8b667SHu Ziji 38606c8b667SHu Ziji ret = xenon_emmc_phy_enable_dll(host); 38706c8b667SHu Ziji if (ret) 38806c8b667SHu Ziji return ret; 38906c8b667SHu Ziji 39006c8b667SHu Ziji /* Achieve TUNING_STEP with HW DLL help */ 39106c8b667SHu Ziji reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); 39206c8b667SHu Ziji tuning_step = reg / params->tun_step_divider; 39306c8b667SHu Ziji if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) { 39406c8b667SHu Ziji dev_warn(mmc_dev(host->mmc), 39506c8b667SHu Ziji "HS200 TUNING_STEP %d is larger than MAX value\n", 39606c8b667SHu Ziji tuning_step); 39706c8b667SHu Ziji tuning_step = XENON_TUNING_STEP_MASK; 39806c8b667SHu Ziji } 39906c8b667SHu Ziji 40006c8b667SHu Ziji /* Set TUNING_STEP for later tuning */ 40106c8b667SHu Ziji reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); 40206c8b667SHu Ziji reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK << 40306c8b667SHu Ziji XENON_TUN_CONSECUTIVE_TIMES_SHIFT); 40406c8b667SHu Ziji reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT); 40506c8b667SHu Ziji reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT); 40606c8b667SHu Ziji reg |= (tuning_step << XENON_TUNING_STEP_SHIFT); 40706c8b667SHu Ziji sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); 40806c8b667SHu Ziji 40906c8b667SHu Ziji return 0; 41006c8b667SHu Ziji } 41106c8b667SHu Ziji 41206c8b667SHu Ziji static void xenon_emmc_phy_disable_data_strobe(struct sdhci_host *host) 41306c8b667SHu Ziji { 41406c8b667SHu Ziji u32 reg; 41506c8b667SHu Ziji 41606c8b667SHu Ziji /* Disable SDHC Data Strobe */ 41706c8b667SHu Ziji reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); 41806c8b667SHu Ziji reg &= ~XENON_ENABLE_DATA_STROBE; 41906c8b667SHu Ziji sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); 42006c8b667SHu Ziji } 42106c8b667SHu Ziji 42206c8b667SHu Ziji /* Set HS400 Data Strobe */ 42306c8b667SHu Ziji static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host) 42406c8b667SHu Ziji { 42506c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 42606c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 42706c8b667SHu Ziji u32 reg; 42806c8b667SHu Ziji 42906c8b667SHu Ziji if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400)) 43006c8b667SHu Ziji return; 43106c8b667SHu Ziji 43206c8b667SHu Ziji if (host->clock <= MMC_HIGH_52_MAX_DTR) 43306c8b667SHu Ziji return; 43406c8b667SHu Ziji 43506c8b667SHu Ziji dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); 43606c8b667SHu Ziji 43706c8b667SHu Ziji xenon_emmc_phy_enable_dll(host); 43806c8b667SHu Ziji 43906c8b667SHu Ziji /* Enable SDHC Data Strobe */ 44006c8b667SHu Ziji reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); 44106c8b667SHu Ziji reg |= XENON_ENABLE_DATA_STROBE; 44206c8b667SHu Ziji sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); 44306c8b667SHu Ziji 44406c8b667SHu Ziji /* Set Data Strobe Pull down */ 44506c8b667SHu Ziji if (priv->phy_type == EMMC_5_0_PHY) { 44606c8b667SHu Ziji reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 44706c8b667SHu Ziji reg |= XENON_EMMC5_FC_QSP_PD; 44806c8b667SHu Ziji reg &= ~XENON_EMMC5_FC_QSP_PU; 44906c8b667SHu Ziji sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 45006c8b667SHu Ziji } else { 45106c8b667SHu Ziji reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 45206c8b667SHu Ziji reg |= XENON_EMMC5_1_FC_QSP_PD; 45306c8b667SHu Ziji reg &= ~XENON_EMMC5_1_FC_QSP_PU; 45406c8b667SHu Ziji sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 45506c8b667SHu Ziji } 45606c8b667SHu Ziji } 45706c8b667SHu Ziji 45806c8b667SHu Ziji /* 45906c8b667SHu Ziji * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz) 46006c8b667SHu Ziji * in SDR mode, enable Slow Mode to bypass eMMC PHY. 46106c8b667SHu Ziji * SDIO slower SDR mode also requires Slow Mode. 46206c8b667SHu Ziji * 46306c8b667SHu Ziji * If Slow Mode is enabled, return true. 46406c8b667SHu Ziji * Otherwise, return false. 46506c8b667SHu Ziji */ 46606c8b667SHu Ziji static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host, 46706c8b667SHu Ziji unsigned char timing) 46806c8b667SHu Ziji { 46906c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 47006c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 47106c8b667SHu Ziji struct xenon_emmc_phy_params *params = priv->phy_params; 47206c8b667SHu Ziji struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 47306c8b667SHu Ziji u32 reg; 47406c8b667SHu Ziji int ret; 47506c8b667SHu Ziji 47606c8b667SHu Ziji if (host->clock > MMC_HIGH_52_MAX_DTR) 47706c8b667SHu Ziji return false; 47806c8b667SHu Ziji 47906c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->timing_adj); 48006c8b667SHu Ziji /* When in slower SDR mode, enable Slow Mode for SDIO 48106c8b667SHu Ziji * or when Slow Mode flag is set 48206c8b667SHu Ziji */ 48306c8b667SHu Ziji switch (timing) { 48406c8b667SHu Ziji case MMC_TIMING_LEGACY: 48506c8b667SHu Ziji /* 48606c8b667SHu Ziji * If Slow Mode is required, enable Slow Mode by default 48706c8b667SHu Ziji * in early init phase to avoid any potential issue. 48806c8b667SHu Ziji */ 48906c8b667SHu Ziji if (params->slow_mode) { 49006c8b667SHu Ziji reg |= XENON_TIMING_ADJUST_SLOW_MODE; 49106c8b667SHu Ziji ret = true; 49206c8b667SHu Ziji } else { 49306c8b667SHu Ziji reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 49406c8b667SHu Ziji ret = false; 49506c8b667SHu Ziji } 49606c8b667SHu Ziji break; 49706c8b667SHu Ziji case MMC_TIMING_UHS_SDR25: 49806c8b667SHu Ziji case MMC_TIMING_UHS_SDR12: 49906c8b667SHu Ziji case MMC_TIMING_SD_HS: 50006c8b667SHu Ziji case MMC_TIMING_MMC_HS: 50106c8b667SHu Ziji if ((priv->init_card_type == MMC_TYPE_SDIO) || 50206c8b667SHu Ziji params->slow_mode) { 50306c8b667SHu Ziji reg |= XENON_TIMING_ADJUST_SLOW_MODE; 50406c8b667SHu Ziji ret = true; 50506c8b667SHu Ziji break; 50606c8b667SHu Ziji } 50706c8b667SHu Ziji default: 50806c8b667SHu Ziji reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 50906c8b667SHu Ziji ret = false; 51006c8b667SHu Ziji } 51106c8b667SHu Ziji 51206c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->timing_adj); 51306c8b667SHu Ziji return ret; 51406c8b667SHu Ziji } 51506c8b667SHu Ziji 51606c8b667SHu Ziji /* 51706c8b667SHu Ziji * Set-up eMMC 5.0/5.1 PHY. 51806c8b667SHu Ziji * Specific configuration depends on the current speed mode in use. 51906c8b667SHu Ziji */ 52006c8b667SHu Ziji static void xenon_emmc_phy_set(struct sdhci_host *host, 52106c8b667SHu Ziji unsigned char timing) 52206c8b667SHu Ziji { 52306c8b667SHu Ziji u32 reg; 52406c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 52506c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 52606c8b667SHu Ziji struct xenon_emmc_phy_params *params = priv->phy_params; 52706c8b667SHu Ziji struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 52806c8b667SHu Ziji 52906c8b667SHu Ziji dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n"); 53006c8b667SHu Ziji 53106c8b667SHu Ziji /* Setup pad, set bit[28] and bits[26:24] */ 53206c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->pad_ctrl); 53306c8b667SHu Ziji reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 53406c8b667SHu Ziji XENON_FC_QSP_RECEN | XENON_OEN_QSN); 53506c8b667SHu Ziji /* All FC_XX_RECEIVCE should be set as CMOS Type */ 53606c8b667SHu Ziji reg |= XENON_FC_ALL_CMOS_RECEIVER; 53706c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->pad_ctrl); 53806c8b667SHu Ziji 53906c8b667SHu Ziji /* Set CMD and DQ Pull Up */ 54006c8b667SHu Ziji if (priv->phy_type == EMMC_5_0_PHY) { 54106c8b667SHu Ziji reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 54206c8b667SHu Ziji reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU); 54306c8b667SHu Ziji reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD); 54406c8b667SHu Ziji sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 54506c8b667SHu Ziji } else { 54606c8b667SHu Ziji reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 54706c8b667SHu Ziji reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU); 54806c8b667SHu Ziji reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD); 54906c8b667SHu Ziji sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 55006c8b667SHu Ziji } 55106c8b667SHu Ziji 55206c8b667SHu Ziji if (timing == MMC_TIMING_LEGACY) { 55306c8b667SHu Ziji xenon_emmc_phy_slow_mode(host, timing); 55406c8b667SHu Ziji goto phy_init; 55506c8b667SHu Ziji } 55606c8b667SHu Ziji 55706c8b667SHu Ziji /* 55806c8b667SHu Ziji * If SDIO card, set SDIO Mode 55906c8b667SHu Ziji * Otherwise, clear SDIO Mode 56006c8b667SHu Ziji */ 56106c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->timing_adj); 56206c8b667SHu Ziji if (priv->init_card_type == MMC_TYPE_SDIO) 56306c8b667SHu Ziji reg |= XENON_TIMING_ADJUST_SDIO_MODE; 56406c8b667SHu Ziji else 56506c8b667SHu Ziji reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 56606c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->timing_adj); 56706c8b667SHu Ziji 56806c8b667SHu Ziji if (xenon_emmc_phy_slow_mode(host, timing)) 56906c8b667SHu Ziji goto phy_init; 57006c8b667SHu Ziji 57106c8b667SHu Ziji /* 57206c8b667SHu Ziji * Set preferred ZNR and ZPR value 57306c8b667SHu Ziji * The ZNR and ZPR value vary between different boards. 57406c8b667SHu Ziji * Define them both in sdhci-xenon-emmc-phy.h. 57506c8b667SHu Ziji */ 57606c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->pad_ctrl2); 57706c8b667SHu Ziji reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 57806c8b667SHu Ziji reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr); 57906c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->pad_ctrl2); 58006c8b667SHu Ziji 58106c8b667SHu Ziji /* 58206c8b667SHu Ziji * When setting EMMC_PHY_FUNC_CONTROL register, 58306c8b667SHu Ziji * SD clock should be disabled 58406c8b667SHu Ziji */ 58506c8b667SHu Ziji reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 58606c8b667SHu Ziji reg &= ~SDHCI_CLOCK_CARD_EN; 58706c8b667SHu Ziji sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 58806c8b667SHu Ziji 58906c8b667SHu Ziji reg = sdhci_readl(host, phy_regs->func_ctrl); 59006c8b667SHu Ziji switch (timing) { 59106c8b667SHu Ziji case MMC_TIMING_MMC_HS400: 59206c8b667SHu Ziji reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 59306c8b667SHu Ziji XENON_CMD_DDR_MODE; 59406c8b667SHu Ziji reg &= ~XENON_DQ_ASYNC_MODE; 59506c8b667SHu Ziji break; 59606c8b667SHu Ziji case MMC_TIMING_UHS_DDR50: 59706c8b667SHu Ziji case MMC_TIMING_MMC_DDR52: 59806c8b667SHu Ziji reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 59906c8b667SHu Ziji XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 60006c8b667SHu Ziji break; 60106c8b667SHu Ziji default: 60206c8b667SHu Ziji reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 60306c8b667SHu Ziji XENON_CMD_DDR_MODE); 60406c8b667SHu Ziji reg |= XENON_DQ_ASYNC_MODE; 60506c8b667SHu Ziji } 60606c8b667SHu Ziji sdhci_writel(host, reg, phy_regs->func_ctrl); 60706c8b667SHu Ziji 60806c8b667SHu Ziji /* Enable bus clock */ 60906c8b667SHu Ziji reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 61006c8b667SHu Ziji reg |= SDHCI_CLOCK_CARD_EN; 61106c8b667SHu Ziji sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 61206c8b667SHu Ziji 61306c8b667SHu Ziji if (timing == MMC_TIMING_MMC_HS400) 61406c8b667SHu Ziji /* Hardware team recommend a value for HS400 */ 615a04b9b47SHu Ziji sdhci_writel(host, phy_regs->logic_timing_val, 61606c8b667SHu Ziji phy_regs->logic_timing_adj); 61706c8b667SHu Ziji else 61806c8b667SHu Ziji xenon_emmc_phy_disable_data_strobe(host); 61906c8b667SHu Ziji 62006c8b667SHu Ziji phy_init: 62106c8b667SHu Ziji xenon_emmc_phy_init(host); 62206c8b667SHu Ziji 62306c8b667SHu Ziji dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n"); 62406c8b667SHu Ziji } 62506c8b667SHu Ziji 626298269c6SHu Ziji static int get_dt_pad_ctrl_data(struct sdhci_host *host, 627298269c6SHu Ziji struct device_node *np, 628298269c6SHu Ziji struct xenon_emmc_phy_params *params) 629298269c6SHu Ziji { 630298269c6SHu Ziji int ret = 0; 631298269c6SHu Ziji const char *name; 632298269c6SHu Ziji struct resource iomem; 633298269c6SHu Ziji 634298269c6SHu Ziji if (of_device_is_compatible(np, "marvell,armada-3700-sdhci")) 635298269c6SHu Ziji params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set; 636298269c6SHu Ziji else 637298269c6SHu Ziji return 0; 638298269c6SHu Ziji 639298269c6SHu Ziji if (of_address_to_resource(np, 1, &iomem)) { 640298269c6SHu Ziji dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n", 641298269c6SHu Ziji np->name); 642298269c6SHu Ziji return -EINVAL; 643298269c6SHu Ziji } 644298269c6SHu Ziji 645298269c6SHu Ziji params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), 646298269c6SHu Ziji &iomem); 647e6e267b0SWei Yongjun if (IS_ERR(params->pad_ctrl.reg)) 648298269c6SHu Ziji return PTR_ERR(params->pad_ctrl.reg); 649298269c6SHu Ziji 650298269c6SHu Ziji ret = of_property_read_string(np, "marvell,pad-type", &name); 651298269c6SHu Ziji if (ret) { 652298269c6SHu Ziji dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n"); 653298269c6SHu Ziji return ret; 654298269c6SHu Ziji } 655298269c6SHu Ziji if (!strcmp(name, "sd")) { 656298269c6SHu Ziji params->pad_ctrl.pad_type = SOC_PAD_SD; 657298269c6SHu Ziji } else if (!strcmp(name, "fixed-1-8v")) { 658298269c6SHu Ziji params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V; 659298269c6SHu Ziji } else { 660298269c6SHu Ziji dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n", 661298269c6SHu Ziji name); 662298269c6SHu Ziji return -EINVAL; 663298269c6SHu Ziji } 664298269c6SHu Ziji 665298269c6SHu Ziji return ret; 666298269c6SHu Ziji } 667298269c6SHu Ziji 66806c8b667SHu Ziji static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host, 66906c8b667SHu Ziji struct device_node *np, 67006c8b667SHu Ziji struct xenon_emmc_phy_params *params) 67106c8b667SHu Ziji { 67206c8b667SHu Ziji u32 value; 67306c8b667SHu Ziji 67406c8b667SHu Ziji params->slow_mode = false; 67506c8b667SHu Ziji if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode")) 67606c8b667SHu Ziji params->slow_mode = true; 67706c8b667SHu Ziji 67806c8b667SHu Ziji params->znr = XENON_ZNR_DEF_VALUE; 67906c8b667SHu Ziji if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value)) 68006c8b667SHu Ziji params->znr = value & XENON_ZNR_MASK; 68106c8b667SHu Ziji 68206c8b667SHu Ziji params->zpr = XENON_ZPR_DEF_VALUE; 68306c8b667SHu Ziji if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value)) 68406c8b667SHu Ziji params->zpr = value & XENON_ZPR_MASK; 68506c8b667SHu Ziji 68606c8b667SHu Ziji params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES; 68706c8b667SHu Ziji if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun", 68806c8b667SHu Ziji &value)) 68906c8b667SHu Ziji params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK; 69006c8b667SHu Ziji 69106c8b667SHu Ziji params->tun_step_divider = XENON_TUNING_STEP_DIVIDER; 69206c8b667SHu Ziji if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider", 69306c8b667SHu Ziji &value)) 69406c8b667SHu Ziji params->tun_step_divider = value & 0xFF; 69506c8b667SHu Ziji 696298269c6SHu Ziji return get_dt_pad_ctrl_data(host, np, params); 697298269c6SHu Ziji } 698298269c6SHu Ziji 699298269c6SHu Ziji /* Set SoC PHY Voltage PAD */ 700298269c6SHu Ziji void xenon_soc_pad_ctrl(struct sdhci_host *host, 701298269c6SHu Ziji unsigned char signal_voltage) 702298269c6SHu Ziji { 703298269c6SHu Ziji xenon_emmc_phy_set_soc_pad(host, signal_voltage); 70406c8b667SHu Ziji } 70506c8b667SHu Ziji 70606c8b667SHu Ziji /* 70706c8b667SHu Ziji * Setting PHY when card is working in High Speed Mode. 70806c8b667SHu Ziji * HS400 set data strobe line. 70906c8b667SHu Ziji * HS200/SDR104 set tuning config to prepare for tuning. 71006c8b667SHu Ziji */ 71106c8b667SHu Ziji static int xenon_hs_delay_adj(struct sdhci_host *host) 71206c8b667SHu Ziji { 71306c8b667SHu Ziji int ret = 0; 71406c8b667SHu Ziji 71506c8b667SHu Ziji if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ)) 71606c8b667SHu Ziji return -EINVAL; 71706c8b667SHu Ziji 71806c8b667SHu Ziji switch (host->timing) { 71906c8b667SHu Ziji case MMC_TIMING_MMC_HS400: 72006c8b667SHu Ziji xenon_emmc_phy_strobe_delay_adj(host); 72106c8b667SHu Ziji return 0; 72206c8b667SHu Ziji case MMC_TIMING_MMC_HS200: 72306c8b667SHu Ziji case MMC_TIMING_UHS_SDR104: 72406c8b667SHu Ziji return xenon_emmc_phy_config_tuning(host); 72506c8b667SHu Ziji case MMC_TIMING_MMC_DDR52: 72606c8b667SHu Ziji case MMC_TIMING_UHS_DDR50: 72706c8b667SHu Ziji /* 72806c8b667SHu Ziji * DDR Mode requires driver to scan Sampling Fixed Delay Line, 72906c8b667SHu Ziji * to find out a perfect operation sampling point. 73006c8b667SHu Ziji * It is hard to implement such a scan in host driver 73106c8b667SHu Ziji * since initiating commands by host driver is not safe. 73206c8b667SHu Ziji * Thus so far just keep PHY Sampling Fixed Delay in 73306c8b667SHu Ziji * default value of DDR mode. 73406c8b667SHu Ziji * 73506c8b667SHu Ziji * If any timing issue occurs in DDR mode on Marvell products, 73606c8b667SHu Ziji * please contact maintainer for internal support in Marvell. 73706c8b667SHu Ziji */ 73806c8b667SHu Ziji dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n"); 73906c8b667SHu Ziji return 0; 74006c8b667SHu Ziji } 74106c8b667SHu Ziji 74206c8b667SHu Ziji return ret; 74306c8b667SHu Ziji } 74406c8b667SHu Ziji 74506c8b667SHu Ziji /* 74606c8b667SHu Ziji * Adjust PHY setting. 74706c8b667SHu Ziji * PHY setting should be adjusted when SDCLK frequency, Bus Width 74806c8b667SHu Ziji * or Speed Mode is changed. 74906c8b667SHu Ziji * Additional config are required when card is working in High Speed mode, 75006c8b667SHu Ziji * after leaving Legacy Mode. 75106c8b667SHu Ziji */ 75206c8b667SHu Ziji int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios) 75306c8b667SHu Ziji { 75406c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 75506c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 75606c8b667SHu Ziji int ret = 0; 75706c8b667SHu Ziji 75806c8b667SHu Ziji if (!host->clock) { 75906c8b667SHu Ziji priv->clock = 0; 76006c8b667SHu Ziji return 0; 76106c8b667SHu Ziji } 76206c8b667SHu Ziji 76306c8b667SHu Ziji /* 76406c8b667SHu Ziji * The timing, frequency or bus width is changed, 76506c8b667SHu Ziji * better to set eMMC PHY based on current setting 76606c8b667SHu Ziji * and adjust Xenon SDHC delay. 76706c8b667SHu Ziji */ 76806c8b667SHu Ziji if ((host->clock == priv->clock) && 76906c8b667SHu Ziji (ios->bus_width == priv->bus_width) && 77006c8b667SHu Ziji (ios->timing == priv->timing)) 77106c8b667SHu Ziji return 0; 77206c8b667SHu Ziji 77306c8b667SHu Ziji xenon_emmc_phy_set(host, ios->timing); 77406c8b667SHu Ziji 77506c8b667SHu Ziji /* Update the record */ 77606c8b667SHu Ziji priv->bus_width = ios->bus_width; 77706c8b667SHu Ziji 77806c8b667SHu Ziji priv->timing = ios->timing; 77906c8b667SHu Ziji priv->clock = host->clock; 78006c8b667SHu Ziji 78106c8b667SHu Ziji /* Legacy mode is a special case */ 78206c8b667SHu Ziji if (ios->timing == MMC_TIMING_LEGACY) 78306c8b667SHu Ziji return 0; 78406c8b667SHu Ziji 78506c8b667SHu Ziji if (host->clock > XENON_DEFAULT_SDCLK_FREQ) 78606c8b667SHu Ziji ret = xenon_hs_delay_adj(host); 78706c8b667SHu Ziji return ret; 78806c8b667SHu Ziji } 78906c8b667SHu Ziji 79006c8b667SHu Ziji void xenon_clean_phy(struct sdhci_host *host) 79106c8b667SHu Ziji { 79206c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 79306c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 79406c8b667SHu Ziji 79506c8b667SHu Ziji kfree(priv->phy_params); 79606c8b667SHu Ziji } 79706c8b667SHu Ziji 79806c8b667SHu Ziji static int xenon_add_phy(struct device_node *np, struct sdhci_host *host, 79906c8b667SHu Ziji const char *phy_name) 80006c8b667SHu Ziji { 80106c8b667SHu Ziji struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 80206c8b667SHu Ziji struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 80306c8b667SHu Ziji int i, ret; 80406c8b667SHu Ziji 80506c8b667SHu Ziji for (i = 0; i < NR_PHY_TYPES; i++) { 80606c8b667SHu Ziji if (!strcmp(phy_name, phy_types[i])) { 80706c8b667SHu Ziji priv->phy_type = i; 80806c8b667SHu Ziji break; 80906c8b667SHu Ziji } 81006c8b667SHu Ziji } 81106c8b667SHu Ziji if (i == NR_PHY_TYPES) { 81206c8b667SHu Ziji dev_err(mmc_dev(host->mmc), 81306c8b667SHu Ziji "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n", 81406c8b667SHu Ziji phy_name); 81506c8b667SHu Ziji priv->phy_type = EMMC_5_1_PHY; 81606c8b667SHu Ziji } 81706c8b667SHu Ziji 81806c8b667SHu Ziji ret = xenon_alloc_emmc_phy(host); 81906c8b667SHu Ziji if (ret) 82006c8b667SHu Ziji return ret; 82106c8b667SHu Ziji 82206c8b667SHu Ziji ret = xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params); 82306c8b667SHu Ziji if (ret) 82406c8b667SHu Ziji xenon_clean_phy(host); 82506c8b667SHu Ziji 82606c8b667SHu Ziji return ret; 82706c8b667SHu Ziji } 82806c8b667SHu Ziji 82906c8b667SHu Ziji int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host) 83006c8b667SHu Ziji { 83106c8b667SHu Ziji const char *phy_type = NULL; 83206c8b667SHu Ziji 83306c8b667SHu Ziji if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type)) 83406c8b667SHu Ziji return xenon_add_phy(np, host, phy_type); 83506c8b667SHu Ziji 83606c8b667SHu Ziji return xenon_add_phy(np, host, "emmc 5.1 phy"); 83706c8b667SHu Ziji } 838