1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 41 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 42 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 43 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 44 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 45 46 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 47 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 48 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 49 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 50 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 51 52 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 53 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 54 55 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 56 #define SDHCI_AUTO_CAL_START BIT(31) 57 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 58 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 59 60 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 61 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 62 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 63 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 64 65 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 66 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 67 68 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 69 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 70 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 71 #define NVQUIRK_ENABLE_SDR50 BIT(3) 72 #define NVQUIRK_ENABLE_SDR104 BIT(4) 73 #define NVQUIRK_ENABLE_DDR50 BIT(5) 74 #define NVQUIRK_HAS_PADCALIB BIT(6) 75 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 76 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 77 78 struct sdhci_tegra_soc_data { 79 const struct sdhci_pltfm_data *pdata; 80 u32 nvquirks; 81 }; 82 83 /* Magic pull up and pull down pad calibration offsets */ 84 struct sdhci_tegra_autocal_offsets { 85 u32 pull_up_3v3; 86 u32 pull_down_3v3; 87 u32 pull_up_3v3_timeout; 88 u32 pull_down_3v3_timeout; 89 u32 pull_up_1v8; 90 u32 pull_down_1v8; 91 u32 pull_up_1v8_timeout; 92 u32 pull_down_1v8_timeout; 93 u32 pull_up_sdr104; 94 u32 pull_down_sdr104; 95 u32 pull_up_hs400; 96 u32 pull_down_hs400; 97 }; 98 99 struct sdhci_tegra { 100 const struct sdhci_tegra_soc_data *soc_data; 101 struct gpio_desc *power_gpio; 102 bool ddr_signaling; 103 bool pad_calib_required; 104 bool pad_control_available; 105 106 struct reset_control *rst; 107 struct pinctrl *pinctrl_sdmmc; 108 struct pinctrl_state *pinctrl_state_3v3; 109 struct pinctrl_state *pinctrl_state_1v8; 110 111 struct sdhci_tegra_autocal_offsets autocal_offsets; 112 113 u32 default_tap; 114 u32 default_trim; 115 }; 116 117 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 118 { 119 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 120 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 121 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 122 123 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 124 (reg == SDHCI_HOST_VERSION))) { 125 /* Erratum: Version register is invalid in HW. */ 126 return SDHCI_SPEC_200; 127 } 128 129 return readw(host->ioaddr + reg); 130 } 131 132 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 133 { 134 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 135 136 switch (reg) { 137 case SDHCI_TRANSFER_MODE: 138 /* 139 * Postpone this write, we must do it together with a 140 * command write that is down below. 141 */ 142 pltfm_host->xfer_mode_shadow = val; 143 return; 144 case SDHCI_COMMAND: 145 writel((val << 16) | pltfm_host->xfer_mode_shadow, 146 host->ioaddr + SDHCI_TRANSFER_MODE); 147 return; 148 } 149 150 writew(val, host->ioaddr + reg); 151 } 152 153 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 154 { 155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 156 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 157 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 158 159 /* Seems like we're getting spurious timeout and crc errors, so 160 * disable signalling of them. In case of real errors software 161 * timers should take care of eventually detecting them. 162 */ 163 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 164 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 165 166 writel(val, host->ioaddr + reg); 167 168 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 169 (reg == SDHCI_INT_ENABLE))) { 170 /* Erratum: Must enable block gap interrupt detection */ 171 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 172 if (val & SDHCI_INT_CARD_INT) 173 gap_ctrl |= 0x8; 174 else 175 gap_ctrl &= ~0x8; 176 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 177 } 178 } 179 180 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 181 { 182 return mmc_gpio_get_ro(host->mmc); 183 } 184 185 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 186 { 187 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 188 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 189 int has_1v8, has_3v3; 190 191 /* 192 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 193 * voltage configuration in order to perform voltage switching. This 194 * means that valid pinctrl info is required on SDHCI instances capable 195 * of performing voltage switching. Whether or not an SDHCI instance is 196 * capable of voltage switching is determined based on the regulator. 197 */ 198 199 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 200 return true; 201 202 if (IS_ERR(host->mmc->supply.vqmmc)) 203 return false; 204 205 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 206 1700000, 1950000); 207 208 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 209 2700000, 3600000); 210 211 if (has_1v8 == 1 && has_3v3 == 1) 212 return tegra_host->pad_control_available; 213 214 /* Fixed voltage, no pad control required. */ 215 return true; 216 } 217 218 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 219 { 220 bool status; 221 u32 reg; 222 223 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 224 status = !!(reg & SDHCI_CLOCK_CARD_EN); 225 226 if (status == enable) 227 return status; 228 229 if (enable) 230 reg |= SDHCI_CLOCK_CARD_EN; 231 else 232 reg &= ~SDHCI_CLOCK_CARD_EN; 233 234 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 235 236 return status; 237 } 238 239 240 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 241 { 242 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 243 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 244 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 245 bool card_clk_enabled = false; 246 u32 reg; 247 248 /* 249 * Touching the tap values is a bit tricky on some SoC generations. 250 * The quirk enables a workaround for a glitch that sometimes occurs if 251 * the tap values are changed. 252 */ 253 254 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 255 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 256 257 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 258 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 259 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 260 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 261 262 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 263 card_clk_enabled) { 264 udelay(1); 265 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 266 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 267 } 268 } 269 270 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 271 { 272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 273 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 274 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 275 u32 misc_ctrl, clk_ctrl, pad_ctrl; 276 277 sdhci_reset(host, mask); 278 279 if (!(mask & SDHCI_RESET_ALL)) 280 return; 281 282 tegra_sdhci_set_tap(host, tegra_host->default_tap); 283 284 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 285 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 286 287 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 288 SDHCI_MISC_CTRL_ENABLE_SDR50 | 289 SDHCI_MISC_CTRL_ENABLE_DDR50 | 290 SDHCI_MISC_CTRL_ENABLE_SDR104); 291 292 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 293 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 294 295 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 296 /* Erratum: Enable SDHCI spec v3.00 support */ 297 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 298 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 299 /* Advertise UHS modes as supported by host */ 300 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 301 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 302 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 303 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 304 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 305 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 306 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 307 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 308 } 309 310 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 311 312 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 313 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 314 315 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 316 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 317 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 318 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 319 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 320 321 tegra_host->pad_calib_required = true; 322 } 323 324 tegra_host->ddr_signaling = false; 325 } 326 327 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 328 { 329 u32 val; 330 331 /* 332 * Enable or disable the additional I/O pad used by the drive strength 333 * calibration process. 334 */ 335 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 336 337 if (enable) 338 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 339 else 340 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 341 342 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 343 344 if (enable) 345 usleep_range(1, 2); 346 } 347 348 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 349 u16 pdpu) 350 { 351 u32 reg; 352 353 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 354 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 355 reg |= pdpu; 356 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 357 } 358 359 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 360 { 361 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 362 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 363 struct sdhci_tegra_autocal_offsets offsets = 364 tegra_host->autocal_offsets; 365 struct mmc_ios *ios = &host->mmc->ios; 366 bool card_clk_enabled; 367 u16 pdpu; 368 u32 reg; 369 int ret; 370 371 switch (ios->timing) { 372 case MMC_TIMING_UHS_SDR104: 373 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 374 break; 375 case MMC_TIMING_MMC_HS400: 376 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 377 break; 378 default: 379 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 380 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 381 else 382 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 383 } 384 385 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 386 387 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 388 389 tegra_sdhci_configure_cal_pad(host, true); 390 391 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 392 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 393 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 394 395 usleep_range(1, 2); 396 /* 10 ms timeout */ 397 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 398 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 399 1000, 10000); 400 401 tegra_sdhci_configure_cal_pad(host, false); 402 403 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 404 405 if (ret) { 406 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 407 408 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 409 pdpu = offsets.pull_down_1v8_timeout << 8 | 410 offsets.pull_up_1v8_timeout; 411 else 412 pdpu = offsets.pull_down_3v3_timeout << 8 | 413 offsets.pull_up_3v3_timeout; 414 415 /* Disable automatic calibration and use fixed offsets */ 416 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 417 reg &= ~SDHCI_AUTO_CAL_ENABLE; 418 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 419 420 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 421 } 422 } 423 424 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 425 { 426 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 427 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 428 struct sdhci_tegra_autocal_offsets *autocal = 429 &tegra_host->autocal_offsets; 430 int err; 431 432 err = device_property_read_u32(host->mmc->parent, 433 "nvidia,pad-autocal-pull-up-offset-3v3", 434 &autocal->pull_up_3v3); 435 if (err) 436 autocal->pull_up_3v3 = 0; 437 438 err = device_property_read_u32(host->mmc->parent, 439 "nvidia,pad-autocal-pull-down-offset-3v3", 440 &autocal->pull_down_3v3); 441 if (err) 442 autocal->pull_down_3v3 = 0; 443 444 err = device_property_read_u32(host->mmc->parent, 445 "nvidia,pad-autocal-pull-up-offset-1v8", 446 &autocal->pull_up_1v8); 447 if (err) 448 autocal->pull_up_1v8 = 0; 449 450 err = device_property_read_u32(host->mmc->parent, 451 "nvidia,pad-autocal-pull-down-offset-1v8", 452 &autocal->pull_down_1v8); 453 if (err) 454 autocal->pull_down_1v8 = 0; 455 456 err = device_property_read_u32(host->mmc->parent, 457 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 458 &autocal->pull_up_3v3); 459 if (err) 460 autocal->pull_up_3v3_timeout = 0; 461 462 err = device_property_read_u32(host->mmc->parent, 463 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 464 &autocal->pull_down_3v3); 465 if (err) 466 autocal->pull_down_3v3_timeout = 0; 467 468 err = device_property_read_u32(host->mmc->parent, 469 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 470 &autocal->pull_up_1v8); 471 if (err) 472 autocal->pull_up_1v8_timeout = 0; 473 474 err = device_property_read_u32(host->mmc->parent, 475 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 476 &autocal->pull_down_1v8); 477 if (err) 478 autocal->pull_down_1v8_timeout = 0; 479 480 err = device_property_read_u32(host->mmc->parent, 481 "nvidia,pad-autocal-pull-up-offset-sdr104", 482 &autocal->pull_up_sdr104); 483 if (err) 484 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 485 486 err = device_property_read_u32(host->mmc->parent, 487 "nvidia,pad-autocal-pull-down-offset-sdr104", 488 &autocal->pull_down_sdr104); 489 if (err) 490 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 491 492 err = device_property_read_u32(host->mmc->parent, 493 "nvidia,pad-autocal-pull-up-offset-hs400", 494 &autocal->pull_up_hs400); 495 if (err) 496 autocal->pull_up_hs400 = autocal->pull_up_1v8; 497 498 err = device_property_read_u32(host->mmc->parent, 499 "nvidia,pad-autocal-pull-down-offset-hs400", 500 &autocal->pull_down_hs400); 501 if (err) 502 autocal->pull_down_hs400 = autocal->pull_down_1v8; 503 } 504 505 static void tegra_sdhci_parse_default_tap_and_trim(struct sdhci_host *host) 506 { 507 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 508 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 509 int err; 510 511 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 512 &tegra_host->default_tap); 513 if (err) 514 tegra_host->default_tap = 0; 515 516 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 517 &tegra_host->default_trim); 518 if (err) 519 tegra_host->default_trim = 0; 520 } 521 522 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 523 { 524 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 525 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 526 unsigned long host_clk; 527 528 if (!clock) 529 return sdhci_set_clock(host, clock); 530 531 /* 532 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 533 * divider to be configured to divided the host clock by two. The SDHCI 534 * clock divider is calculated as part of sdhci_set_clock() by 535 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 536 * the requested clock rate. 537 * 538 * By setting the host->max_clk to clock * 2 the divider calculation 539 * will always result in the correct value for DDR50/52 modes, 540 * regardless of clock rate rounding, which may happen if the value 541 * from clk_get_rate() is used. 542 */ 543 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 544 clk_set_rate(pltfm_host->clk, host_clk); 545 if (tegra_host->ddr_signaling) 546 host->max_clk = host_clk; 547 else 548 host->max_clk = clk_get_rate(pltfm_host->clk); 549 550 sdhci_set_clock(host, clock); 551 552 if (tegra_host->pad_calib_required) { 553 tegra_sdhci_pad_autocalib(host); 554 tegra_host->pad_calib_required = false; 555 } 556 } 557 558 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 559 { 560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 561 562 return clk_round_rate(pltfm_host->clk, UINT_MAX); 563 } 564 565 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 566 unsigned timing) 567 { 568 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 569 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 570 bool set_default_tap = false; 571 572 switch (timing) { 573 case MMC_TIMING_UHS_SDR50: 574 case MMC_TIMING_UHS_SDR104: 575 case MMC_TIMING_MMC_HS200: 576 case MMC_TIMING_MMC_HS400: 577 /* Don't set default tap on tunable modes. */ 578 break; 579 case MMC_TIMING_MMC_DDR52: 580 case MMC_TIMING_UHS_DDR50: 581 tegra_host->ddr_signaling = true; 582 set_default_tap = true; 583 break; 584 default: 585 set_default_tap = true; 586 break; 587 } 588 589 sdhci_set_uhs_signaling(host, timing); 590 591 tegra_sdhci_pad_autocalib(host); 592 593 if (set_default_tap) 594 tegra_sdhci_set_tap(host, tegra_host->default_tap); 595 } 596 597 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 598 { 599 unsigned int min, max; 600 601 /* 602 * Start search for minimum tap value at 10, as smaller values are 603 * may wrongly be reported as working but fail at higher speeds, 604 * according to the TRM. 605 */ 606 min = 10; 607 while (min < 255) { 608 tegra_sdhci_set_tap(host, min); 609 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 610 break; 611 min++; 612 } 613 614 /* Find the maximum tap value that still passes. */ 615 max = min + 1; 616 while (max < 255) { 617 tegra_sdhci_set_tap(host, max); 618 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 619 max--; 620 break; 621 } 622 max++; 623 } 624 625 /* The TRM states the ideal tap value is at 75% in the passing range. */ 626 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 627 628 return mmc_send_tuning(host->mmc, opcode, NULL); 629 } 630 631 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 632 { 633 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 634 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 635 int ret; 636 637 if (!tegra_host->pad_control_available) 638 return 0; 639 640 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 641 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 642 tegra_host->pinctrl_state_1v8); 643 if (ret < 0) 644 dev_err(mmc_dev(host->mmc), 645 "setting 1.8V failed, ret: %d\n", ret); 646 } else { 647 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 648 tegra_host->pinctrl_state_3v3); 649 if (ret < 0) 650 dev_err(mmc_dev(host->mmc), 651 "setting 3.3V failed, ret: %d\n", ret); 652 } 653 654 return ret; 655 } 656 657 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 658 struct mmc_ios *ios) 659 { 660 struct sdhci_host *host = mmc_priv(mmc); 661 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 662 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 663 int ret = 0; 664 665 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 666 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 667 if (ret < 0) 668 return ret; 669 ret = sdhci_start_signal_voltage_switch(mmc, ios); 670 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 671 ret = sdhci_start_signal_voltage_switch(mmc, ios); 672 if (ret < 0) 673 return ret; 674 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 675 } 676 677 if (tegra_host->pad_calib_required) 678 tegra_sdhci_pad_autocalib(host); 679 680 return ret; 681 } 682 683 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 684 struct sdhci_tegra *tegra_host) 685 { 686 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 687 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 688 dev_dbg(dev, "No pinctrl info, err: %ld\n", 689 PTR_ERR(tegra_host->pinctrl_sdmmc)); 690 return -1; 691 } 692 693 tegra_host->pinctrl_state_3v3 = 694 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 695 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 696 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 697 PTR_ERR(tegra_host->pinctrl_state_3v3)); 698 return -1; 699 } 700 701 tegra_host->pinctrl_state_1v8 = 702 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 703 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 704 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 705 PTR_ERR(tegra_host->pinctrl_state_3v3)); 706 return -1; 707 } 708 709 tegra_host->pad_control_available = true; 710 711 return 0; 712 } 713 714 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 715 { 716 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 717 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 718 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 719 720 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 721 tegra_host->pad_calib_required = true; 722 } 723 724 static const struct sdhci_ops tegra_sdhci_ops = { 725 .get_ro = tegra_sdhci_get_ro, 726 .read_w = tegra_sdhci_readw, 727 .write_l = tegra_sdhci_writel, 728 .set_clock = tegra_sdhci_set_clock, 729 .set_bus_width = sdhci_set_bus_width, 730 .reset = tegra_sdhci_reset, 731 .platform_execute_tuning = tegra_sdhci_execute_tuning, 732 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 733 .voltage_switch = tegra_sdhci_voltage_switch, 734 .get_max_clock = tegra_sdhci_get_max_clock, 735 }; 736 737 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 738 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 739 SDHCI_QUIRK_SINGLE_POWER_WRITE | 740 SDHCI_QUIRK_NO_HISPD_BIT | 741 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 742 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 743 .ops = &tegra_sdhci_ops, 744 }; 745 746 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 747 .pdata = &sdhci_tegra20_pdata, 748 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 749 NVQUIRK_ENABLE_BLOCK_GAP_DET, 750 }; 751 752 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 753 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 754 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 755 SDHCI_QUIRK_SINGLE_POWER_WRITE | 756 SDHCI_QUIRK_NO_HISPD_BIT | 757 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 758 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 759 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 760 SDHCI_QUIRK2_BROKEN_HS200 | 761 /* 762 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 763 * though no command operation was in progress." 764 * 765 * The exact reason is unknown, as the same hardware seems 766 * to support Auto CMD23 on a downstream 3.1 kernel. 767 */ 768 SDHCI_QUIRK2_ACMD23_BROKEN, 769 .ops = &tegra_sdhci_ops, 770 }; 771 772 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 773 .pdata = &sdhci_tegra30_pdata, 774 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 775 NVQUIRK_ENABLE_SDR50 | 776 NVQUIRK_ENABLE_SDR104 | 777 NVQUIRK_HAS_PADCALIB, 778 }; 779 780 static const struct sdhci_ops tegra114_sdhci_ops = { 781 .get_ro = tegra_sdhci_get_ro, 782 .read_w = tegra_sdhci_readw, 783 .write_w = tegra_sdhci_writew, 784 .write_l = tegra_sdhci_writel, 785 .set_clock = tegra_sdhci_set_clock, 786 .set_bus_width = sdhci_set_bus_width, 787 .reset = tegra_sdhci_reset, 788 .platform_execute_tuning = tegra_sdhci_execute_tuning, 789 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 790 .voltage_switch = tegra_sdhci_voltage_switch, 791 .get_max_clock = tegra_sdhci_get_max_clock, 792 }; 793 794 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 795 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 796 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 797 SDHCI_QUIRK_SINGLE_POWER_WRITE | 798 SDHCI_QUIRK_NO_HISPD_BIT | 799 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 800 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 801 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 802 .ops = &tegra114_sdhci_ops, 803 }; 804 805 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 806 .pdata = &sdhci_tegra114_pdata, 807 }; 808 809 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 810 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 811 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 812 SDHCI_QUIRK_SINGLE_POWER_WRITE | 813 SDHCI_QUIRK_NO_HISPD_BIT | 814 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 815 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 816 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 817 /* 818 * The TRM states that the SD/MMC controller found on 819 * Tegra124 can address 34 bits (the maximum supported by 820 * the Tegra memory controller), but tests show that DMA 821 * to or from above 4 GiB doesn't work. This is possibly 822 * caused by missing programming, though it's not obvious 823 * what sequence is required. Mark 64-bit DMA broken for 824 * now to fix this for existing users (e.g. Nyan boards). 825 */ 826 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 827 .ops = &tegra114_sdhci_ops, 828 }; 829 830 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 831 .pdata = &sdhci_tegra124_pdata, 832 }; 833 834 static const struct sdhci_ops tegra210_sdhci_ops = { 835 .get_ro = tegra_sdhci_get_ro, 836 .read_w = tegra_sdhci_readw, 837 .write_l = tegra_sdhci_writel, 838 .set_clock = tegra_sdhci_set_clock, 839 .set_bus_width = sdhci_set_bus_width, 840 .reset = tegra_sdhci_reset, 841 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 842 .voltage_switch = tegra_sdhci_voltage_switch, 843 .get_max_clock = tegra_sdhci_get_max_clock, 844 }; 845 846 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 847 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 848 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 849 SDHCI_QUIRK_SINGLE_POWER_WRITE | 850 SDHCI_QUIRK_NO_HISPD_BIT | 851 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 852 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 853 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 854 .ops = &tegra210_sdhci_ops, 855 }; 856 857 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 858 .pdata = &sdhci_tegra210_pdata, 859 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 860 NVQUIRK_HAS_PADCALIB | 861 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 862 }; 863 864 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 865 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 866 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 867 SDHCI_QUIRK_SINGLE_POWER_WRITE | 868 SDHCI_QUIRK_NO_HISPD_BIT | 869 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 870 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 871 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 872 /* SDHCI controllers on Tegra186 support 40-bit addressing. 873 * IOVA addresses are 48-bit wide on Tegra186. 874 * With 64-bit dma mask used for SDHCI, accesses can 875 * be broken. Disable 64-bit dma, which would fall back 876 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 877 * But it is not supported as of now. 878 */ 879 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 880 .ops = &tegra210_sdhci_ops, 881 }; 882 883 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 884 .pdata = &sdhci_tegra186_pdata, 885 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 886 NVQUIRK_HAS_PADCALIB | 887 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 888 }; 889 890 static const struct of_device_id sdhci_tegra_dt_match[] = { 891 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 892 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 893 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 894 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 895 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 896 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 897 {} 898 }; 899 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 900 901 static int sdhci_tegra_probe(struct platform_device *pdev) 902 { 903 const struct of_device_id *match; 904 const struct sdhci_tegra_soc_data *soc_data; 905 struct sdhci_host *host; 906 struct sdhci_pltfm_host *pltfm_host; 907 struct sdhci_tegra *tegra_host; 908 struct clk *clk; 909 int rc; 910 911 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 912 if (!match) 913 return -EINVAL; 914 soc_data = match->data; 915 916 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 917 if (IS_ERR(host)) 918 return PTR_ERR(host); 919 pltfm_host = sdhci_priv(host); 920 921 tegra_host = sdhci_pltfm_priv(pltfm_host); 922 tegra_host->ddr_signaling = false; 923 tegra_host->pad_calib_required = false; 924 tegra_host->pad_control_available = false; 925 tegra_host->soc_data = soc_data; 926 927 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 928 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 929 if (rc == 0) 930 host->mmc_host_ops.start_signal_voltage_switch = 931 sdhci_tegra_start_signal_voltage_switch; 932 } 933 934 rc = mmc_of_parse(host->mmc); 935 if (rc) 936 goto err_parse_dt; 937 938 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 939 host->mmc->caps |= MMC_CAP_1_8V_DDR; 940 941 tegra_sdhci_parse_pad_autocal_dt(host); 942 943 tegra_sdhci_parse_default_tap_and_trim(host); 944 945 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 946 GPIOD_OUT_HIGH); 947 if (IS_ERR(tegra_host->power_gpio)) { 948 rc = PTR_ERR(tegra_host->power_gpio); 949 goto err_power_req; 950 } 951 952 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 953 if (IS_ERR(clk)) { 954 dev_err(mmc_dev(host->mmc), "clk err\n"); 955 rc = PTR_ERR(clk); 956 goto err_clk_get; 957 } 958 clk_prepare_enable(clk); 959 pltfm_host->clk = clk; 960 961 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 962 "sdhci"); 963 if (IS_ERR(tegra_host->rst)) { 964 rc = PTR_ERR(tegra_host->rst); 965 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 966 goto err_rst_get; 967 } 968 969 rc = reset_control_assert(tegra_host->rst); 970 if (rc) 971 goto err_rst_get; 972 973 usleep_range(2000, 4000); 974 975 rc = reset_control_deassert(tegra_host->rst); 976 if (rc) 977 goto err_rst_get; 978 979 usleep_range(2000, 4000); 980 981 rc = sdhci_add_host(host); 982 if (rc) 983 goto err_add_host; 984 985 return 0; 986 987 err_add_host: 988 reset_control_assert(tegra_host->rst); 989 err_rst_get: 990 clk_disable_unprepare(pltfm_host->clk); 991 err_clk_get: 992 err_power_req: 993 err_parse_dt: 994 sdhci_pltfm_free(pdev); 995 return rc; 996 } 997 998 static int sdhci_tegra_remove(struct platform_device *pdev) 999 { 1000 struct sdhci_host *host = platform_get_drvdata(pdev); 1001 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1002 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1003 1004 sdhci_remove_host(host, 0); 1005 1006 reset_control_assert(tegra_host->rst); 1007 usleep_range(2000, 4000); 1008 clk_disable_unprepare(pltfm_host->clk); 1009 1010 sdhci_pltfm_free(pdev); 1011 1012 return 0; 1013 } 1014 1015 static struct platform_driver sdhci_tegra_driver = { 1016 .driver = { 1017 .name = "sdhci-tegra", 1018 .of_match_table = sdhci_tegra_dt_match, 1019 .pm = &sdhci_pltfm_pmops, 1020 }, 1021 .probe = sdhci_tegra_probe, 1022 .remove = sdhci_tegra_remove, 1023 }; 1024 1025 module_platform_driver(sdhci_tegra_driver); 1026 1027 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1028 MODULE_AUTHOR("Google, Inc."); 1029 MODULE_LICENSE("GPL v2"); 1030