1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/reset.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/gpio/consumer.h> 30 31 #include "sdhci-pltfm.h" 32 33 /* Tegra SDHOST controller vendor register definitions */ 34 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 35 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 36 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 37 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 38 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 39 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 40 41 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 42 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 43 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 44 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 45 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 46 47 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 48 #define SDHCI_AUTO_CAL_START BIT(31) 49 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 50 51 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 52 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 53 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 54 #define NVQUIRK_ENABLE_SDR50 BIT(3) 55 #define NVQUIRK_ENABLE_SDR104 BIT(4) 56 #define NVQUIRK_ENABLE_DDR50 BIT(5) 57 #define NVQUIRK_HAS_PADCALIB BIT(6) 58 59 struct sdhci_tegra_soc_data { 60 const struct sdhci_pltfm_data *pdata; 61 u32 nvquirks; 62 }; 63 64 struct sdhci_tegra { 65 const struct sdhci_tegra_soc_data *soc_data; 66 struct gpio_desc *power_gpio; 67 bool ddr_signaling; 68 bool pad_calib_required; 69 70 struct reset_control *rst; 71 }; 72 73 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 74 { 75 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 76 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 77 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 78 79 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 80 (reg == SDHCI_HOST_VERSION))) { 81 /* Erratum: Version register is invalid in HW. */ 82 return SDHCI_SPEC_200; 83 } 84 85 return readw(host->ioaddr + reg); 86 } 87 88 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 89 { 90 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 91 92 switch (reg) { 93 case SDHCI_TRANSFER_MODE: 94 /* 95 * Postpone this write, we must do it together with a 96 * command write that is down below. 97 */ 98 pltfm_host->xfer_mode_shadow = val; 99 return; 100 case SDHCI_COMMAND: 101 writel((val << 16) | pltfm_host->xfer_mode_shadow, 102 host->ioaddr + SDHCI_TRANSFER_MODE); 103 return; 104 } 105 106 writew(val, host->ioaddr + reg); 107 } 108 109 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 110 { 111 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 112 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 113 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 114 115 /* Seems like we're getting spurious timeout and crc errors, so 116 * disable signalling of them. In case of real errors software 117 * timers should take care of eventually detecting them. 118 */ 119 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 120 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 121 122 writel(val, host->ioaddr + reg); 123 124 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 125 (reg == SDHCI_INT_ENABLE))) { 126 /* Erratum: Must enable block gap interrupt detection */ 127 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 128 if (val & SDHCI_INT_CARD_INT) 129 gap_ctrl |= 0x8; 130 else 131 gap_ctrl &= ~0x8; 132 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 133 } 134 } 135 136 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 137 { 138 return mmc_gpio_get_ro(host->mmc); 139 } 140 141 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 142 { 143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 144 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 145 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 146 u32 misc_ctrl, clk_ctrl; 147 148 sdhci_reset(host, mask); 149 150 if (!(mask & SDHCI_RESET_ALL)) 151 return; 152 153 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 154 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 155 156 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 157 SDHCI_MISC_CTRL_ENABLE_SDR50 | 158 SDHCI_MISC_CTRL_ENABLE_DDR50 | 159 SDHCI_MISC_CTRL_ENABLE_SDR104); 160 161 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 162 163 /* 164 * If the board does not define a regulator for the SDHCI 165 * IO voltage, then don't advertise support for UHS modes 166 * even if the device supports it because the IO voltage 167 * cannot be configured. 168 */ 169 if (!IS_ERR(host->mmc->supply.vqmmc)) { 170 /* Erratum: Enable SDHCI spec v3.00 support */ 171 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 172 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 173 /* Advertise UHS modes as supported by host */ 174 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 175 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 176 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 177 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 178 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 179 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 180 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 181 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 182 } 183 184 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 185 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 186 187 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 188 tegra_host->pad_calib_required = true; 189 190 tegra_host->ddr_signaling = false; 191 } 192 193 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 194 { 195 u32 val; 196 197 mdelay(1); 198 199 val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 200 val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 201 sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); 202 } 203 204 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 205 { 206 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 207 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 208 unsigned long host_clk; 209 210 if (!clock) 211 return sdhci_set_clock(host, clock); 212 213 /* 214 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 215 * divider to be configured to divided the host clock by two. The SDHCI 216 * clock divider is calculated as part of sdhci_set_clock() by 217 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 218 * the requested clock rate. 219 * 220 * By setting the host->max_clk to clock * 2 the divider calculation 221 * will always result in the correct value for DDR50/52 modes, 222 * regardless of clock rate rounding, which may happen if the value 223 * from clk_get_rate() is used. 224 */ 225 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 226 clk_set_rate(pltfm_host->clk, host_clk); 227 if (tegra_host->ddr_signaling) 228 host->max_clk = host_clk; 229 else 230 host->max_clk = clk_get_rate(pltfm_host->clk); 231 232 sdhci_set_clock(host, clock); 233 234 if (tegra_host->pad_calib_required) { 235 tegra_sdhci_pad_autocalib(host); 236 tegra_host->pad_calib_required = false; 237 } 238 } 239 240 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 241 unsigned timing) 242 { 243 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 244 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 245 246 if (timing == MMC_TIMING_UHS_DDR50 || 247 timing == MMC_TIMING_MMC_DDR52) 248 tegra_host->ddr_signaling = true; 249 250 sdhci_set_uhs_signaling(host, timing); 251 } 252 253 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 254 { 255 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 256 257 return clk_round_rate(pltfm_host->clk, UINT_MAX); 258 } 259 260 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 261 { 262 u32 reg; 263 264 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 265 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 266 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 267 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 268 } 269 270 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 271 { 272 unsigned int min, max; 273 274 /* 275 * Start search for minimum tap value at 10, as smaller values are 276 * may wrongly be reported as working but fail at higher speeds, 277 * according to the TRM. 278 */ 279 min = 10; 280 while (min < 255) { 281 tegra_sdhci_set_tap(host, min); 282 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 283 break; 284 min++; 285 } 286 287 /* Find the maximum tap value that still passes. */ 288 max = min + 1; 289 while (max < 255) { 290 tegra_sdhci_set_tap(host, max); 291 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 292 max--; 293 break; 294 } 295 max++; 296 } 297 298 /* The TRM states the ideal tap value is at 75% in the passing range. */ 299 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 300 301 return mmc_send_tuning(host->mmc, opcode, NULL); 302 } 303 304 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 305 { 306 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 307 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 308 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 309 310 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 311 tegra_host->pad_calib_required = true; 312 } 313 314 static const struct sdhci_ops tegra_sdhci_ops = { 315 .get_ro = tegra_sdhci_get_ro, 316 .read_w = tegra_sdhci_readw, 317 .write_l = tegra_sdhci_writel, 318 .set_clock = tegra_sdhci_set_clock, 319 .set_bus_width = sdhci_set_bus_width, 320 .reset = tegra_sdhci_reset, 321 .platform_execute_tuning = tegra_sdhci_execute_tuning, 322 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 323 .voltage_switch = tegra_sdhci_voltage_switch, 324 .get_max_clock = tegra_sdhci_get_max_clock, 325 }; 326 327 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 328 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 329 SDHCI_QUIRK_SINGLE_POWER_WRITE | 330 SDHCI_QUIRK_NO_HISPD_BIT | 331 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 332 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 333 .ops = &tegra_sdhci_ops, 334 }; 335 336 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 337 .pdata = &sdhci_tegra20_pdata, 338 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 339 NVQUIRK_ENABLE_BLOCK_GAP_DET, 340 }; 341 342 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 343 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 344 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 345 SDHCI_QUIRK_SINGLE_POWER_WRITE | 346 SDHCI_QUIRK_NO_HISPD_BIT | 347 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 348 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 349 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 350 SDHCI_QUIRK2_BROKEN_HS200 | 351 /* 352 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 353 * though no command operation was in progress." 354 * 355 * The exact reason is unknown, as the same hardware seems 356 * to support Auto CMD23 on a downstream 3.1 kernel. 357 */ 358 SDHCI_QUIRK2_ACMD23_BROKEN, 359 .ops = &tegra_sdhci_ops, 360 }; 361 362 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 363 .pdata = &sdhci_tegra30_pdata, 364 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 365 NVQUIRK_ENABLE_SDR50 | 366 NVQUIRK_ENABLE_SDR104 | 367 NVQUIRK_HAS_PADCALIB, 368 }; 369 370 static const struct sdhci_ops tegra114_sdhci_ops = { 371 .get_ro = tegra_sdhci_get_ro, 372 .read_w = tegra_sdhci_readw, 373 .write_w = tegra_sdhci_writew, 374 .write_l = tegra_sdhci_writel, 375 .set_clock = tegra_sdhci_set_clock, 376 .set_bus_width = sdhci_set_bus_width, 377 .reset = tegra_sdhci_reset, 378 .platform_execute_tuning = tegra_sdhci_execute_tuning, 379 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 380 .voltage_switch = tegra_sdhci_voltage_switch, 381 .get_max_clock = tegra_sdhci_get_max_clock, 382 }; 383 384 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 385 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 386 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 387 SDHCI_QUIRK_SINGLE_POWER_WRITE | 388 SDHCI_QUIRK_NO_HISPD_BIT | 389 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 390 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 391 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 392 .ops = &tegra114_sdhci_ops, 393 }; 394 395 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 396 .pdata = &sdhci_tegra114_pdata, 397 }; 398 399 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 400 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 401 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 402 SDHCI_QUIRK_SINGLE_POWER_WRITE | 403 SDHCI_QUIRK_NO_HISPD_BIT | 404 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 405 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 406 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 407 /* 408 * The TRM states that the SD/MMC controller found on 409 * Tegra124 can address 34 bits (the maximum supported by 410 * the Tegra memory controller), but tests show that DMA 411 * to or from above 4 GiB doesn't work. This is possibly 412 * caused by missing programming, though it's not obvious 413 * what sequence is required. Mark 64-bit DMA broken for 414 * now to fix this for existing users (e.g. Nyan boards). 415 */ 416 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 417 .ops = &tegra114_sdhci_ops, 418 }; 419 420 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 421 .pdata = &sdhci_tegra124_pdata, 422 }; 423 424 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 425 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 426 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 427 SDHCI_QUIRK_SINGLE_POWER_WRITE | 428 SDHCI_QUIRK_NO_HISPD_BIT | 429 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 430 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 431 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 432 .ops = &tegra114_sdhci_ops, 433 }; 434 435 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 436 .pdata = &sdhci_tegra210_pdata, 437 }; 438 439 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 440 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 441 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 442 SDHCI_QUIRK_SINGLE_POWER_WRITE | 443 SDHCI_QUIRK_NO_HISPD_BIT | 444 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 445 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 446 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 447 /* SDHCI controllers on Tegra186 support 40-bit addressing. 448 * IOVA addresses are 48-bit wide on Tegra186. 449 * With 64-bit dma mask used for SDHCI, accesses can 450 * be broken. Disable 64-bit dma, which would fall back 451 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 452 * But it is not supported as of now. 453 */ 454 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 455 .ops = &tegra114_sdhci_ops, 456 }; 457 458 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 459 .pdata = &sdhci_tegra186_pdata, 460 }; 461 462 static const struct of_device_id sdhci_tegra_dt_match[] = { 463 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 464 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 465 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 466 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 467 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 468 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 469 {} 470 }; 471 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 472 473 static int sdhci_tegra_probe(struct platform_device *pdev) 474 { 475 const struct of_device_id *match; 476 const struct sdhci_tegra_soc_data *soc_data; 477 struct sdhci_host *host; 478 struct sdhci_pltfm_host *pltfm_host; 479 struct sdhci_tegra *tegra_host; 480 struct clk *clk; 481 int rc; 482 483 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 484 if (!match) 485 return -EINVAL; 486 soc_data = match->data; 487 488 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 489 if (IS_ERR(host)) 490 return PTR_ERR(host); 491 pltfm_host = sdhci_priv(host); 492 493 tegra_host = sdhci_pltfm_priv(pltfm_host); 494 tegra_host->ddr_signaling = false; 495 tegra_host->pad_calib_required = false; 496 tegra_host->soc_data = soc_data; 497 498 rc = mmc_of_parse(host->mmc); 499 if (rc) 500 goto err_parse_dt; 501 502 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 503 host->mmc->caps |= MMC_CAP_1_8V_DDR; 504 505 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 506 GPIOD_OUT_HIGH); 507 if (IS_ERR(tegra_host->power_gpio)) { 508 rc = PTR_ERR(tegra_host->power_gpio); 509 goto err_power_req; 510 } 511 512 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 513 if (IS_ERR(clk)) { 514 dev_err(mmc_dev(host->mmc), "clk err\n"); 515 rc = PTR_ERR(clk); 516 goto err_clk_get; 517 } 518 clk_prepare_enable(clk); 519 pltfm_host->clk = clk; 520 521 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 522 "sdhci"); 523 if (IS_ERR(tegra_host->rst)) { 524 rc = PTR_ERR(tegra_host->rst); 525 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 526 goto err_rst_get; 527 } 528 529 rc = reset_control_assert(tegra_host->rst); 530 if (rc) 531 goto err_rst_get; 532 533 usleep_range(2000, 4000); 534 535 rc = reset_control_deassert(tegra_host->rst); 536 if (rc) 537 goto err_rst_get; 538 539 usleep_range(2000, 4000); 540 541 rc = sdhci_add_host(host); 542 if (rc) 543 goto err_add_host; 544 545 return 0; 546 547 err_add_host: 548 reset_control_assert(tegra_host->rst); 549 err_rst_get: 550 clk_disable_unprepare(pltfm_host->clk); 551 err_clk_get: 552 err_power_req: 553 err_parse_dt: 554 sdhci_pltfm_free(pdev); 555 return rc; 556 } 557 558 static int sdhci_tegra_remove(struct platform_device *pdev) 559 { 560 struct sdhci_host *host = platform_get_drvdata(pdev); 561 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 562 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 563 564 sdhci_remove_host(host, 0); 565 566 reset_control_assert(tegra_host->rst); 567 usleep_range(2000, 4000); 568 clk_disable_unprepare(pltfm_host->clk); 569 570 sdhci_pltfm_free(pdev); 571 572 return 0; 573 } 574 575 static struct platform_driver sdhci_tegra_driver = { 576 .driver = { 577 .name = "sdhci-tegra", 578 .of_match_table = sdhci_tegra_dt_match, 579 .pm = &sdhci_pltfm_pmops, 580 }, 581 .probe = sdhci_tegra_probe, 582 .remove = sdhci_tegra_remove, 583 }; 584 585 module_platform_driver(sdhci_tegra_driver); 586 587 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 588 MODULE_AUTHOR("Google, Inc."); 589 MODULE_LICENSE("GPL v2"); 590