1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/ktime.h> 34 35 #include "sdhci-pltfm.h" 36 #include "cqhci.h" 37 38 /* Tegra SDHOST controller vendor register definitions */ 39 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 40 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 41 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 42 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 43 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 44 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 45 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 46 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 47 48 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 49 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 50 51 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 52 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 53 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 54 55 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 56 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 57 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 58 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 59 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 60 61 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 62 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 63 64 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 65 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 66 67 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 68 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 69 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 70 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 71 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 72 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 73 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 74 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 75 #define TRIES_128 2 76 #define TRIES_256 4 77 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 78 79 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 80 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 81 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 82 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 83 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 84 #define TUNING_WORD_BIT_SIZE 32 85 86 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 87 #define SDHCI_AUTO_CAL_START BIT(31) 88 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 89 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 90 91 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 92 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 93 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 94 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 95 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 96 97 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 98 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 99 100 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 101 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 102 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 103 #define NVQUIRK_ENABLE_SDR50 BIT(3) 104 #define NVQUIRK_ENABLE_SDR104 BIT(4) 105 #define NVQUIRK_ENABLE_DDR50 BIT(5) 106 #define NVQUIRK_HAS_PADCALIB BIT(6) 107 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 108 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 109 110 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 111 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 112 113 struct sdhci_tegra_soc_data { 114 const struct sdhci_pltfm_data *pdata; 115 u32 nvquirks; 116 u8 min_tap_delay; 117 u8 max_tap_delay; 118 }; 119 120 /* Magic pull up and pull down pad calibration offsets */ 121 struct sdhci_tegra_autocal_offsets { 122 u32 pull_up_3v3; 123 u32 pull_down_3v3; 124 u32 pull_up_3v3_timeout; 125 u32 pull_down_3v3_timeout; 126 u32 pull_up_1v8; 127 u32 pull_down_1v8; 128 u32 pull_up_1v8_timeout; 129 u32 pull_down_1v8_timeout; 130 u32 pull_up_sdr104; 131 u32 pull_down_sdr104; 132 u32 pull_up_hs400; 133 u32 pull_down_hs400; 134 }; 135 136 struct sdhci_tegra { 137 const struct sdhci_tegra_soc_data *soc_data; 138 struct gpio_desc *power_gpio; 139 bool ddr_signaling; 140 bool pad_calib_required; 141 bool pad_control_available; 142 143 struct reset_control *rst; 144 struct pinctrl *pinctrl_sdmmc; 145 struct pinctrl_state *pinctrl_state_3v3; 146 struct pinctrl_state *pinctrl_state_1v8; 147 struct pinctrl_state *pinctrl_state_3v3_drv; 148 struct pinctrl_state *pinctrl_state_1v8_drv; 149 150 struct sdhci_tegra_autocal_offsets autocal_offsets; 151 ktime_t last_calib; 152 153 u32 default_tap; 154 u32 default_trim; 155 u32 dqs_trim; 156 bool enable_hwcq; 157 unsigned long curr_clk_rate; 158 u8 tuned_tap_delay; 159 }; 160 161 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 162 { 163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 164 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 165 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 166 167 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 168 (reg == SDHCI_HOST_VERSION))) { 169 /* Erratum: Version register is invalid in HW. */ 170 return SDHCI_SPEC_200; 171 } 172 173 return readw(host->ioaddr + reg); 174 } 175 176 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 177 { 178 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 179 180 switch (reg) { 181 case SDHCI_TRANSFER_MODE: 182 /* 183 * Postpone this write, we must do it together with a 184 * command write that is down below. 185 */ 186 pltfm_host->xfer_mode_shadow = val; 187 return; 188 case SDHCI_COMMAND: 189 writel((val << 16) | pltfm_host->xfer_mode_shadow, 190 host->ioaddr + SDHCI_TRANSFER_MODE); 191 return; 192 } 193 194 writew(val, host->ioaddr + reg); 195 } 196 197 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 198 { 199 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 200 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 201 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 202 203 /* Seems like we're getting spurious timeout and crc errors, so 204 * disable signalling of them. In case of real errors software 205 * timers should take care of eventually detecting them. 206 */ 207 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 208 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 209 210 writel(val, host->ioaddr + reg); 211 212 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 213 (reg == SDHCI_INT_ENABLE))) { 214 /* Erratum: Must enable block gap interrupt detection */ 215 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 216 if (val & SDHCI_INT_CARD_INT) 217 gap_ctrl |= 0x8; 218 else 219 gap_ctrl &= ~0x8; 220 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 221 } 222 } 223 224 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 225 { 226 bool status; 227 u32 reg; 228 229 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 230 status = !!(reg & SDHCI_CLOCK_CARD_EN); 231 232 if (status == enable) 233 return status; 234 235 if (enable) 236 reg |= SDHCI_CLOCK_CARD_EN; 237 else 238 reg &= ~SDHCI_CLOCK_CARD_EN; 239 240 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 241 242 return status; 243 } 244 245 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 246 { 247 bool is_tuning_cmd = 0; 248 bool clk_enabled; 249 u8 cmd; 250 251 if (reg == SDHCI_COMMAND) { 252 cmd = SDHCI_GET_CMD(val); 253 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 254 cmd == MMC_SEND_TUNING_BLOCK_HS200; 255 } 256 257 if (is_tuning_cmd) 258 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 259 260 writew(val, host->ioaddr + reg); 261 262 if (is_tuning_cmd) { 263 udelay(1); 264 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 265 tegra_sdhci_configure_card_clk(host, clk_enabled); 266 } 267 } 268 269 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 270 { 271 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 272 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 273 int has_1v8, has_3v3; 274 275 /* 276 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 277 * voltage configuration in order to perform voltage switching. This 278 * means that valid pinctrl info is required on SDHCI instances capable 279 * of performing voltage switching. Whether or not an SDHCI instance is 280 * capable of voltage switching is determined based on the regulator. 281 */ 282 283 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 284 return true; 285 286 if (IS_ERR(host->mmc->supply.vqmmc)) 287 return false; 288 289 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 290 1700000, 1950000); 291 292 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 293 2700000, 3600000); 294 295 if (has_1v8 == 1 && has_3v3 == 1) 296 return tegra_host->pad_control_available; 297 298 /* Fixed voltage, no pad control required. */ 299 return true; 300 } 301 302 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 303 { 304 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 305 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 306 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 307 bool card_clk_enabled = false; 308 u32 reg; 309 310 /* 311 * Touching the tap values is a bit tricky on some SoC generations. 312 * The quirk enables a workaround for a glitch that sometimes occurs if 313 * the tap values are changed. 314 */ 315 316 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 317 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 318 319 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 320 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 321 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 322 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 323 324 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 325 card_clk_enabled) { 326 udelay(1); 327 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 328 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 329 } 330 } 331 332 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 333 struct mmc_ios *ios) 334 { 335 struct sdhci_host *host = mmc_priv(mmc); 336 u32 val; 337 338 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 339 340 if (ios->enhanced_strobe) 341 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 342 else 343 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 344 345 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 346 347 } 348 349 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 350 { 351 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 352 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 353 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 354 u32 misc_ctrl, clk_ctrl, pad_ctrl; 355 356 sdhci_reset(host, mask); 357 358 if (!(mask & SDHCI_RESET_ALL)) 359 return; 360 361 tegra_sdhci_set_tap(host, tegra_host->default_tap); 362 363 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 364 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 365 366 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 367 SDHCI_MISC_CTRL_ENABLE_SDR50 | 368 SDHCI_MISC_CTRL_ENABLE_DDR50 | 369 SDHCI_MISC_CTRL_ENABLE_SDR104); 370 371 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 372 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 373 374 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 375 /* Erratum: Enable SDHCI spec v3.00 support */ 376 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 377 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 378 /* Advertise UHS modes as supported by host */ 379 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 380 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 381 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 382 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 383 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 384 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 385 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 386 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 387 } 388 389 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 390 391 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 392 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 393 394 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 395 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 396 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 397 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 398 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 399 400 tegra_host->pad_calib_required = true; 401 } 402 403 tegra_host->ddr_signaling = false; 404 } 405 406 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 407 { 408 u32 val; 409 410 /* 411 * Enable or disable the additional I/O pad used by the drive strength 412 * calibration process. 413 */ 414 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 415 416 if (enable) 417 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 418 else 419 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 420 421 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 422 423 if (enable) 424 usleep_range(1, 2); 425 } 426 427 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 428 u16 pdpu) 429 { 430 u32 reg; 431 432 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 433 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 434 reg |= pdpu; 435 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 436 } 437 438 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 439 bool state_drvupdn) 440 { 441 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 442 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 443 struct sdhci_tegra_autocal_offsets *offsets = 444 &tegra_host->autocal_offsets; 445 struct pinctrl_state *pinctrl_drvupdn = NULL; 446 int ret = 0; 447 u8 drvup = 0, drvdn = 0; 448 u32 reg; 449 450 if (!state_drvupdn) { 451 /* PADS Drive Strength */ 452 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 453 if (tegra_host->pinctrl_state_1v8_drv) { 454 pinctrl_drvupdn = 455 tegra_host->pinctrl_state_1v8_drv; 456 } else { 457 drvup = offsets->pull_up_1v8_timeout; 458 drvdn = offsets->pull_down_1v8_timeout; 459 } 460 } else { 461 if (tegra_host->pinctrl_state_3v3_drv) { 462 pinctrl_drvupdn = 463 tegra_host->pinctrl_state_3v3_drv; 464 } else { 465 drvup = offsets->pull_up_3v3_timeout; 466 drvdn = offsets->pull_down_3v3_timeout; 467 } 468 } 469 470 if (pinctrl_drvupdn != NULL) { 471 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 472 pinctrl_drvupdn); 473 if (ret < 0) 474 dev_err(mmc_dev(host->mmc), 475 "failed pads drvupdn, ret: %d\n", ret); 476 } else if ((drvup) || (drvdn)) { 477 reg = sdhci_readl(host, 478 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 479 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 480 reg |= (drvup << 20) | (drvdn << 12); 481 sdhci_writel(host, reg, 482 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 483 } 484 485 } else { 486 /* Dual Voltage PADS Voltage selection */ 487 if (!tegra_host->pad_control_available) 488 return 0; 489 490 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 491 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 492 tegra_host->pinctrl_state_1v8); 493 if (ret < 0) 494 dev_err(mmc_dev(host->mmc), 495 "setting 1.8V failed, ret: %d\n", ret); 496 } else { 497 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 498 tegra_host->pinctrl_state_3v3); 499 if (ret < 0) 500 dev_err(mmc_dev(host->mmc), 501 "setting 3.3V failed, ret: %d\n", ret); 502 } 503 } 504 505 return ret; 506 } 507 508 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 509 { 510 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 511 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 512 struct sdhci_tegra_autocal_offsets offsets = 513 tegra_host->autocal_offsets; 514 struct mmc_ios *ios = &host->mmc->ios; 515 bool card_clk_enabled; 516 u16 pdpu; 517 u32 reg; 518 int ret; 519 520 switch (ios->timing) { 521 case MMC_TIMING_UHS_SDR104: 522 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 523 break; 524 case MMC_TIMING_MMC_HS400: 525 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 526 break; 527 default: 528 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 529 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 530 else 531 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 532 } 533 534 /* Set initial offset before auto-calibration */ 535 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 536 537 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 538 539 tegra_sdhci_configure_cal_pad(host, true); 540 541 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 542 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 543 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 544 545 usleep_range(1, 2); 546 /* 10 ms timeout */ 547 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 548 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 549 1000, 10000); 550 551 tegra_sdhci_configure_cal_pad(host, false); 552 553 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 554 555 if (ret) { 556 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 557 558 /* Disable automatic cal and use fixed Drive Strengths */ 559 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 560 reg &= ~SDHCI_AUTO_CAL_ENABLE; 561 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 562 563 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 564 if (ret < 0) 565 dev_err(mmc_dev(host->mmc), 566 "Setting drive strengths failed: %d\n", ret); 567 } 568 } 569 570 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 571 { 572 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 573 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 574 struct sdhci_tegra_autocal_offsets *autocal = 575 &tegra_host->autocal_offsets; 576 int err; 577 578 err = device_property_read_u32(host->mmc->parent, 579 "nvidia,pad-autocal-pull-up-offset-3v3", 580 &autocal->pull_up_3v3); 581 if (err) 582 autocal->pull_up_3v3 = 0; 583 584 err = device_property_read_u32(host->mmc->parent, 585 "nvidia,pad-autocal-pull-down-offset-3v3", 586 &autocal->pull_down_3v3); 587 if (err) 588 autocal->pull_down_3v3 = 0; 589 590 err = device_property_read_u32(host->mmc->parent, 591 "nvidia,pad-autocal-pull-up-offset-1v8", 592 &autocal->pull_up_1v8); 593 if (err) 594 autocal->pull_up_1v8 = 0; 595 596 err = device_property_read_u32(host->mmc->parent, 597 "nvidia,pad-autocal-pull-down-offset-1v8", 598 &autocal->pull_down_1v8); 599 if (err) 600 autocal->pull_down_1v8 = 0; 601 602 err = device_property_read_u32(host->mmc->parent, 603 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 604 &autocal->pull_up_3v3_timeout); 605 if (err) { 606 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 607 (tegra_host->pinctrl_state_3v3_drv == NULL)) 608 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 609 mmc_hostname(host->mmc)); 610 autocal->pull_up_3v3_timeout = 0; 611 } 612 613 err = device_property_read_u32(host->mmc->parent, 614 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 615 &autocal->pull_down_3v3_timeout); 616 if (err) { 617 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 618 (tegra_host->pinctrl_state_3v3_drv == NULL)) 619 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 620 mmc_hostname(host->mmc)); 621 autocal->pull_down_3v3_timeout = 0; 622 } 623 624 err = device_property_read_u32(host->mmc->parent, 625 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 626 &autocal->pull_up_1v8_timeout); 627 if (err) { 628 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 629 (tegra_host->pinctrl_state_1v8_drv == NULL)) 630 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 631 mmc_hostname(host->mmc)); 632 autocal->pull_up_1v8_timeout = 0; 633 } 634 635 err = device_property_read_u32(host->mmc->parent, 636 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 637 &autocal->pull_down_1v8_timeout); 638 if (err) { 639 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 640 (tegra_host->pinctrl_state_1v8_drv == NULL)) 641 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 642 mmc_hostname(host->mmc)); 643 autocal->pull_down_1v8_timeout = 0; 644 } 645 646 err = device_property_read_u32(host->mmc->parent, 647 "nvidia,pad-autocal-pull-up-offset-sdr104", 648 &autocal->pull_up_sdr104); 649 if (err) 650 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 651 652 err = device_property_read_u32(host->mmc->parent, 653 "nvidia,pad-autocal-pull-down-offset-sdr104", 654 &autocal->pull_down_sdr104); 655 if (err) 656 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 657 658 err = device_property_read_u32(host->mmc->parent, 659 "nvidia,pad-autocal-pull-up-offset-hs400", 660 &autocal->pull_up_hs400); 661 if (err) 662 autocal->pull_up_hs400 = autocal->pull_up_1v8; 663 664 err = device_property_read_u32(host->mmc->parent, 665 "nvidia,pad-autocal-pull-down-offset-hs400", 666 &autocal->pull_down_hs400); 667 if (err) 668 autocal->pull_down_hs400 = autocal->pull_down_1v8; 669 } 670 671 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 672 { 673 struct sdhci_host *host = mmc_priv(mmc); 674 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 675 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 676 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 677 678 /* 100 ms calibration interval is specified in the TRM */ 679 if (ktime_to_ms(since_calib) > 100) { 680 tegra_sdhci_pad_autocalib(host); 681 tegra_host->last_calib = ktime_get(); 682 } 683 684 sdhci_request(mmc, mrq); 685 } 686 687 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 688 { 689 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 690 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 691 int err; 692 693 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 694 &tegra_host->default_tap); 695 if (err) 696 tegra_host->default_tap = 0; 697 698 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 699 &tegra_host->default_trim); 700 if (err) 701 tegra_host->default_trim = 0; 702 703 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 704 &tegra_host->dqs_trim); 705 if (err) 706 tegra_host->dqs_trim = 0x11; 707 } 708 709 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 710 { 711 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 712 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 713 714 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) 715 tegra_host->enable_hwcq = true; 716 else 717 tegra_host->enable_hwcq = false; 718 719 tegra_sdhci_parse_pad_autocal_dt(host); 720 tegra_sdhci_parse_tap_and_trim(host); 721 } 722 723 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 724 { 725 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 726 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 727 unsigned long host_clk; 728 729 if (!clock) 730 return sdhci_set_clock(host, clock); 731 732 /* 733 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 734 * divider to be configured to divided the host clock by two. The SDHCI 735 * clock divider is calculated as part of sdhci_set_clock() by 736 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 737 * the requested clock rate. 738 * 739 * By setting the host->max_clk to clock * 2 the divider calculation 740 * will always result in the correct value for DDR50/52 modes, 741 * regardless of clock rate rounding, which may happen if the value 742 * from clk_get_rate() is used. 743 */ 744 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 745 clk_set_rate(pltfm_host->clk, host_clk); 746 tegra_host->curr_clk_rate = host_clk; 747 if (tegra_host->ddr_signaling) 748 host->max_clk = host_clk; 749 else 750 host->max_clk = clk_get_rate(pltfm_host->clk); 751 752 sdhci_set_clock(host, clock); 753 754 if (tegra_host->pad_calib_required) { 755 tegra_sdhci_pad_autocalib(host); 756 tegra_host->pad_calib_required = false; 757 } 758 } 759 760 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 761 { 762 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 763 764 return clk_round_rate(pltfm_host->clk, UINT_MAX); 765 } 766 767 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 768 { 769 u32 val; 770 771 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 772 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 773 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 774 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 775 } 776 777 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 778 { 779 u32 reg; 780 int err; 781 782 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 783 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 784 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 785 786 /* 1 ms sleep, 5 ms timeout */ 787 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 788 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 789 1000, 5000); 790 if (err) 791 dev_err(mmc_dev(host->mmc), 792 "HS400 delay line calibration timed out\n"); 793 } 794 795 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 796 u8 thd_low, u8 fixed_tap) 797 { 798 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 799 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 800 u32 val, tun_status; 801 u8 word, bit, edge1, tap, window; 802 bool tap_result; 803 bool start_fail = false; 804 bool start_pass = false; 805 bool end_pass = false; 806 bool first_fail = false; 807 bool first_pass = false; 808 u8 start_pass_tap = 0; 809 u8 end_pass_tap = 0; 810 u8 first_fail_tap = 0; 811 u8 first_pass_tap = 0; 812 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 813 814 /* 815 * Read auto-tuned results and extract good valid passing window by 816 * filtering out un-wanted bubble/partial/merged windows. 817 */ 818 for (word = 0; word < total_tuning_words; word++) { 819 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 820 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 821 val |= word; 822 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 823 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 824 bit = 0; 825 while (bit < TUNING_WORD_BIT_SIZE) { 826 tap = word * TUNING_WORD_BIT_SIZE + bit; 827 tap_result = tun_status & (1 << bit); 828 if (!tap_result && !start_fail) { 829 start_fail = true; 830 if (!first_fail) { 831 first_fail_tap = tap; 832 first_fail = true; 833 } 834 835 } else if (tap_result && start_fail && !start_pass) { 836 start_pass_tap = tap; 837 start_pass = true; 838 if (!first_pass) { 839 first_pass_tap = tap; 840 first_pass = true; 841 } 842 843 } else if (!tap_result && start_fail && start_pass && 844 !end_pass) { 845 end_pass_tap = tap - 1; 846 end_pass = true; 847 } else if (tap_result && start_pass && start_fail && 848 end_pass) { 849 window = end_pass_tap - start_pass_tap; 850 /* discard merged window and bubble window */ 851 if (window >= thd_up || window < thd_low) { 852 start_pass_tap = tap; 853 end_pass = false; 854 } else { 855 /* set tap at middle of valid window */ 856 tap = start_pass_tap + window / 2; 857 tegra_host->tuned_tap_delay = tap; 858 return; 859 } 860 } 861 862 bit++; 863 } 864 } 865 866 if (!first_fail) { 867 WARN_ON("no edge detected, continue with hw tuned delay.\n"); 868 } else if (first_pass) { 869 /* set tap location at fixed tap relative to the first edge */ 870 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 871 if (edge1 - 1 > fixed_tap) 872 tegra_host->tuned_tap_delay = edge1 - fixed_tap; 873 else 874 tegra_host->tuned_tap_delay = edge1 + fixed_tap; 875 } 876 } 877 878 static void tegra_sdhci_post_tuning(struct sdhci_host *host) 879 { 880 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 881 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 882 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 883 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 884 u8 fixed_tap, start_tap, end_tap, window_width; 885 u8 thdupper, thdlower; 886 u8 num_iter; 887 u32 clk_rate_mhz, period_ps, bestcase, worstcase; 888 889 /* retain HW tuned tap to use incase if no correction is needed */ 890 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 891 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 892 SDHCI_CLOCK_CTRL_TAP_SHIFT; 893 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 894 min_tap_dly = soc_data->min_tap_delay; 895 max_tap_dly = soc_data->max_tap_delay; 896 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 897 period_ps = USEC_PER_SEC / clk_rate_mhz; 898 bestcase = period_ps / min_tap_dly; 899 worstcase = period_ps / max_tap_dly; 900 /* 901 * Upper and Lower bound thresholds used to detect merged and 902 * bubble windows 903 */ 904 thdupper = (2 * worstcase + bestcase) / 2; 905 thdlower = worstcase / 4; 906 /* 907 * fixed tap is used when HW tuning result contains single edge 908 * and tap is set at fixed tap delay relative to the first edge 909 */ 910 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 911 fixed_tap = avg_tap_dly / 2; 912 913 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 914 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 915 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 916 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 917 window_width = end_tap - start_tap; 918 num_iter = host->tuning_loop_count; 919 /* 920 * partial window includes edges of the tuning range. 921 * merged window includes more taps so window width is higher 922 * than upper threshold. 923 */ 924 if (start_tap == 0 || (end_tap == (num_iter - 1)) || 925 (end_tap == num_iter - 2) || window_width >= thdupper) { 926 pr_debug("%s: Apply tuning correction\n", 927 mmc_hostname(host->mmc)); 928 tegra_sdhci_tap_correction(host, thdupper, thdlower, 929 fixed_tap); 930 } 931 } 932 933 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 934 } 935 936 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 937 { 938 struct sdhci_host *host = mmc_priv(mmc); 939 int err; 940 941 err = sdhci_execute_tuning(mmc, opcode); 942 if (!err && !host->tuning_err) 943 tegra_sdhci_post_tuning(host); 944 945 return err; 946 } 947 948 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 949 unsigned timing) 950 { 951 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 952 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 953 bool set_default_tap = false; 954 bool set_dqs_trim = false; 955 bool do_hs400_dll_cal = false; 956 u8 iter = TRIES_256; 957 u32 val; 958 959 tegra_host->ddr_signaling = false; 960 switch (timing) { 961 case MMC_TIMING_UHS_SDR50: 962 break; 963 case MMC_TIMING_UHS_SDR104: 964 case MMC_TIMING_MMC_HS200: 965 /* Don't set default tap on tunable modes. */ 966 iter = TRIES_128; 967 break; 968 case MMC_TIMING_MMC_HS400: 969 set_dqs_trim = true; 970 do_hs400_dll_cal = true; 971 iter = TRIES_128; 972 break; 973 case MMC_TIMING_MMC_DDR52: 974 case MMC_TIMING_UHS_DDR50: 975 tegra_host->ddr_signaling = true; 976 set_default_tap = true; 977 break; 978 default: 979 set_default_tap = true; 980 break; 981 } 982 983 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 984 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 985 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 986 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 987 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 988 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 989 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 990 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 991 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 992 993 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 994 995 sdhci_set_uhs_signaling(host, timing); 996 997 tegra_sdhci_pad_autocalib(host); 998 999 if (tegra_host->tuned_tap_delay && !set_default_tap) 1000 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1001 else 1002 tegra_sdhci_set_tap(host, tegra_host->default_tap); 1003 1004 if (set_dqs_trim) 1005 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1006 1007 if (do_hs400_dll_cal) 1008 tegra_sdhci_hs400_dll_cal(host); 1009 } 1010 1011 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1012 { 1013 unsigned int min, max; 1014 1015 /* 1016 * Start search for minimum tap value at 10, as smaller values are 1017 * may wrongly be reported as working but fail at higher speeds, 1018 * according to the TRM. 1019 */ 1020 min = 10; 1021 while (min < 255) { 1022 tegra_sdhci_set_tap(host, min); 1023 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1024 break; 1025 min++; 1026 } 1027 1028 /* Find the maximum tap value that still passes. */ 1029 max = min + 1; 1030 while (max < 255) { 1031 tegra_sdhci_set_tap(host, max); 1032 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1033 max--; 1034 break; 1035 } 1036 max++; 1037 } 1038 1039 /* The TRM states the ideal tap value is at 75% in the passing range. */ 1040 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1041 1042 return mmc_send_tuning(host->mmc, opcode, NULL); 1043 } 1044 1045 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 1046 struct mmc_ios *ios) 1047 { 1048 struct sdhci_host *host = mmc_priv(mmc); 1049 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1050 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1051 int ret = 0; 1052 1053 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1054 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1055 if (ret < 0) 1056 return ret; 1057 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1058 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 1059 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1060 if (ret < 0) 1061 return ret; 1062 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1063 } 1064 1065 if (tegra_host->pad_calib_required) 1066 tegra_sdhci_pad_autocalib(host); 1067 1068 return ret; 1069 } 1070 1071 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 1072 struct sdhci_tegra *tegra_host) 1073 { 1074 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 1075 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 1076 dev_dbg(dev, "No pinctrl info, err: %ld\n", 1077 PTR_ERR(tegra_host->pinctrl_sdmmc)); 1078 return -1; 1079 } 1080 1081 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1082 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1083 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1084 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1085 tegra_host->pinctrl_state_1v8_drv = NULL; 1086 } 1087 1088 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1089 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1090 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1091 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1092 tegra_host->pinctrl_state_3v3_drv = NULL; 1093 } 1094 1095 tegra_host->pinctrl_state_3v3 = 1096 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 1097 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 1098 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 1099 PTR_ERR(tegra_host->pinctrl_state_3v3)); 1100 return -1; 1101 } 1102 1103 tegra_host->pinctrl_state_1v8 = 1104 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 1105 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 1106 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1107 PTR_ERR(tegra_host->pinctrl_state_1v8)); 1108 return -1; 1109 } 1110 1111 tegra_host->pad_control_available = true; 1112 1113 return 0; 1114 } 1115 1116 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1117 { 1118 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1119 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1120 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1121 1122 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1123 tegra_host->pad_calib_required = true; 1124 } 1125 1126 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 1127 { 1128 struct cqhci_host *cq_host = mmc->cqe_private; 1129 u32 cqcfg = 0; 1130 1131 /* 1132 * Tegra SDMMC Controller design prevents write access to BLOCK_COUNT 1133 * registers when CQE is enabled. 1134 */ 1135 cqcfg = cqhci_readl(cq_host, CQHCI_CFG); 1136 if (cqcfg & CQHCI_ENABLE) 1137 cqhci_writel(cq_host, (cqcfg & ~CQHCI_ENABLE), CQHCI_CFG); 1138 1139 sdhci_cqe_enable(mmc); 1140 1141 if (cqcfg & CQHCI_ENABLE) 1142 cqhci_writel(cq_host, cqcfg, CQHCI_CFG); 1143 } 1144 1145 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 1146 { 1147 sdhci_dumpregs(mmc_priv(mmc)); 1148 } 1149 1150 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 1151 { 1152 int cmd_error = 0; 1153 int data_error = 0; 1154 1155 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1156 return intmask; 1157 1158 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1159 1160 return 0; 1161 } 1162 1163 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1164 .enable = sdhci_tegra_cqe_enable, 1165 .disable = sdhci_cqe_disable, 1166 .dumpregs = sdhci_tegra_dumpregs, 1167 }; 1168 1169 static const struct sdhci_ops tegra_sdhci_ops = { 1170 .read_w = tegra_sdhci_readw, 1171 .write_l = tegra_sdhci_writel, 1172 .set_clock = tegra_sdhci_set_clock, 1173 .set_bus_width = sdhci_set_bus_width, 1174 .reset = tegra_sdhci_reset, 1175 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1176 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1177 .voltage_switch = tegra_sdhci_voltage_switch, 1178 .get_max_clock = tegra_sdhci_get_max_clock, 1179 }; 1180 1181 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 1182 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1183 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1184 SDHCI_QUIRK_NO_HISPD_BIT | 1185 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1186 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1187 .ops = &tegra_sdhci_ops, 1188 }; 1189 1190 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 1191 .pdata = &sdhci_tegra20_pdata, 1192 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 1193 NVQUIRK_ENABLE_BLOCK_GAP_DET, 1194 }; 1195 1196 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1197 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1198 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1199 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1200 SDHCI_QUIRK_NO_HISPD_BIT | 1201 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1202 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1203 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1204 SDHCI_QUIRK2_BROKEN_HS200 | 1205 /* 1206 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1207 * though no command operation was in progress." 1208 * 1209 * The exact reason is unknown, as the same hardware seems 1210 * to support Auto CMD23 on a downstream 3.1 kernel. 1211 */ 1212 SDHCI_QUIRK2_ACMD23_BROKEN, 1213 .ops = &tegra_sdhci_ops, 1214 }; 1215 1216 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1217 .pdata = &sdhci_tegra30_pdata, 1218 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1219 NVQUIRK_ENABLE_SDR50 | 1220 NVQUIRK_ENABLE_SDR104 | 1221 NVQUIRK_HAS_PADCALIB, 1222 }; 1223 1224 static const struct sdhci_ops tegra114_sdhci_ops = { 1225 .read_w = tegra_sdhci_readw, 1226 .write_w = tegra_sdhci_writew, 1227 .write_l = tegra_sdhci_writel, 1228 .set_clock = tegra_sdhci_set_clock, 1229 .set_bus_width = sdhci_set_bus_width, 1230 .reset = tegra_sdhci_reset, 1231 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1232 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1233 .voltage_switch = tegra_sdhci_voltage_switch, 1234 .get_max_clock = tegra_sdhci_get_max_clock, 1235 }; 1236 1237 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1238 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1239 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1240 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1241 SDHCI_QUIRK_NO_HISPD_BIT | 1242 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1243 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1244 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1245 .ops = &tegra114_sdhci_ops, 1246 }; 1247 1248 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1249 .pdata = &sdhci_tegra114_pdata, 1250 }; 1251 1252 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1253 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1254 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1255 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1256 SDHCI_QUIRK_NO_HISPD_BIT | 1257 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1258 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1259 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1260 /* 1261 * The TRM states that the SD/MMC controller found on 1262 * Tegra124 can address 34 bits (the maximum supported by 1263 * the Tegra memory controller), but tests show that DMA 1264 * to or from above 4 GiB doesn't work. This is possibly 1265 * caused by missing programming, though it's not obvious 1266 * what sequence is required. Mark 64-bit DMA broken for 1267 * now to fix this for existing users (e.g. Nyan boards). 1268 */ 1269 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1270 .ops = &tegra114_sdhci_ops, 1271 }; 1272 1273 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1274 .pdata = &sdhci_tegra124_pdata, 1275 }; 1276 1277 static const struct sdhci_ops tegra210_sdhci_ops = { 1278 .read_w = tegra_sdhci_readw, 1279 .write_w = tegra210_sdhci_writew, 1280 .write_l = tegra_sdhci_writel, 1281 .set_clock = tegra_sdhci_set_clock, 1282 .set_bus_width = sdhci_set_bus_width, 1283 .reset = tegra_sdhci_reset, 1284 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1285 .voltage_switch = tegra_sdhci_voltage_switch, 1286 .get_max_clock = tegra_sdhci_get_max_clock, 1287 }; 1288 1289 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1290 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1291 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1292 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1293 SDHCI_QUIRK_NO_HISPD_BIT | 1294 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1295 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1296 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1297 .ops = &tegra210_sdhci_ops, 1298 }; 1299 1300 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1301 .pdata = &sdhci_tegra210_pdata, 1302 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1303 NVQUIRK_HAS_PADCALIB | 1304 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1305 NVQUIRK_ENABLE_SDR50 | 1306 NVQUIRK_ENABLE_SDR104, 1307 .min_tap_delay = 106, 1308 .max_tap_delay = 185, 1309 }; 1310 1311 static const struct sdhci_ops tegra186_sdhci_ops = { 1312 .read_w = tegra_sdhci_readw, 1313 .write_l = tegra_sdhci_writel, 1314 .set_clock = tegra_sdhci_set_clock, 1315 .set_bus_width = sdhci_set_bus_width, 1316 .reset = tegra_sdhci_reset, 1317 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1318 .voltage_switch = tegra_sdhci_voltage_switch, 1319 .get_max_clock = tegra_sdhci_get_max_clock, 1320 .irq = sdhci_tegra_cqhci_irq, 1321 }; 1322 1323 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1324 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1325 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1326 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1327 SDHCI_QUIRK_NO_HISPD_BIT | 1328 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1329 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1330 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1331 /* SDHCI controllers on Tegra186 support 40-bit addressing. 1332 * IOVA addresses are 48-bit wide on Tegra186. 1333 * With 64-bit dma mask used for SDHCI, accesses can 1334 * be broken. Disable 64-bit dma, which would fall back 1335 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 1336 * But it is not supported as of now. 1337 */ 1338 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1339 .ops = &tegra186_sdhci_ops, 1340 }; 1341 1342 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1343 .pdata = &sdhci_tegra186_pdata, 1344 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1345 NVQUIRK_HAS_PADCALIB | 1346 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1347 NVQUIRK_ENABLE_SDR50 | 1348 NVQUIRK_ENABLE_SDR104, 1349 .min_tap_delay = 84, 1350 .max_tap_delay = 136, 1351 }; 1352 1353 static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1354 .pdata = &sdhci_tegra186_pdata, 1355 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1356 NVQUIRK_HAS_PADCALIB | 1357 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1358 NVQUIRK_ENABLE_SDR50 | 1359 NVQUIRK_ENABLE_SDR104, 1360 .min_tap_delay = 96, 1361 .max_tap_delay = 139, 1362 }; 1363 1364 static const struct of_device_id sdhci_tegra_dt_match[] = { 1365 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 1366 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1367 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1368 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1369 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1370 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1371 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1372 {} 1373 }; 1374 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1375 1376 static int sdhci_tegra_add_host(struct sdhci_host *host) 1377 { 1378 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1379 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1380 struct cqhci_host *cq_host; 1381 bool dma64; 1382 int ret; 1383 1384 if (!tegra_host->enable_hwcq) 1385 return sdhci_add_host(host); 1386 1387 sdhci_enable_v4_mode(host); 1388 1389 ret = sdhci_setup_host(host); 1390 if (ret) 1391 return ret; 1392 1393 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1394 1395 cq_host = devm_kzalloc(host->mmc->parent, 1396 sizeof(*cq_host), GFP_KERNEL); 1397 if (!cq_host) { 1398 ret = -ENOMEM; 1399 goto cleanup; 1400 } 1401 1402 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1403 cq_host->ops = &sdhci_tegra_cqhci_ops; 1404 1405 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1406 if (dma64) 1407 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1408 1409 ret = cqhci_init(cq_host, host->mmc, dma64); 1410 if (ret) 1411 goto cleanup; 1412 1413 ret = __sdhci_add_host(host); 1414 if (ret) 1415 goto cleanup; 1416 1417 return 0; 1418 1419 cleanup: 1420 sdhci_cleanup_host(host); 1421 return ret; 1422 } 1423 1424 static int sdhci_tegra_probe(struct platform_device *pdev) 1425 { 1426 const struct of_device_id *match; 1427 const struct sdhci_tegra_soc_data *soc_data; 1428 struct sdhci_host *host; 1429 struct sdhci_pltfm_host *pltfm_host; 1430 struct sdhci_tegra *tegra_host; 1431 struct clk *clk; 1432 int rc; 1433 1434 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1435 if (!match) 1436 return -EINVAL; 1437 soc_data = match->data; 1438 1439 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1440 if (IS_ERR(host)) 1441 return PTR_ERR(host); 1442 pltfm_host = sdhci_priv(host); 1443 1444 tegra_host = sdhci_pltfm_priv(pltfm_host); 1445 tegra_host->ddr_signaling = false; 1446 tegra_host->pad_calib_required = false; 1447 tegra_host->pad_control_available = false; 1448 tegra_host->soc_data = soc_data; 1449 1450 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1451 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1452 if (rc == 0) 1453 host->mmc_host_ops.start_signal_voltage_switch = 1454 sdhci_tegra_start_signal_voltage_switch; 1455 } 1456 1457 /* Hook to periodically rerun pad calibration */ 1458 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1459 host->mmc_host_ops.request = tegra_sdhci_request; 1460 1461 host->mmc_host_ops.hs400_enhanced_strobe = 1462 tegra_sdhci_hs400_enhanced_strobe; 1463 1464 if (!host->ops->platform_execute_tuning) 1465 host->mmc_host_ops.execute_tuning = 1466 tegra_sdhci_execute_hw_tuning; 1467 1468 rc = mmc_of_parse(host->mmc); 1469 if (rc) 1470 goto err_parse_dt; 1471 1472 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1473 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1474 1475 tegra_sdhci_parse_dt(host); 1476 1477 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1478 GPIOD_OUT_HIGH); 1479 if (IS_ERR(tegra_host->power_gpio)) { 1480 rc = PTR_ERR(tegra_host->power_gpio); 1481 goto err_power_req; 1482 } 1483 1484 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1485 if (IS_ERR(clk)) { 1486 dev_err(mmc_dev(host->mmc), "clk err\n"); 1487 rc = PTR_ERR(clk); 1488 goto err_clk_get; 1489 } 1490 clk_prepare_enable(clk); 1491 pltfm_host->clk = clk; 1492 1493 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1494 "sdhci"); 1495 if (IS_ERR(tegra_host->rst)) { 1496 rc = PTR_ERR(tegra_host->rst); 1497 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1498 goto err_rst_get; 1499 } 1500 1501 rc = reset_control_assert(tegra_host->rst); 1502 if (rc) 1503 goto err_rst_get; 1504 1505 usleep_range(2000, 4000); 1506 1507 rc = reset_control_deassert(tegra_host->rst); 1508 if (rc) 1509 goto err_rst_get; 1510 1511 usleep_range(2000, 4000); 1512 1513 rc = sdhci_tegra_add_host(host); 1514 if (rc) 1515 goto err_add_host; 1516 1517 return 0; 1518 1519 err_add_host: 1520 reset_control_assert(tegra_host->rst); 1521 err_rst_get: 1522 clk_disable_unprepare(pltfm_host->clk); 1523 err_clk_get: 1524 err_power_req: 1525 err_parse_dt: 1526 sdhci_pltfm_free(pdev); 1527 return rc; 1528 } 1529 1530 static int sdhci_tegra_remove(struct platform_device *pdev) 1531 { 1532 struct sdhci_host *host = platform_get_drvdata(pdev); 1533 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1534 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1535 1536 sdhci_remove_host(host, 0); 1537 1538 reset_control_assert(tegra_host->rst); 1539 usleep_range(2000, 4000); 1540 clk_disable_unprepare(pltfm_host->clk); 1541 1542 sdhci_pltfm_free(pdev); 1543 1544 return 0; 1545 } 1546 1547 static struct platform_driver sdhci_tegra_driver = { 1548 .driver = { 1549 .name = "sdhci-tegra", 1550 .of_match_table = sdhci_tegra_dt_match, 1551 .pm = &sdhci_pltfm_pmops, 1552 }, 1553 .probe = sdhci_tegra_probe, 1554 .remove = sdhci_tegra_remove, 1555 }; 1556 1557 module_platform_driver(sdhci_tegra_driver); 1558 1559 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1560 MODULE_AUTHOR("Google, Inc."); 1561 MODULE_LICENSE("GPL v2"); 1562