1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 51 #define SDHCI_AUTO_CAL_START BIT(31) 52 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 53 54 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 55 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 56 57 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 58 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 59 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 60 #define NVQUIRK_ENABLE_SDR50 BIT(3) 61 #define NVQUIRK_ENABLE_SDR104 BIT(4) 62 #define NVQUIRK_ENABLE_DDR50 BIT(5) 63 #define NVQUIRK_HAS_PADCALIB BIT(6) 64 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 65 66 struct sdhci_tegra_soc_data { 67 const struct sdhci_pltfm_data *pdata; 68 u32 nvquirks; 69 }; 70 71 struct sdhci_tegra { 72 const struct sdhci_tegra_soc_data *soc_data; 73 struct gpio_desc *power_gpio; 74 bool ddr_signaling; 75 bool pad_calib_required; 76 bool pad_control_available; 77 78 struct reset_control *rst; 79 struct pinctrl *pinctrl_sdmmc; 80 struct pinctrl_state *pinctrl_state_3v3; 81 struct pinctrl_state *pinctrl_state_1v8; 82 }; 83 84 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 85 { 86 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 87 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 88 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 89 90 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 91 (reg == SDHCI_HOST_VERSION))) { 92 /* Erratum: Version register is invalid in HW. */ 93 return SDHCI_SPEC_200; 94 } 95 96 return readw(host->ioaddr + reg); 97 } 98 99 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 100 { 101 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 102 103 switch (reg) { 104 case SDHCI_TRANSFER_MODE: 105 /* 106 * Postpone this write, we must do it together with a 107 * command write that is down below. 108 */ 109 pltfm_host->xfer_mode_shadow = val; 110 return; 111 case SDHCI_COMMAND: 112 writel((val << 16) | pltfm_host->xfer_mode_shadow, 113 host->ioaddr + SDHCI_TRANSFER_MODE); 114 return; 115 } 116 117 writew(val, host->ioaddr + reg); 118 } 119 120 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 121 { 122 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 123 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 124 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 125 126 /* Seems like we're getting spurious timeout and crc errors, so 127 * disable signalling of them. In case of real errors software 128 * timers should take care of eventually detecting them. 129 */ 130 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 131 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 132 133 writel(val, host->ioaddr + reg); 134 135 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 136 (reg == SDHCI_INT_ENABLE))) { 137 /* Erratum: Must enable block gap interrupt detection */ 138 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 139 if (val & SDHCI_INT_CARD_INT) 140 gap_ctrl |= 0x8; 141 else 142 gap_ctrl &= ~0x8; 143 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 144 } 145 } 146 147 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 148 { 149 return mmc_gpio_get_ro(host->mmc); 150 } 151 152 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 153 { 154 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 155 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 156 int has_1v8, has_3v3; 157 158 /* 159 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 160 * voltage configuration in order to perform voltage switching. This 161 * means that valid pinctrl info is required on SDHCI instances capable 162 * of performing voltage switching. Whether or not an SDHCI instance is 163 * capable of voltage switching is determined based on the regulator. 164 */ 165 166 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 167 return true; 168 169 if (IS_ERR(host->mmc->supply.vqmmc)) 170 return false; 171 172 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 173 1700000, 1950000); 174 175 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 176 2700000, 3600000); 177 178 if (has_1v8 == 1 && has_3v3 == 1) 179 return tegra_host->pad_control_available; 180 181 /* Fixed voltage, no pad control required. */ 182 return true; 183 } 184 185 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 186 { 187 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 188 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 189 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 190 u32 misc_ctrl, clk_ctrl; 191 192 sdhci_reset(host, mask); 193 194 if (!(mask & SDHCI_RESET_ALL)) 195 return; 196 197 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 198 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 199 200 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 201 SDHCI_MISC_CTRL_ENABLE_SDR50 | 202 SDHCI_MISC_CTRL_ENABLE_DDR50 | 203 SDHCI_MISC_CTRL_ENABLE_SDR104); 204 205 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 206 207 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 208 /* Erratum: Enable SDHCI spec v3.00 support */ 209 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 210 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 211 /* Advertise UHS modes as supported by host */ 212 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 213 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 214 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 215 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 216 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 217 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 218 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 219 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 220 } 221 222 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 223 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 224 225 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 226 tegra_host->pad_calib_required = true; 227 228 tegra_host->ddr_signaling = false; 229 } 230 231 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 232 { 233 u32 reg; 234 int ret; 235 236 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 237 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 238 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 239 240 usleep_range(1, 2); 241 /* 10 ms timeout */ 242 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 243 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 244 1000, 10000); 245 246 if (ret) 247 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 248 } 249 250 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 251 { 252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 253 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 254 unsigned long host_clk; 255 256 if (!clock) 257 return sdhci_set_clock(host, clock); 258 259 /* 260 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 261 * divider to be configured to divided the host clock by two. The SDHCI 262 * clock divider is calculated as part of sdhci_set_clock() by 263 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 264 * the requested clock rate. 265 * 266 * By setting the host->max_clk to clock * 2 the divider calculation 267 * will always result in the correct value for DDR50/52 modes, 268 * regardless of clock rate rounding, which may happen if the value 269 * from clk_get_rate() is used. 270 */ 271 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 272 clk_set_rate(pltfm_host->clk, host_clk); 273 if (tegra_host->ddr_signaling) 274 host->max_clk = host_clk; 275 else 276 host->max_clk = clk_get_rate(pltfm_host->clk); 277 278 sdhci_set_clock(host, clock); 279 280 if (tegra_host->pad_calib_required) { 281 tegra_sdhci_pad_autocalib(host); 282 tegra_host->pad_calib_required = false; 283 } 284 } 285 286 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 287 unsigned timing) 288 { 289 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 290 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 291 292 if (timing == MMC_TIMING_UHS_DDR50 || 293 timing == MMC_TIMING_MMC_DDR52) 294 tegra_host->ddr_signaling = true; 295 296 sdhci_set_uhs_signaling(host, timing); 297 } 298 299 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 300 { 301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 302 303 return clk_round_rate(pltfm_host->clk, UINT_MAX); 304 } 305 306 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 307 { 308 u32 reg; 309 310 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 311 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 312 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 313 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 314 } 315 316 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 317 { 318 unsigned int min, max; 319 320 /* 321 * Start search for minimum tap value at 10, as smaller values are 322 * may wrongly be reported as working but fail at higher speeds, 323 * according to the TRM. 324 */ 325 min = 10; 326 while (min < 255) { 327 tegra_sdhci_set_tap(host, min); 328 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 329 break; 330 min++; 331 } 332 333 /* Find the maximum tap value that still passes. */ 334 max = min + 1; 335 while (max < 255) { 336 tegra_sdhci_set_tap(host, max); 337 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 338 max--; 339 break; 340 } 341 max++; 342 } 343 344 /* The TRM states the ideal tap value is at 75% in the passing range. */ 345 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 346 347 return mmc_send_tuning(host->mmc, opcode, NULL); 348 } 349 350 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 351 { 352 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 353 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 354 int ret; 355 356 if (!tegra_host->pad_control_available) 357 return 0; 358 359 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 360 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 361 tegra_host->pinctrl_state_1v8); 362 if (ret < 0) 363 dev_err(mmc_dev(host->mmc), 364 "setting 1.8V failed, ret: %d\n", ret); 365 } else { 366 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 367 tegra_host->pinctrl_state_3v3); 368 if (ret < 0) 369 dev_err(mmc_dev(host->mmc), 370 "setting 3.3V failed, ret: %d\n", ret); 371 } 372 373 return ret; 374 } 375 376 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 377 struct mmc_ios *ios) 378 { 379 struct sdhci_host *host = mmc_priv(mmc); 380 int ret = 0; 381 382 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 383 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 384 if (ret < 0) 385 return ret; 386 ret = sdhci_start_signal_voltage_switch(mmc, ios); 387 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 388 ret = sdhci_start_signal_voltage_switch(mmc, ios); 389 if (ret < 0) 390 return ret; 391 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 392 } 393 394 return ret; 395 } 396 397 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 398 struct sdhci_tegra *tegra_host) 399 { 400 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 401 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 402 dev_dbg(dev, "No pinctrl info, err: %ld\n", 403 PTR_ERR(tegra_host->pinctrl_sdmmc)); 404 return -1; 405 } 406 407 tegra_host->pinctrl_state_3v3 = 408 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 409 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 410 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 411 PTR_ERR(tegra_host->pinctrl_state_3v3)); 412 return -1; 413 } 414 415 tegra_host->pinctrl_state_1v8 = 416 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 417 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 418 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 419 PTR_ERR(tegra_host->pinctrl_state_3v3)); 420 return -1; 421 } 422 423 tegra_host->pad_control_available = true; 424 425 return 0; 426 } 427 428 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 429 { 430 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 431 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 432 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 433 434 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 435 tegra_host->pad_calib_required = true; 436 } 437 438 static const struct sdhci_ops tegra_sdhci_ops = { 439 .get_ro = tegra_sdhci_get_ro, 440 .read_w = tegra_sdhci_readw, 441 .write_l = tegra_sdhci_writel, 442 .set_clock = tegra_sdhci_set_clock, 443 .set_bus_width = sdhci_set_bus_width, 444 .reset = tegra_sdhci_reset, 445 .platform_execute_tuning = tegra_sdhci_execute_tuning, 446 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 447 .voltage_switch = tegra_sdhci_voltage_switch, 448 .get_max_clock = tegra_sdhci_get_max_clock, 449 }; 450 451 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 452 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 453 SDHCI_QUIRK_SINGLE_POWER_WRITE | 454 SDHCI_QUIRK_NO_HISPD_BIT | 455 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 456 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 457 .ops = &tegra_sdhci_ops, 458 }; 459 460 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 461 .pdata = &sdhci_tegra20_pdata, 462 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 463 NVQUIRK_ENABLE_BLOCK_GAP_DET, 464 }; 465 466 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 467 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 468 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 469 SDHCI_QUIRK_SINGLE_POWER_WRITE | 470 SDHCI_QUIRK_NO_HISPD_BIT | 471 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 472 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 473 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 474 SDHCI_QUIRK2_BROKEN_HS200 | 475 /* 476 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 477 * though no command operation was in progress." 478 * 479 * The exact reason is unknown, as the same hardware seems 480 * to support Auto CMD23 on a downstream 3.1 kernel. 481 */ 482 SDHCI_QUIRK2_ACMD23_BROKEN, 483 .ops = &tegra_sdhci_ops, 484 }; 485 486 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 487 .pdata = &sdhci_tegra30_pdata, 488 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 489 NVQUIRK_ENABLE_SDR50 | 490 NVQUIRK_ENABLE_SDR104 | 491 NVQUIRK_HAS_PADCALIB, 492 }; 493 494 static const struct sdhci_ops tegra114_sdhci_ops = { 495 .get_ro = tegra_sdhci_get_ro, 496 .read_w = tegra_sdhci_readw, 497 .write_w = tegra_sdhci_writew, 498 .write_l = tegra_sdhci_writel, 499 .set_clock = tegra_sdhci_set_clock, 500 .set_bus_width = sdhci_set_bus_width, 501 .reset = tegra_sdhci_reset, 502 .platform_execute_tuning = tegra_sdhci_execute_tuning, 503 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 504 .voltage_switch = tegra_sdhci_voltage_switch, 505 .get_max_clock = tegra_sdhci_get_max_clock, 506 }; 507 508 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 509 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 510 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 511 SDHCI_QUIRK_SINGLE_POWER_WRITE | 512 SDHCI_QUIRK_NO_HISPD_BIT | 513 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 514 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 515 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 516 .ops = &tegra114_sdhci_ops, 517 }; 518 519 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 520 .pdata = &sdhci_tegra114_pdata, 521 }; 522 523 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 524 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 525 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 526 SDHCI_QUIRK_SINGLE_POWER_WRITE | 527 SDHCI_QUIRK_NO_HISPD_BIT | 528 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 529 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 530 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 531 /* 532 * The TRM states that the SD/MMC controller found on 533 * Tegra124 can address 34 bits (the maximum supported by 534 * the Tegra memory controller), but tests show that DMA 535 * to or from above 4 GiB doesn't work. This is possibly 536 * caused by missing programming, though it's not obvious 537 * what sequence is required. Mark 64-bit DMA broken for 538 * now to fix this for existing users (e.g. Nyan boards). 539 */ 540 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 541 .ops = &tegra114_sdhci_ops, 542 }; 543 544 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 545 .pdata = &sdhci_tegra124_pdata, 546 }; 547 548 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 549 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 550 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 551 SDHCI_QUIRK_SINGLE_POWER_WRITE | 552 SDHCI_QUIRK_NO_HISPD_BIT | 553 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 554 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 555 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 556 .ops = &tegra114_sdhci_ops, 557 }; 558 559 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 560 .pdata = &sdhci_tegra210_pdata, 561 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 562 }; 563 564 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 565 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 566 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 567 SDHCI_QUIRK_SINGLE_POWER_WRITE | 568 SDHCI_QUIRK_NO_HISPD_BIT | 569 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 570 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 571 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 572 /* SDHCI controllers on Tegra186 support 40-bit addressing. 573 * IOVA addresses are 48-bit wide on Tegra186. 574 * With 64-bit dma mask used for SDHCI, accesses can 575 * be broken. Disable 64-bit dma, which would fall back 576 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 577 * But it is not supported as of now. 578 */ 579 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 580 .ops = &tegra114_sdhci_ops, 581 }; 582 583 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 584 .pdata = &sdhci_tegra186_pdata, 585 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL, 586 }; 587 588 static const struct of_device_id sdhci_tegra_dt_match[] = { 589 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 590 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 591 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 592 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 593 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 594 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 595 {} 596 }; 597 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 598 599 static int sdhci_tegra_probe(struct platform_device *pdev) 600 { 601 const struct of_device_id *match; 602 const struct sdhci_tegra_soc_data *soc_data; 603 struct sdhci_host *host; 604 struct sdhci_pltfm_host *pltfm_host; 605 struct sdhci_tegra *tegra_host; 606 struct clk *clk; 607 int rc; 608 609 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 610 if (!match) 611 return -EINVAL; 612 soc_data = match->data; 613 614 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 615 if (IS_ERR(host)) 616 return PTR_ERR(host); 617 pltfm_host = sdhci_priv(host); 618 619 tegra_host = sdhci_pltfm_priv(pltfm_host); 620 tegra_host->ddr_signaling = false; 621 tegra_host->pad_calib_required = false; 622 tegra_host->pad_control_available = false; 623 tegra_host->soc_data = soc_data; 624 625 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 626 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 627 if (rc == 0) 628 host->mmc_host_ops.start_signal_voltage_switch = 629 sdhci_tegra_start_signal_voltage_switch; 630 } 631 632 rc = mmc_of_parse(host->mmc); 633 if (rc) 634 goto err_parse_dt; 635 636 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 637 host->mmc->caps |= MMC_CAP_1_8V_DDR; 638 639 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 640 GPIOD_OUT_HIGH); 641 if (IS_ERR(tegra_host->power_gpio)) { 642 rc = PTR_ERR(tegra_host->power_gpio); 643 goto err_power_req; 644 } 645 646 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 647 if (IS_ERR(clk)) { 648 dev_err(mmc_dev(host->mmc), "clk err\n"); 649 rc = PTR_ERR(clk); 650 goto err_clk_get; 651 } 652 clk_prepare_enable(clk); 653 pltfm_host->clk = clk; 654 655 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 656 "sdhci"); 657 if (IS_ERR(tegra_host->rst)) { 658 rc = PTR_ERR(tegra_host->rst); 659 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 660 goto err_rst_get; 661 } 662 663 rc = reset_control_assert(tegra_host->rst); 664 if (rc) 665 goto err_rst_get; 666 667 usleep_range(2000, 4000); 668 669 rc = reset_control_deassert(tegra_host->rst); 670 if (rc) 671 goto err_rst_get; 672 673 usleep_range(2000, 4000); 674 675 rc = sdhci_add_host(host); 676 if (rc) 677 goto err_add_host; 678 679 return 0; 680 681 err_add_host: 682 reset_control_assert(tegra_host->rst); 683 err_rst_get: 684 clk_disable_unprepare(pltfm_host->clk); 685 err_clk_get: 686 err_power_req: 687 err_parse_dt: 688 sdhci_pltfm_free(pdev); 689 return rc; 690 } 691 692 static int sdhci_tegra_remove(struct platform_device *pdev) 693 { 694 struct sdhci_host *host = platform_get_drvdata(pdev); 695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 696 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 697 698 sdhci_remove_host(host, 0); 699 700 reset_control_assert(tegra_host->rst); 701 usleep_range(2000, 4000); 702 clk_disable_unprepare(pltfm_host->clk); 703 704 sdhci_pltfm_free(pdev); 705 706 return 0; 707 } 708 709 static struct platform_driver sdhci_tegra_driver = { 710 .driver = { 711 .name = "sdhci-tegra", 712 .of_match_table = sdhci_tegra_dt_match, 713 .pm = &sdhci_pltfm_pmops, 714 }, 715 .probe = sdhci_tegra_probe, 716 .remove = sdhci_tegra_remove, 717 }; 718 719 module_platform_driver(sdhci_tegra_driver); 720 721 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 722 MODULE_AUTHOR("Google, Inc."); 723 MODULE_LICENSE("GPL v2"); 724