1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/ktime.h> 34 35 #include "sdhci-pltfm.h" 36 37 /* Tegra SDHOST controller vendor register definitions */ 38 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 39 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 40 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 41 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 42 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 43 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 44 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 45 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 46 47 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 48 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 49 50 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 51 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 52 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 53 54 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 55 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 56 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 57 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 58 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 59 60 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 61 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 62 63 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 64 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 65 66 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 67 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 68 69 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 70 #define SDHCI_AUTO_CAL_START BIT(31) 71 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 72 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 73 74 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 75 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 76 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 77 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 78 79 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 80 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 81 82 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 83 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 84 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 85 #define NVQUIRK_ENABLE_SDR50 BIT(3) 86 #define NVQUIRK_ENABLE_SDR104 BIT(4) 87 #define NVQUIRK_ENABLE_DDR50 BIT(5) 88 #define NVQUIRK_HAS_PADCALIB BIT(6) 89 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 90 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 91 92 struct sdhci_tegra_soc_data { 93 const struct sdhci_pltfm_data *pdata; 94 u32 nvquirks; 95 }; 96 97 /* Magic pull up and pull down pad calibration offsets */ 98 struct sdhci_tegra_autocal_offsets { 99 u32 pull_up_3v3; 100 u32 pull_down_3v3; 101 u32 pull_up_3v3_timeout; 102 u32 pull_down_3v3_timeout; 103 u32 pull_up_1v8; 104 u32 pull_down_1v8; 105 u32 pull_up_1v8_timeout; 106 u32 pull_down_1v8_timeout; 107 u32 pull_up_sdr104; 108 u32 pull_down_sdr104; 109 u32 pull_up_hs400; 110 u32 pull_down_hs400; 111 }; 112 113 struct sdhci_tegra { 114 const struct sdhci_tegra_soc_data *soc_data; 115 struct gpio_desc *power_gpio; 116 bool ddr_signaling; 117 bool pad_calib_required; 118 bool pad_control_available; 119 120 struct reset_control *rst; 121 struct pinctrl *pinctrl_sdmmc; 122 struct pinctrl_state *pinctrl_state_3v3; 123 struct pinctrl_state *pinctrl_state_1v8; 124 125 struct sdhci_tegra_autocal_offsets autocal_offsets; 126 ktime_t last_calib; 127 128 u32 default_tap; 129 u32 default_trim; 130 u32 dqs_trim; 131 }; 132 133 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 134 { 135 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 136 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 137 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 138 139 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 140 (reg == SDHCI_HOST_VERSION))) { 141 /* Erratum: Version register is invalid in HW. */ 142 return SDHCI_SPEC_200; 143 } 144 145 return readw(host->ioaddr + reg); 146 } 147 148 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 149 { 150 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 151 152 switch (reg) { 153 case SDHCI_TRANSFER_MODE: 154 /* 155 * Postpone this write, we must do it together with a 156 * command write that is down below. 157 */ 158 pltfm_host->xfer_mode_shadow = val; 159 return; 160 case SDHCI_COMMAND: 161 writel((val << 16) | pltfm_host->xfer_mode_shadow, 162 host->ioaddr + SDHCI_TRANSFER_MODE); 163 return; 164 } 165 166 writew(val, host->ioaddr + reg); 167 } 168 169 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 170 { 171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 172 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 173 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 174 175 /* Seems like we're getting spurious timeout and crc errors, so 176 * disable signalling of them. In case of real errors software 177 * timers should take care of eventually detecting them. 178 */ 179 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 180 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 181 182 writel(val, host->ioaddr + reg); 183 184 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 185 (reg == SDHCI_INT_ENABLE))) { 186 /* Erratum: Must enable block gap interrupt detection */ 187 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 188 if (val & SDHCI_INT_CARD_INT) 189 gap_ctrl |= 0x8; 190 else 191 gap_ctrl &= ~0x8; 192 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 193 } 194 } 195 196 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 197 { 198 bool status; 199 u32 reg; 200 201 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 202 status = !!(reg & SDHCI_CLOCK_CARD_EN); 203 204 if (status == enable) 205 return status; 206 207 if (enable) 208 reg |= SDHCI_CLOCK_CARD_EN; 209 else 210 reg &= ~SDHCI_CLOCK_CARD_EN; 211 212 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 213 214 return status; 215 } 216 217 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 218 { 219 bool is_tuning_cmd = 0; 220 bool clk_enabled; 221 u8 cmd; 222 223 if (reg == SDHCI_COMMAND) { 224 cmd = SDHCI_GET_CMD(val); 225 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 226 cmd == MMC_SEND_TUNING_BLOCK_HS200; 227 } 228 229 if (is_tuning_cmd) 230 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 231 232 writew(val, host->ioaddr + reg); 233 234 if (is_tuning_cmd) { 235 udelay(1); 236 tegra_sdhci_configure_card_clk(host, clk_enabled); 237 } 238 } 239 240 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 241 { 242 return mmc_gpio_get_ro(host->mmc); 243 } 244 245 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 246 { 247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 248 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 249 int has_1v8, has_3v3; 250 251 /* 252 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 253 * voltage configuration in order to perform voltage switching. This 254 * means that valid pinctrl info is required on SDHCI instances capable 255 * of performing voltage switching. Whether or not an SDHCI instance is 256 * capable of voltage switching is determined based on the regulator. 257 */ 258 259 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 260 return true; 261 262 if (IS_ERR(host->mmc->supply.vqmmc)) 263 return false; 264 265 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 266 1700000, 1950000); 267 268 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 269 2700000, 3600000); 270 271 if (has_1v8 == 1 && has_3v3 == 1) 272 return tegra_host->pad_control_available; 273 274 /* Fixed voltage, no pad control required. */ 275 return true; 276 } 277 278 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 279 { 280 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 281 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 282 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 283 bool card_clk_enabled = false; 284 u32 reg; 285 286 /* 287 * Touching the tap values is a bit tricky on some SoC generations. 288 * The quirk enables a workaround for a glitch that sometimes occurs if 289 * the tap values are changed. 290 */ 291 292 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 293 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 294 295 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 296 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 297 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 298 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 299 300 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 301 card_clk_enabled) { 302 udelay(1); 303 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 304 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 305 } 306 } 307 308 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 309 struct mmc_ios *ios) 310 { 311 struct sdhci_host *host = mmc_priv(mmc); 312 u32 val; 313 314 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 315 316 if (ios->enhanced_strobe) 317 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 318 else 319 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 320 321 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 322 323 } 324 325 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 326 { 327 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 328 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 329 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 330 u32 misc_ctrl, clk_ctrl, pad_ctrl; 331 332 sdhci_reset(host, mask); 333 334 if (!(mask & SDHCI_RESET_ALL)) 335 return; 336 337 tegra_sdhci_set_tap(host, tegra_host->default_tap); 338 339 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 340 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 341 342 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 343 SDHCI_MISC_CTRL_ENABLE_SDR50 | 344 SDHCI_MISC_CTRL_ENABLE_DDR50 | 345 SDHCI_MISC_CTRL_ENABLE_SDR104); 346 347 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 348 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 349 350 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 351 /* Erratum: Enable SDHCI spec v3.00 support */ 352 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 353 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 354 /* Advertise UHS modes as supported by host */ 355 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 356 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 357 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 358 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 359 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 360 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 361 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 362 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 363 } 364 365 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 366 367 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 368 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 369 370 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 371 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 372 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 373 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 374 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 375 376 tegra_host->pad_calib_required = true; 377 } 378 379 tegra_host->ddr_signaling = false; 380 } 381 382 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 383 { 384 u32 val; 385 386 /* 387 * Enable or disable the additional I/O pad used by the drive strength 388 * calibration process. 389 */ 390 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 391 392 if (enable) 393 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 394 else 395 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 396 397 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 398 399 if (enable) 400 usleep_range(1, 2); 401 } 402 403 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 404 u16 pdpu) 405 { 406 u32 reg; 407 408 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 409 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 410 reg |= pdpu; 411 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 412 } 413 414 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 415 { 416 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 417 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 418 struct sdhci_tegra_autocal_offsets offsets = 419 tegra_host->autocal_offsets; 420 struct mmc_ios *ios = &host->mmc->ios; 421 bool card_clk_enabled; 422 u16 pdpu; 423 u32 reg; 424 int ret; 425 426 switch (ios->timing) { 427 case MMC_TIMING_UHS_SDR104: 428 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 429 break; 430 case MMC_TIMING_MMC_HS400: 431 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 432 break; 433 default: 434 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 435 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 436 else 437 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 438 } 439 440 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 441 442 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 443 444 tegra_sdhci_configure_cal_pad(host, true); 445 446 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 447 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 448 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 449 450 usleep_range(1, 2); 451 /* 10 ms timeout */ 452 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 453 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 454 1000, 10000); 455 456 tegra_sdhci_configure_cal_pad(host, false); 457 458 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 459 460 if (ret) { 461 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 462 463 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 464 pdpu = offsets.pull_down_1v8_timeout << 8 | 465 offsets.pull_up_1v8_timeout; 466 else 467 pdpu = offsets.pull_down_3v3_timeout << 8 | 468 offsets.pull_up_3v3_timeout; 469 470 /* Disable automatic calibration and use fixed offsets */ 471 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 472 reg &= ~SDHCI_AUTO_CAL_ENABLE; 473 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 474 475 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 476 } 477 } 478 479 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 480 { 481 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 482 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 483 struct sdhci_tegra_autocal_offsets *autocal = 484 &tegra_host->autocal_offsets; 485 int err; 486 487 err = device_property_read_u32(host->mmc->parent, 488 "nvidia,pad-autocal-pull-up-offset-3v3", 489 &autocal->pull_up_3v3); 490 if (err) 491 autocal->pull_up_3v3 = 0; 492 493 err = device_property_read_u32(host->mmc->parent, 494 "nvidia,pad-autocal-pull-down-offset-3v3", 495 &autocal->pull_down_3v3); 496 if (err) 497 autocal->pull_down_3v3 = 0; 498 499 err = device_property_read_u32(host->mmc->parent, 500 "nvidia,pad-autocal-pull-up-offset-1v8", 501 &autocal->pull_up_1v8); 502 if (err) 503 autocal->pull_up_1v8 = 0; 504 505 err = device_property_read_u32(host->mmc->parent, 506 "nvidia,pad-autocal-pull-down-offset-1v8", 507 &autocal->pull_down_1v8); 508 if (err) 509 autocal->pull_down_1v8 = 0; 510 511 err = device_property_read_u32(host->mmc->parent, 512 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 513 &autocal->pull_up_3v3); 514 if (err) 515 autocal->pull_up_3v3_timeout = 0; 516 517 err = device_property_read_u32(host->mmc->parent, 518 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 519 &autocal->pull_down_3v3); 520 if (err) 521 autocal->pull_down_3v3_timeout = 0; 522 523 err = device_property_read_u32(host->mmc->parent, 524 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 525 &autocal->pull_up_1v8); 526 if (err) 527 autocal->pull_up_1v8_timeout = 0; 528 529 err = device_property_read_u32(host->mmc->parent, 530 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 531 &autocal->pull_down_1v8); 532 if (err) 533 autocal->pull_down_1v8_timeout = 0; 534 535 err = device_property_read_u32(host->mmc->parent, 536 "nvidia,pad-autocal-pull-up-offset-sdr104", 537 &autocal->pull_up_sdr104); 538 if (err) 539 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 540 541 err = device_property_read_u32(host->mmc->parent, 542 "nvidia,pad-autocal-pull-down-offset-sdr104", 543 &autocal->pull_down_sdr104); 544 if (err) 545 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 546 547 err = device_property_read_u32(host->mmc->parent, 548 "nvidia,pad-autocal-pull-up-offset-hs400", 549 &autocal->pull_up_hs400); 550 if (err) 551 autocal->pull_up_hs400 = autocal->pull_up_1v8; 552 553 err = device_property_read_u32(host->mmc->parent, 554 "nvidia,pad-autocal-pull-down-offset-hs400", 555 &autocal->pull_down_hs400); 556 if (err) 557 autocal->pull_down_hs400 = autocal->pull_down_1v8; 558 } 559 560 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 561 { 562 struct sdhci_host *host = mmc_priv(mmc); 563 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 564 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 565 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 566 567 /* 100 ms calibration interval is specified in the TRM */ 568 if (ktime_to_ms(since_calib) > 100) { 569 tegra_sdhci_pad_autocalib(host); 570 tegra_host->last_calib = ktime_get(); 571 } 572 573 sdhci_request(mmc, mrq); 574 } 575 576 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 577 { 578 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 579 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 580 int err; 581 582 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 583 &tegra_host->default_tap); 584 if (err) 585 tegra_host->default_tap = 0; 586 587 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 588 &tegra_host->default_trim); 589 if (err) 590 tegra_host->default_trim = 0; 591 592 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 593 &tegra_host->dqs_trim); 594 if (err) 595 tegra_host->dqs_trim = 0x11; 596 } 597 598 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 599 { 600 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 601 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 602 unsigned long host_clk; 603 604 if (!clock) 605 return sdhci_set_clock(host, clock); 606 607 /* 608 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 609 * divider to be configured to divided the host clock by two. The SDHCI 610 * clock divider is calculated as part of sdhci_set_clock() by 611 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 612 * the requested clock rate. 613 * 614 * By setting the host->max_clk to clock * 2 the divider calculation 615 * will always result in the correct value for DDR50/52 modes, 616 * regardless of clock rate rounding, which may happen if the value 617 * from clk_get_rate() is used. 618 */ 619 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 620 clk_set_rate(pltfm_host->clk, host_clk); 621 if (tegra_host->ddr_signaling) 622 host->max_clk = host_clk; 623 else 624 host->max_clk = clk_get_rate(pltfm_host->clk); 625 626 sdhci_set_clock(host, clock); 627 628 if (tegra_host->pad_calib_required) { 629 tegra_sdhci_pad_autocalib(host); 630 tegra_host->pad_calib_required = false; 631 } 632 } 633 634 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 635 { 636 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 637 638 return clk_round_rate(pltfm_host->clk, UINT_MAX); 639 } 640 641 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 642 { 643 u32 val; 644 645 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 646 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 647 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 648 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 649 } 650 651 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 652 { 653 u32 reg; 654 int err; 655 656 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 657 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 658 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 659 660 /* 1 ms sleep, 5 ms timeout */ 661 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 662 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 663 1000, 5000); 664 if (err) 665 dev_err(mmc_dev(host->mmc), 666 "HS400 delay line calibration timed out\n"); 667 } 668 669 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 670 unsigned timing) 671 { 672 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 673 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 674 bool set_default_tap = false; 675 bool set_dqs_trim = false; 676 bool do_hs400_dll_cal = false; 677 678 switch (timing) { 679 case MMC_TIMING_UHS_SDR50: 680 case MMC_TIMING_UHS_SDR104: 681 case MMC_TIMING_MMC_HS200: 682 /* Don't set default tap on tunable modes. */ 683 break; 684 case MMC_TIMING_MMC_HS400: 685 set_dqs_trim = true; 686 do_hs400_dll_cal = true; 687 break; 688 case MMC_TIMING_MMC_DDR52: 689 case MMC_TIMING_UHS_DDR50: 690 tegra_host->ddr_signaling = true; 691 set_default_tap = true; 692 break; 693 default: 694 set_default_tap = true; 695 break; 696 } 697 698 sdhci_set_uhs_signaling(host, timing); 699 700 tegra_sdhci_pad_autocalib(host); 701 702 if (set_default_tap) 703 tegra_sdhci_set_tap(host, tegra_host->default_tap); 704 705 if (set_dqs_trim) 706 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 707 708 if (do_hs400_dll_cal) 709 tegra_sdhci_hs400_dll_cal(host); 710 } 711 712 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 713 { 714 unsigned int min, max; 715 716 /* 717 * Start search for minimum tap value at 10, as smaller values are 718 * may wrongly be reported as working but fail at higher speeds, 719 * according to the TRM. 720 */ 721 min = 10; 722 while (min < 255) { 723 tegra_sdhci_set_tap(host, min); 724 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 725 break; 726 min++; 727 } 728 729 /* Find the maximum tap value that still passes. */ 730 max = min + 1; 731 while (max < 255) { 732 tegra_sdhci_set_tap(host, max); 733 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 734 max--; 735 break; 736 } 737 max++; 738 } 739 740 /* The TRM states the ideal tap value is at 75% in the passing range. */ 741 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 742 743 return mmc_send_tuning(host->mmc, opcode, NULL); 744 } 745 746 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 747 { 748 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 749 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 750 int ret; 751 752 if (!tegra_host->pad_control_available) 753 return 0; 754 755 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 756 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 757 tegra_host->pinctrl_state_1v8); 758 if (ret < 0) 759 dev_err(mmc_dev(host->mmc), 760 "setting 1.8V failed, ret: %d\n", ret); 761 } else { 762 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 763 tegra_host->pinctrl_state_3v3); 764 if (ret < 0) 765 dev_err(mmc_dev(host->mmc), 766 "setting 3.3V failed, ret: %d\n", ret); 767 } 768 769 return ret; 770 } 771 772 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 773 struct mmc_ios *ios) 774 { 775 struct sdhci_host *host = mmc_priv(mmc); 776 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 777 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 778 int ret = 0; 779 780 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 781 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 782 if (ret < 0) 783 return ret; 784 ret = sdhci_start_signal_voltage_switch(mmc, ios); 785 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 786 ret = sdhci_start_signal_voltage_switch(mmc, ios); 787 if (ret < 0) 788 return ret; 789 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 790 } 791 792 if (tegra_host->pad_calib_required) 793 tegra_sdhci_pad_autocalib(host); 794 795 return ret; 796 } 797 798 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 799 struct sdhci_tegra *tegra_host) 800 { 801 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 802 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 803 dev_dbg(dev, "No pinctrl info, err: %ld\n", 804 PTR_ERR(tegra_host->pinctrl_sdmmc)); 805 return -1; 806 } 807 808 tegra_host->pinctrl_state_3v3 = 809 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 810 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 811 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 812 PTR_ERR(tegra_host->pinctrl_state_3v3)); 813 return -1; 814 } 815 816 tegra_host->pinctrl_state_1v8 = 817 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 818 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 819 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 820 PTR_ERR(tegra_host->pinctrl_state_1v8)); 821 return -1; 822 } 823 824 tegra_host->pad_control_available = true; 825 826 return 0; 827 } 828 829 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 830 { 831 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 832 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 833 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 834 835 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 836 tegra_host->pad_calib_required = true; 837 } 838 839 static const struct sdhci_ops tegra_sdhci_ops = { 840 .get_ro = tegra_sdhci_get_ro, 841 .read_w = tegra_sdhci_readw, 842 .write_l = tegra_sdhci_writel, 843 .set_clock = tegra_sdhci_set_clock, 844 .set_bus_width = sdhci_set_bus_width, 845 .reset = tegra_sdhci_reset, 846 .platform_execute_tuning = tegra_sdhci_execute_tuning, 847 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 848 .voltage_switch = tegra_sdhci_voltage_switch, 849 .get_max_clock = tegra_sdhci_get_max_clock, 850 }; 851 852 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 853 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 854 SDHCI_QUIRK_SINGLE_POWER_WRITE | 855 SDHCI_QUIRK_NO_HISPD_BIT | 856 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 857 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 858 .ops = &tegra_sdhci_ops, 859 }; 860 861 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 862 .pdata = &sdhci_tegra20_pdata, 863 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 864 NVQUIRK_ENABLE_BLOCK_GAP_DET, 865 }; 866 867 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 868 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 869 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 870 SDHCI_QUIRK_SINGLE_POWER_WRITE | 871 SDHCI_QUIRK_NO_HISPD_BIT | 872 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 873 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 874 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 875 SDHCI_QUIRK2_BROKEN_HS200 | 876 /* 877 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 878 * though no command operation was in progress." 879 * 880 * The exact reason is unknown, as the same hardware seems 881 * to support Auto CMD23 on a downstream 3.1 kernel. 882 */ 883 SDHCI_QUIRK2_ACMD23_BROKEN, 884 .ops = &tegra_sdhci_ops, 885 }; 886 887 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 888 .pdata = &sdhci_tegra30_pdata, 889 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 890 NVQUIRK_ENABLE_SDR50 | 891 NVQUIRK_ENABLE_SDR104 | 892 NVQUIRK_HAS_PADCALIB, 893 }; 894 895 static const struct sdhci_ops tegra114_sdhci_ops = { 896 .get_ro = tegra_sdhci_get_ro, 897 .read_w = tegra_sdhci_readw, 898 .write_w = tegra_sdhci_writew, 899 .write_l = tegra_sdhci_writel, 900 .set_clock = tegra_sdhci_set_clock, 901 .set_bus_width = sdhci_set_bus_width, 902 .reset = tegra_sdhci_reset, 903 .platform_execute_tuning = tegra_sdhci_execute_tuning, 904 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 905 .voltage_switch = tegra_sdhci_voltage_switch, 906 .get_max_clock = tegra_sdhci_get_max_clock, 907 }; 908 909 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 910 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 911 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 912 SDHCI_QUIRK_SINGLE_POWER_WRITE | 913 SDHCI_QUIRK_NO_HISPD_BIT | 914 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 915 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 916 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 917 .ops = &tegra114_sdhci_ops, 918 }; 919 920 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 921 .pdata = &sdhci_tegra114_pdata, 922 }; 923 924 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 925 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 926 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 927 SDHCI_QUIRK_SINGLE_POWER_WRITE | 928 SDHCI_QUIRK_NO_HISPD_BIT | 929 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 930 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 931 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 932 /* 933 * The TRM states that the SD/MMC controller found on 934 * Tegra124 can address 34 bits (the maximum supported by 935 * the Tegra memory controller), but tests show that DMA 936 * to or from above 4 GiB doesn't work. This is possibly 937 * caused by missing programming, though it's not obvious 938 * what sequence is required. Mark 64-bit DMA broken for 939 * now to fix this for existing users (e.g. Nyan boards). 940 */ 941 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 942 .ops = &tegra114_sdhci_ops, 943 }; 944 945 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 946 .pdata = &sdhci_tegra124_pdata, 947 }; 948 949 static const struct sdhci_ops tegra210_sdhci_ops = { 950 .get_ro = tegra_sdhci_get_ro, 951 .read_w = tegra_sdhci_readw, 952 .write_w = tegra210_sdhci_writew, 953 .write_l = tegra_sdhci_writel, 954 .set_clock = tegra_sdhci_set_clock, 955 .set_bus_width = sdhci_set_bus_width, 956 .reset = tegra_sdhci_reset, 957 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 958 .voltage_switch = tegra_sdhci_voltage_switch, 959 .get_max_clock = tegra_sdhci_get_max_clock, 960 }; 961 962 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 963 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 964 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 965 SDHCI_QUIRK_SINGLE_POWER_WRITE | 966 SDHCI_QUIRK_NO_HISPD_BIT | 967 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 968 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 969 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 970 .ops = &tegra210_sdhci_ops, 971 }; 972 973 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 974 .pdata = &sdhci_tegra210_pdata, 975 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 976 NVQUIRK_HAS_PADCALIB | 977 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 978 NVQUIRK_ENABLE_SDR50 | 979 NVQUIRK_ENABLE_SDR104, 980 }; 981 982 static const struct sdhci_ops tegra186_sdhci_ops = { 983 .get_ro = tegra_sdhci_get_ro, 984 .read_w = tegra_sdhci_readw, 985 .write_l = tegra_sdhci_writel, 986 .set_clock = tegra_sdhci_set_clock, 987 .set_bus_width = sdhci_set_bus_width, 988 .reset = tegra_sdhci_reset, 989 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 990 .voltage_switch = tegra_sdhci_voltage_switch, 991 .get_max_clock = tegra_sdhci_get_max_clock, 992 }; 993 994 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 995 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 996 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 997 SDHCI_QUIRK_SINGLE_POWER_WRITE | 998 SDHCI_QUIRK_NO_HISPD_BIT | 999 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1000 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1001 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1002 /* SDHCI controllers on Tegra186 support 40-bit addressing. 1003 * IOVA addresses are 48-bit wide on Tegra186. 1004 * With 64-bit dma mask used for SDHCI, accesses can 1005 * be broken. Disable 64-bit dma, which would fall back 1006 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 1007 * But it is not supported as of now. 1008 */ 1009 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1010 .ops = &tegra186_sdhci_ops, 1011 }; 1012 1013 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1014 .pdata = &sdhci_tegra186_pdata, 1015 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1016 NVQUIRK_HAS_PADCALIB | 1017 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1018 NVQUIRK_ENABLE_SDR50 | 1019 NVQUIRK_ENABLE_SDR104, 1020 }; 1021 1022 static const struct of_device_id sdhci_tegra_dt_match[] = { 1023 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1024 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1025 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1026 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1027 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1028 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1029 {} 1030 }; 1031 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1032 1033 static int sdhci_tegra_probe(struct platform_device *pdev) 1034 { 1035 const struct of_device_id *match; 1036 const struct sdhci_tegra_soc_data *soc_data; 1037 struct sdhci_host *host; 1038 struct sdhci_pltfm_host *pltfm_host; 1039 struct sdhci_tegra *tegra_host; 1040 struct clk *clk; 1041 int rc; 1042 1043 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1044 if (!match) 1045 return -EINVAL; 1046 soc_data = match->data; 1047 1048 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1049 if (IS_ERR(host)) 1050 return PTR_ERR(host); 1051 pltfm_host = sdhci_priv(host); 1052 1053 tegra_host = sdhci_pltfm_priv(pltfm_host); 1054 tegra_host->ddr_signaling = false; 1055 tegra_host->pad_calib_required = false; 1056 tegra_host->pad_control_available = false; 1057 tegra_host->soc_data = soc_data; 1058 1059 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1060 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1061 if (rc == 0) 1062 host->mmc_host_ops.start_signal_voltage_switch = 1063 sdhci_tegra_start_signal_voltage_switch; 1064 } 1065 1066 /* Hook to periodically rerun pad calibration */ 1067 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1068 host->mmc_host_ops.request = tegra_sdhci_request; 1069 1070 host->mmc_host_ops.hs400_enhanced_strobe = 1071 tegra_sdhci_hs400_enhanced_strobe; 1072 1073 rc = mmc_of_parse(host->mmc); 1074 if (rc) 1075 goto err_parse_dt; 1076 1077 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1078 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1079 1080 tegra_sdhci_parse_pad_autocal_dt(host); 1081 1082 tegra_sdhci_parse_tap_and_trim(host); 1083 1084 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1085 GPIOD_OUT_HIGH); 1086 if (IS_ERR(tegra_host->power_gpio)) { 1087 rc = PTR_ERR(tegra_host->power_gpio); 1088 goto err_power_req; 1089 } 1090 1091 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1092 if (IS_ERR(clk)) { 1093 dev_err(mmc_dev(host->mmc), "clk err\n"); 1094 rc = PTR_ERR(clk); 1095 goto err_clk_get; 1096 } 1097 clk_prepare_enable(clk); 1098 pltfm_host->clk = clk; 1099 1100 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1101 "sdhci"); 1102 if (IS_ERR(tegra_host->rst)) { 1103 rc = PTR_ERR(tegra_host->rst); 1104 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1105 goto err_rst_get; 1106 } 1107 1108 rc = reset_control_assert(tegra_host->rst); 1109 if (rc) 1110 goto err_rst_get; 1111 1112 usleep_range(2000, 4000); 1113 1114 rc = reset_control_deassert(tegra_host->rst); 1115 if (rc) 1116 goto err_rst_get; 1117 1118 usleep_range(2000, 4000); 1119 1120 rc = sdhci_add_host(host); 1121 if (rc) 1122 goto err_add_host; 1123 1124 return 0; 1125 1126 err_add_host: 1127 reset_control_assert(tegra_host->rst); 1128 err_rst_get: 1129 clk_disable_unprepare(pltfm_host->clk); 1130 err_clk_get: 1131 err_power_req: 1132 err_parse_dt: 1133 sdhci_pltfm_free(pdev); 1134 return rc; 1135 } 1136 1137 static int sdhci_tegra_remove(struct platform_device *pdev) 1138 { 1139 struct sdhci_host *host = platform_get_drvdata(pdev); 1140 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1141 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1142 1143 sdhci_remove_host(host, 0); 1144 1145 reset_control_assert(tegra_host->rst); 1146 usleep_range(2000, 4000); 1147 clk_disable_unprepare(pltfm_host->clk); 1148 1149 sdhci_pltfm_free(pdev); 1150 1151 return 0; 1152 } 1153 1154 static struct platform_driver sdhci_tegra_driver = { 1155 .driver = { 1156 .name = "sdhci-tegra", 1157 .of_match_table = sdhci_tegra_dt_match, 1158 .pm = &sdhci_pltfm_pmops, 1159 }, 1160 .probe = sdhci_tegra_probe, 1161 .remove = sdhci_tegra_remove, 1162 }; 1163 1164 module_platform_driver(sdhci_tegra_driver); 1165 1166 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1167 MODULE_AUTHOR("Google, Inc."); 1168 MODULE_LICENSE("GPL v2"); 1169