1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/ktime.h> 34 35 #include "sdhci-pltfm.h" 36 37 /* Tegra SDHOST controller vendor register definitions */ 38 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 39 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 40 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 41 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 42 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 43 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 44 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 45 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 46 47 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 48 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 49 50 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 51 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 52 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 53 54 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 55 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 56 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 57 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 58 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 59 60 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 61 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 62 63 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 64 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 65 66 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 67 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 68 69 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 70 #define SDHCI_AUTO_CAL_START BIT(31) 71 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 72 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 73 74 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 75 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 76 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 77 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 78 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 79 80 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 81 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 82 83 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 84 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 85 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 86 #define NVQUIRK_ENABLE_SDR50 BIT(3) 87 #define NVQUIRK_ENABLE_SDR104 BIT(4) 88 #define NVQUIRK_ENABLE_DDR50 BIT(5) 89 #define NVQUIRK_HAS_PADCALIB BIT(6) 90 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 91 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 92 93 struct sdhci_tegra_soc_data { 94 const struct sdhci_pltfm_data *pdata; 95 u32 nvquirks; 96 }; 97 98 /* Magic pull up and pull down pad calibration offsets */ 99 struct sdhci_tegra_autocal_offsets { 100 u32 pull_up_3v3; 101 u32 pull_down_3v3; 102 u32 pull_up_3v3_timeout; 103 u32 pull_down_3v3_timeout; 104 u32 pull_up_1v8; 105 u32 pull_down_1v8; 106 u32 pull_up_1v8_timeout; 107 u32 pull_down_1v8_timeout; 108 u32 pull_up_sdr104; 109 u32 pull_down_sdr104; 110 u32 pull_up_hs400; 111 u32 pull_down_hs400; 112 }; 113 114 struct sdhci_tegra { 115 const struct sdhci_tegra_soc_data *soc_data; 116 struct gpio_desc *power_gpio; 117 bool ddr_signaling; 118 bool pad_calib_required; 119 bool pad_control_available; 120 121 struct reset_control *rst; 122 struct pinctrl *pinctrl_sdmmc; 123 struct pinctrl_state *pinctrl_state_3v3; 124 struct pinctrl_state *pinctrl_state_1v8; 125 struct pinctrl_state *pinctrl_state_3v3_drv; 126 struct pinctrl_state *pinctrl_state_1v8_drv; 127 128 struct sdhci_tegra_autocal_offsets autocal_offsets; 129 ktime_t last_calib; 130 131 u32 default_tap; 132 u32 default_trim; 133 u32 dqs_trim; 134 }; 135 136 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 137 { 138 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 139 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 140 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 141 142 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 143 (reg == SDHCI_HOST_VERSION))) { 144 /* Erratum: Version register is invalid in HW. */ 145 return SDHCI_SPEC_200; 146 } 147 148 return readw(host->ioaddr + reg); 149 } 150 151 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 152 { 153 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 154 155 switch (reg) { 156 case SDHCI_TRANSFER_MODE: 157 /* 158 * Postpone this write, we must do it together with a 159 * command write that is down below. 160 */ 161 pltfm_host->xfer_mode_shadow = val; 162 return; 163 case SDHCI_COMMAND: 164 writel((val << 16) | pltfm_host->xfer_mode_shadow, 165 host->ioaddr + SDHCI_TRANSFER_MODE); 166 return; 167 } 168 169 writew(val, host->ioaddr + reg); 170 } 171 172 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 173 { 174 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 175 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 176 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 177 178 /* Seems like we're getting spurious timeout and crc errors, so 179 * disable signalling of them. In case of real errors software 180 * timers should take care of eventually detecting them. 181 */ 182 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 183 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 184 185 writel(val, host->ioaddr + reg); 186 187 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 188 (reg == SDHCI_INT_ENABLE))) { 189 /* Erratum: Must enable block gap interrupt detection */ 190 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 191 if (val & SDHCI_INT_CARD_INT) 192 gap_ctrl |= 0x8; 193 else 194 gap_ctrl &= ~0x8; 195 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 196 } 197 } 198 199 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 200 { 201 bool status; 202 u32 reg; 203 204 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 205 status = !!(reg & SDHCI_CLOCK_CARD_EN); 206 207 if (status == enable) 208 return status; 209 210 if (enable) 211 reg |= SDHCI_CLOCK_CARD_EN; 212 else 213 reg &= ~SDHCI_CLOCK_CARD_EN; 214 215 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 216 217 return status; 218 } 219 220 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 221 { 222 bool is_tuning_cmd = 0; 223 bool clk_enabled; 224 u8 cmd; 225 226 if (reg == SDHCI_COMMAND) { 227 cmd = SDHCI_GET_CMD(val); 228 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 229 cmd == MMC_SEND_TUNING_BLOCK_HS200; 230 } 231 232 if (is_tuning_cmd) 233 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 234 235 writew(val, host->ioaddr + reg); 236 237 if (is_tuning_cmd) { 238 udelay(1); 239 tegra_sdhci_configure_card_clk(host, clk_enabled); 240 } 241 } 242 243 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 244 { 245 return mmc_gpio_get_ro(host->mmc); 246 } 247 248 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 249 { 250 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 251 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 252 int has_1v8, has_3v3; 253 254 /* 255 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 256 * voltage configuration in order to perform voltage switching. This 257 * means that valid pinctrl info is required on SDHCI instances capable 258 * of performing voltage switching. Whether or not an SDHCI instance is 259 * capable of voltage switching is determined based on the regulator. 260 */ 261 262 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 263 return true; 264 265 if (IS_ERR(host->mmc->supply.vqmmc)) 266 return false; 267 268 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 269 1700000, 1950000); 270 271 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 272 2700000, 3600000); 273 274 if (has_1v8 == 1 && has_3v3 == 1) 275 return tegra_host->pad_control_available; 276 277 /* Fixed voltage, no pad control required. */ 278 return true; 279 } 280 281 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 282 { 283 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 284 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 285 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 286 bool card_clk_enabled = false; 287 u32 reg; 288 289 /* 290 * Touching the tap values is a bit tricky on some SoC generations. 291 * The quirk enables a workaround for a glitch that sometimes occurs if 292 * the tap values are changed. 293 */ 294 295 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 296 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 297 298 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 299 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 300 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 301 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 302 303 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 304 card_clk_enabled) { 305 udelay(1); 306 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 307 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 308 } 309 } 310 311 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 312 struct mmc_ios *ios) 313 { 314 struct sdhci_host *host = mmc_priv(mmc); 315 u32 val; 316 317 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 318 319 if (ios->enhanced_strobe) 320 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 321 else 322 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 323 324 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 325 326 } 327 328 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 329 { 330 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 331 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 332 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 333 u32 misc_ctrl, clk_ctrl, pad_ctrl; 334 335 sdhci_reset(host, mask); 336 337 if (!(mask & SDHCI_RESET_ALL)) 338 return; 339 340 tegra_sdhci_set_tap(host, tegra_host->default_tap); 341 342 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 343 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 344 345 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 346 SDHCI_MISC_CTRL_ENABLE_SDR50 | 347 SDHCI_MISC_CTRL_ENABLE_DDR50 | 348 SDHCI_MISC_CTRL_ENABLE_SDR104); 349 350 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 351 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 352 353 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 354 /* Erratum: Enable SDHCI spec v3.00 support */ 355 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 356 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 357 /* Advertise UHS modes as supported by host */ 358 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 359 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 360 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 361 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 362 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 363 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 364 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 365 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 366 } 367 368 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 369 370 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 371 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 372 373 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 374 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 375 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 376 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 377 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 378 379 tegra_host->pad_calib_required = true; 380 } 381 382 tegra_host->ddr_signaling = false; 383 } 384 385 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 386 { 387 u32 val; 388 389 /* 390 * Enable or disable the additional I/O pad used by the drive strength 391 * calibration process. 392 */ 393 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 394 395 if (enable) 396 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 397 else 398 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 399 400 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 401 402 if (enable) 403 usleep_range(1, 2); 404 } 405 406 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 407 u16 pdpu) 408 { 409 u32 reg; 410 411 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 412 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 413 reg |= pdpu; 414 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 415 } 416 417 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 418 bool state_drvupdn) 419 { 420 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 421 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 422 struct sdhci_tegra_autocal_offsets *offsets = 423 &tegra_host->autocal_offsets; 424 struct pinctrl_state *pinctrl_drvupdn = NULL; 425 int ret = 0; 426 u8 drvup = 0, drvdn = 0; 427 u32 reg; 428 429 if (!state_drvupdn) { 430 /* PADS Drive Strength */ 431 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 432 if (tegra_host->pinctrl_state_1v8_drv) { 433 pinctrl_drvupdn = 434 tegra_host->pinctrl_state_1v8_drv; 435 } else { 436 drvup = offsets->pull_up_1v8_timeout; 437 drvdn = offsets->pull_down_1v8_timeout; 438 } 439 } else { 440 if (tegra_host->pinctrl_state_3v3_drv) { 441 pinctrl_drvupdn = 442 tegra_host->pinctrl_state_3v3_drv; 443 } else { 444 drvup = offsets->pull_up_3v3_timeout; 445 drvdn = offsets->pull_down_3v3_timeout; 446 } 447 } 448 449 if (pinctrl_drvupdn != NULL) { 450 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 451 pinctrl_drvupdn); 452 if (ret < 0) 453 dev_err(mmc_dev(host->mmc), 454 "failed pads drvupdn, ret: %d\n", ret); 455 } else if ((drvup) || (drvdn)) { 456 reg = sdhci_readl(host, 457 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 458 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 459 reg |= (drvup << 20) | (drvdn << 12); 460 sdhci_writel(host, reg, 461 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 462 } 463 464 } else { 465 /* Dual Voltage PADS Voltage selection */ 466 if (!tegra_host->pad_control_available) 467 return 0; 468 469 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 470 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 471 tegra_host->pinctrl_state_1v8); 472 if (ret < 0) 473 dev_err(mmc_dev(host->mmc), 474 "setting 1.8V failed, ret: %d\n", ret); 475 } else { 476 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 477 tegra_host->pinctrl_state_3v3); 478 if (ret < 0) 479 dev_err(mmc_dev(host->mmc), 480 "setting 3.3V failed, ret: %d\n", ret); 481 } 482 } 483 484 return ret; 485 } 486 487 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 488 { 489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 490 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 491 struct sdhci_tegra_autocal_offsets offsets = 492 tegra_host->autocal_offsets; 493 struct mmc_ios *ios = &host->mmc->ios; 494 bool card_clk_enabled; 495 u16 pdpu; 496 u32 reg; 497 int ret; 498 499 switch (ios->timing) { 500 case MMC_TIMING_UHS_SDR104: 501 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 502 break; 503 case MMC_TIMING_MMC_HS400: 504 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 505 break; 506 default: 507 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 508 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 509 else 510 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 511 } 512 513 /* Set initial offset before auto-calibration */ 514 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 515 516 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 517 518 tegra_sdhci_configure_cal_pad(host, true); 519 520 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 521 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 522 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 523 524 usleep_range(1, 2); 525 /* 10 ms timeout */ 526 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 527 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 528 1000, 10000); 529 530 tegra_sdhci_configure_cal_pad(host, false); 531 532 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 533 534 if (ret) { 535 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 536 537 /* Disable automatic cal and use fixed Drive Strengths */ 538 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 539 reg &= ~SDHCI_AUTO_CAL_ENABLE; 540 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 541 542 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 543 if (ret < 0) 544 dev_err(mmc_dev(host->mmc), 545 "Setting drive strengths failed: %d\n", ret); 546 } 547 } 548 549 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 550 { 551 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 552 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 553 struct sdhci_tegra_autocal_offsets *autocal = 554 &tegra_host->autocal_offsets; 555 int err; 556 557 err = device_property_read_u32(host->mmc->parent, 558 "nvidia,pad-autocal-pull-up-offset-3v3", 559 &autocal->pull_up_3v3); 560 if (err) 561 autocal->pull_up_3v3 = 0; 562 563 err = device_property_read_u32(host->mmc->parent, 564 "nvidia,pad-autocal-pull-down-offset-3v3", 565 &autocal->pull_down_3v3); 566 if (err) 567 autocal->pull_down_3v3 = 0; 568 569 err = device_property_read_u32(host->mmc->parent, 570 "nvidia,pad-autocal-pull-up-offset-1v8", 571 &autocal->pull_up_1v8); 572 if (err) 573 autocal->pull_up_1v8 = 0; 574 575 err = device_property_read_u32(host->mmc->parent, 576 "nvidia,pad-autocal-pull-down-offset-1v8", 577 &autocal->pull_down_1v8); 578 if (err) 579 autocal->pull_down_1v8 = 0; 580 581 err = device_property_read_u32(host->mmc->parent, 582 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 583 &autocal->pull_up_3v3_timeout); 584 if (err) { 585 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 586 (tegra_host->pinctrl_state_3v3_drv == NULL)) 587 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 588 mmc_hostname(host->mmc)); 589 autocal->pull_up_3v3_timeout = 0; 590 } 591 592 err = device_property_read_u32(host->mmc->parent, 593 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 594 &autocal->pull_down_3v3_timeout); 595 if (err) { 596 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 597 (tegra_host->pinctrl_state_3v3_drv == NULL)) 598 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 599 mmc_hostname(host->mmc)); 600 autocal->pull_down_3v3_timeout = 0; 601 } 602 603 err = device_property_read_u32(host->mmc->parent, 604 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 605 &autocal->pull_up_1v8_timeout); 606 if (err) { 607 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 608 (tegra_host->pinctrl_state_1v8_drv == NULL)) 609 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 610 mmc_hostname(host->mmc)); 611 autocal->pull_up_1v8_timeout = 0; 612 } 613 614 err = device_property_read_u32(host->mmc->parent, 615 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 616 &autocal->pull_down_1v8_timeout); 617 if (err) { 618 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 619 (tegra_host->pinctrl_state_1v8_drv == NULL)) 620 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 621 mmc_hostname(host->mmc)); 622 autocal->pull_down_1v8_timeout = 0; 623 } 624 625 err = device_property_read_u32(host->mmc->parent, 626 "nvidia,pad-autocal-pull-up-offset-sdr104", 627 &autocal->pull_up_sdr104); 628 if (err) 629 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 630 631 err = device_property_read_u32(host->mmc->parent, 632 "nvidia,pad-autocal-pull-down-offset-sdr104", 633 &autocal->pull_down_sdr104); 634 if (err) 635 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 636 637 err = device_property_read_u32(host->mmc->parent, 638 "nvidia,pad-autocal-pull-up-offset-hs400", 639 &autocal->pull_up_hs400); 640 if (err) 641 autocal->pull_up_hs400 = autocal->pull_up_1v8; 642 643 err = device_property_read_u32(host->mmc->parent, 644 "nvidia,pad-autocal-pull-down-offset-hs400", 645 &autocal->pull_down_hs400); 646 if (err) 647 autocal->pull_down_hs400 = autocal->pull_down_1v8; 648 } 649 650 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 651 { 652 struct sdhci_host *host = mmc_priv(mmc); 653 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 654 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 655 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 656 657 /* 100 ms calibration interval is specified in the TRM */ 658 if (ktime_to_ms(since_calib) > 100) { 659 tegra_sdhci_pad_autocalib(host); 660 tegra_host->last_calib = ktime_get(); 661 } 662 663 sdhci_request(mmc, mrq); 664 } 665 666 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 667 { 668 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 669 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 670 int err; 671 672 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 673 &tegra_host->default_tap); 674 if (err) 675 tegra_host->default_tap = 0; 676 677 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 678 &tegra_host->default_trim); 679 if (err) 680 tegra_host->default_trim = 0; 681 682 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 683 &tegra_host->dqs_trim); 684 if (err) 685 tegra_host->dqs_trim = 0x11; 686 } 687 688 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 689 { 690 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 691 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 692 unsigned long host_clk; 693 694 if (!clock) 695 return sdhci_set_clock(host, clock); 696 697 /* 698 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 699 * divider to be configured to divided the host clock by two. The SDHCI 700 * clock divider is calculated as part of sdhci_set_clock() by 701 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 702 * the requested clock rate. 703 * 704 * By setting the host->max_clk to clock * 2 the divider calculation 705 * will always result in the correct value for DDR50/52 modes, 706 * regardless of clock rate rounding, which may happen if the value 707 * from clk_get_rate() is used. 708 */ 709 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 710 clk_set_rate(pltfm_host->clk, host_clk); 711 if (tegra_host->ddr_signaling) 712 host->max_clk = host_clk; 713 else 714 host->max_clk = clk_get_rate(pltfm_host->clk); 715 716 sdhci_set_clock(host, clock); 717 718 if (tegra_host->pad_calib_required) { 719 tegra_sdhci_pad_autocalib(host); 720 tegra_host->pad_calib_required = false; 721 } 722 } 723 724 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 725 { 726 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 727 728 return clk_round_rate(pltfm_host->clk, UINT_MAX); 729 } 730 731 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 732 { 733 u32 val; 734 735 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 736 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 737 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 738 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 739 } 740 741 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 742 { 743 u32 reg; 744 int err; 745 746 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 747 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 748 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 749 750 /* 1 ms sleep, 5 ms timeout */ 751 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 752 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 753 1000, 5000); 754 if (err) 755 dev_err(mmc_dev(host->mmc), 756 "HS400 delay line calibration timed out\n"); 757 } 758 759 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 760 unsigned timing) 761 { 762 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 763 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 764 bool set_default_tap = false; 765 bool set_dqs_trim = false; 766 bool do_hs400_dll_cal = false; 767 768 switch (timing) { 769 case MMC_TIMING_UHS_SDR50: 770 case MMC_TIMING_UHS_SDR104: 771 case MMC_TIMING_MMC_HS200: 772 /* Don't set default tap on tunable modes. */ 773 break; 774 case MMC_TIMING_MMC_HS400: 775 set_dqs_trim = true; 776 do_hs400_dll_cal = true; 777 break; 778 case MMC_TIMING_MMC_DDR52: 779 case MMC_TIMING_UHS_DDR50: 780 tegra_host->ddr_signaling = true; 781 set_default_tap = true; 782 break; 783 default: 784 set_default_tap = true; 785 break; 786 } 787 788 sdhci_set_uhs_signaling(host, timing); 789 790 tegra_sdhci_pad_autocalib(host); 791 792 if (set_default_tap) 793 tegra_sdhci_set_tap(host, tegra_host->default_tap); 794 795 if (set_dqs_trim) 796 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 797 798 if (do_hs400_dll_cal) 799 tegra_sdhci_hs400_dll_cal(host); 800 } 801 802 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 803 { 804 unsigned int min, max; 805 806 /* 807 * Start search for minimum tap value at 10, as smaller values are 808 * may wrongly be reported as working but fail at higher speeds, 809 * according to the TRM. 810 */ 811 min = 10; 812 while (min < 255) { 813 tegra_sdhci_set_tap(host, min); 814 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 815 break; 816 min++; 817 } 818 819 /* Find the maximum tap value that still passes. */ 820 max = min + 1; 821 while (max < 255) { 822 tegra_sdhci_set_tap(host, max); 823 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 824 max--; 825 break; 826 } 827 max++; 828 } 829 830 /* The TRM states the ideal tap value is at 75% in the passing range. */ 831 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 832 833 return mmc_send_tuning(host->mmc, opcode, NULL); 834 } 835 836 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 837 struct mmc_ios *ios) 838 { 839 struct sdhci_host *host = mmc_priv(mmc); 840 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 841 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 842 int ret = 0; 843 844 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 845 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 846 if (ret < 0) 847 return ret; 848 ret = sdhci_start_signal_voltage_switch(mmc, ios); 849 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 850 ret = sdhci_start_signal_voltage_switch(mmc, ios); 851 if (ret < 0) 852 return ret; 853 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 854 } 855 856 if (tegra_host->pad_calib_required) 857 tegra_sdhci_pad_autocalib(host); 858 859 return ret; 860 } 861 862 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 863 struct sdhci_tegra *tegra_host) 864 { 865 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 866 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 867 dev_dbg(dev, "No pinctrl info, err: %ld\n", 868 PTR_ERR(tegra_host->pinctrl_sdmmc)); 869 return -1; 870 } 871 872 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 873 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 874 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 875 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 876 tegra_host->pinctrl_state_1v8_drv = NULL; 877 } 878 879 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 880 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 881 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 882 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 883 tegra_host->pinctrl_state_3v3_drv = NULL; 884 } 885 886 tegra_host->pinctrl_state_3v3 = 887 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 888 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 889 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 890 PTR_ERR(tegra_host->pinctrl_state_3v3)); 891 return -1; 892 } 893 894 tegra_host->pinctrl_state_1v8 = 895 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 896 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 897 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 898 PTR_ERR(tegra_host->pinctrl_state_1v8)); 899 return -1; 900 } 901 902 tegra_host->pad_control_available = true; 903 904 return 0; 905 } 906 907 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 908 { 909 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 910 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 911 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 912 913 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 914 tegra_host->pad_calib_required = true; 915 } 916 917 static const struct sdhci_ops tegra_sdhci_ops = { 918 .get_ro = tegra_sdhci_get_ro, 919 .read_w = tegra_sdhci_readw, 920 .write_l = tegra_sdhci_writel, 921 .set_clock = tegra_sdhci_set_clock, 922 .set_bus_width = sdhci_set_bus_width, 923 .reset = tegra_sdhci_reset, 924 .platform_execute_tuning = tegra_sdhci_execute_tuning, 925 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 926 .voltage_switch = tegra_sdhci_voltage_switch, 927 .get_max_clock = tegra_sdhci_get_max_clock, 928 }; 929 930 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 931 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 932 SDHCI_QUIRK_SINGLE_POWER_WRITE | 933 SDHCI_QUIRK_NO_HISPD_BIT | 934 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 935 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 936 .ops = &tegra_sdhci_ops, 937 }; 938 939 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 940 .pdata = &sdhci_tegra20_pdata, 941 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 942 NVQUIRK_ENABLE_BLOCK_GAP_DET, 943 }; 944 945 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 946 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 947 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 948 SDHCI_QUIRK_SINGLE_POWER_WRITE | 949 SDHCI_QUIRK_NO_HISPD_BIT | 950 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 951 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 952 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 953 SDHCI_QUIRK2_BROKEN_HS200 | 954 /* 955 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 956 * though no command operation was in progress." 957 * 958 * The exact reason is unknown, as the same hardware seems 959 * to support Auto CMD23 on a downstream 3.1 kernel. 960 */ 961 SDHCI_QUIRK2_ACMD23_BROKEN, 962 .ops = &tegra_sdhci_ops, 963 }; 964 965 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 966 .pdata = &sdhci_tegra30_pdata, 967 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 968 NVQUIRK_ENABLE_SDR50 | 969 NVQUIRK_ENABLE_SDR104 | 970 NVQUIRK_HAS_PADCALIB, 971 }; 972 973 static const struct sdhci_ops tegra114_sdhci_ops = { 974 .get_ro = tegra_sdhci_get_ro, 975 .read_w = tegra_sdhci_readw, 976 .write_w = tegra_sdhci_writew, 977 .write_l = tegra_sdhci_writel, 978 .set_clock = tegra_sdhci_set_clock, 979 .set_bus_width = sdhci_set_bus_width, 980 .reset = tegra_sdhci_reset, 981 .platform_execute_tuning = tegra_sdhci_execute_tuning, 982 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 983 .voltage_switch = tegra_sdhci_voltage_switch, 984 .get_max_clock = tegra_sdhci_get_max_clock, 985 }; 986 987 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 988 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 989 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 990 SDHCI_QUIRK_SINGLE_POWER_WRITE | 991 SDHCI_QUIRK_NO_HISPD_BIT | 992 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 993 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 994 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 995 .ops = &tegra114_sdhci_ops, 996 }; 997 998 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 999 .pdata = &sdhci_tegra114_pdata, 1000 }; 1001 1002 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1003 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1004 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1005 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1006 SDHCI_QUIRK_NO_HISPD_BIT | 1007 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1008 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1009 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1010 /* 1011 * The TRM states that the SD/MMC controller found on 1012 * Tegra124 can address 34 bits (the maximum supported by 1013 * the Tegra memory controller), but tests show that DMA 1014 * to or from above 4 GiB doesn't work. This is possibly 1015 * caused by missing programming, though it's not obvious 1016 * what sequence is required. Mark 64-bit DMA broken for 1017 * now to fix this for existing users (e.g. Nyan boards). 1018 */ 1019 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1020 .ops = &tegra114_sdhci_ops, 1021 }; 1022 1023 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1024 .pdata = &sdhci_tegra124_pdata, 1025 }; 1026 1027 static const struct sdhci_ops tegra210_sdhci_ops = { 1028 .get_ro = tegra_sdhci_get_ro, 1029 .read_w = tegra_sdhci_readw, 1030 .write_w = tegra210_sdhci_writew, 1031 .write_l = tegra_sdhci_writel, 1032 .set_clock = tegra_sdhci_set_clock, 1033 .set_bus_width = sdhci_set_bus_width, 1034 .reset = tegra_sdhci_reset, 1035 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1036 .voltage_switch = tegra_sdhci_voltage_switch, 1037 .get_max_clock = tegra_sdhci_get_max_clock, 1038 }; 1039 1040 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1041 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1042 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1043 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1044 SDHCI_QUIRK_NO_HISPD_BIT | 1045 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1046 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1047 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1048 .ops = &tegra210_sdhci_ops, 1049 }; 1050 1051 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1052 .pdata = &sdhci_tegra210_pdata, 1053 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1054 NVQUIRK_HAS_PADCALIB | 1055 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1056 NVQUIRK_ENABLE_SDR50 | 1057 NVQUIRK_ENABLE_SDR104, 1058 }; 1059 1060 static const struct sdhci_ops tegra186_sdhci_ops = { 1061 .get_ro = tegra_sdhci_get_ro, 1062 .read_w = tegra_sdhci_readw, 1063 .write_l = tegra_sdhci_writel, 1064 .set_clock = tegra_sdhci_set_clock, 1065 .set_bus_width = sdhci_set_bus_width, 1066 .reset = tegra_sdhci_reset, 1067 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1068 .voltage_switch = tegra_sdhci_voltage_switch, 1069 .get_max_clock = tegra_sdhci_get_max_clock, 1070 }; 1071 1072 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1073 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1074 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1075 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1076 SDHCI_QUIRK_NO_HISPD_BIT | 1077 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1078 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1079 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1080 /* SDHCI controllers on Tegra186 support 40-bit addressing. 1081 * IOVA addresses are 48-bit wide on Tegra186. 1082 * With 64-bit dma mask used for SDHCI, accesses can 1083 * be broken. Disable 64-bit dma, which would fall back 1084 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 1085 * But it is not supported as of now. 1086 */ 1087 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 1088 .ops = &tegra186_sdhci_ops, 1089 }; 1090 1091 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1092 .pdata = &sdhci_tegra186_pdata, 1093 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1094 NVQUIRK_HAS_PADCALIB | 1095 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1096 NVQUIRK_ENABLE_SDR50 | 1097 NVQUIRK_ENABLE_SDR104, 1098 }; 1099 1100 static const struct of_device_id sdhci_tegra_dt_match[] = { 1101 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1102 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1103 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1104 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1105 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1106 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1107 {} 1108 }; 1109 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1110 1111 static int sdhci_tegra_probe(struct platform_device *pdev) 1112 { 1113 const struct of_device_id *match; 1114 const struct sdhci_tegra_soc_data *soc_data; 1115 struct sdhci_host *host; 1116 struct sdhci_pltfm_host *pltfm_host; 1117 struct sdhci_tegra *tegra_host; 1118 struct clk *clk; 1119 int rc; 1120 1121 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1122 if (!match) 1123 return -EINVAL; 1124 soc_data = match->data; 1125 1126 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1127 if (IS_ERR(host)) 1128 return PTR_ERR(host); 1129 pltfm_host = sdhci_priv(host); 1130 1131 tegra_host = sdhci_pltfm_priv(pltfm_host); 1132 tegra_host->ddr_signaling = false; 1133 tegra_host->pad_calib_required = false; 1134 tegra_host->pad_control_available = false; 1135 tegra_host->soc_data = soc_data; 1136 1137 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1138 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1139 if (rc == 0) 1140 host->mmc_host_ops.start_signal_voltage_switch = 1141 sdhci_tegra_start_signal_voltage_switch; 1142 } 1143 1144 /* Hook to periodically rerun pad calibration */ 1145 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1146 host->mmc_host_ops.request = tegra_sdhci_request; 1147 1148 host->mmc_host_ops.hs400_enhanced_strobe = 1149 tegra_sdhci_hs400_enhanced_strobe; 1150 1151 rc = mmc_of_parse(host->mmc); 1152 if (rc) 1153 goto err_parse_dt; 1154 1155 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1156 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1157 1158 tegra_sdhci_parse_pad_autocal_dt(host); 1159 1160 tegra_sdhci_parse_tap_and_trim(host); 1161 1162 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1163 GPIOD_OUT_HIGH); 1164 if (IS_ERR(tegra_host->power_gpio)) { 1165 rc = PTR_ERR(tegra_host->power_gpio); 1166 goto err_power_req; 1167 } 1168 1169 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1170 if (IS_ERR(clk)) { 1171 dev_err(mmc_dev(host->mmc), "clk err\n"); 1172 rc = PTR_ERR(clk); 1173 goto err_clk_get; 1174 } 1175 clk_prepare_enable(clk); 1176 pltfm_host->clk = clk; 1177 1178 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1179 "sdhci"); 1180 if (IS_ERR(tegra_host->rst)) { 1181 rc = PTR_ERR(tegra_host->rst); 1182 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1183 goto err_rst_get; 1184 } 1185 1186 rc = reset_control_assert(tegra_host->rst); 1187 if (rc) 1188 goto err_rst_get; 1189 1190 usleep_range(2000, 4000); 1191 1192 rc = reset_control_deassert(tegra_host->rst); 1193 if (rc) 1194 goto err_rst_get; 1195 1196 usleep_range(2000, 4000); 1197 1198 rc = sdhci_add_host(host); 1199 if (rc) 1200 goto err_add_host; 1201 1202 return 0; 1203 1204 err_add_host: 1205 reset_control_assert(tegra_host->rst); 1206 err_rst_get: 1207 clk_disable_unprepare(pltfm_host->clk); 1208 err_clk_get: 1209 err_power_req: 1210 err_parse_dt: 1211 sdhci_pltfm_free(pdev); 1212 return rc; 1213 } 1214 1215 static int sdhci_tegra_remove(struct platform_device *pdev) 1216 { 1217 struct sdhci_host *host = platform_get_drvdata(pdev); 1218 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1219 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1220 1221 sdhci_remove_host(host, 0); 1222 1223 reset_control_assert(tegra_host->rst); 1224 usleep_range(2000, 4000); 1225 clk_disable_unprepare(pltfm_host->clk); 1226 1227 sdhci_pltfm_free(pdev); 1228 1229 return 0; 1230 } 1231 1232 static struct platform_driver sdhci_tegra_driver = { 1233 .driver = { 1234 .name = "sdhci-tegra", 1235 .of_match_table = sdhci_tegra_dt_match, 1236 .pm = &sdhci_pltfm_pmops, 1237 }, 1238 .probe = sdhci_tegra_probe, 1239 .remove = sdhci_tegra_remove, 1240 }; 1241 1242 module_platform_driver(sdhci_tegra_driver); 1243 1244 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1245 MODULE_AUTHOR("Google, Inc."); 1246 MODULE_LICENSE("GPL v2"); 1247