1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 51 #define SDHCI_AUTO_CAL_START BIT(31) 52 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 53 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 54 55 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 56 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 57 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 58 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 59 60 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 61 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 62 63 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 64 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 65 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 66 #define NVQUIRK_ENABLE_SDR50 BIT(3) 67 #define NVQUIRK_ENABLE_SDR104 BIT(4) 68 #define NVQUIRK_ENABLE_DDR50 BIT(5) 69 #define NVQUIRK_HAS_PADCALIB BIT(6) 70 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 71 72 struct sdhci_tegra_soc_data { 73 const struct sdhci_pltfm_data *pdata; 74 u32 nvquirks; 75 }; 76 77 /* Magic pull up and pull down pad calibration offsets */ 78 struct sdhci_tegra_autocal_offsets { 79 u32 pull_up_3v3; 80 u32 pull_down_3v3; 81 u32 pull_up_3v3_timeout; 82 u32 pull_down_3v3_timeout; 83 u32 pull_up_1v8; 84 u32 pull_down_1v8; 85 u32 pull_up_1v8_timeout; 86 u32 pull_down_1v8_timeout; 87 u32 pull_up_sdr104; 88 u32 pull_down_sdr104; 89 u32 pull_up_hs400; 90 u32 pull_down_hs400; 91 }; 92 93 struct sdhci_tegra { 94 const struct sdhci_tegra_soc_data *soc_data; 95 struct gpio_desc *power_gpio; 96 bool ddr_signaling; 97 bool pad_calib_required; 98 bool pad_control_available; 99 100 struct reset_control *rst; 101 struct pinctrl *pinctrl_sdmmc; 102 struct pinctrl_state *pinctrl_state_3v3; 103 struct pinctrl_state *pinctrl_state_1v8; 104 105 struct sdhci_tegra_autocal_offsets autocal_offsets; 106 }; 107 108 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 109 { 110 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 111 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 112 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 113 114 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 115 (reg == SDHCI_HOST_VERSION))) { 116 /* Erratum: Version register is invalid in HW. */ 117 return SDHCI_SPEC_200; 118 } 119 120 return readw(host->ioaddr + reg); 121 } 122 123 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 124 { 125 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 126 127 switch (reg) { 128 case SDHCI_TRANSFER_MODE: 129 /* 130 * Postpone this write, we must do it together with a 131 * command write that is down below. 132 */ 133 pltfm_host->xfer_mode_shadow = val; 134 return; 135 case SDHCI_COMMAND: 136 writel((val << 16) | pltfm_host->xfer_mode_shadow, 137 host->ioaddr + SDHCI_TRANSFER_MODE); 138 return; 139 } 140 141 writew(val, host->ioaddr + reg); 142 } 143 144 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 145 { 146 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 147 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 148 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 149 150 /* Seems like we're getting spurious timeout and crc errors, so 151 * disable signalling of them. In case of real errors software 152 * timers should take care of eventually detecting them. 153 */ 154 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 155 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 156 157 writel(val, host->ioaddr + reg); 158 159 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 160 (reg == SDHCI_INT_ENABLE))) { 161 /* Erratum: Must enable block gap interrupt detection */ 162 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 163 if (val & SDHCI_INT_CARD_INT) 164 gap_ctrl |= 0x8; 165 else 166 gap_ctrl &= ~0x8; 167 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 168 } 169 } 170 171 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 172 { 173 return mmc_gpio_get_ro(host->mmc); 174 } 175 176 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 177 { 178 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 179 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 180 int has_1v8, has_3v3; 181 182 /* 183 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 184 * voltage configuration in order to perform voltage switching. This 185 * means that valid pinctrl info is required on SDHCI instances capable 186 * of performing voltage switching. Whether or not an SDHCI instance is 187 * capable of voltage switching is determined based on the regulator. 188 */ 189 190 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 191 return true; 192 193 if (IS_ERR(host->mmc->supply.vqmmc)) 194 return false; 195 196 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 197 1700000, 1950000); 198 199 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 200 2700000, 3600000); 201 202 if (has_1v8 == 1 && has_3v3 == 1) 203 return tegra_host->pad_control_available; 204 205 /* Fixed voltage, no pad control required. */ 206 return true; 207 } 208 209 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 210 { 211 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 212 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 213 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 214 u32 misc_ctrl, clk_ctrl, pad_ctrl; 215 216 sdhci_reset(host, mask); 217 218 if (!(mask & SDHCI_RESET_ALL)) 219 return; 220 221 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 222 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 223 224 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 225 SDHCI_MISC_CTRL_ENABLE_SDR50 | 226 SDHCI_MISC_CTRL_ENABLE_DDR50 | 227 SDHCI_MISC_CTRL_ENABLE_SDR104); 228 229 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 230 231 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 232 /* Erratum: Enable SDHCI spec v3.00 support */ 233 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 234 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 235 /* Advertise UHS modes as supported by host */ 236 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 237 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 238 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 239 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 240 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 241 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 242 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 243 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 244 } 245 246 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 247 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 248 249 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 250 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 251 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 252 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 253 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 254 255 tegra_host->pad_calib_required = true; 256 } 257 258 tegra_host->ddr_signaling = false; 259 } 260 261 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 262 { 263 u32 val; 264 265 /* 266 * Enable or disable the additional I/O pad used by the drive strength 267 * calibration process. 268 */ 269 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 270 271 if (enable) 272 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 273 else 274 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 275 276 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 277 278 if (enable) 279 usleep_range(1, 2); 280 } 281 282 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 283 { 284 bool status; 285 u32 reg; 286 287 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 288 status = !!(reg & SDHCI_CLOCK_CARD_EN); 289 290 if (status == enable) 291 return status; 292 293 if (enable) 294 reg |= SDHCI_CLOCK_CARD_EN; 295 else 296 reg &= ~SDHCI_CLOCK_CARD_EN; 297 298 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 299 300 return status; 301 } 302 303 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 304 u16 pdpu) 305 { 306 u32 reg; 307 308 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 309 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 310 reg |= pdpu; 311 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 312 } 313 314 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 315 { 316 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 317 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 318 struct sdhci_tegra_autocal_offsets offsets = 319 tegra_host->autocal_offsets; 320 struct mmc_ios *ios = &host->mmc->ios; 321 bool card_clk_enabled; 322 u16 pdpu; 323 u32 reg; 324 int ret; 325 326 switch (ios->timing) { 327 case MMC_TIMING_UHS_SDR104: 328 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 329 break; 330 case MMC_TIMING_MMC_HS400: 331 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 332 break; 333 default: 334 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 335 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 336 else 337 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 338 } 339 340 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 341 342 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 343 344 tegra_sdhci_configure_cal_pad(host, true); 345 346 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 347 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 348 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 349 350 usleep_range(1, 2); 351 /* 10 ms timeout */ 352 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 353 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 354 1000, 10000); 355 356 tegra_sdhci_configure_cal_pad(host, false); 357 358 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 359 360 if (ret) { 361 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 362 363 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 364 pdpu = offsets.pull_down_1v8_timeout << 8 | 365 offsets.pull_up_1v8_timeout; 366 else 367 pdpu = offsets.pull_down_3v3_timeout << 8 | 368 offsets.pull_up_3v3_timeout; 369 370 /* Disable automatic calibration and use fixed offsets */ 371 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 372 reg &= ~SDHCI_AUTO_CAL_ENABLE; 373 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 374 375 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 376 } 377 } 378 379 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 380 { 381 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 382 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 383 struct sdhci_tegra_autocal_offsets *autocal = 384 &tegra_host->autocal_offsets; 385 int err; 386 387 err = device_property_read_u32(host->mmc->parent, 388 "nvidia,pad-autocal-pull-up-offset-3v3", 389 &autocal->pull_up_3v3); 390 if (err) 391 autocal->pull_up_3v3 = 0; 392 393 err = device_property_read_u32(host->mmc->parent, 394 "nvidia,pad-autocal-pull-down-offset-3v3", 395 &autocal->pull_down_3v3); 396 if (err) 397 autocal->pull_down_3v3 = 0; 398 399 err = device_property_read_u32(host->mmc->parent, 400 "nvidia,pad-autocal-pull-up-offset-1v8", 401 &autocal->pull_up_1v8); 402 if (err) 403 autocal->pull_up_1v8 = 0; 404 405 err = device_property_read_u32(host->mmc->parent, 406 "nvidia,pad-autocal-pull-down-offset-1v8", 407 &autocal->pull_down_1v8); 408 if (err) 409 autocal->pull_down_1v8 = 0; 410 411 err = device_property_read_u32(host->mmc->parent, 412 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 413 &autocal->pull_up_3v3); 414 if (err) 415 autocal->pull_up_3v3_timeout = 0; 416 417 err = device_property_read_u32(host->mmc->parent, 418 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 419 &autocal->pull_down_3v3); 420 if (err) 421 autocal->pull_down_3v3_timeout = 0; 422 423 err = device_property_read_u32(host->mmc->parent, 424 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 425 &autocal->pull_up_1v8); 426 if (err) 427 autocal->pull_up_1v8_timeout = 0; 428 429 err = device_property_read_u32(host->mmc->parent, 430 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 431 &autocal->pull_down_1v8); 432 if (err) 433 autocal->pull_down_1v8_timeout = 0; 434 435 err = device_property_read_u32(host->mmc->parent, 436 "nvidia,pad-autocal-pull-up-offset-sdr104", 437 &autocal->pull_up_sdr104); 438 if (err) 439 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 440 441 err = device_property_read_u32(host->mmc->parent, 442 "nvidia,pad-autocal-pull-down-offset-sdr104", 443 &autocal->pull_down_sdr104); 444 if (err) 445 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 446 447 err = device_property_read_u32(host->mmc->parent, 448 "nvidia,pad-autocal-pull-up-offset-hs400", 449 &autocal->pull_up_hs400); 450 if (err) 451 autocal->pull_up_hs400 = autocal->pull_up_1v8; 452 453 err = device_property_read_u32(host->mmc->parent, 454 "nvidia,pad-autocal-pull-down-offset-hs400", 455 &autocal->pull_down_hs400); 456 if (err) 457 autocal->pull_down_hs400 = autocal->pull_down_1v8; 458 } 459 460 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 461 { 462 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 463 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 464 unsigned long host_clk; 465 466 if (!clock) 467 return sdhci_set_clock(host, clock); 468 469 /* 470 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 471 * divider to be configured to divided the host clock by two. The SDHCI 472 * clock divider is calculated as part of sdhci_set_clock() by 473 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 474 * the requested clock rate. 475 * 476 * By setting the host->max_clk to clock * 2 the divider calculation 477 * will always result in the correct value for DDR50/52 modes, 478 * regardless of clock rate rounding, which may happen if the value 479 * from clk_get_rate() is used. 480 */ 481 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 482 clk_set_rate(pltfm_host->clk, host_clk); 483 if (tegra_host->ddr_signaling) 484 host->max_clk = host_clk; 485 else 486 host->max_clk = clk_get_rate(pltfm_host->clk); 487 488 sdhci_set_clock(host, clock); 489 490 if (tegra_host->pad_calib_required) { 491 tegra_sdhci_pad_autocalib(host); 492 tegra_host->pad_calib_required = false; 493 } 494 } 495 496 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 497 unsigned timing) 498 { 499 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 500 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 501 502 if (timing == MMC_TIMING_UHS_DDR50 || 503 timing == MMC_TIMING_MMC_DDR52) 504 tegra_host->ddr_signaling = true; 505 506 sdhci_set_uhs_signaling(host, timing); 507 } 508 509 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 510 { 511 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 512 513 return clk_round_rate(pltfm_host->clk, UINT_MAX); 514 } 515 516 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 517 { 518 u32 reg; 519 520 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 521 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 522 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 523 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 524 } 525 526 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 527 { 528 unsigned int min, max; 529 530 /* 531 * Start search for minimum tap value at 10, as smaller values are 532 * may wrongly be reported as working but fail at higher speeds, 533 * according to the TRM. 534 */ 535 min = 10; 536 while (min < 255) { 537 tegra_sdhci_set_tap(host, min); 538 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 539 break; 540 min++; 541 } 542 543 /* Find the maximum tap value that still passes. */ 544 max = min + 1; 545 while (max < 255) { 546 tegra_sdhci_set_tap(host, max); 547 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 548 max--; 549 break; 550 } 551 max++; 552 } 553 554 /* The TRM states the ideal tap value is at 75% in the passing range. */ 555 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 556 557 return mmc_send_tuning(host->mmc, opcode, NULL); 558 } 559 560 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 561 { 562 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 563 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 564 int ret; 565 566 if (!tegra_host->pad_control_available) 567 return 0; 568 569 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 570 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 571 tegra_host->pinctrl_state_1v8); 572 if (ret < 0) 573 dev_err(mmc_dev(host->mmc), 574 "setting 1.8V failed, ret: %d\n", ret); 575 } else { 576 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 577 tegra_host->pinctrl_state_3v3); 578 if (ret < 0) 579 dev_err(mmc_dev(host->mmc), 580 "setting 3.3V failed, ret: %d\n", ret); 581 } 582 583 return ret; 584 } 585 586 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 587 struct mmc_ios *ios) 588 { 589 struct sdhci_host *host = mmc_priv(mmc); 590 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 591 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 592 int ret = 0; 593 594 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 595 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 596 if (ret < 0) 597 return ret; 598 ret = sdhci_start_signal_voltage_switch(mmc, ios); 599 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 600 ret = sdhci_start_signal_voltage_switch(mmc, ios); 601 if (ret < 0) 602 return ret; 603 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 604 } 605 606 if (tegra_host->pad_calib_required) 607 tegra_sdhci_pad_autocalib(host); 608 609 return ret; 610 } 611 612 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 613 struct sdhci_tegra *tegra_host) 614 { 615 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 616 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 617 dev_dbg(dev, "No pinctrl info, err: %ld\n", 618 PTR_ERR(tegra_host->pinctrl_sdmmc)); 619 return -1; 620 } 621 622 tegra_host->pinctrl_state_3v3 = 623 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 624 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 625 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 626 PTR_ERR(tegra_host->pinctrl_state_3v3)); 627 return -1; 628 } 629 630 tegra_host->pinctrl_state_1v8 = 631 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 632 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 633 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 634 PTR_ERR(tegra_host->pinctrl_state_3v3)); 635 return -1; 636 } 637 638 tegra_host->pad_control_available = true; 639 640 return 0; 641 } 642 643 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 644 { 645 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 646 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 647 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 648 649 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 650 tegra_host->pad_calib_required = true; 651 } 652 653 static const struct sdhci_ops tegra_sdhci_ops = { 654 .get_ro = tegra_sdhci_get_ro, 655 .read_w = tegra_sdhci_readw, 656 .write_l = tegra_sdhci_writel, 657 .set_clock = tegra_sdhci_set_clock, 658 .set_bus_width = sdhci_set_bus_width, 659 .reset = tegra_sdhci_reset, 660 .platform_execute_tuning = tegra_sdhci_execute_tuning, 661 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 662 .voltage_switch = tegra_sdhci_voltage_switch, 663 .get_max_clock = tegra_sdhci_get_max_clock, 664 }; 665 666 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 667 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 668 SDHCI_QUIRK_SINGLE_POWER_WRITE | 669 SDHCI_QUIRK_NO_HISPD_BIT | 670 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 671 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 672 .ops = &tegra_sdhci_ops, 673 }; 674 675 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 676 .pdata = &sdhci_tegra20_pdata, 677 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 678 NVQUIRK_ENABLE_BLOCK_GAP_DET, 679 }; 680 681 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 682 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 683 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 684 SDHCI_QUIRK_SINGLE_POWER_WRITE | 685 SDHCI_QUIRK_NO_HISPD_BIT | 686 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 687 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 688 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 689 SDHCI_QUIRK2_BROKEN_HS200 | 690 /* 691 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 692 * though no command operation was in progress." 693 * 694 * The exact reason is unknown, as the same hardware seems 695 * to support Auto CMD23 on a downstream 3.1 kernel. 696 */ 697 SDHCI_QUIRK2_ACMD23_BROKEN, 698 .ops = &tegra_sdhci_ops, 699 }; 700 701 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 702 .pdata = &sdhci_tegra30_pdata, 703 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 704 NVQUIRK_ENABLE_SDR50 | 705 NVQUIRK_ENABLE_SDR104 | 706 NVQUIRK_HAS_PADCALIB, 707 }; 708 709 static const struct sdhci_ops tegra114_sdhci_ops = { 710 .get_ro = tegra_sdhci_get_ro, 711 .read_w = tegra_sdhci_readw, 712 .write_w = tegra_sdhci_writew, 713 .write_l = tegra_sdhci_writel, 714 .set_clock = tegra_sdhci_set_clock, 715 .set_bus_width = sdhci_set_bus_width, 716 .reset = tegra_sdhci_reset, 717 .platform_execute_tuning = tegra_sdhci_execute_tuning, 718 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 719 .voltage_switch = tegra_sdhci_voltage_switch, 720 .get_max_clock = tegra_sdhci_get_max_clock, 721 }; 722 723 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 724 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 725 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 726 SDHCI_QUIRK_SINGLE_POWER_WRITE | 727 SDHCI_QUIRK_NO_HISPD_BIT | 728 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 729 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 730 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 731 .ops = &tegra114_sdhci_ops, 732 }; 733 734 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 735 .pdata = &sdhci_tegra114_pdata, 736 }; 737 738 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 739 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 740 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 741 SDHCI_QUIRK_SINGLE_POWER_WRITE | 742 SDHCI_QUIRK_NO_HISPD_BIT | 743 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 744 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 745 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 746 /* 747 * The TRM states that the SD/MMC controller found on 748 * Tegra124 can address 34 bits (the maximum supported by 749 * the Tegra memory controller), but tests show that DMA 750 * to or from above 4 GiB doesn't work. This is possibly 751 * caused by missing programming, though it's not obvious 752 * what sequence is required. Mark 64-bit DMA broken for 753 * now to fix this for existing users (e.g. Nyan boards). 754 */ 755 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 756 .ops = &tegra114_sdhci_ops, 757 }; 758 759 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 760 .pdata = &sdhci_tegra124_pdata, 761 }; 762 763 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 764 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 765 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 766 SDHCI_QUIRK_SINGLE_POWER_WRITE | 767 SDHCI_QUIRK_NO_HISPD_BIT | 768 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 769 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 770 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 771 .ops = &tegra114_sdhci_ops, 772 }; 773 774 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 775 .pdata = &sdhci_tegra210_pdata, 776 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 777 NVQUIRK_HAS_PADCALIB, 778 }; 779 780 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 781 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 782 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 783 SDHCI_QUIRK_SINGLE_POWER_WRITE | 784 SDHCI_QUIRK_NO_HISPD_BIT | 785 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 786 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 787 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 788 /* SDHCI controllers on Tegra186 support 40-bit addressing. 789 * IOVA addresses are 48-bit wide on Tegra186. 790 * With 64-bit dma mask used for SDHCI, accesses can 791 * be broken. Disable 64-bit dma, which would fall back 792 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 793 * But it is not supported as of now. 794 */ 795 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 796 .ops = &tegra114_sdhci_ops, 797 }; 798 799 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 800 .pdata = &sdhci_tegra186_pdata, 801 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 802 NVQUIRK_HAS_PADCALIB, 803 }; 804 805 static const struct of_device_id sdhci_tegra_dt_match[] = { 806 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 807 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 808 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 809 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 810 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 811 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 812 {} 813 }; 814 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 815 816 static int sdhci_tegra_probe(struct platform_device *pdev) 817 { 818 const struct of_device_id *match; 819 const struct sdhci_tegra_soc_data *soc_data; 820 struct sdhci_host *host; 821 struct sdhci_pltfm_host *pltfm_host; 822 struct sdhci_tegra *tegra_host; 823 struct clk *clk; 824 int rc; 825 826 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 827 if (!match) 828 return -EINVAL; 829 soc_data = match->data; 830 831 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 832 if (IS_ERR(host)) 833 return PTR_ERR(host); 834 pltfm_host = sdhci_priv(host); 835 836 tegra_host = sdhci_pltfm_priv(pltfm_host); 837 tegra_host->ddr_signaling = false; 838 tegra_host->pad_calib_required = false; 839 tegra_host->pad_control_available = false; 840 tegra_host->soc_data = soc_data; 841 842 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 843 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 844 if (rc == 0) 845 host->mmc_host_ops.start_signal_voltage_switch = 846 sdhci_tegra_start_signal_voltage_switch; 847 } 848 849 rc = mmc_of_parse(host->mmc); 850 if (rc) 851 goto err_parse_dt; 852 853 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 854 host->mmc->caps |= MMC_CAP_1_8V_DDR; 855 856 tegra_sdhci_parse_pad_autocal_dt(host); 857 858 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 859 GPIOD_OUT_HIGH); 860 if (IS_ERR(tegra_host->power_gpio)) { 861 rc = PTR_ERR(tegra_host->power_gpio); 862 goto err_power_req; 863 } 864 865 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 866 if (IS_ERR(clk)) { 867 dev_err(mmc_dev(host->mmc), "clk err\n"); 868 rc = PTR_ERR(clk); 869 goto err_clk_get; 870 } 871 clk_prepare_enable(clk); 872 pltfm_host->clk = clk; 873 874 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 875 "sdhci"); 876 if (IS_ERR(tegra_host->rst)) { 877 rc = PTR_ERR(tegra_host->rst); 878 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 879 goto err_rst_get; 880 } 881 882 rc = reset_control_assert(tegra_host->rst); 883 if (rc) 884 goto err_rst_get; 885 886 usleep_range(2000, 4000); 887 888 rc = reset_control_deassert(tegra_host->rst); 889 if (rc) 890 goto err_rst_get; 891 892 usleep_range(2000, 4000); 893 894 rc = sdhci_add_host(host); 895 if (rc) 896 goto err_add_host; 897 898 return 0; 899 900 err_add_host: 901 reset_control_assert(tegra_host->rst); 902 err_rst_get: 903 clk_disable_unprepare(pltfm_host->clk); 904 err_clk_get: 905 err_power_req: 906 err_parse_dt: 907 sdhci_pltfm_free(pdev); 908 return rc; 909 } 910 911 static int sdhci_tegra_remove(struct platform_device *pdev) 912 { 913 struct sdhci_host *host = platform_get_drvdata(pdev); 914 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 915 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 916 917 sdhci_remove_host(host, 0); 918 919 reset_control_assert(tegra_host->rst); 920 usleep_range(2000, 4000); 921 clk_disable_unprepare(pltfm_host->clk); 922 923 sdhci_pltfm_free(pdev); 924 925 return 0; 926 } 927 928 static struct platform_driver sdhci_tegra_driver = { 929 .driver = { 930 .name = "sdhci-tegra", 931 .of_match_table = sdhci_tegra_dt_match, 932 .pm = &sdhci_pltfm_pmops, 933 }, 934 .probe = sdhci_tegra_probe, 935 .remove = sdhci_tegra_remove, 936 }; 937 938 module_platform_driver(sdhci_tegra_driver); 939 940 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 941 MODULE_AUTHOR("Google, Inc."); 942 MODULE_LICENSE("GPL v2"); 943