1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/pm_opp.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/mmc/card.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/mmc/slot-gpio.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/ktime.h> 28 29 #include <soc/tegra/common.h> 30 31 #include "sdhci-pltfm.h" 32 #include "cqhci.h" 33 34 /* Tegra SDHOST controller vendor register definitions */ 35 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 36 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 37 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 38 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 39 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 45 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 46 47 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 48 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 49 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 50 51 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 52 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) 53 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 54 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 55 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 56 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 57 58 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 59 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 60 61 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 62 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 63 64 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 65 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 66 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 67 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 68 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 69 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 70 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 71 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 72 #define TRIES_128 2 73 #define TRIES_256 4 74 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 75 76 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 77 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 78 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 79 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 80 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 81 #define TUNING_WORD_BIT_SIZE 32 82 83 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 84 #define SDHCI_AUTO_CAL_START BIT(31) 85 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 86 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 87 88 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 89 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 90 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 91 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 92 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 93 94 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 95 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 96 97 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 98 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 99 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 100 #define NVQUIRK_ENABLE_SDR50 BIT(3) 101 #define NVQUIRK_ENABLE_SDR104 BIT(4) 102 #define NVQUIRK_ENABLE_DDR50 BIT(5) 103 /* 104 * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads 105 * drive strength. 106 */ 107 #define NVQUIRK_HAS_PADCALIB BIT(6) 108 /* 109 * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads. 110 * 3V3/1V8 pad selection happens through pinctrl state selection depending 111 * on the signaling mode. 112 */ 113 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 114 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 115 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) 116 117 /* 118 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra 119 * SDMMC hardware data timeout. 120 */ 121 #define NVQUIRK_HAS_TMCLK BIT(10) 122 123 #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) 124 125 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 126 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 127 128 #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 129 SDHCI_TRNS_BLK_CNT_EN | \ 130 SDHCI_TRNS_DMA) 131 132 struct sdhci_tegra_soc_data { 133 const struct sdhci_pltfm_data *pdata; 134 u64 dma_mask; 135 u32 nvquirks; 136 u8 min_tap_delay; 137 u8 max_tap_delay; 138 }; 139 140 /* Magic pull up and pull down pad calibration offsets */ 141 struct sdhci_tegra_autocal_offsets { 142 u32 pull_up_3v3; 143 u32 pull_down_3v3; 144 u32 pull_up_3v3_timeout; 145 u32 pull_down_3v3_timeout; 146 u32 pull_up_1v8; 147 u32 pull_down_1v8; 148 u32 pull_up_1v8_timeout; 149 u32 pull_down_1v8_timeout; 150 u32 pull_up_sdr104; 151 u32 pull_down_sdr104; 152 u32 pull_up_hs400; 153 u32 pull_down_hs400; 154 }; 155 156 struct sdhci_tegra { 157 const struct sdhci_tegra_soc_data *soc_data; 158 struct gpio_desc *power_gpio; 159 struct clk *tmclk; 160 bool ddr_signaling; 161 bool pad_calib_required; 162 bool pad_control_available; 163 164 struct reset_control *rst; 165 struct pinctrl *pinctrl_sdmmc; 166 struct pinctrl_state *pinctrl_state_3v3; 167 struct pinctrl_state *pinctrl_state_1v8; 168 struct pinctrl_state *pinctrl_state_3v3_drv; 169 struct pinctrl_state *pinctrl_state_1v8_drv; 170 171 struct sdhci_tegra_autocal_offsets autocal_offsets; 172 ktime_t last_calib; 173 174 u32 default_tap; 175 u32 default_trim; 176 u32 dqs_trim; 177 bool enable_hwcq; 178 unsigned long curr_clk_rate; 179 u8 tuned_tap_delay; 180 }; 181 182 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 183 { 184 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 185 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 186 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 187 188 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 189 (reg == SDHCI_HOST_VERSION))) { 190 /* Erratum: Version register is invalid in HW. */ 191 return SDHCI_SPEC_200; 192 } 193 194 return readw(host->ioaddr + reg); 195 } 196 197 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 198 { 199 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 200 201 switch (reg) { 202 case SDHCI_TRANSFER_MODE: 203 /* 204 * Postpone this write, we must do it together with a 205 * command write that is down below. 206 */ 207 pltfm_host->xfer_mode_shadow = val; 208 return; 209 case SDHCI_COMMAND: 210 writel((val << 16) | pltfm_host->xfer_mode_shadow, 211 host->ioaddr + SDHCI_TRANSFER_MODE); 212 return; 213 } 214 215 writew(val, host->ioaddr + reg); 216 } 217 218 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 219 { 220 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 221 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 222 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 223 224 /* Seems like we're getting spurious timeout and crc errors, so 225 * disable signalling of them. In case of real errors software 226 * timers should take care of eventually detecting them. 227 */ 228 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 229 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 230 231 writel(val, host->ioaddr + reg); 232 233 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 234 (reg == SDHCI_INT_ENABLE))) { 235 /* Erratum: Must enable block gap interrupt detection */ 236 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 237 if (val & SDHCI_INT_CARD_INT) 238 gap_ctrl |= 0x8; 239 else 240 gap_ctrl &= ~0x8; 241 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 242 } 243 } 244 245 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 246 { 247 bool status; 248 u32 reg; 249 250 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 251 status = !!(reg & SDHCI_CLOCK_CARD_EN); 252 253 if (status == enable) 254 return status; 255 256 if (enable) 257 reg |= SDHCI_CLOCK_CARD_EN; 258 else 259 reg &= ~SDHCI_CLOCK_CARD_EN; 260 261 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 262 263 return status; 264 } 265 266 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 267 { 268 bool is_tuning_cmd = 0; 269 bool clk_enabled; 270 u8 cmd; 271 272 if (reg == SDHCI_COMMAND) { 273 cmd = SDHCI_GET_CMD(val); 274 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 275 cmd == MMC_SEND_TUNING_BLOCK_HS200; 276 } 277 278 if (is_tuning_cmd) 279 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 280 281 writew(val, host->ioaddr + reg); 282 283 if (is_tuning_cmd) { 284 udelay(1); 285 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 286 tegra_sdhci_configure_card_clk(host, clk_enabled); 287 } 288 } 289 290 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 291 { 292 /* 293 * Write-enable shall be assumed if GPIO is missing in a board's 294 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on 295 * Tegra. 296 */ 297 return mmc_gpio_get_ro(host->mmc); 298 } 299 300 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 301 { 302 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 303 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 304 int has_1v8, has_3v3; 305 306 /* 307 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 308 * voltage configuration in order to perform voltage switching. This 309 * means that valid pinctrl info is required on SDHCI instances capable 310 * of performing voltage switching. Whether or not an SDHCI instance is 311 * capable of voltage switching is determined based on the regulator. 312 */ 313 314 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 315 return true; 316 317 if (IS_ERR(host->mmc->supply.vqmmc)) 318 return false; 319 320 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 321 1700000, 1950000); 322 323 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 324 2700000, 3600000); 325 326 if (has_1v8 == 1 && has_3v3 == 1) 327 return tegra_host->pad_control_available; 328 329 /* Fixed voltage, no pad control required. */ 330 return true; 331 } 332 333 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 334 { 335 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 336 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 337 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 338 bool card_clk_enabled = false; 339 u32 reg; 340 341 /* 342 * Touching the tap values is a bit tricky on some SoC generations. 343 * The quirk enables a workaround for a glitch that sometimes occurs if 344 * the tap values are changed. 345 */ 346 347 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 348 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 349 350 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 351 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 352 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 353 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 354 355 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 356 card_clk_enabled) { 357 udelay(1); 358 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 359 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 360 } 361 } 362 363 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 364 struct mmc_ios *ios) 365 { 366 struct sdhci_host *host = mmc_priv(mmc); 367 u32 val; 368 369 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 370 371 if (ios->enhanced_strobe) 372 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 373 else 374 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 375 376 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 377 378 } 379 380 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 381 { 382 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 383 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 384 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 385 u32 misc_ctrl, clk_ctrl, pad_ctrl; 386 387 sdhci_reset(host, mask); 388 389 if (!(mask & SDHCI_RESET_ALL)) 390 return; 391 392 tegra_sdhci_set_tap(host, tegra_host->default_tap); 393 394 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 395 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 396 397 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 398 SDHCI_MISC_CTRL_ENABLE_SDR50 | 399 SDHCI_MISC_CTRL_ENABLE_DDR50 | 400 SDHCI_MISC_CTRL_ENABLE_SDR104); 401 402 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 403 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 404 405 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 406 /* Erratum: Enable SDHCI spec v3.00 support */ 407 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 408 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 409 /* Advertise UHS modes as supported by host */ 410 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 411 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 412 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 413 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 414 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 415 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 416 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 417 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 418 } 419 420 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 421 422 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 423 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 424 425 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 426 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 427 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 428 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 429 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 430 431 tegra_host->pad_calib_required = true; 432 } 433 434 tegra_host->ddr_signaling = false; 435 } 436 437 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 438 { 439 u32 val; 440 441 /* 442 * Enable or disable the additional I/O pad used by the drive strength 443 * calibration process. 444 */ 445 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 446 447 if (enable) 448 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 449 else 450 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 451 452 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 453 454 if (enable) 455 usleep_range(1, 2); 456 } 457 458 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 459 u16 pdpu) 460 { 461 u32 reg; 462 463 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 464 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 465 reg |= pdpu; 466 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 467 } 468 469 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 470 bool state_drvupdn) 471 { 472 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 473 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 474 struct sdhci_tegra_autocal_offsets *offsets = 475 &tegra_host->autocal_offsets; 476 struct pinctrl_state *pinctrl_drvupdn = NULL; 477 int ret = 0; 478 u8 drvup = 0, drvdn = 0; 479 u32 reg; 480 481 if (!state_drvupdn) { 482 /* PADS Drive Strength */ 483 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 484 if (tegra_host->pinctrl_state_1v8_drv) { 485 pinctrl_drvupdn = 486 tegra_host->pinctrl_state_1v8_drv; 487 } else { 488 drvup = offsets->pull_up_1v8_timeout; 489 drvdn = offsets->pull_down_1v8_timeout; 490 } 491 } else { 492 if (tegra_host->pinctrl_state_3v3_drv) { 493 pinctrl_drvupdn = 494 tegra_host->pinctrl_state_3v3_drv; 495 } else { 496 drvup = offsets->pull_up_3v3_timeout; 497 drvdn = offsets->pull_down_3v3_timeout; 498 } 499 } 500 501 if (pinctrl_drvupdn != NULL) { 502 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 503 pinctrl_drvupdn); 504 if (ret < 0) 505 dev_err(mmc_dev(host->mmc), 506 "failed pads drvupdn, ret: %d\n", ret); 507 } else if ((drvup) || (drvdn)) { 508 reg = sdhci_readl(host, 509 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 510 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 511 reg |= (drvup << 20) | (drvdn << 12); 512 sdhci_writel(host, reg, 513 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 514 } 515 516 } else { 517 /* Dual Voltage PADS Voltage selection */ 518 if (!tegra_host->pad_control_available) 519 return 0; 520 521 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 522 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 523 tegra_host->pinctrl_state_1v8); 524 if (ret < 0) 525 dev_err(mmc_dev(host->mmc), 526 "setting 1.8V failed, ret: %d\n", ret); 527 } else { 528 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 529 tegra_host->pinctrl_state_3v3); 530 if (ret < 0) 531 dev_err(mmc_dev(host->mmc), 532 "setting 3.3V failed, ret: %d\n", ret); 533 } 534 } 535 536 return ret; 537 } 538 539 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 540 { 541 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 542 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 543 struct sdhci_tegra_autocal_offsets offsets = 544 tegra_host->autocal_offsets; 545 struct mmc_ios *ios = &host->mmc->ios; 546 bool card_clk_enabled; 547 u16 pdpu; 548 u32 reg; 549 int ret; 550 551 switch (ios->timing) { 552 case MMC_TIMING_UHS_SDR104: 553 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 554 break; 555 case MMC_TIMING_MMC_HS400: 556 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 557 break; 558 default: 559 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 560 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 561 else 562 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 563 } 564 565 /* Set initial offset before auto-calibration */ 566 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 567 568 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 569 570 tegra_sdhci_configure_cal_pad(host, true); 571 572 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 573 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 574 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 575 576 usleep_range(1, 2); 577 /* 10 ms timeout */ 578 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 579 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 580 1000, 10000); 581 582 tegra_sdhci_configure_cal_pad(host, false); 583 584 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 585 586 if (ret) { 587 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 588 589 /* Disable automatic cal and use fixed Drive Strengths */ 590 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 591 reg &= ~SDHCI_AUTO_CAL_ENABLE; 592 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 593 594 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 595 if (ret < 0) 596 dev_err(mmc_dev(host->mmc), 597 "Setting drive strengths failed: %d\n", ret); 598 } 599 } 600 601 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 602 { 603 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 604 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 605 struct sdhci_tegra_autocal_offsets *autocal = 606 &tegra_host->autocal_offsets; 607 int err; 608 609 err = device_property_read_u32(mmc_dev(host->mmc), 610 "nvidia,pad-autocal-pull-up-offset-3v3", 611 &autocal->pull_up_3v3); 612 if (err) 613 autocal->pull_up_3v3 = 0; 614 615 err = device_property_read_u32(mmc_dev(host->mmc), 616 "nvidia,pad-autocal-pull-down-offset-3v3", 617 &autocal->pull_down_3v3); 618 if (err) 619 autocal->pull_down_3v3 = 0; 620 621 err = device_property_read_u32(mmc_dev(host->mmc), 622 "nvidia,pad-autocal-pull-up-offset-1v8", 623 &autocal->pull_up_1v8); 624 if (err) 625 autocal->pull_up_1v8 = 0; 626 627 err = device_property_read_u32(mmc_dev(host->mmc), 628 "nvidia,pad-autocal-pull-down-offset-1v8", 629 &autocal->pull_down_1v8); 630 if (err) 631 autocal->pull_down_1v8 = 0; 632 633 err = device_property_read_u32(mmc_dev(host->mmc), 634 "nvidia,pad-autocal-pull-up-offset-sdr104", 635 &autocal->pull_up_sdr104); 636 if (err) 637 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 638 639 err = device_property_read_u32(mmc_dev(host->mmc), 640 "nvidia,pad-autocal-pull-down-offset-sdr104", 641 &autocal->pull_down_sdr104); 642 if (err) 643 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 644 645 err = device_property_read_u32(mmc_dev(host->mmc), 646 "nvidia,pad-autocal-pull-up-offset-hs400", 647 &autocal->pull_up_hs400); 648 if (err) 649 autocal->pull_up_hs400 = autocal->pull_up_1v8; 650 651 err = device_property_read_u32(mmc_dev(host->mmc), 652 "nvidia,pad-autocal-pull-down-offset-hs400", 653 &autocal->pull_down_hs400); 654 if (err) 655 autocal->pull_down_hs400 = autocal->pull_down_1v8; 656 657 /* 658 * Different fail-safe drive strength values based on the signaling 659 * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls. 660 * So, avoid reading below device tree properties for SoCs that don't 661 * have NVQUIRK_NEEDS_PAD_CONTROL. 662 */ 663 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 664 return; 665 666 err = device_property_read_u32(mmc_dev(host->mmc), 667 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 668 &autocal->pull_up_3v3_timeout); 669 if (err) { 670 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 671 (tegra_host->pinctrl_state_3v3_drv == NULL)) 672 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 673 mmc_hostname(host->mmc)); 674 autocal->pull_up_3v3_timeout = 0; 675 } 676 677 err = device_property_read_u32(mmc_dev(host->mmc), 678 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 679 &autocal->pull_down_3v3_timeout); 680 if (err) { 681 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 682 (tegra_host->pinctrl_state_3v3_drv == NULL)) 683 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 684 mmc_hostname(host->mmc)); 685 autocal->pull_down_3v3_timeout = 0; 686 } 687 688 err = device_property_read_u32(mmc_dev(host->mmc), 689 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 690 &autocal->pull_up_1v8_timeout); 691 if (err) { 692 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 693 (tegra_host->pinctrl_state_1v8_drv == NULL)) 694 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 695 mmc_hostname(host->mmc)); 696 autocal->pull_up_1v8_timeout = 0; 697 } 698 699 err = device_property_read_u32(mmc_dev(host->mmc), 700 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 701 &autocal->pull_down_1v8_timeout); 702 if (err) { 703 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 704 (tegra_host->pinctrl_state_1v8_drv == NULL)) 705 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 706 mmc_hostname(host->mmc)); 707 autocal->pull_down_1v8_timeout = 0; 708 } 709 } 710 711 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 712 { 713 struct sdhci_host *host = mmc_priv(mmc); 714 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 715 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 716 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 717 718 /* 100 ms calibration interval is specified in the TRM */ 719 if (ktime_to_ms(since_calib) > 100) { 720 tegra_sdhci_pad_autocalib(host); 721 tegra_host->last_calib = ktime_get(); 722 } 723 724 sdhci_request(mmc, mrq); 725 } 726 727 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 728 { 729 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 730 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 731 int err; 732 733 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", 734 &tegra_host->default_tap); 735 if (err) 736 tegra_host->default_tap = 0; 737 738 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", 739 &tegra_host->default_trim); 740 if (err) 741 tegra_host->default_trim = 0; 742 743 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", 744 &tegra_host->dqs_trim); 745 if (err) 746 tegra_host->dqs_trim = 0x11; 747 } 748 749 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 750 { 751 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 752 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 753 754 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) 755 tegra_host->enable_hwcq = true; 756 else 757 tegra_host->enable_hwcq = false; 758 759 tegra_sdhci_parse_pad_autocal_dt(host); 760 tegra_sdhci_parse_tap_and_trim(host); 761 } 762 763 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 764 { 765 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 766 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 767 struct device *dev = mmc_dev(host->mmc); 768 unsigned long host_clk; 769 int err; 770 771 if (!clock) 772 return sdhci_set_clock(host, clock); 773 774 /* 775 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 776 * divider to be configured to divided the host clock by two. The SDHCI 777 * clock divider is calculated as part of sdhci_set_clock() by 778 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 779 * the requested clock rate. 780 * 781 * By setting the host->max_clk to clock * 2 the divider calculation 782 * will always result in the correct value for DDR50/52 modes, 783 * regardless of clock rate rounding, which may happen if the value 784 * from clk_get_rate() is used. 785 */ 786 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 787 788 err = dev_pm_opp_set_rate(dev, host_clk); 789 if (err) 790 dev_err(dev, "failed to set clk rate to %luHz: %d\n", 791 host_clk, err); 792 793 tegra_host->curr_clk_rate = host_clk; 794 if (tegra_host->ddr_signaling) 795 host->max_clk = host_clk; 796 else 797 host->max_clk = clk_get_rate(pltfm_host->clk); 798 799 sdhci_set_clock(host, clock); 800 801 if (tegra_host->pad_calib_required) { 802 tegra_sdhci_pad_autocalib(host); 803 tegra_host->pad_calib_required = false; 804 } 805 } 806 807 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 808 { 809 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 810 811 return clk_round_rate(pltfm_host->clk, UINT_MAX); 812 } 813 814 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 815 { 816 u32 val; 817 818 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 819 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 820 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 821 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 822 } 823 824 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 825 { 826 u32 reg; 827 int err; 828 829 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 830 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 831 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 832 833 /* 1 ms sleep, 5 ms timeout */ 834 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 835 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 836 1000, 5000); 837 if (err) 838 dev_err(mmc_dev(host->mmc), 839 "HS400 delay line calibration timed out\n"); 840 } 841 842 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 843 u8 thd_low, u8 fixed_tap) 844 { 845 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 846 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 847 u32 val, tun_status; 848 u8 word, bit, edge1, tap, window; 849 bool tap_result; 850 bool start_fail = false; 851 bool start_pass = false; 852 bool end_pass = false; 853 bool first_fail = false; 854 bool first_pass = false; 855 u8 start_pass_tap = 0; 856 u8 end_pass_tap = 0; 857 u8 first_fail_tap = 0; 858 u8 first_pass_tap = 0; 859 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 860 861 /* 862 * Read auto-tuned results and extract good valid passing window by 863 * filtering out un-wanted bubble/partial/merged windows. 864 */ 865 for (word = 0; word < total_tuning_words; word++) { 866 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 867 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 868 val |= word; 869 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 870 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 871 bit = 0; 872 while (bit < TUNING_WORD_BIT_SIZE) { 873 tap = word * TUNING_WORD_BIT_SIZE + bit; 874 tap_result = tun_status & (1 << bit); 875 if (!tap_result && !start_fail) { 876 start_fail = true; 877 if (!first_fail) { 878 first_fail_tap = tap; 879 first_fail = true; 880 } 881 882 } else if (tap_result && start_fail && !start_pass) { 883 start_pass_tap = tap; 884 start_pass = true; 885 if (!first_pass) { 886 first_pass_tap = tap; 887 first_pass = true; 888 } 889 890 } else if (!tap_result && start_fail && start_pass && 891 !end_pass) { 892 end_pass_tap = tap - 1; 893 end_pass = true; 894 } else if (tap_result && start_pass && start_fail && 895 end_pass) { 896 window = end_pass_tap - start_pass_tap; 897 /* discard merged window and bubble window */ 898 if (window >= thd_up || window < thd_low) { 899 start_pass_tap = tap; 900 end_pass = false; 901 } else { 902 /* set tap at middle of valid window */ 903 tap = start_pass_tap + window / 2; 904 tegra_host->tuned_tap_delay = tap; 905 return; 906 } 907 } 908 909 bit++; 910 } 911 } 912 913 if (!first_fail) { 914 WARN(1, "no edge detected, continue with hw tuned delay.\n"); 915 } else if (first_pass) { 916 /* set tap location at fixed tap relative to the first edge */ 917 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 918 if (edge1 - 1 > fixed_tap) 919 tegra_host->tuned_tap_delay = edge1 - fixed_tap; 920 else 921 tegra_host->tuned_tap_delay = edge1 + fixed_tap; 922 } 923 } 924 925 static void tegra_sdhci_post_tuning(struct sdhci_host *host) 926 { 927 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 928 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 929 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 930 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 931 u8 fixed_tap, start_tap, end_tap, window_width; 932 u8 thdupper, thdlower; 933 u8 num_iter; 934 u32 clk_rate_mhz, period_ps, bestcase, worstcase; 935 936 /* retain HW tuned tap to use incase if no correction is needed */ 937 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 938 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 939 SDHCI_CLOCK_CTRL_TAP_SHIFT; 940 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 941 min_tap_dly = soc_data->min_tap_delay; 942 max_tap_dly = soc_data->max_tap_delay; 943 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 944 period_ps = USEC_PER_SEC / clk_rate_mhz; 945 bestcase = period_ps / min_tap_dly; 946 worstcase = period_ps / max_tap_dly; 947 /* 948 * Upper and Lower bound thresholds used to detect merged and 949 * bubble windows 950 */ 951 thdupper = (2 * worstcase + bestcase) / 2; 952 thdlower = worstcase / 4; 953 /* 954 * fixed tap is used when HW tuning result contains single edge 955 * and tap is set at fixed tap delay relative to the first edge 956 */ 957 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 958 fixed_tap = avg_tap_dly / 2; 959 960 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 961 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 962 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 963 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 964 window_width = end_tap - start_tap; 965 num_iter = host->tuning_loop_count; 966 /* 967 * partial window includes edges of the tuning range. 968 * merged window includes more taps so window width is higher 969 * than upper threshold. 970 */ 971 if (start_tap == 0 || (end_tap == (num_iter - 1)) || 972 (end_tap == num_iter - 2) || window_width >= thdupper) { 973 pr_debug("%s: Apply tuning correction\n", 974 mmc_hostname(host->mmc)); 975 tegra_sdhci_tap_correction(host, thdupper, thdlower, 976 fixed_tap); 977 } 978 } 979 980 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 981 } 982 983 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 984 { 985 struct sdhci_host *host = mmc_priv(mmc); 986 int err; 987 988 err = sdhci_execute_tuning(mmc, opcode); 989 if (!err && !host->tuning_err) 990 tegra_sdhci_post_tuning(host); 991 992 return err; 993 } 994 995 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 996 unsigned timing) 997 { 998 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 999 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1000 bool set_default_tap = false; 1001 bool set_dqs_trim = false; 1002 bool do_hs400_dll_cal = false; 1003 u8 iter = TRIES_256; 1004 u32 val; 1005 1006 tegra_host->ddr_signaling = false; 1007 switch (timing) { 1008 case MMC_TIMING_UHS_SDR50: 1009 break; 1010 case MMC_TIMING_UHS_SDR104: 1011 case MMC_TIMING_MMC_HS200: 1012 /* Don't set default tap on tunable modes. */ 1013 iter = TRIES_128; 1014 break; 1015 case MMC_TIMING_MMC_HS400: 1016 set_dqs_trim = true; 1017 do_hs400_dll_cal = true; 1018 iter = TRIES_128; 1019 break; 1020 case MMC_TIMING_MMC_DDR52: 1021 case MMC_TIMING_UHS_DDR50: 1022 tegra_host->ddr_signaling = true; 1023 set_default_tap = true; 1024 break; 1025 default: 1026 set_default_tap = true; 1027 break; 1028 } 1029 1030 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 1031 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 1032 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 1033 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 1034 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 1035 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 1036 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 1037 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 1038 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 1039 1040 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 1041 1042 sdhci_set_uhs_signaling(host, timing); 1043 1044 tegra_sdhci_pad_autocalib(host); 1045 1046 if (tegra_host->tuned_tap_delay && !set_default_tap) 1047 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1048 else 1049 tegra_sdhci_set_tap(host, tegra_host->default_tap); 1050 1051 if (set_dqs_trim) 1052 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1053 1054 if (do_hs400_dll_cal) 1055 tegra_sdhci_hs400_dll_cal(host); 1056 } 1057 1058 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1059 { 1060 unsigned int min, max; 1061 1062 /* 1063 * Start search for minimum tap value at 10, as smaller values are 1064 * may wrongly be reported as working but fail at higher speeds, 1065 * according to the TRM. 1066 */ 1067 min = 10; 1068 while (min < 255) { 1069 tegra_sdhci_set_tap(host, min); 1070 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1071 break; 1072 min++; 1073 } 1074 1075 /* Find the maximum tap value that still passes. */ 1076 max = min + 1; 1077 while (max < 255) { 1078 tegra_sdhci_set_tap(host, max); 1079 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1080 max--; 1081 break; 1082 } 1083 max++; 1084 } 1085 1086 /* The TRM states the ideal tap value is at 75% in the passing range. */ 1087 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1088 1089 return mmc_send_tuning(host->mmc, opcode, NULL); 1090 } 1091 1092 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 1093 struct mmc_ios *ios) 1094 { 1095 struct sdhci_host *host = mmc_priv(mmc); 1096 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1097 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1098 int ret = 0; 1099 1100 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1101 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1102 if (ret < 0) 1103 return ret; 1104 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1105 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 1106 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1107 if (ret < 0) 1108 return ret; 1109 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1110 } 1111 1112 if (tegra_host->pad_calib_required) 1113 tegra_sdhci_pad_autocalib(host); 1114 1115 return ret; 1116 } 1117 1118 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 1119 struct sdhci_tegra *tegra_host) 1120 { 1121 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 1122 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 1123 dev_dbg(dev, "No pinctrl info, err: %ld\n", 1124 PTR_ERR(tegra_host->pinctrl_sdmmc)); 1125 return -1; 1126 } 1127 1128 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1129 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1130 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1131 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1132 tegra_host->pinctrl_state_1v8_drv = NULL; 1133 } 1134 1135 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1136 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1137 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1138 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1139 tegra_host->pinctrl_state_3v3_drv = NULL; 1140 } 1141 1142 tegra_host->pinctrl_state_3v3 = 1143 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 1144 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 1145 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 1146 PTR_ERR(tegra_host->pinctrl_state_3v3)); 1147 return -1; 1148 } 1149 1150 tegra_host->pinctrl_state_1v8 = 1151 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 1152 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 1153 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1154 PTR_ERR(tegra_host->pinctrl_state_1v8)); 1155 return -1; 1156 } 1157 1158 tegra_host->pad_control_available = true; 1159 1160 return 0; 1161 } 1162 1163 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1164 { 1165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1166 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1167 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1168 1169 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1170 tegra_host->pad_calib_required = true; 1171 } 1172 1173 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) 1174 { 1175 struct mmc_host *mmc = cq_host->mmc; 1176 struct sdhci_host *host = mmc_priv(mmc); 1177 u8 ctrl; 1178 ktime_t timeout; 1179 bool timed_out; 1180 1181 /* 1182 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to 1183 * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need 1184 * to be re-configured. 1185 * Tegra CQHCI/SDHCI prevents write access to block size register when 1186 * CQE is unhalted. So handling CQE resume sequence here to configure 1187 * SDHCI block registers prior to exiting CQE halt state. 1188 */ 1189 if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && 1190 cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 1191 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1192 sdhci_cqe_enable(mmc); 1193 writel(val, cq_host->mmio + reg); 1194 timeout = ktime_add_us(ktime_get(), 50); 1195 while (1) { 1196 timed_out = ktime_compare(ktime_get(), timeout) > 0; 1197 ctrl = cqhci_readl(cq_host, CQHCI_CTL); 1198 if (!(ctrl & CQHCI_HALT) || timed_out) 1199 break; 1200 } 1201 /* 1202 * CQE usually resumes very quick, but incase if Tegra CQE 1203 * doesn't resume retry unhalt. 1204 */ 1205 if (timed_out) 1206 writel(val, cq_host->mmio + reg); 1207 } else { 1208 writel(val, cq_host->mmio + reg); 1209 } 1210 } 1211 1212 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc, 1213 struct mmc_request *mrq, u64 *data) 1214 { 1215 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc)); 1216 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1217 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1218 1219 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && 1220 mrq->cmd->flags & MMC_RSP_R1B) 1221 *data |= CQHCI_CMD_TIMING(1); 1222 } 1223 1224 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 1225 { 1226 struct cqhci_host *cq_host = mmc->cqe_private; 1227 struct sdhci_host *host = mmc_priv(mmc); 1228 u32 val; 1229 1230 /* 1231 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size 1232 * register when CQE is enabled and unhalted. 1233 * CQHCI driver enables CQE prior to activation, so disable CQE before 1234 * programming block size in sdhci controller and enable it back. 1235 */ 1236 if (!cq_host->activated) { 1237 val = cqhci_readl(cq_host, CQHCI_CFG); 1238 if (val & CQHCI_ENABLE) 1239 cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), 1240 CQHCI_CFG); 1241 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1242 sdhci_cqe_enable(mmc); 1243 if (val & CQHCI_ENABLE) 1244 cqhci_writel(cq_host, val, CQHCI_CFG); 1245 } 1246 1247 /* 1248 * CMD CRC errors are seen sometimes with some eMMC devices when status 1249 * command is sent during transfer of last data block which is the 1250 * default case as send status command block counter (CBC) is 1. 1251 * Recommended fix to set CBC to 0 allowing send status command only 1252 * when data lines are idle. 1253 */ 1254 val = cqhci_readl(cq_host, CQHCI_SSC1); 1255 val &= ~CQHCI_SSC1_CBC_MASK; 1256 cqhci_writel(cq_host, val, CQHCI_SSC1); 1257 } 1258 1259 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 1260 { 1261 sdhci_dumpregs(mmc_priv(mmc)); 1262 } 1263 1264 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 1265 { 1266 int cmd_error = 0; 1267 int data_error = 0; 1268 1269 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1270 return intmask; 1271 1272 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1273 1274 return 0; 1275 } 1276 1277 static void tegra_sdhci_set_timeout(struct sdhci_host *host, 1278 struct mmc_command *cmd) 1279 { 1280 u32 val; 1281 1282 /* 1283 * HW busy detection timeout is based on programmed data timeout 1284 * counter and maximum supported timeout is 11s which may not be 1285 * enough for long operations like cache flush, sleep awake, erase. 1286 * 1287 * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows 1288 * host controller to wait for busy state until the card is busy 1289 * without HW timeout. 1290 * 1291 * So, use infinite busy wait mode for operations that may take 1292 * more than maximum HW busy timeout of 11s otherwise use finite 1293 * busy wait mode. 1294 */ 1295 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1296 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) 1297 val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1298 else 1299 val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1300 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1301 1302 __sdhci_set_timeout(host, cmd); 1303 } 1304 1305 static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc) 1306 { 1307 struct cqhci_host *cq_host = mmc->cqe_private; 1308 u32 reg; 1309 1310 reg = cqhci_readl(cq_host, CQHCI_CFG); 1311 reg |= CQHCI_ENABLE; 1312 cqhci_writel(cq_host, reg, CQHCI_CFG); 1313 } 1314 1315 static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc) 1316 { 1317 struct cqhci_host *cq_host = mmc->cqe_private; 1318 struct sdhci_host *host = mmc_priv(mmc); 1319 u32 reg; 1320 1321 reg = cqhci_readl(cq_host, CQHCI_CFG); 1322 reg &= ~CQHCI_ENABLE; 1323 cqhci_writel(cq_host, reg, CQHCI_CFG); 1324 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1325 } 1326 1327 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1328 .write_l = tegra_cqhci_writel, 1329 .enable = sdhci_tegra_cqe_enable, 1330 .disable = sdhci_cqe_disable, 1331 .dumpregs = sdhci_tegra_dumpregs, 1332 .update_dcmd_desc = sdhci_tegra_update_dcmd_desc, 1333 .pre_enable = sdhci_tegra_cqe_pre_enable, 1334 .post_disable = sdhci_tegra_cqe_post_disable, 1335 }; 1336 1337 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host) 1338 { 1339 struct sdhci_pltfm_host *platform = sdhci_priv(host); 1340 struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform); 1341 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; 1342 struct device *dev = mmc_dev(host->mmc); 1343 1344 if (soc->dma_mask) 1345 return dma_set_mask_and_coherent(dev, soc->dma_mask); 1346 1347 return 0; 1348 } 1349 1350 static const struct sdhci_ops tegra_sdhci_ops = { 1351 .get_ro = tegra_sdhci_get_ro, 1352 .read_w = tegra_sdhci_readw, 1353 .write_l = tegra_sdhci_writel, 1354 .set_clock = tegra_sdhci_set_clock, 1355 .set_dma_mask = tegra_sdhci_set_dma_mask, 1356 .set_bus_width = sdhci_set_bus_width, 1357 .reset = tegra_sdhci_reset, 1358 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1359 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1360 .voltage_switch = tegra_sdhci_voltage_switch, 1361 .get_max_clock = tegra_sdhci_get_max_clock, 1362 }; 1363 1364 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 1365 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1366 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1367 SDHCI_QUIRK_NO_HISPD_BIT | 1368 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1369 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1370 .ops = &tegra_sdhci_ops, 1371 }; 1372 1373 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 1374 .pdata = &sdhci_tegra20_pdata, 1375 .dma_mask = DMA_BIT_MASK(32), 1376 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 1377 NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1378 NVQUIRK_ENABLE_BLOCK_GAP_DET, 1379 }; 1380 1381 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1382 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1383 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1384 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1385 SDHCI_QUIRK_NO_HISPD_BIT | 1386 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1387 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1388 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1389 SDHCI_QUIRK2_BROKEN_HS200 | 1390 /* 1391 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1392 * though no command operation was in progress." 1393 * 1394 * The exact reason is unknown, as the same hardware seems 1395 * to support Auto CMD23 on a downstream 3.1 kernel. 1396 */ 1397 SDHCI_QUIRK2_ACMD23_BROKEN, 1398 .ops = &tegra_sdhci_ops, 1399 }; 1400 1401 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1402 .pdata = &sdhci_tegra30_pdata, 1403 .dma_mask = DMA_BIT_MASK(32), 1404 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1405 NVQUIRK_ENABLE_SDR50 | 1406 NVQUIRK_ENABLE_SDR104 | 1407 NVQUIRK_HAS_ANDROID_GPT_SECTOR | 1408 NVQUIRK_HAS_PADCALIB, 1409 }; 1410 1411 static const struct sdhci_ops tegra114_sdhci_ops = { 1412 .get_ro = tegra_sdhci_get_ro, 1413 .read_w = tegra_sdhci_readw, 1414 .write_w = tegra_sdhci_writew, 1415 .write_l = tegra_sdhci_writel, 1416 .set_clock = tegra_sdhci_set_clock, 1417 .set_dma_mask = tegra_sdhci_set_dma_mask, 1418 .set_bus_width = sdhci_set_bus_width, 1419 .reset = tegra_sdhci_reset, 1420 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1421 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1422 .voltage_switch = tegra_sdhci_voltage_switch, 1423 .get_max_clock = tegra_sdhci_get_max_clock, 1424 }; 1425 1426 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1427 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1428 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1429 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1430 SDHCI_QUIRK_NO_HISPD_BIT | 1431 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1432 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1433 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1434 .ops = &tegra114_sdhci_ops, 1435 }; 1436 1437 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1438 .pdata = &sdhci_tegra114_pdata, 1439 .dma_mask = DMA_BIT_MASK(32), 1440 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 1441 }; 1442 1443 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1444 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1445 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1446 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1447 SDHCI_QUIRK_NO_HISPD_BIT | 1448 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1449 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1450 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1451 .ops = &tegra114_sdhci_ops, 1452 }; 1453 1454 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1455 .pdata = &sdhci_tegra124_pdata, 1456 .dma_mask = DMA_BIT_MASK(34), 1457 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR, 1458 }; 1459 1460 static const struct sdhci_ops tegra210_sdhci_ops = { 1461 .get_ro = tegra_sdhci_get_ro, 1462 .read_w = tegra_sdhci_readw, 1463 .write_w = tegra210_sdhci_writew, 1464 .write_l = tegra_sdhci_writel, 1465 .set_clock = tegra_sdhci_set_clock, 1466 .set_dma_mask = tegra_sdhci_set_dma_mask, 1467 .set_bus_width = sdhci_set_bus_width, 1468 .reset = tegra_sdhci_reset, 1469 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1470 .voltage_switch = tegra_sdhci_voltage_switch, 1471 .get_max_clock = tegra_sdhci_get_max_clock, 1472 .set_timeout = tegra_sdhci_set_timeout, 1473 }; 1474 1475 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1476 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1477 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1478 SDHCI_QUIRK_NO_HISPD_BIT | 1479 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1480 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1481 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1482 .ops = &tegra210_sdhci_ops, 1483 }; 1484 1485 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1486 .pdata = &sdhci_tegra210_pdata, 1487 .dma_mask = DMA_BIT_MASK(34), 1488 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1489 NVQUIRK_HAS_PADCALIB | 1490 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1491 NVQUIRK_ENABLE_SDR50 | 1492 NVQUIRK_ENABLE_SDR104 | 1493 NVQUIRK_HAS_TMCLK, 1494 .min_tap_delay = 106, 1495 .max_tap_delay = 185, 1496 }; 1497 1498 static const struct sdhci_ops tegra186_sdhci_ops = { 1499 .get_ro = tegra_sdhci_get_ro, 1500 .read_w = tegra_sdhci_readw, 1501 .write_l = tegra_sdhci_writel, 1502 .set_clock = tegra_sdhci_set_clock, 1503 .set_dma_mask = tegra_sdhci_set_dma_mask, 1504 .set_bus_width = sdhci_set_bus_width, 1505 .reset = tegra_sdhci_reset, 1506 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1507 .voltage_switch = tegra_sdhci_voltage_switch, 1508 .get_max_clock = tegra_sdhci_get_max_clock, 1509 .irq = sdhci_tegra_cqhci_irq, 1510 .set_timeout = tegra_sdhci_set_timeout, 1511 }; 1512 1513 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1514 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1515 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1516 SDHCI_QUIRK_NO_HISPD_BIT | 1517 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1518 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1519 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1520 .ops = &tegra186_sdhci_ops, 1521 }; 1522 1523 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1524 .pdata = &sdhci_tegra186_pdata, 1525 .dma_mask = DMA_BIT_MASK(40), 1526 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1527 NVQUIRK_HAS_PADCALIB | 1528 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1529 NVQUIRK_ENABLE_SDR50 | 1530 NVQUIRK_ENABLE_SDR104 | 1531 NVQUIRK_HAS_TMCLK | 1532 NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING, 1533 .min_tap_delay = 84, 1534 .max_tap_delay = 136, 1535 }; 1536 1537 static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1538 .pdata = &sdhci_tegra186_pdata, 1539 .dma_mask = DMA_BIT_MASK(39), 1540 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1541 NVQUIRK_HAS_PADCALIB | 1542 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1543 NVQUIRK_ENABLE_SDR50 | 1544 NVQUIRK_ENABLE_SDR104 | 1545 NVQUIRK_HAS_TMCLK, 1546 .min_tap_delay = 96, 1547 .max_tap_delay = 139, 1548 }; 1549 1550 static const struct of_device_id sdhci_tegra_dt_match[] = { 1551 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 1552 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1553 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1554 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1555 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1556 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1557 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1558 {} 1559 }; 1560 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1561 1562 static int sdhci_tegra_add_host(struct sdhci_host *host) 1563 { 1564 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1565 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1566 struct cqhci_host *cq_host; 1567 bool dma64; 1568 int ret; 1569 1570 if (!tegra_host->enable_hwcq) 1571 return sdhci_add_host(host); 1572 1573 sdhci_enable_v4_mode(host); 1574 1575 ret = sdhci_setup_host(host); 1576 if (ret) 1577 return ret; 1578 1579 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1580 1581 cq_host = devm_kzalloc(mmc_dev(host->mmc), 1582 sizeof(*cq_host), GFP_KERNEL); 1583 if (!cq_host) { 1584 ret = -ENOMEM; 1585 goto cleanup; 1586 } 1587 1588 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1589 cq_host->ops = &sdhci_tegra_cqhci_ops; 1590 1591 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1592 if (dma64) 1593 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1594 1595 ret = cqhci_init(cq_host, host->mmc, dma64); 1596 if (ret) 1597 goto cleanup; 1598 1599 ret = __sdhci_add_host(host); 1600 if (ret) 1601 goto cleanup; 1602 1603 return 0; 1604 1605 cleanup: 1606 sdhci_cleanup_host(host); 1607 return ret; 1608 } 1609 1610 static int sdhci_tegra_probe(struct platform_device *pdev) 1611 { 1612 const struct of_device_id *match; 1613 const struct sdhci_tegra_soc_data *soc_data; 1614 struct sdhci_host *host; 1615 struct sdhci_pltfm_host *pltfm_host; 1616 struct sdhci_tegra *tegra_host; 1617 struct clk *clk; 1618 int rc; 1619 1620 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1621 if (!match) 1622 return -EINVAL; 1623 soc_data = match->data; 1624 1625 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1626 if (IS_ERR(host)) 1627 return PTR_ERR(host); 1628 pltfm_host = sdhci_priv(host); 1629 1630 tegra_host = sdhci_pltfm_priv(pltfm_host); 1631 tegra_host->ddr_signaling = false; 1632 tegra_host->pad_calib_required = false; 1633 tegra_host->pad_control_available = false; 1634 tegra_host->soc_data = soc_data; 1635 1636 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) 1637 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; 1638 1639 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1640 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1641 if (rc == 0) 1642 host->mmc_host_ops.start_signal_voltage_switch = 1643 sdhci_tegra_start_signal_voltage_switch; 1644 } 1645 1646 /* Hook to periodically rerun pad calibration */ 1647 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1648 host->mmc_host_ops.request = tegra_sdhci_request; 1649 1650 host->mmc_host_ops.hs400_enhanced_strobe = 1651 tegra_sdhci_hs400_enhanced_strobe; 1652 1653 if (!host->ops->platform_execute_tuning) 1654 host->mmc_host_ops.execute_tuning = 1655 tegra_sdhci_execute_hw_tuning; 1656 1657 rc = mmc_of_parse(host->mmc); 1658 if (rc) 1659 goto err_parse_dt; 1660 1661 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1662 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1663 1664 /* HW busy detection is supported, but R1B responses are required. */ 1665 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 1666 1667 tegra_sdhci_parse_dt(host); 1668 1669 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1670 GPIOD_OUT_HIGH); 1671 if (IS_ERR(tegra_host->power_gpio)) { 1672 rc = PTR_ERR(tegra_host->power_gpio); 1673 goto err_power_req; 1674 } 1675 1676 /* 1677 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host 1678 * timeout clock and SW can choose TMCLK or SDCLK for hardware 1679 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of 1680 * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL. 1681 * 1682 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses 1683 * 12Mhz TMCLK which is advertised in host capability register. 1684 * With TMCLK of 12Mhz provides maximum data timeout period that can 1685 * be achieved is 11s better than using SDCLK for data timeout. 1686 * 1687 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's 1688 * supporting separate TMCLK. 1689 */ 1690 1691 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { 1692 clk = devm_clk_get(&pdev->dev, "tmclk"); 1693 if (IS_ERR(clk)) { 1694 rc = PTR_ERR(clk); 1695 if (rc == -EPROBE_DEFER) 1696 goto err_power_req; 1697 1698 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); 1699 clk = NULL; 1700 } 1701 1702 clk_set_rate(clk, 12000000); 1703 rc = clk_prepare_enable(clk); 1704 if (rc) { 1705 dev_err(&pdev->dev, 1706 "failed to enable tmclk: %d\n", rc); 1707 goto err_power_req; 1708 } 1709 1710 tegra_host->tmclk = clk; 1711 } 1712 1713 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1714 if (IS_ERR(clk)) { 1715 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), 1716 "failed to get clock\n"); 1717 goto err_clk_get; 1718 } 1719 pltfm_host->clk = clk; 1720 1721 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1722 "sdhci"); 1723 if (IS_ERR(tegra_host->rst)) { 1724 rc = PTR_ERR(tegra_host->rst); 1725 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1726 goto err_rst_get; 1727 } 1728 1729 rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1730 if (rc) 1731 goto err_rst_get; 1732 1733 pm_runtime_enable(&pdev->dev); 1734 rc = pm_runtime_resume_and_get(&pdev->dev); 1735 if (rc) 1736 goto err_pm_get; 1737 1738 rc = reset_control_assert(tegra_host->rst); 1739 if (rc) 1740 goto err_rst_assert; 1741 1742 usleep_range(2000, 4000); 1743 1744 rc = reset_control_deassert(tegra_host->rst); 1745 if (rc) 1746 goto err_rst_assert; 1747 1748 usleep_range(2000, 4000); 1749 1750 rc = sdhci_tegra_add_host(host); 1751 if (rc) 1752 goto err_add_host; 1753 1754 return 0; 1755 1756 err_add_host: 1757 reset_control_assert(tegra_host->rst); 1758 err_rst_assert: 1759 pm_runtime_put_sync_suspend(&pdev->dev); 1760 err_pm_get: 1761 pm_runtime_disable(&pdev->dev); 1762 err_rst_get: 1763 err_clk_get: 1764 clk_disable_unprepare(tegra_host->tmclk); 1765 err_power_req: 1766 err_parse_dt: 1767 sdhci_pltfm_free(pdev); 1768 return rc; 1769 } 1770 1771 static int sdhci_tegra_remove(struct platform_device *pdev) 1772 { 1773 struct sdhci_host *host = platform_get_drvdata(pdev); 1774 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1775 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1776 1777 sdhci_remove_host(host, 0); 1778 1779 reset_control_assert(tegra_host->rst); 1780 usleep_range(2000, 4000); 1781 1782 pm_runtime_put_sync_suspend(&pdev->dev); 1783 pm_runtime_force_suspend(&pdev->dev); 1784 1785 clk_disable_unprepare(tegra_host->tmclk); 1786 sdhci_pltfm_free(pdev); 1787 1788 return 0; 1789 } 1790 1791 static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev) 1792 { 1793 struct sdhci_host *host = dev_get_drvdata(dev); 1794 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1795 1796 clk_disable_unprepare(pltfm_host->clk); 1797 1798 return 0; 1799 } 1800 1801 static int __maybe_unused sdhci_tegra_runtime_resume(struct device *dev) 1802 { 1803 struct sdhci_host *host = dev_get_drvdata(dev); 1804 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1805 1806 return clk_prepare_enable(pltfm_host->clk); 1807 } 1808 1809 #ifdef CONFIG_PM_SLEEP 1810 static int sdhci_tegra_suspend(struct device *dev) 1811 { 1812 struct sdhci_host *host = dev_get_drvdata(dev); 1813 int ret; 1814 1815 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1816 ret = cqhci_suspend(host->mmc); 1817 if (ret) 1818 return ret; 1819 } 1820 1821 ret = sdhci_suspend_host(host); 1822 if (ret) { 1823 cqhci_resume(host->mmc); 1824 return ret; 1825 } 1826 1827 ret = pm_runtime_force_suspend(dev); 1828 if (ret) { 1829 sdhci_resume_host(host); 1830 cqhci_resume(host->mmc); 1831 return ret; 1832 } 1833 1834 return 0; 1835 } 1836 1837 static int sdhci_tegra_resume(struct device *dev) 1838 { 1839 struct sdhci_host *host = dev_get_drvdata(dev); 1840 int ret; 1841 1842 ret = pm_runtime_force_resume(dev); 1843 if (ret) 1844 return ret; 1845 1846 ret = sdhci_resume_host(host); 1847 if (ret) 1848 goto disable_clk; 1849 1850 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1851 ret = cqhci_resume(host->mmc); 1852 if (ret) 1853 goto suspend_host; 1854 } 1855 1856 return 0; 1857 1858 suspend_host: 1859 sdhci_suspend_host(host); 1860 disable_clk: 1861 pm_runtime_force_suspend(dev); 1862 return ret; 1863 } 1864 #endif 1865 1866 static const struct dev_pm_ops sdhci_tegra_dev_pm_ops = { 1867 SET_RUNTIME_PM_OPS(sdhci_tegra_runtime_suspend, sdhci_tegra_runtime_resume, 1868 NULL) 1869 SET_SYSTEM_SLEEP_PM_OPS(sdhci_tegra_suspend, sdhci_tegra_resume) 1870 }; 1871 1872 static struct platform_driver sdhci_tegra_driver = { 1873 .driver = { 1874 .name = "sdhci-tegra", 1875 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1876 .of_match_table = sdhci_tegra_dt_match, 1877 .pm = &sdhci_tegra_dev_pm_ops, 1878 }, 1879 .probe = sdhci_tegra_probe, 1880 .remove = sdhci_tegra_remove, 1881 }; 1882 1883 module_platform_driver(sdhci_tegra_driver); 1884 1885 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1886 MODULE_AUTHOR("Google, Inc."); 1887 MODULE_LICENSE("GPL v2"); 1888