1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 51 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 52 53 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 54 #define SDHCI_AUTO_CAL_START BIT(31) 55 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 56 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 57 58 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 59 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 60 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 61 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 62 63 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 64 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 65 66 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 67 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 68 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 69 #define NVQUIRK_ENABLE_SDR50 BIT(3) 70 #define NVQUIRK_ENABLE_SDR104 BIT(4) 71 #define NVQUIRK_ENABLE_DDR50 BIT(5) 72 #define NVQUIRK_HAS_PADCALIB BIT(6) 73 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 74 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 75 76 struct sdhci_tegra_soc_data { 77 const struct sdhci_pltfm_data *pdata; 78 u32 nvquirks; 79 }; 80 81 /* Magic pull up and pull down pad calibration offsets */ 82 struct sdhci_tegra_autocal_offsets { 83 u32 pull_up_3v3; 84 u32 pull_down_3v3; 85 u32 pull_up_3v3_timeout; 86 u32 pull_down_3v3_timeout; 87 u32 pull_up_1v8; 88 u32 pull_down_1v8; 89 u32 pull_up_1v8_timeout; 90 u32 pull_down_1v8_timeout; 91 u32 pull_up_sdr104; 92 u32 pull_down_sdr104; 93 u32 pull_up_hs400; 94 u32 pull_down_hs400; 95 }; 96 97 struct sdhci_tegra { 98 const struct sdhci_tegra_soc_data *soc_data; 99 struct gpio_desc *power_gpio; 100 bool ddr_signaling; 101 bool pad_calib_required; 102 bool pad_control_available; 103 104 struct reset_control *rst; 105 struct pinctrl *pinctrl_sdmmc; 106 struct pinctrl_state *pinctrl_state_3v3; 107 struct pinctrl_state *pinctrl_state_1v8; 108 109 struct sdhci_tegra_autocal_offsets autocal_offsets; 110 }; 111 112 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 113 { 114 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 115 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 116 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 117 118 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 119 (reg == SDHCI_HOST_VERSION))) { 120 /* Erratum: Version register is invalid in HW. */ 121 return SDHCI_SPEC_200; 122 } 123 124 return readw(host->ioaddr + reg); 125 } 126 127 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 128 { 129 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 130 131 switch (reg) { 132 case SDHCI_TRANSFER_MODE: 133 /* 134 * Postpone this write, we must do it together with a 135 * command write that is down below. 136 */ 137 pltfm_host->xfer_mode_shadow = val; 138 return; 139 case SDHCI_COMMAND: 140 writel((val << 16) | pltfm_host->xfer_mode_shadow, 141 host->ioaddr + SDHCI_TRANSFER_MODE); 142 return; 143 } 144 145 writew(val, host->ioaddr + reg); 146 } 147 148 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 149 { 150 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 151 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 152 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 153 154 /* Seems like we're getting spurious timeout and crc errors, so 155 * disable signalling of them. In case of real errors software 156 * timers should take care of eventually detecting them. 157 */ 158 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 159 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 160 161 writel(val, host->ioaddr + reg); 162 163 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 164 (reg == SDHCI_INT_ENABLE))) { 165 /* Erratum: Must enable block gap interrupt detection */ 166 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 167 if (val & SDHCI_INT_CARD_INT) 168 gap_ctrl |= 0x8; 169 else 170 gap_ctrl &= ~0x8; 171 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 172 } 173 } 174 175 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 176 { 177 return mmc_gpio_get_ro(host->mmc); 178 } 179 180 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 181 { 182 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 183 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 184 int has_1v8, has_3v3; 185 186 /* 187 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 188 * voltage configuration in order to perform voltage switching. This 189 * means that valid pinctrl info is required on SDHCI instances capable 190 * of performing voltage switching. Whether or not an SDHCI instance is 191 * capable of voltage switching is determined based on the regulator. 192 */ 193 194 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 195 return true; 196 197 if (IS_ERR(host->mmc->supply.vqmmc)) 198 return false; 199 200 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 201 1700000, 1950000); 202 203 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 204 2700000, 3600000); 205 206 if (has_1v8 == 1 && has_3v3 == 1) 207 return tegra_host->pad_control_available; 208 209 /* Fixed voltage, no pad control required. */ 210 return true; 211 } 212 213 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 214 { 215 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 216 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 217 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 218 u32 misc_ctrl, clk_ctrl, pad_ctrl; 219 220 sdhci_reset(host, mask); 221 222 if (!(mask & SDHCI_RESET_ALL)) 223 return; 224 225 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 226 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 227 228 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 229 SDHCI_MISC_CTRL_ENABLE_SDR50 | 230 SDHCI_MISC_CTRL_ENABLE_DDR50 | 231 SDHCI_MISC_CTRL_ENABLE_SDR104); 232 233 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 234 235 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 236 /* Erratum: Enable SDHCI spec v3.00 support */ 237 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 238 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 239 /* Advertise UHS modes as supported by host */ 240 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 241 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 242 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 243 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 244 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 245 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 246 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 247 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 248 } 249 250 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 251 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 252 253 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 254 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 255 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 256 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 257 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 258 259 tegra_host->pad_calib_required = true; 260 } 261 262 tegra_host->ddr_signaling = false; 263 } 264 265 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 266 { 267 u32 val; 268 269 /* 270 * Enable or disable the additional I/O pad used by the drive strength 271 * calibration process. 272 */ 273 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 274 275 if (enable) 276 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 277 else 278 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 279 280 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 281 282 if (enable) 283 usleep_range(1, 2); 284 } 285 286 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 287 { 288 bool status; 289 u32 reg; 290 291 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 292 status = !!(reg & SDHCI_CLOCK_CARD_EN); 293 294 if (status == enable) 295 return status; 296 297 if (enable) 298 reg |= SDHCI_CLOCK_CARD_EN; 299 else 300 reg &= ~SDHCI_CLOCK_CARD_EN; 301 302 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 303 304 return status; 305 } 306 307 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 308 u16 pdpu) 309 { 310 u32 reg; 311 312 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 313 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 314 reg |= pdpu; 315 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 316 } 317 318 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 319 { 320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 321 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 322 struct sdhci_tegra_autocal_offsets offsets = 323 tegra_host->autocal_offsets; 324 struct mmc_ios *ios = &host->mmc->ios; 325 bool card_clk_enabled; 326 u16 pdpu; 327 u32 reg; 328 int ret; 329 330 switch (ios->timing) { 331 case MMC_TIMING_UHS_SDR104: 332 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 333 break; 334 case MMC_TIMING_MMC_HS400: 335 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 336 break; 337 default: 338 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 339 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 340 else 341 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 342 } 343 344 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 345 346 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 347 348 tegra_sdhci_configure_cal_pad(host, true); 349 350 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 351 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 352 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 353 354 usleep_range(1, 2); 355 /* 10 ms timeout */ 356 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 357 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 358 1000, 10000); 359 360 tegra_sdhci_configure_cal_pad(host, false); 361 362 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 363 364 if (ret) { 365 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 366 367 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 368 pdpu = offsets.pull_down_1v8_timeout << 8 | 369 offsets.pull_up_1v8_timeout; 370 else 371 pdpu = offsets.pull_down_3v3_timeout << 8 | 372 offsets.pull_up_3v3_timeout; 373 374 /* Disable automatic calibration and use fixed offsets */ 375 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 376 reg &= ~SDHCI_AUTO_CAL_ENABLE; 377 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 378 379 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 380 } 381 } 382 383 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 384 { 385 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 386 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 387 struct sdhci_tegra_autocal_offsets *autocal = 388 &tegra_host->autocal_offsets; 389 int err; 390 391 err = device_property_read_u32(host->mmc->parent, 392 "nvidia,pad-autocal-pull-up-offset-3v3", 393 &autocal->pull_up_3v3); 394 if (err) 395 autocal->pull_up_3v3 = 0; 396 397 err = device_property_read_u32(host->mmc->parent, 398 "nvidia,pad-autocal-pull-down-offset-3v3", 399 &autocal->pull_down_3v3); 400 if (err) 401 autocal->pull_down_3v3 = 0; 402 403 err = device_property_read_u32(host->mmc->parent, 404 "nvidia,pad-autocal-pull-up-offset-1v8", 405 &autocal->pull_up_1v8); 406 if (err) 407 autocal->pull_up_1v8 = 0; 408 409 err = device_property_read_u32(host->mmc->parent, 410 "nvidia,pad-autocal-pull-down-offset-1v8", 411 &autocal->pull_down_1v8); 412 if (err) 413 autocal->pull_down_1v8 = 0; 414 415 err = device_property_read_u32(host->mmc->parent, 416 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 417 &autocal->pull_up_3v3); 418 if (err) 419 autocal->pull_up_3v3_timeout = 0; 420 421 err = device_property_read_u32(host->mmc->parent, 422 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 423 &autocal->pull_down_3v3); 424 if (err) 425 autocal->pull_down_3v3_timeout = 0; 426 427 err = device_property_read_u32(host->mmc->parent, 428 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 429 &autocal->pull_up_1v8); 430 if (err) 431 autocal->pull_up_1v8_timeout = 0; 432 433 err = device_property_read_u32(host->mmc->parent, 434 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 435 &autocal->pull_down_1v8); 436 if (err) 437 autocal->pull_down_1v8_timeout = 0; 438 439 err = device_property_read_u32(host->mmc->parent, 440 "nvidia,pad-autocal-pull-up-offset-sdr104", 441 &autocal->pull_up_sdr104); 442 if (err) 443 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 444 445 err = device_property_read_u32(host->mmc->parent, 446 "nvidia,pad-autocal-pull-down-offset-sdr104", 447 &autocal->pull_down_sdr104); 448 if (err) 449 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 450 451 err = device_property_read_u32(host->mmc->parent, 452 "nvidia,pad-autocal-pull-up-offset-hs400", 453 &autocal->pull_up_hs400); 454 if (err) 455 autocal->pull_up_hs400 = autocal->pull_up_1v8; 456 457 err = device_property_read_u32(host->mmc->parent, 458 "nvidia,pad-autocal-pull-down-offset-hs400", 459 &autocal->pull_down_hs400); 460 if (err) 461 autocal->pull_down_hs400 = autocal->pull_down_1v8; 462 } 463 464 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 465 { 466 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 467 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 468 unsigned long host_clk; 469 470 if (!clock) 471 return sdhci_set_clock(host, clock); 472 473 /* 474 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 475 * divider to be configured to divided the host clock by two. The SDHCI 476 * clock divider is calculated as part of sdhci_set_clock() by 477 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 478 * the requested clock rate. 479 * 480 * By setting the host->max_clk to clock * 2 the divider calculation 481 * will always result in the correct value for DDR50/52 modes, 482 * regardless of clock rate rounding, which may happen if the value 483 * from clk_get_rate() is used. 484 */ 485 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 486 clk_set_rate(pltfm_host->clk, host_clk); 487 if (tegra_host->ddr_signaling) 488 host->max_clk = host_clk; 489 else 490 host->max_clk = clk_get_rate(pltfm_host->clk); 491 492 sdhci_set_clock(host, clock); 493 494 if (tegra_host->pad_calib_required) { 495 tegra_sdhci_pad_autocalib(host); 496 tegra_host->pad_calib_required = false; 497 } 498 } 499 500 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 501 unsigned timing) 502 { 503 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 504 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 505 506 if (timing == MMC_TIMING_UHS_DDR50 || 507 timing == MMC_TIMING_MMC_DDR52) 508 tegra_host->ddr_signaling = true; 509 510 sdhci_set_uhs_signaling(host, timing); 511 } 512 513 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 514 { 515 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 516 517 return clk_round_rate(pltfm_host->clk, UINT_MAX); 518 } 519 520 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 521 { 522 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 523 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 524 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 525 bool card_clk_enabled = false; 526 u32 reg; 527 528 /* 529 * Touching the tap values is a bit tricky on some SoC generations. 530 * The quirk enables a workaround for a glitch that sometimes occurs if 531 * the tap values are changed. 532 */ 533 534 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 535 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 536 537 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 538 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 539 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 540 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 541 542 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 543 card_clk_enabled) { 544 usleep_range(1, 2); 545 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 546 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 547 } 548 } 549 550 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 551 { 552 unsigned int min, max; 553 554 /* 555 * Start search for minimum tap value at 10, as smaller values are 556 * may wrongly be reported as working but fail at higher speeds, 557 * according to the TRM. 558 */ 559 min = 10; 560 while (min < 255) { 561 tegra_sdhci_set_tap(host, min); 562 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 563 break; 564 min++; 565 } 566 567 /* Find the maximum tap value that still passes. */ 568 max = min + 1; 569 while (max < 255) { 570 tegra_sdhci_set_tap(host, max); 571 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 572 max--; 573 break; 574 } 575 max++; 576 } 577 578 /* The TRM states the ideal tap value is at 75% in the passing range. */ 579 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 580 581 return mmc_send_tuning(host->mmc, opcode, NULL); 582 } 583 584 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 585 { 586 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 587 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 588 int ret; 589 590 if (!tegra_host->pad_control_available) 591 return 0; 592 593 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 594 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 595 tegra_host->pinctrl_state_1v8); 596 if (ret < 0) 597 dev_err(mmc_dev(host->mmc), 598 "setting 1.8V failed, ret: %d\n", ret); 599 } else { 600 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 601 tegra_host->pinctrl_state_3v3); 602 if (ret < 0) 603 dev_err(mmc_dev(host->mmc), 604 "setting 3.3V failed, ret: %d\n", ret); 605 } 606 607 return ret; 608 } 609 610 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 611 struct mmc_ios *ios) 612 { 613 struct sdhci_host *host = mmc_priv(mmc); 614 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 615 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 616 int ret = 0; 617 618 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 619 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 620 if (ret < 0) 621 return ret; 622 ret = sdhci_start_signal_voltage_switch(mmc, ios); 623 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 624 ret = sdhci_start_signal_voltage_switch(mmc, ios); 625 if (ret < 0) 626 return ret; 627 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 628 } 629 630 if (tegra_host->pad_calib_required) 631 tegra_sdhci_pad_autocalib(host); 632 633 return ret; 634 } 635 636 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 637 struct sdhci_tegra *tegra_host) 638 { 639 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 640 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 641 dev_dbg(dev, "No pinctrl info, err: %ld\n", 642 PTR_ERR(tegra_host->pinctrl_sdmmc)); 643 return -1; 644 } 645 646 tegra_host->pinctrl_state_3v3 = 647 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 648 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 649 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 650 PTR_ERR(tegra_host->pinctrl_state_3v3)); 651 return -1; 652 } 653 654 tegra_host->pinctrl_state_1v8 = 655 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 656 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 657 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 658 PTR_ERR(tegra_host->pinctrl_state_3v3)); 659 return -1; 660 } 661 662 tegra_host->pad_control_available = true; 663 664 return 0; 665 } 666 667 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 668 { 669 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 670 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 671 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 672 673 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 674 tegra_host->pad_calib_required = true; 675 } 676 677 static const struct sdhci_ops tegra_sdhci_ops = { 678 .get_ro = tegra_sdhci_get_ro, 679 .read_w = tegra_sdhci_readw, 680 .write_l = tegra_sdhci_writel, 681 .set_clock = tegra_sdhci_set_clock, 682 .set_bus_width = sdhci_set_bus_width, 683 .reset = tegra_sdhci_reset, 684 .platform_execute_tuning = tegra_sdhci_execute_tuning, 685 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 686 .voltage_switch = tegra_sdhci_voltage_switch, 687 .get_max_clock = tegra_sdhci_get_max_clock, 688 }; 689 690 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 691 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 692 SDHCI_QUIRK_SINGLE_POWER_WRITE | 693 SDHCI_QUIRK_NO_HISPD_BIT | 694 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 695 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 696 .ops = &tegra_sdhci_ops, 697 }; 698 699 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 700 .pdata = &sdhci_tegra20_pdata, 701 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 702 NVQUIRK_ENABLE_BLOCK_GAP_DET, 703 }; 704 705 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 706 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 707 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 708 SDHCI_QUIRK_SINGLE_POWER_WRITE | 709 SDHCI_QUIRK_NO_HISPD_BIT | 710 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 711 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 712 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 713 SDHCI_QUIRK2_BROKEN_HS200 | 714 /* 715 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 716 * though no command operation was in progress." 717 * 718 * The exact reason is unknown, as the same hardware seems 719 * to support Auto CMD23 on a downstream 3.1 kernel. 720 */ 721 SDHCI_QUIRK2_ACMD23_BROKEN, 722 .ops = &tegra_sdhci_ops, 723 }; 724 725 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 726 .pdata = &sdhci_tegra30_pdata, 727 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 728 NVQUIRK_ENABLE_SDR50 | 729 NVQUIRK_ENABLE_SDR104 | 730 NVQUIRK_HAS_PADCALIB, 731 }; 732 733 static const struct sdhci_ops tegra114_sdhci_ops = { 734 .get_ro = tegra_sdhci_get_ro, 735 .read_w = tegra_sdhci_readw, 736 .write_w = tegra_sdhci_writew, 737 .write_l = tegra_sdhci_writel, 738 .set_clock = tegra_sdhci_set_clock, 739 .set_bus_width = sdhci_set_bus_width, 740 .reset = tegra_sdhci_reset, 741 .platform_execute_tuning = tegra_sdhci_execute_tuning, 742 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 743 .voltage_switch = tegra_sdhci_voltage_switch, 744 .get_max_clock = tegra_sdhci_get_max_clock, 745 }; 746 747 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 748 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 749 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 750 SDHCI_QUIRK_SINGLE_POWER_WRITE | 751 SDHCI_QUIRK_NO_HISPD_BIT | 752 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 753 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 754 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 755 .ops = &tegra114_sdhci_ops, 756 }; 757 758 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 759 .pdata = &sdhci_tegra114_pdata, 760 }; 761 762 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 763 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 764 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 765 SDHCI_QUIRK_SINGLE_POWER_WRITE | 766 SDHCI_QUIRK_NO_HISPD_BIT | 767 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 768 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 769 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 770 /* 771 * The TRM states that the SD/MMC controller found on 772 * Tegra124 can address 34 bits (the maximum supported by 773 * the Tegra memory controller), but tests show that DMA 774 * to or from above 4 GiB doesn't work. This is possibly 775 * caused by missing programming, though it's not obvious 776 * what sequence is required. Mark 64-bit DMA broken for 777 * now to fix this for existing users (e.g. Nyan boards). 778 */ 779 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 780 .ops = &tegra114_sdhci_ops, 781 }; 782 783 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 784 .pdata = &sdhci_tegra124_pdata, 785 }; 786 787 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 788 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 789 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 790 SDHCI_QUIRK_SINGLE_POWER_WRITE | 791 SDHCI_QUIRK_NO_HISPD_BIT | 792 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 793 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 794 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 795 .ops = &tegra114_sdhci_ops, 796 }; 797 798 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 799 .pdata = &sdhci_tegra210_pdata, 800 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 801 NVQUIRK_HAS_PADCALIB | 802 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 803 }; 804 805 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 806 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 807 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 808 SDHCI_QUIRK_SINGLE_POWER_WRITE | 809 SDHCI_QUIRK_NO_HISPD_BIT | 810 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 811 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 812 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 813 /* SDHCI controllers on Tegra186 support 40-bit addressing. 814 * IOVA addresses are 48-bit wide on Tegra186. 815 * With 64-bit dma mask used for SDHCI, accesses can 816 * be broken. Disable 64-bit dma, which would fall back 817 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 818 * But it is not supported as of now. 819 */ 820 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 821 .ops = &tegra114_sdhci_ops, 822 }; 823 824 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 825 .pdata = &sdhci_tegra186_pdata, 826 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 827 NVQUIRK_HAS_PADCALIB | 828 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 829 }; 830 831 static const struct of_device_id sdhci_tegra_dt_match[] = { 832 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 833 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 834 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 835 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 836 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 837 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 838 {} 839 }; 840 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 841 842 static int sdhci_tegra_probe(struct platform_device *pdev) 843 { 844 const struct of_device_id *match; 845 const struct sdhci_tegra_soc_data *soc_data; 846 struct sdhci_host *host; 847 struct sdhci_pltfm_host *pltfm_host; 848 struct sdhci_tegra *tegra_host; 849 struct clk *clk; 850 int rc; 851 852 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 853 if (!match) 854 return -EINVAL; 855 soc_data = match->data; 856 857 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 858 if (IS_ERR(host)) 859 return PTR_ERR(host); 860 pltfm_host = sdhci_priv(host); 861 862 tegra_host = sdhci_pltfm_priv(pltfm_host); 863 tegra_host->ddr_signaling = false; 864 tegra_host->pad_calib_required = false; 865 tegra_host->pad_control_available = false; 866 tegra_host->soc_data = soc_data; 867 868 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 869 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 870 if (rc == 0) 871 host->mmc_host_ops.start_signal_voltage_switch = 872 sdhci_tegra_start_signal_voltage_switch; 873 } 874 875 rc = mmc_of_parse(host->mmc); 876 if (rc) 877 goto err_parse_dt; 878 879 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 880 host->mmc->caps |= MMC_CAP_1_8V_DDR; 881 882 tegra_sdhci_parse_pad_autocal_dt(host); 883 884 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 885 GPIOD_OUT_HIGH); 886 if (IS_ERR(tegra_host->power_gpio)) { 887 rc = PTR_ERR(tegra_host->power_gpio); 888 goto err_power_req; 889 } 890 891 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 892 if (IS_ERR(clk)) { 893 dev_err(mmc_dev(host->mmc), "clk err\n"); 894 rc = PTR_ERR(clk); 895 goto err_clk_get; 896 } 897 clk_prepare_enable(clk); 898 pltfm_host->clk = clk; 899 900 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 901 "sdhci"); 902 if (IS_ERR(tegra_host->rst)) { 903 rc = PTR_ERR(tegra_host->rst); 904 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 905 goto err_rst_get; 906 } 907 908 rc = reset_control_assert(tegra_host->rst); 909 if (rc) 910 goto err_rst_get; 911 912 usleep_range(2000, 4000); 913 914 rc = reset_control_deassert(tegra_host->rst); 915 if (rc) 916 goto err_rst_get; 917 918 usleep_range(2000, 4000); 919 920 rc = sdhci_add_host(host); 921 if (rc) 922 goto err_add_host; 923 924 return 0; 925 926 err_add_host: 927 reset_control_assert(tegra_host->rst); 928 err_rst_get: 929 clk_disable_unprepare(pltfm_host->clk); 930 err_clk_get: 931 err_power_req: 932 err_parse_dt: 933 sdhci_pltfm_free(pdev); 934 return rc; 935 } 936 937 static int sdhci_tegra_remove(struct platform_device *pdev) 938 { 939 struct sdhci_host *host = platform_get_drvdata(pdev); 940 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 941 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 942 943 sdhci_remove_host(host, 0); 944 945 reset_control_assert(tegra_host->rst); 946 usleep_range(2000, 4000); 947 clk_disable_unprepare(pltfm_host->clk); 948 949 sdhci_pltfm_free(pdev); 950 951 return 0; 952 } 953 954 static struct platform_driver sdhci_tegra_driver = { 955 .driver = { 956 .name = "sdhci-tegra", 957 .of_match_table = sdhci_tegra_dt_match, 958 .pm = &sdhci_pltfm_pmops, 959 }, 960 .probe = sdhci_tegra_probe, 961 .remove = sdhci_tegra_remove, 962 }; 963 964 module_platform_driver(sdhci_tegra_driver); 965 966 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 967 MODULE_AUTHOR("Google, Inc."); 968 MODULE_LICENSE("GPL v2"); 969