1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/gpio.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 28 #include <asm/gpio.h> 29 30 #include <mach/gpio-tegra.h> 31 #include <mach/sdhci.h> 32 33 #include "sdhci-pltfm.h" 34 35 /* Tegra SDHOST controller vendor register definitions */ 36 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 37 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 38 39 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 40 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 41 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 42 43 struct sdhci_tegra_soc_data { 44 struct sdhci_pltfm_data *pdata; 45 u32 nvquirks; 46 }; 47 48 struct sdhci_tegra { 49 const struct tegra_sdhci_platform_data *plat; 50 const struct sdhci_tegra_soc_data *soc_data; 51 }; 52 53 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg) 54 { 55 u32 val; 56 57 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 58 /* Use wp_gpio here instead? */ 59 val = readl(host->ioaddr + reg); 60 return val | SDHCI_WRITE_PROTECT; 61 } 62 63 return readl(host->ioaddr + reg); 64 } 65 66 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 67 { 68 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 69 struct sdhci_tegra *tegra_host = pltfm_host->priv; 70 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 71 72 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 73 (reg == SDHCI_HOST_VERSION))) { 74 /* Erratum: Version register is invalid in HW. */ 75 return SDHCI_SPEC_200; 76 } 77 78 return readw(host->ioaddr + reg); 79 } 80 81 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 82 { 83 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 84 struct sdhci_tegra *tegra_host = pltfm_host->priv; 85 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 86 87 /* Seems like we're getting spurious timeout and crc errors, so 88 * disable signalling of them. In case of real errors software 89 * timers should take care of eventually detecting them. 90 */ 91 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 92 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 93 94 writel(val, host->ioaddr + reg); 95 96 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 97 (reg == SDHCI_INT_ENABLE))) { 98 /* Erratum: Must enable block gap interrupt detection */ 99 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 100 if (val & SDHCI_INT_CARD_INT) 101 gap_ctrl |= 0x8; 102 else 103 gap_ctrl &= ~0x8; 104 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 105 } 106 } 107 108 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 109 { 110 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 111 struct sdhci_tegra *tegra_host = pltfm_host->priv; 112 const struct tegra_sdhci_platform_data *plat = tegra_host->plat; 113 114 if (!gpio_is_valid(plat->wp_gpio)) 115 return -1; 116 117 return gpio_get_value(plat->wp_gpio); 118 } 119 120 static irqreturn_t carddetect_irq(int irq, void *data) 121 { 122 struct sdhci_host *sdhost = (struct sdhci_host *)data; 123 124 tasklet_schedule(&sdhost->card_tasklet); 125 return IRQ_HANDLED; 126 }; 127 128 static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask) 129 { 130 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 131 struct sdhci_tegra *tegra_host = pltfm_host->priv; 132 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 133 134 if (!(mask & SDHCI_RESET_ALL)) 135 return; 136 137 /* Erratum: Enable SDHCI spec v3.00 support */ 138 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) { 139 u32 misc_ctrl; 140 141 misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 142 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 143 sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 144 } 145 } 146 147 static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width) 148 { 149 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 150 struct sdhci_tegra *tegra_host = pltfm_host->priv; 151 const struct tegra_sdhci_platform_data *plat = tegra_host->plat; 152 u32 ctrl; 153 154 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 155 if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) { 156 ctrl &= ~SDHCI_CTRL_4BITBUS; 157 ctrl |= SDHCI_CTRL_8BITBUS; 158 } else { 159 ctrl &= ~SDHCI_CTRL_8BITBUS; 160 if (bus_width == MMC_BUS_WIDTH_4) 161 ctrl |= SDHCI_CTRL_4BITBUS; 162 else 163 ctrl &= ~SDHCI_CTRL_4BITBUS; 164 } 165 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 166 return 0; 167 } 168 169 static struct sdhci_ops tegra_sdhci_ops = { 170 .get_ro = tegra_sdhci_get_ro, 171 .read_l = tegra_sdhci_readl, 172 .read_w = tegra_sdhci_readw, 173 .write_l = tegra_sdhci_writel, 174 .platform_8bit_width = tegra_sdhci_8bit, 175 .platform_reset_exit = tegra_sdhci_reset_exit, 176 }; 177 178 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 179 static struct sdhci_pltfm_data sdhci_tegra20_pdata = { 180 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 181 SDHCI_QUIRK_SINGLE_POWER_WRITE | 182 SDHCI_QUIRK_NO_HISPD_BIT | 183 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 184 .ops = &tegra_sdhci_ops, 185 }; 186 187 static struct sdhci_tegra_soc_data soc_data_tegra20 = { 188 .pdata = &sdhci_tegra20_pdata, 189 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 190 NVQUIRK_ENABLE_BLOCK_GAP_DET, 191 }; 192 #endif 193 194 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 195 static struct sdhci_pltfm_data sdhci_tegra30_pdata = { 196 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 197 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 198 SDHCI_QUIRK_SINGLE_POWER_WRITE | 199 SDHCI_QUIRK_NO_HISPD_BIT | 200 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, 201 .ops = &tegra_sdhci_ops, 202 }; 203 204 static struct sdhci_tegra_soc_data soc_data_tegra30 = { 205 .pdata = &sdhci_tegra30_pdata, 206 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300, 207 }; 208 #endif 209 210 static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = { 211 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 212 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 213 #endif 214 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 215 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 216 #endif 217 {} 218 }; 219 MODULE_DEVICE_TABLE(of, sdhci_dt_ids); 220 221 static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata( 222 struct platform_device *pdev) 223 { 224 struct tegra_sdhci_platform_data *plat; 225 struct device_node *np = pdev->dev.of_node; 226 227 if (!np) 228 return NULL; 229 230 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 231 if (!plat) { 232 dev_err(&pdev->dev, "Can't allocate platform data\n"); 233 return NULL; 234 } 235 236 plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 237 plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 238 plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0); 239 if (of_find_property(np, "support-8bit", NULL)) 240 plat->is_8bit = 1; 241 242 return plat; 243 } 244 245 static int __devinit sdhci_tegra_probe(struct platform_device *pdev) 246 { 247 const struct of_device_id *match; 248 const struct sdhci_tegra_soc_data *soc_data; 249 struct sdhci_host *host; 250 struct sdhci_pltfm_host *pltfm_host; 251 struct tegra_sdhci_platform_data *plat; 252 struct sdhci_tegra *tegra_host; 253 struct clk *clk; 254 int rc; 255 256 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 257 if (match) 258 soc_data = match->data; 259 else 260 soc_data = &soc_data_tegra20; 261 262 host = sdhci_pltfm_init(pdev, soc_data->pdata); 263 if (IS_ERR(host)) 264 return PTR_ERR(host); 265 266 pltfm_host = sdhci_priv(host); 267 268 plat = pdev->dev.platform_data; 269 270 if (plat == NULL) 271 plat = sdhci_tegra_dt_parse_pdata(pdev); 272 273 if (plat == NULL) { 274 dev_err(mmc_dev(host->mmc), "missing platform data\n"); 275 rc = -ENXIO; 276 goto err_no_plat; 277 } 278 279 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); 280 if (!tegra_host) { 281 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); 282 rc = -ENOMEM; 283 goto err_no_plat; 284 } 285 286 tegra_host->plat = plat; 287 tegra_host->soc_data = soc_data; 288 289 pltfm_host->priv = tegra_host; 290 291 if (gpio_is_valid(plat->power_gpio)) { 292 rc = gpio_request(plat->power_gpio, "sdhci_power"); 293 if (rc) { 294 dev_err(mmc_dev(host->mmc), 295 "failed to allocate power gpio\n"); 296 goto err_power_req; 297 } 298 tegra_gpio_enable(plat->power_gpio); 299 gpio_direction_output(plat->power_gpio, 1); 300 } 301 302 if (gpio_is_valid(plat->cd_gpio)) { 303 rc = gpio_request(plat->cd_gpio, "sdhci_cd"); 304 if (rc) { 305 dev_err(mmc_dev(host->mmc), 306 "failed to allocate cd gpio\n"); 307 goto err_cd_req; 308 } 309 tegra_gpio_enable(plat->cd_gpio); 310 gpio_direction_input(plat->cd_gpio); 311 312 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, 313 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 314 mmc_hostname(host->mmc), host); 315 316 if (rc) { 317 dev_err(mmc_dev(host->mmc), "request irq error\n"); 318 goto err_cd_irq_req; 319 } 320 321 } 322 323 if (gpio_is_valid(plat->wp_gpio)) { 324 rc = gpio_request(plat->wp_gpio, "sdhci_wp"); 325 if (rc) { 326 dev_err(mmc_dev(host->mmc), 327 "failed to allocate wp gpio\n"); 328 goto err_wp_req; 329 } 330 tegra_gpio_enable(plat->wp_gpio); 331 gpio_direction_input(plat->wp_gpio); 332 } 333 334 clk = clk_get(mmc_dev(host->mmc), NULL); 335 if (IS_ERR(clk)) { 336 dev_err(mmc_dev(host->mmc), "clk err\n"); 337 rc = PTR_ERR(clk); 338 goto err_clk_get; 339 } 340 clk_enable(clk); 341 pltfm_host->clk = clk; 342 343 host->mmc->pm_caps = plat->pm_flags; 344 345 if (plat->is_8bit) 346 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 347 348 rc = sdhci_add_host(host); 349 if (rc) 350 goto err_add_host; 351 352 return 0; 353 354 err_add_host: 355 clk_disable(pltfm_host->clk); 356 clk_put(pltfm_host->clk); 357 err_clk_get: 358 if (gpio_is_valid(plat->wp_gpio)) { 359 tegra_gpio_disable(plat->wp_gpio); 360 gpio_free(plat->wp_gpio); 361 } 362 err_wp_req: 363 if (gpio_is_valid(plat->cd_gpio)) 364 free_irq(gpio_to_irq(plat->cd_gpio), host); 365 err_cd_irq_req: 366 if (gpio_is_valid(plat->cd_gpio)) { 367 tegra_gpio_disable(plat->cd_gpio); 368 gpio_free(plat->cd_gpio); 369 } 370 err_cd_req: 371 if (gpio_is_valid(plat->power_gpio)) { 372 tegra_gpio_disable(plat->power_gpio); 373 gpio_free(plat->power_gpio); 374 } 375 err_power_req: 376 err_no_plat: 377 sdhci_pltfm_free(pdev); 378 return rc; 379 } 380 381 static int __devexit sdhci_tegra_remove(struct platform_device *pdev) 382 { 383 struct sdhci_host *host = platform_get_drvdata(pdev); 384 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 385 struct sdhci_tegra *tegra_host = pltfm_host->priv; 386 const struct tegra_sdhci_platform_data *plat = tegra_host->plat; 387 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 388 389 sdhci_remove_host(host, dead); 390 391 if (gpio_is_valid(plat->wp_gpio)) { 392 tegra_gpio_disable(plat->wp_gpio); 393 gpio_free(plat->wp_gpio); 394 } 395 396 if (gpio_is_valid(plat->cd_gpio)) { 397 free_irq(gpio_to_irq(plat->cd_gpio), host); 398 tegra_gpio_disable(plat->cd_gpio); 399 gpio_free(plat->cd_gpio); 400 } 401 402 if (gpio_is_valid(plat->power_gpio)) { 403 tegra_gpio_disable(plat->power_gpio); 404 gpio_free(plat->power_gpio); 405 } 406 407 clk_disable(pltfm_host->clk); 408 clk_put(pltfm_host->clk); 409 410 sdhci_pltfm_free(pdev); 411 412 return 0; 413 } 414 415 static struct platform_driver sdhci_tegra_driver = { 416 .driver = { 417 .name = "sdhci-tegra", 418 .owner = THIS_MODULE, 419 .of_match_table = sdhci_tegra_dt_match, 420 .pm = SDHCI_PLTFM_PMOPS, 421 }, 422 .probe = sdhci_tegra_probe, 423 .remove = __devexit_p(sdhci_tegra_remove), 424 }; 425 426 module_platform_driver(sdhci_tegra_driver); 427 428 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 429 MODULE_AUTHOR("Google, Inc."); 430 MODULE_LICENSE("GPL v2"); 431