1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/gpio/consumer.h> 33 34 #include "sdhci-pltfm.h" 35 36 /* Tegra SDHOST controller vendor register definitions */ 37 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 38 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 39 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 40 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 41 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 42 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 43 44 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 45 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 46 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 47 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 48 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 49 50 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 51 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 52 53 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 54 #define SDHCI_AUTO_CAL_START BIT(31) 55 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 56 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 57 58 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 59 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 60 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 61 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 62 63 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 64 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 65 66 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 67 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 68 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 69 #define NVQUIRK_ENABLE_SDR50 BIT(3) 70 #define NVQUIRK_ENABLE_SDR104 BIT(4) 71 #define NVQUIRK_ENABLE_DDR50 BIT(5) 72 #define NVQUIRK_HAS_PADCALIB BIT(6) 73 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 74 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 75 76 struct sdhci_tegra_soc_data { 77 const struct sdhci_pltfm_data *pdata; 78 u32 nvquirks; 79 }; 80 81 /* Magic pull up and pull down pad calibration offsets */ 82 struct sdhci_tegra_autocal_offsets { 83 u32 pull_up_3v3; 84 u32 pull_down_3v3; 85 u32 pull_up_3v3_timeout; 86 u32 pull_down_3v3_timeout; 87 u32 pull_up_1v8; 88 u32 pull_down_1v8; 89 u32 pull_up_1v8_timeout; 90 u32 pull_down_1v8_timeout; 91 u32 pull_up_sdr104; 92 u32 pull_down_sdr104; 93 u32 pull_up_hs400; 94 u32 pull_down_hs400; 95 }; 96 97 struct sdhci_tegra { 98 const struct sdhci_tegra_soc_data *soc_data; 99 struct gpio_desc *power_gpio; 100 bool ddr_signaling; 101 bool pad_calib_required; 102 bool pad_control_available; 103 104 struct reset_control *rst; 105 struct pinctrl *pinctrl_sdmmc; 106 struct pinctrl_state *pinctrl_state_3v3; 107 struct pinctrl_state *pinctrl_state_1v8; 108 109 struct sdhci_tegra_autocal_offsets autocal_offsets; 110 111 u32 default_tap; 112 u32 default_trim; 113 }; 114 115 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 116 { 117 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 118 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 119 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 120 121 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 122 (reg == SDHCI_HOST_VERSION))) { 123 /* Erratum: Version register is invalid in HW. */ 124 return SDHCI_SPEC_200; 125 } 126 127 return readw(host->ioaddr + reg); 128 } 129 130 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 131 { 132 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 133 134 switch (reg) { 135 case SDHCI_TRANSFER_MODE: 136 /* 137 * Postpone this write, we must do it together with a 138 * command write that is down below. 139 */ 140 pltfm_host->xfer_mode_shadow = val; 141 return; 142 case SDHCI_COMMAND: 143 writel((val << 16) | pltfm_host->xfer_mode_shadow, 144 host->ioaddr + SDHCI_TRANSFER_MODE); 145 return; 146 } 147 148 writew(val, host->ioaddr + reg); 149 } 150 151 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 152 { 153 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 154 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 155 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 156 157 /* Seems like we're getting spurious timeout and crc errors, so 158 * disable signalling of them. In case of real errors software 159 * timers should take care of eventually detecting them. 160 */ 161 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 162 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 163 164 writel(val, host->ioaddr + reg); 165 166 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 167 (reg == SDHCI_INT_ENABLE))) { 168 /* Erratum: Must enable block gap interrupt detection */ 169 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 170 if (val & SDHCI_INT_CARD_INT) 171 gap_ctrl |= 0x8; 172 else 173 gap_ctrl &= ~0x8; 174 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 175 } 176 } 177 178 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 179 { 180 return mmc_gpio_get_ro(host->mmc); 181 } 182 183 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 184 { 185 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 186 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 187 int has_1v8, has_3v3; 188 189 /* 190 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 191 * voltage configuration in order to perform voltage switching. This 192 * means that valid pinctrl info is required on SDHCI instances capable 193 * of performing voltage switching. Whether or not an SDHCI instance is 194 * capable of voltage switching is determined based on the regulator. 195 */ 196 197 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 198 return true; 199 200 if (IS_ERR(host->mmc->supply.vqmmc)) 201 return false; 202 203 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 204 1700000, 1950000); 205 206 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 207 2700000, 3600000); 208 209 if (has_1v8 == 1 && has_3v3 == 1) 210 return tegra_host->pad_control_available; 211 212 /* Fixed voltage, no pad control required. */ 213 return true; 214 } 215 216 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 217 { 218 bool status; 219 u32 reg; 220 221 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 222 status = !!(reg & SDHCI_CLOCK_CARD_EN); 223 224 if (status == enable) 225 return status; 226 227 if (enable) 228 reg |= SDHCI_CLOCK_CARD_EN; 229 else 230 reg &= ~SDHCI_CLOCK_CARD_EN; 231 232 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 233 234 return status; 235 } 236 237 238 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 239 { 240 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 241 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 242 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 243 bool card_clk_enabled = false; 244 u32 reg; 245 246 /* 247 * Touching the tap values is a bit tricky on some SoC generations. 248 * The quirk enables a workaround for a glitch that sometimes occurs if 249 * the tap values are changed. 250 */ 251 252 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 253 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 254 255 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 256 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 257 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 258 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 259 260 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 261 card_clk_enabled) { 262 udelay(1); 263 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 264 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 265 } 266 } 267 268 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 269 { 270 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 271 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 272 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 273 u32 misc_ctrl, clk_ctrl, pad_ctrl; 274 275 sdhci_reset(host, mask); 276 277 if (!(mask & SDHCI_RESET_ALL)) 278 return; 279 280 tegra_sdhci_set_tap(host, tegra_host->default_tap); 281 282 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 283 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 284 285 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 286 SDHCI_MISC_CTRL_ENABLE_SDR50 | 287 SDHCI_MISC_CTRL_ENABLE_DDR50 | 288 SDHCI_MISC_CTRL_ENABLE_SDR104); 289 290 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 291 292 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 293 /* Erratum: Enable SDHCI spec v3.00 support */ 294 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 295 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 296 /* Advertise UHS modes as supported by host */ 297 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 298 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 299 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 300 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 301 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 302 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 303 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 304 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 305 } 306 307 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 308 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 309 310 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 311 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 312 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 313 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 314 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 315 316 tegra_host->pad_calib_required = true; 317 } 318 319 tegra_host->ddr_signaling = false; 320 } 321 322 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 323 { 324 u32 val; 325 326 /* 327 * Enable or disable the additional I/O pad used by the drive strength 328 * calibration process. 329 */ 330 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 331 332 if (enable) 333 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 334 else 335 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 336 337 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 338 339 if (enable) 340 usleep_range(1, 2); 341 } 342 343 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 344 u16 pdpu) 345 { 346 u32 reg; 347 348 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 349 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 350 reg |= pdpu; 351 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 352 } 353 354 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 355 { 356 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 357 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 358 struct sdhci_tegra_autocal_offsets offsets = 359 tegra_host->autocal_offsets; 360 struct mmc_ios *ios = &host->mmc->ios; 361 bool card_clk_enabled; 362 u16 pdpu; 363 u32 reg; 364 int ret; 365 366 switch (ios->timing) { 367 case MMC_TIMING_UHS_SDR104: 368 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 369 break; 370 case MMC_TIMING_MMC_HS400: 371 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 372 break; 373 default: 374 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 375 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 376 else 377 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 378 } 379 380 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 381 382 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 383 384 tegra_sdhci_configure_cal_pad(host, true); 385 386 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 387 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 388 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 389 390 usleep_range(1, 2); 391 /* 10 ms timeout */ 392 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 393 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 394 1000, 10000); 395 396 tegra_sdhci_configure_cal_pad(host, false); 397 398 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 399 400 if (ret) { 401 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 402 403 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 404 pdpu = offsets.pull_down_1v8_timeout << 8 | 405 offsets.pull_up_1v8_timeout; 406 else 407 pdpu = offsets.pull_down_3v3_timeout << 8 | 408 offsets.pull_up_3v3_timeout; 409 410 /* Disable automatic calibration and use fixed offsets */ 411 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 412 reg &= ~SDHCI_AUTO_CAL_ENABLE; 413 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 414 415 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 416 } 417 } 418 419 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 420 { 421 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 422 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 423 struct sdhci_tegra_autocal_offsets *autocal = 424 &tegra_host->autocal_offsets; 425 int err; 426 427 err = device_property_read_u32(host->mmc->parent, 428 "nvidia,pad-autocal-pull-up-offset-3v3", 429 &autocal->pull_up_3v3); 430 if (err) 431 autocal->pull_up_3v3 = 0; 432 433 err = device_property_read_u32(host->mmc->parent, 434 "nvidia,pad-autocal-pull-down-offset-3v3", 435 &autocal->pull_down_3v3); 436 if (err) 437 autocal->pull_down_3v3 = 0; 438 439 err = device_property_read_u32(host->mmc->parent, 440 "nvidia,pad-autocal-pull-up-offset-1v8", 441 &autocal->pull_up_1v8); 442 if (err) 443 autocal->pull_up_1v8 = 0; 444 445 err = device_property_read_u32(host->mmc->parent, 446 "nvidia,pad-autocal-pull-down-offset-1v8", 447 &autocal->pull_down_1v8); 448 if (err) 449 autocal->pull_down_1v8 = 0; 450 451 err = device_property_read_u32(host->mmc->parent, 452 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 453 &autocal->pull_up_3v3); 454 if (err) 455 autocal->pull_up_3v3_timeout = 0; 456 457 err = device_property_read_u32(host->mmc->parent, 458 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 459 &autocal->pull_down_3v3); 460 if (err) 461 autocal->pull_down_3v3_timeout = 0; 462 463 err = device_property_read_u32(host->mmc->parent, 464 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 465 &autocal->pull_up_1v8); 466 if (err) 467 autocal->pull_up_1v8_timeout = 0; 468 469 err = device_property_read_u32(host->mmc->parent, 470 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 471 &autocal->pull_down_1v8); 472 if (err) 473 autocal->pull_down_1v8_timeout = 0; 474 475 err = device_property_read_u32(host->mmc->parent, 476 "nvidia,pad-autocal-pull-up-offset-sdr104", 477 &autocal->pull_up_sdr104); 478 if (err) 479 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 480 481 err = device_property_read_u32(host->mmc->parent, 482 "nvidia,pad-autocal-pull-down-offset-sdr104", 483 &autocal->pull_down_sdr104); 484 if (err) 485 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 486 487 err = device_property_read_u32(host->mmc->parent, 488 "nvidia,pad-autocal-pull-up-offset-hs400", 489 &autocal->pull_up_hs400); 490 if (err) 491 autocal->pull_up_hs400 = autocal->pull_up_1v8; 492 493 err = device_property_read_u32(host->mmc->parent, 494 "nvidia,pad-autocal-pull-down-offset-hs400", 495 &autocal->pull_down_hs400); 496 if (err) 497 autocal->pull_down_hs400 = autocal->pull_down_1v8; 498 } 499 500 static void tegra_sdhci_parse_default_tap_and_trim(struct sdhci_host *host) 501 { 502 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 503 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 504 int err; 505 506 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 507 &tegra_host->default_tap); 508 if (err) 509 tegra_host->default_tap = 0; 510 511 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 512 &tegra_host->default_trim); 513 if (err) 514 tegra_host->default_trim = 0; 515 } 516 517 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 518 { 519 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 520 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 521 unsigned long host_clk; 522 523 if (!clock) 524 return sdhci_set_clock(host, clock); 525 526 /* 527 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 528 * divider to be configured to divided the host clock by two. The SDHCI 529 * clock divider is calculated as part of sdhci_set_clock() by 530 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 531 * the requested clock rate. 532 * 533 * By setting the host->max_clk to clock * 2 the divider calculation 534 * will always result in the correct value for DDR50/52 modes, 535 * regardless of clock rate rounding, which may happen if the value 536 * from clk_get_rate() is used. 537 */ 538 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 539 clk_set_rate(pltfm_host->clk, host_clk); 540 if (tegra_host->ddr_signaling) 541 host->max_clk = host_clk; 542 else 543 host->max_clk = clk_get_rate(pltfm_host->clk); 544 545 sdhci_set_clock(host, clock); 546 547 if (tegra_host->pad_calib_required) { 548 tegra_sdhci_pad_autocalib(host); 549 tegra_host->pad_calib_required = false; 550 } 551 } 552 553 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 554 { 555 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 556 557 return clk_round_rate(pltfm_host->clk, UINT_MAX); 558 } 559 560 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 561 unsigned timing) 562 { 563 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 564 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 565 bool set_default_tap = false; 566 567 switch (timing) { 568 case MMC_TIMING_UHS_SDR50: 569 case MMC_TIMING_UHS_SDR104: 570 case MMC_TIMING_MMC_HS200: 571 case MMC_TIMING_MMC_HS400: 572 /* Don't set default tap on tunable modes. */ 573 break; 574 case MMC_TIMING_MMC_DDR52: 575 case MMC_TIMING_UHS_DDR50: 576 tegra_host->ddr_signaling = true; 577 set_default_tap = true; 578 break; 579 default: 580 set_default_tap = true; 581 break; 582 } 583 584 sdhci_set_uhs_signaling(host, timing); 585 586 tegra_sdhci_pad_autocalib(host); 587 588 if (set_default_tap) 589 tegra_sdhci_set_tap(host, tegra_host->default_tap); 590 } 591 592 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 593 { 594 unsigned int min, max; 595 596 /* 597 * Start search for minimum tap value at 10, as smaller values are 598 * may wrongly be reported as working but fail at higher speeds, 599 * according to the TRM. 600 */ 601 min = 10; 602 while (min < 255) { 603 tegra_sdhci_set_tap(host, min); 604 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 605 break; 606 min++; 607 } 608 609 /* Find the maximum tap value that still passes. */ 610 max = min + 1; 611 while (max < 255) { 612 tegra_sdhci_set_tap(host, max); 613 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 614 max--; 615 break; 616 } 617 max++; 618 } 619 620 /* The TRM states the ideal tap value is at 75% in the passing range. */ 621 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 622 623 return mmc_send_tuning(host->mmc, opcode, NULL); 624 } 625 626 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage) 627 { 628 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 629 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 630 int ret; 631 632 if (!tegra_host->pad_control_available) 633 return 0; 634 635 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 636 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 637 tegra_host->pinctrl_state_1v8); 638 if (ret < 0) 639 dev_err(mmc_dev(host->mmc), 640 "setting 1.8V failed, ret: %d\n", ret); 641 } else { 642 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 643 tegra_host->pinctrl_state_3v3); 644 if (ret < 0) 645 dev_err(mmc_dev(host->mmc), 646 "setting 3.3V failed, ret: %d\n", ret); 647 } 648 649 return ret; 650 } 651 652 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 653 struct mmc_ios *ios) 654 { 655 struct sdhci_host *host = mmc_priv(mmc); 656 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 657 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 658 int ret = 0; 659 660 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 661 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 662 if (ret < 0) 663 return ret; 664 ret = sdhci_start_signal_voltage_switch(mmc, ios); 665 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 666 ret = sdhci_start_signal_voltage_switch(mmc, ios); 667 if (ret < 0) 668 return ret; 669 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage); 670 } 671 672 if (tegra_host->pad_calib_required) 673 tegra_sdhci_pad_autocalib(host); 674 675 return ret; 676 } 677 678 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 679 struct sdhci_tegra *tegra_host) 680 { 681 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 682 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 683 dev_dbg(dev, "No pinctrl info, err: %ld\n", 684 PTR_ERR(tegra_host->pinctrl_sdmmc)); 685 return -1; 686 } 687 688 tegra_host->pinctrl_state_3v3 = 689 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 690 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 691 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 692 PTR_ERR(tegra_host->pinctrl_state_3v3)); 693 return -1; 694 } 695 696 tegra_host->pinctrl_state_1v8 = 697 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 698 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 699 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 700 PTR_ERR(tegra_host->pinctrl_state_3v3)); 701 return -1; 702 } 703 704 tegra_host->pad_control_available = true; 705 706 return 0; 707 } 708 709 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 710 { 711 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 712 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 713 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 714 715 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 716 tegra_host->pad_calib_required = true; 717 } 718 719 static const struct sdhci_ops tegra_sdhci_ops = { 720 .get_ro = tegra_sdhci_get_ro, 721 .read_w = tegra_sdhci_readw, 722 .write_l = tegra_sdhci_writel, 723 .set_clock = tegra_sdhci_set_clock, 724 .set_bus_width = sdhci_set_bus_width, 725 .reset = tegra_sdhci_reset, 726 .platform_execute_tuning = tegra_sdhci_execute_tuning, 727 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 728 .voltage_switch = tegra_sdhci_voltage_switch, 729 .get_max_clock = tegra_sdhci_get_max_clock, 730 }; 731 732 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 733 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 734 SDHCI_QUIRK_SINGLE_POWER_WRITE | 735 SDHCI_QUIRK_NO_HISPD_BIT | 736 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 737 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 738 .ops = &tegra_sdhci_ops, 739 }; 740 741 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 742 .pdata = &sdhci_tegra20_pdata, 743 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 744 NVQUIRK_ENABLE_BLOCK_GAP_DET, 745 }; 746 747 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 748 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 749 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 750 SDHCI_QUIRK_SINGLE_POWER_WRITE | 751 SDHCI_QUIRK_NO_HISPD_BIT | 752 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 753 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 754 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 755 SDHCI_QUIRK2_BROKEN_HS200 | 756 /* 757 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 758 * though no command operation was in progress." 759 * 760 * The exact reason is unknown, as the same hardware seems 761 * to support Auto CMD23 on a downstream 3.1 kernel. 762 */ 763 SDHCI_QUIRK2_ACMD23_BROKEN, 764 .ops = &tegra_sdhci_ops, 765 }; 766 767 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 768 .pdata = &sdhci_tegra30_pdata, 769 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 770 NVQUIRK_ENABLE_SDR50 | 771 NVQUIRK_ENABLE_SDR104 | 772 NVQUIRK_HAS_PADCALIB, 773 }; 774 775 static const struct sdhci_ops tegra114_sdhci_ops = { 776 .get_ro = tegra_sdhci_get_ro, 777 .read_w = tegra_sdhci_readw, 778 .write_w = tegra_sdhci_writew, 779 .write_l = tegra_sdhci_writel, 780 .set_clock = tegra_sdhci_set_clock, 781 .set_bus_width = sdhci_set_bus_width, 782 .reset = tegra_sdhci_reset, 783 .platform_execute_tuning = tegra_sdhci_execute_tuning, 784 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 785 .voltage_switch = tegra_sdhci_voltage_switch, 786 .get_max_clock = tegra_sdhci_get_max_clock, 787 }; 788 789 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 790 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 791 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 792 SDHCI_QUIRK_SINGLE_POWER_WRITE | 793 SDHCI_QUIRK_NO_HISPD_BIT | 794 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 795 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 796 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 797 .ops = &tegra114_sdhci_ops, 798 }; 799 800 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 801 .pdata = &sdhci_tegra114_pdata, 802 }; 803 804 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 805 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 806 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 807 SDHCI_QUIRK_SINGLE_POWER_WRITE | 808 SDHCI_QUIRK_NO_HISPD_BIT | 809 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 810 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 811 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 812 /* 813 * The TRM states that the SD/MMC controller found on 814 * Tegra124 can address 34 bits (the maximum supported by 815 * the Tegra memory controller), but tests show that DMA 816 * to or from above 4 GiB doesn't work. This is possibly 817 * caused by missing programming, though it's not obvious 818 * what sequence is required. Mark 64-bit DMA broken for 819 * now to fix this for existing users (e.g. Nyan boards). 820 */ 821 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 822 .ops = &tegra114_sdhci_ops, 823 }; 824 825 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 826 .pdata = &sdhci_tegra124_pdata, 827 }; 828 829 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 830 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 831 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 832 SDHCI_QUIRK_SINGLE_POWER_WRITE | 833 SDHCI_QUIRK_NO_HISPD_BIT | 834 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 835 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 836 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 837 .ops = &tegra114_sdhci_ops, 838 }; 839 840 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 841 .pdata = &sdhci_tegra210_pdata, 842 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 843 NVQUIRK_HAS_PADCALIB | 844 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 845 }; 846 847 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 848 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 849 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 850 SDHCI_QUIRK_SINGLE_POWER_WRITE | 851 SDHCI_QUIRK_NO_HISPD_BIT | 852 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 853 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 854 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 855 /* SDHCI controllers on Tegra186 support 40-bit addressing. 856 * IOVA addresses are 48-bit wide on Tegra186. 857 * With 64-bit dma mask used for SDHCI, accesses can 858 * be broken. Disable 64-bit dma, which would fall back 859 * to 32-bit dma mask. Ideally 40-bit dma mask would work, 860 * But it is not supported as of now. 861 */ 862 SDHCI_QUIRK2_BROKEN_64_BIT_DMA, 863 .ops = &tegra114_sdhci_ops, 864 }; 865 866 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 867 .pdata = &sdhci_tegra186_pdata, 868 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 869 NVQUIRK_HAS_PADCALIB | 870 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, 871 }; 872 873 static const struct of_device_id sdhci_tegra_dt_match[] = { 874 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 875 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 876 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 877 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 878 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 879 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 880 {} 881 }; 882 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 883 884 static int sdhci_tegra_probe(struct platform_device *pdev) 885 { 886 const struct of_device_id *match; 887 const struct sdhci_tegra_soc_data *soc_data; 888 struct sdhci_host *host; 889 struct sdhci_pltfm_host *pltfm_host; 890 struct sdhci_tegra *tegra_host; 891 struct clk *clk; 892 int rc; 893 894 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 895 if (!match) 896 return -EINVAL; 897 soc_data = match->data; 898 899 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 900 if (IS_ERR(host)) 901 return PTR_ERR(host); 902 pltfm_host = sdhci_priv(host); 903 904 tegra_host = sdhci_pltfm_priv(pltfm_host); 905 tegra_host->ddr_signaling = false; 906 tegra_host->pad_calib_required = false; 907 tegra_host->pad_control_available = false; 908 tegra_host->soc_data = soc_data; 909 910 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 911 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 912 if (rc == 0) 913 host->mmc_host_ops.start_signal_voltage_switch = 914 sdhci_tegra_start_signal_voltage_switch; 915 } 916 917 rc = mmc_of_parse(host->mmc); 918 if (rc) 919 goto err_parse_dt; 920 921 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 922 host->mmc->caps |= MMC_CAP_1_8V_DDR; 923 924 tegra_sdhci_parse_pad_autocal_dt(host); 925 926 tegra_sdhci_parse_default_tap_and_trim(host); 927 928 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 929 GPIOD_OUT_HIGH); 930 if (IS_ERR(tegra_host->power_gpio)) { 931 rc = PTR_ERR(tegra_host->power_gpio); 932 goto err_power_req; 933 } 934 935 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 936 if (IS_ERR(clk)) { 937 dev_err(mmc_dev(host->mmc), "clk err\n"); 938 rc = PTR_ERR(clk); 939 goto err_clk_get; 940 } 941 clk_prepare_enable(clk); 942 pltfm_host->clk = clk; 943 944 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 945 "sdhci"); 946 if (IS_ERR(tegra_host->rst)) { 947 rc = PTR_ERR(tegra_host->rst); 948 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 949 goto err_rst_get; 950 } 951 952 rc = reset_control_assert(tegra_host->rst); 953 if (rc) 954 goto err_rst_get; 955 956 usleep_range(2000, 4000); 957 958 rc = reset_control_deassert(tegra_host->rst); 959 if (rc) 960 goto err_rst_get; 961 962 usleep_range(2000, 4000); 963 964 rc = sdhci_add_host(host); 965 if (rc) 966 goto err_add_host; 967 968 return 0; 969 970 err_add_host: 971 reset_control_assert(tegra_host->rst); 972 err_rst_get: 973 clk_disable_unprepare(pltfm_host->clk); 974 err_clk_get: 975 err_power_req: 976 err_parse_dt: 977 sdhci_pltfm_free(pdev); 978 return rc; 979 } 980 981 static int sdhci_tegra_remove(struct platform_device *pdev) 982 { 983 struct sdhci_host *host = platform_get_drvdata(pdev); 984 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 985 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 986 987 sdhci_remove_host(host, 0); 988 989 reset_control_assert(tegra_host->rst); 990 usleep_range(2000, 4000); 991 clk_disable_unprepare(pltfm_host->clk); 992 993 sdhci_pltfm_free(pdev); 994 995 return 0; 996 } 997 998 static struct platform_driver sdhci_tegra_driver = { 999 .driver = { 1000 .name = "sdhci-tegra", 1001 .of_match_table = sdhci_tegra_dt_match, 1002 .pm = &sdhci_pltfm_pmops, 1003 }, 1004 .probe = sdhci_tegra_probe, 1005 .remove = sdhci_tegra_remove, 1006 }; 1007 1008 module_platform_driver(sdhci_tegra_driver); 1009 1010 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1011 MODULE_AUTHOR("Google, Inc."); 1012 MODULE_LICENSE("GPL v2"); 1013